138388f7eSRichard Henderson# AArch64 SVE instruction descriptions 238388f7eSRichard Henderson# 338388f7eSRichard Henderson# Copyright (c) 2017 Linaro, Ltd 438388f7eSRichard Henderson# 538388f7eSRichard Henderson# This library is free software; you can redistribute it and/or 638388f7eSRichard Henderson# modify it under the terms of the GNU Lesser General Public 738388f7eSRichard Henderson# License as published by the Free Software Foundation; either 838388f7eSRichard Henderson# version 2 of the License, or (at your option) any later version. 938388f7eSRichard Henderson# 1038388f7eSRichard Henderson# This library is distributed in the hope that it will be useful, 1138388f7eSRichard Henderson# but WITHOUT ANY WARRANTY; without even the implied warranty of 1238388f7eSRichard Henderson# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1338388f7eSRichard Henderson# Lesser General Public License for more details. 1438388f7eSRichard Henderson# 1538388f7eSRichard Henderson# You should have received a copy of the GNU Lesser General Public 1638388f7eSRichard Henderson# License along with this library; if not, see <http://www.gnu.org/licenses/>. 1738388f7eSRichard Henderson 1838388f7eSRichard Henderson# 1938388f7eSRichard Henderson# This file is processed by scripts/decodetree.py 2038388f7eSRichard Henderson# 2138388f7eSRichard Henderson 2238388f7eSRichard Henderson########################################################################### 23d1822297SRichard Henderson# Named fields. These are primarily for disjoint fields. 24d1822297SRichard Henderson 2524e82e68SRichard Henderson%imm4_16_p1 16:4 !function=plus1 26ccd841c3SRichard Henderson%imm6_22_5 22:1 5:5 2730562ab7SRichard Henderson%imm7_22_16 22:2 16:5 28b94f8f60SRichard Henderson%imm8_16_10 16:5 10:3 29d1822297SRichard Henderson%imm9_16_10 16:s6 10:3 30d1822297SRichard Henderson 31ccd841c3SRichard Henderson# A combination of tsz:imm3 -- extract esize. 32ccd841c3SRichard Henderson%tszimm_esz 22:2 5:5 !function=tszimm_esz 33ccd841c3SRichard Henderson# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) 34ccd841c3SRichard Henderson%tszimm_shr 22:2 5:5 !function=tszimm_shr 35ccd841c3SRichard Henderson# A combination of tsz:imm3 -- extract (tsz:imm3) - esize 36ccd841c3SRichard Henderson%tszimm_shl 22:2 5:5 !function=tszimm_shl 37ccd841c3SRichard Henderson 38d9d78dccSRichard Henderson# Similarly for the tszh/tszl pair at 22/16 for zzi 39d9d78dccSRichard Henderson%tszimm16_esz 22:2 16:5 !function=tszimm_esz 40d9d78dccSRichard Henderson%tszimm16_shr 22:2 16:5 !function=tszimm_shr 41d9d78dccSRichard Henderson%tszimm16_shl 22:2 16:5 !function=tszimm_shl 42d9d78dccSRichard Henderson 43f25a2361SRichard Henderson# Signed 8-bit immediate, optionally shifted left by 8. 44f25a2361SRichard Henderson%sh8_i8s 5:9 !function=expand_imm_sh8s 45f25a2361SRichard Henderson 46f97cfd59SRichard Henderson# Either a copy of rd (at bit 0), or a different source 47f97cfd59SRichard Henderson# as propagated via the MOVPRFX instruction. 48f97cfd59SRichard Henderson%reg_movprfx 0:5 49f97cfd59SRichard Henderson 50d1822297SRichard Henderson########################################################################### 5138388f7eSRichard Henderson# Named attribute sets. These are used to make nice(er) names 5238388f7eSRichard Henderson# when creating helpers common to those for the individual 5338388f7eSRichard Henderson# instruction patterns. 5438388f7eSRichard Henderson 55028e2a7bSRichard Henderson&rr_esz rd rn esz 56d1822297SRichard Henderson&rri rd rn imm 57e1fa1164SRichard Henderson&rr_dbm rd rn dbm 584b242d9cSRichard Henderson&rrri rd rn rm imm 59d9d78dccSRichard Henderson&rri_esz rd rn imm esz 6038388f7eSRichard Henderson&rrr_esz rd rn rm esz 61047cec97SRichard Henderson&rpr_esz rd pg rn esz 62516e246aSRichard Henderson&rprr_s rd pg rn rm s 63f97cfd59SRichard Henderson&rprr_esz rd pg rn rm esz 6496a36e4aSRichard Henderson&rprrr_esz rd pg rn rm ra esz 65ccd841c3SRichard Henderson&rpri_esz rd pg rn imm esz 6624e82e68SRichard Henderson&ptrue rd esz pat s 6724e82e68SRichard Henderson&incdec_cnt rd pat esz imm d u 6824e82e68SRichard Henderson&incdec2_cnt rd rn pat esz imm d u 6938388f7eSRichard Henderson 7038388f7eSRichard Henderson########################################################################### 7138388f7eSRichard Henderson# Named instruction formats. These are generally used to 7238388f7eSRichard Henderson# reduce the amount of duplication between instruction patterns. 7338388f7eSRichard Henderson 74028e2a7bSRichard Henderson# Two operand with unused vector element size 75028e2a7bSRichard Henderson@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 76028e2a7bSRichard Henderson 77028e2a7bSRichard Henderson# Two operand 78028e2a7bSRichard Henderson@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz 790762cd42SRichard Henderson@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz 80028e2a7bSRichard Henderson 8138388f7eSRichard Henderson# Three operand with unused vector element size 8238388f7eSRichard Henderson@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 8338388f7eSRichard Henderson 84516e246aSRichard Henderson# Three predicate operand, with governing predicate, flag setting 85516e246aSRichard Henderson@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s 86516e246aSRichard Henderson 87fea98f9cSRichard Henderson# Three operand, vector element size 88fea98f9cSRichard Henderson@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz 89d731d8cbSRichard Henderson@pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz 9030562ab7SRichard Henderson@rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ 9130562ab7SRichard Henderson &rrr_esz rn=%reg_movprfx 92fea98f9cSRichard Henderson 934b242d9cSRichard Henderson# Three operand with "memory" size, aka immediate left shift 944b242d9cSRichard Henderson@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri 954b242d9cSRichard Henderson 96f97cfd59SRichard Henderson# Two register operand, with governing predicate, vector element size 97f97cfd59SRichard Henderson@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ 98f97cfd59SRichard Henderson &rprr_esz rn=%reg_movprfx 99f97cfd59SRichard Henderson@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ 100f97cfd59SRichard Henderson &rprr_esz rm=%reg_movprfx 101f97cfd59SRichard Henderson 10296a36e4aSRichard Henderson# Three register operand, with governing predicate, vector element size 10396a36e4aSRichard Henderson@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ 10496a36e4aSRichard Henderson &rprrr_esz ra=%reg_movprfx 10596a36e4aSRichard Henderson@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ 10696a36e4aSRichard Henderson &rprrr_esz rn=%reg_movprfx 10796a36e4aSRichard Henderson 108047cec97SRichard Henderson# One register operand, with governing predicate, vector element size 109047cec97SRichard Henderson@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz 110047cec97SRichard Henderson 11196f922ccSRichard Henderson# Two register operands with a 6-bit signed immediate. 11296f922ccSRichard Henderson@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri 11396f922ccSRichard Henderson 114ccd841c3SRichard Henderson# Two register operand, one immediate operand, with predicate, 115ccd841c3SRichard Henderson# element size encoded as TSZHL. User must fill in imm. 116ccd841c3SRichard Henderson@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ 117ccd841c3SRichard Henderson &rpri_esz rn=%reg_movprfx esz=%tszimm_esz 118ccd841c3SRichard Henderson 119d9d78dccSRichard Henderson# Similarly without predicate. 120d9d78dccSRichard Henderson@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ 121d9d78dccSRichard Henderson &rri_esz esz=%tszimm16_esz 122d9d78dccSRichard Henderson 123f25a2361SRichard Henderson# Two register operand, one immediate operand, with 4-bit predicate. 124f25a2361SRichard Henderson# User must fill in imm. 125f25a2361SRichard Henderson@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ 126f25a2361SRichard Henderson &rpri_esz rn=%reg_movprfx 127f25a2361SRichard Henderson 128e1fa1164SRichard Henderson# Two register operand, one encoded bitmask. 129e1fa1164SRichard Henderson@rdn_dbm ........ .. .... dbm:13 rd:5 \ 130e1fa1164SRichard Henderson &rr_dbm rn=%reg_movprfx 131e1fa1164SRichard Henderson 132d1822297SRichard Henderson# Basic Load/Store with 9-bit immediate offset 133d1822297SRichard Henderson@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ 134d1822297SRichard Henderson &rri imm=%imm9_16_10 135d1822297SRichard Henderson@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ 136d1822297SRichard Henderson &rri imm=%imm9_16_10 137d1822297SRichard Henderson 13824e82e68SRichard Henderson# One register, pattern, and uint4+1. 13924e82e68SRichard Henderson# User must fill in U and D. 14024e82e68SRichard Henderson@incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 14124e82e68SRichard Henderson &incdec_cnt imm=%imm4_16_p1 14224e82e68SRichard Henderson@incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 14324e82e68SRichard Henderson &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx 14424e82e68SRichard Henderson 14538388f7eSRichard Henderson########################################################################### 14638388f7eSRichard Henderson# Instruction patterns. Grouped according to the SVE encodingindex.xhtml. 14738388f7eSRichard Henderson 148f97cfd59SRichard Henderson### SVE Integer Arithmetic - Binary Predicated Group 149f97cfd59SRichard Henderson 150f97cfd59SRichard Henderson# SVE bitwise logical vector operations (predicated) 151f97cfd59SRichard HendersonORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm 152f97cfd59SRichard HendersonEOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm 153f97cfd59SRichard HendersonAND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm 154f97cfd59SRichard HendersonBIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm 155f97cfd59SRichard Henderson 156f97cfd59SRichard Henderson# SVE integer add/subtract vectors (predicated) 157f97cfd59SRichard HendersonADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm 158f97cfd59SRichard HendersonSUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm 159f97cfd59SRichard HendersonSUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR 160f97cfd59SRichard Henderson 161f97cfd59SRichard Henderson# SVE integer min/max/difference (predicated) 162f97cfd59SRichard HendersonSMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm 163f97cfd59SRichard HendersonUMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm 164f97cfd59SRichard HendersonSMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm 165f97cfd59SRichard HendersonUMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm 166f97cfd59SRichard HendersonSABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm 167f97cfd59SRichard HendersonUABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm 168f97cfd59SRichard Henderson 169f97cfd59SRichard Henderson# SVE integer multiply/divide (predicated) 170f97cfd59SRichard HendersonMUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm 171f97cfd59SRichard HendersonSMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm 172f97cfd59SRichard HendersonUMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm 173f97cfd59SRichard Henderson# Note that divide requires size >= 2; below 2 is unallocated. 174f97cfd59SRichard HendersonSDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm 175f97cfd59SRichard HendersonUDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm 176f97cfd59SRichard HendersonSDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR 177f97cfd59SRichard HendersonUDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR 178f97cfd59SRichard Henderson 179047cec97SRichard Henderson### SVE Integer Reduction Group 180047cec97SRichard Henderson 181047cec97SRichard Henderson# SVE bitwise logical reduction (predicated) 182047cec97SRichard HendersonORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn 183047cec97SRichard HendersonEORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn 184047cec97SRichard HendersonANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn 185047cec97SRichard Henderson 186047cec97SRichard Henderson# SVE integer add reduction (predicated) 187047cec97SRichard Henderson# Note that saddv requires size != 3. 188047cec97SRichard HendersonUADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn 189047cec97SRichard HendersonSADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn 190047cec97SRichard Henderson 191047cec97SRichard Henderson# SVE integer min/max reduction (predicated) 192047cec97SRichard HendersonSMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn 193047cec97SRichard HendersonUMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn 194047cec97SRichard HendersonSMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn 195047cec97SRichard HendersonUMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn 196047cec97SRichard Henderson 197ccd841c3SRichard Henderson### SVE Shift by Immediate - Predicated Group 198ccd841c3SRichard Henderson 199ccd841c3SRichard Henderson# SVE bitwise shift by immediate (predicated) 200ccd841c3SRichard HendersonASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \ 201ccd841c3SRichard Henderson @rdn_pg_tszimm imm=%tszimm_shr 202ccd841c3SRichard HendersonLSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \ 203ccd841c3SRichard Henderson @rdn_pg_tszimm imm=%tszimm_shr 204ccd841c3SRichard HendersonLSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \ 205ccd841c3SRichard Henderson @rdn_pg_tszimm imm=%tszimm_shl 206ccd841c3SRichard HendersonASRD 00000100 .. 000 100 100 ... .. ... ..... \ 207ccd841c3SRichard Henderson @rdn_pg_tszimm imm=%tszimm_shr 208ccd841c3SRichard Henderson 20927721dbbSRichard Henderson# SVE bitwise shift by vector (predicated) 21027721dbbSRichard HendersonASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm 21127721dbbSRichard HendersonLSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm 21227721dbbSRichard HendersonLSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm 21327721dbbSRichard HendersonASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR 21427721dbbSRichard HendersonLSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR 21527721dbbSRichard HendersonLSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR 21627721dbbSRichard Henderson 217fe7f8dfbSRichard Henderson# SVE bitwise shift by wide elements (predicated) 218fe7f8dfbSRichard Henderson# Note these require size != 3. 219fe7f8dfbSRichard HendersonASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm 220fe7f8dfbSRichard HendersonLSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm 221fe7f8dfbSRichard HendersonLSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm 222fe7f8dfbSRichard Henderson 223afac6d04SRichard Henderson### SVE Integer Arithmetic - Unary Predicated Group 224afac6d04SRichard Henderson 225afac6d04SRichard Henderson# SVE unary bit operations (predicated) 226afac6d04SRichard Henderson# Note esz != 0 for FABS and FNEG. 227afac6d04SRichard HendersonCLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn 228afac6d04SRichard HendersonCLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn 229afac6d04SRichard HendersonCNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn 230afac6d04SRichard HendersonCNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn 231afac6d04SRichard HendersonNOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn 232afac6d04SRichard HendersonFABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn 233afac6d04SRichard HendersonFNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn 234afac6d04SRichard Henderson 235afac6d04SRichard Henderson# SVE integer unary operations (predicated) 236afac6d04SRichard Henderson# Note esz > original size for extensions. 237afac6d04SRichard HendersonABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn 238afac6d04SRichard HendersonNEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn 239afac6d04SRichard HendersonSXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn 240afac6d04SRichard HendersonUXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn 241afac6d04SRichard HendersonSXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn 242afac6d04SRichard HendersonUXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn 243afac6d04SRichard HendersonSXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn 244afac6d04SRichard HendersonUXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn 245afac6d04SRichard Henderson 24696a36e4aSRichard Henderson### SVE Integer Multiply-Add Group 24796a36e4aSRichard Henderson 24896a36e4aSRichard Henderson# SVE integer multiply-add writing addend (predicated) 24996a36e4aSRichard HendersonMLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm 25096a36e4aSRichard HendersonMLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm 25196a36e4aSRichard Henderson 25296a36e4aSRichard Henderson# SVE integer multiply-add writing multiplicand (predicated) 25396a36e4aSRichard HendersonMLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD 25496a36e4aSRichard HendersonMLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB 25596a36e4aSRichard Henderson 256fea98f9cSRichard Henderson### SVE Integer Arithmetic - Unpredicated Group 257fea98f9cSRichard Henderson 258fea98f9cSRichard Henderson# SVE integer add/subtract vectors (unpredicated) 259fea98f9cSRichard HendersonADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm 260fea98f9cSRichard HendersonSUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm 261fea98f9cSRichard HendersonSQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm 262fea98f9cSRichard HendersonUQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm 263fea98f9cSRichard HendersonSQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm 264fea98f9cSRichard HendersonUQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm 265fea98f9cSRichard Henderson 26638388f7eSRichard Henderson### SVE Logical - Unpredicated Group 26738388f7eSRichard Henderson 26838388f7eSRichard Henderson# SVE bitwise logical operations (unpredicated) 26938388f7eSRichard HendersonAND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 27038388f7eSRichard HendersonORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 27138388f7eSRichard HendersonEOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 27238388f7eSRichard HendersonBIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 273d1822297SRichard Henderson 2749a56c9c3SRichard Henderson### SVE Index Generation Group 2759a56c9c3SRichard Henderson 2769a56c9c3SRichard Henderson# SVE index generation (immediate start, immediate increment) 2779a56c9c3SRichard HendersonINDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 2789a56c9c3SRichard Henderson 2799a56c9c3SRichard Henderson# SVE index generation (immediate start, register increment) 2809a56c9c3SRichard HendersonINDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 2819a56c9c3SRichard Henderson 2829a56c9c3SRichard Henderson# SVE index generation (register start, immediate increment) 2839a56c9c3SRichard HendersonINDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 2849a56c9c3SRichard Henderson 2859a56c9c3SRichard Henderson# SVE index generation (register start, register increment) 2869a56c9c3SRichard HendersonINDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm 2879a56c9c3SRichard Henderson 28896f922ccSRichard Henderson### SVE Stack Allocation Group 28996f922ccSRichard Henderson 29096f922ccSRichard Henderson# SVE stack frame adjustment 29196f922ccSRichard HendersonADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 29296f922ccSRichard HendersonADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 29396f922ccSRichard Henderson 29496f922ccSRichard Henderson# SVE stack frame size 29596f922ccSRichard HendersonRDVL 00000100 101 11111 01010 imm:s6 rd:5 29696f922ccSRichard Henderson 297d9d78dccSRichard Henderson### SVE Bitwise Shift - Unpredicated Group 298d9d78dccSRichard Henderson 299d9d78dccSRichard Henderson# SVE bitwise shift by immediate (unpredicated) 300d9d78dccSRichard HendersonASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \ 301d9d78dccSRichard Henderson @rd_rn_tszimm imm=%tszimm16_shr 302d9d78dccSRichard HendersonLSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \ 303d9d78dccSRichard Henderson @rd_rn_tszimm imm=%tszimm16_shr 304d9d78dccSRichard HendersonLSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \ 305d9d78dccSRichard Henderson @rd_rn_tszimm imm=%tszimm16_shl 306d9d78dccSRichard Henderson 307d9d78dccSRichard Henderson# SVE bitwise shift by wide elements (unpredicated) 308d9d78dccSRichard Henderson# Note esz != 3 309d9d78dccSRichard HendersonASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm 310d9d78dccSRichard HendersonLSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm 311d9d78dccSRichard HendersonLSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm 312d9d78dccSRichard Henderson 3134b242d9cSRichard Henderson### SVE Compute Vector Address Group 3144b242d9cSRichard Henderson 3154b242d9cSRichard Henderson# SVE vector address generation 3164b242d9cSRichard HendersonADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 3174b242d9cSRichard HendersonADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 3184b242d9cSRichard HendersonADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 3194b242d9cSRichard HendersonADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 3204b242d9cSRichard Henderson 3210762cd42SRichard Henderson### SVE Integer Misc - Unpredicated Group 3220762cd42SRichard Henderson 3230762cd42SRichard Henderson# SVE floating-point exponential accelerator 3240762cd42SRichard Henderson# Note esz != 0 3250762cd42SRichard HendersonFEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn 3260762cd42SRichard Henderson 327a1f233f2SRichard Henderson# SVE floating-point trig select coefficient 328a1f233f2SRichard Henderson# Note esz != 0 329a1f233f2SRichard HendersonFTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm 330a1f233f2SRichard Henderson 33124e82e68SRichard Henderson### SVE Element Count Group 33224e82e68SRichard Henderson 33324e82e68SRichard Henderson# SVE element count 33424e82e68SRichard HendersonCNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 33524e82e68SRichard Henderson 33624e82e68SRichard Henderson# SVE inc/dec register by element count 33724e82e68SRichard HendersonINCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 33824e82e68SRichard Henderson 33924e82e68SRichard Henderson# SVE saturating inc/dec register by element count 34024e82e68SRichard HendersonSINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 34124e82e68SRichard HendersonSINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 34224e82e68SRichard Henderson 34324e82e68SRichard Henderson# SVE inc/dec vector by element count 34424e82e68SRichard Henderson# Note this requires esz != 0. 34524e82e68SRichard HendersonINCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 34624e82e68SRichard Henderson 34724e82e68SRichard Henderson# SVE saturating inc/dec vector by element count 34824e82e68SRichard Henderson# Note these require esz != 0. 34924e82e68SRichard HendersonSINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt 350516e246aSRichard Henderson 351e1fa1164SRichard Henderson### SVE Bitwise Immediate Group 352e1fa1164SRichard Henderson 353e1fa1164SRichard Henderson# SVE bitwise logical with immediate (unpredicated) 354e1fa1164SRichard HendersonORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm 355e1fa1164SRichard HendersonEOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm 356e1fa1164SRichard HendersonAND_zzi 00000101 10 0000 ............. ..... @rdn_dbm 357e1fa1164SRichard Henderson 358e1fa1164SRichard Henderson# SVE broadcast bitmask immediate 359e1fa1164SRichard HendersonDUPM 00000101 11 0000 dbm:13 rd:5 360e1fa1164SRichard Henderson 361f25a2361SRichard Henderson### SVE Integer Wide Immediate - Predicated Group 362f25a2361SRichard Henderson 363f25a2361SRichard Henderson# SVE copy floating-point immediate (predicated) 364f25a2361SRichard HendersonFCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 365f25a2361SRichard Henderson 366f25a2361SRichard Henderson# SVE copy integer immediate (predicated) 367f25a2361SRichard HendersonCPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s 368f25a2361SRichard HendersonCPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s 369f25a2361SRichard Henderson 370b94f8f60SRichard Henderson### SVE Permute - Extract Group 371b94f8f60SRichard Henderson 372b94f8f60SRichard Henderson# SVE extract vector (immediate offset) 373b94f8f60SRichard HendersonEXT 00000101 001 ..... 000 ... rm:5 rd:5 \ 374b94f8f60SRichard Henderson &rrri rn=%reg_movprfx imm=%imm8_16_10 375b94f8f60SRichard Henderson 37630562ab7SRichard Henderson### SVE Permute - Unpredicated Group 37730562ab7SRichard Henderson 37830562ab7SRichard Henderson# SVE broadcast general register 37930562ab7SRichard HendersonDUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn 38030562ab7SRichard Henderson 38130562ab7SRichard Henderson# SVE broadcast indexed element 38230562ab7SRichard HendersonDUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ 38330562ab7SRichard Henderson &rri imm=%imm7_22_16 38430562ab7SRichard Henderson 38530562ab7SRichard Henderson# SVE insert SIMD&FP scalar register 38630562ab7SRichard HendersonINSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm 38730562ab7SRichard Henderson 38830562ab7SRichard Henderson# SVE insert general register 38930562ab7SRichard HendersonINSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm 39030562ab7SRichard Henderson 39130562ab7SRichard Henderson# SVE reverse vector elements 39230562ab7SRichard HendersonREV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn 39330562ab7SRichard Henderson 39430562ab7SRichard Henderson# SVE vector table lookup 39530562ab7SRichard HendersonTBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm 39630562ab7SRichard Henderson 39730562ab7SRichard Henderson# SVE unpack vector elements 39830562ab7SRichard HendersonUNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 39930562ab7SRichard Henderson 400d731d8cbSRichard Henderson### SVE Permute - Predicates Group 401d731d8cbSRichard Henderson 402d731d8cbSRichard Henderson# SVE permute predicate elements 403d731d8cbSRichard HendersonZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm 404d731d8cbSRichard HendersonZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm 405d731d8cbSRichard HendersonUZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm 406d731d8cbSRichard HendersonUZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm 407d731d8cbSRichard HendersonTRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm 408d731d8cbSRichard HendersonTRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm 409d731d8cbSRichard Henderson 410d731d8cbSRichard Henderson# SVE reverse predicate elements 411d731d8cbSRichard HendersonREV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn 412d731d8cbSRichard Henderson 413d731d8cbSRichard Henderson# SVE unpack predicate elements 414d731d8cbSRichard HendersonPUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 415d731d8cbSRichard HendersonPUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 416d731d8cbSRichard Henderson 417234b48e9SRichard Henderson### SVE Permute - Interleaving Group 418234b48e9SRichard Henderson 419234b48e9SRichard Henderson# SVE permute vector elements 420234b48e9SRichard HendersonZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm 421234b48e9SRichard HendersonZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm 422234b48e9SRichard HendersonUZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm 423234b48e9SRichard HendersonUZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm 424234b48e9SRichard HendersonTRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm 425234b48e9SRichard HendersonTRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm 426234b48e9SRichard Henderson 427*3ca879aeSRichard Henderson### SVE Permute - Predicated Group 428*3ca879aeSRichard Henderson 429*3ca879aeSRichard Henderson# SVE compress active elements 430*3ca879aeSRichard Henderson# Note esz >= 2 431*3ca879aeSRichard HendersonCOMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn 432*3ca879aeSRichard Henderson 433e1fa1164SRichard Henderson### SVE Predicate Logical Operations Group 434e1fa1164SRichard Henderson 435516e246aSRichard Henderson# SVE predicate logical operations 436516e246aSRichard HendersonAND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 437516e246aSRichard HendersonBIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 438516e246aSRichard HendersonEOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 439516e246aSRichard HendersonSEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 440516e246aSRichard HendersonORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 441516e246aSRichard HendersonORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 442516e246aSRichard HendersonNOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 443516e246aSRichard HendersonNAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 444516e246aSRichard Henderson 4459e18d7a6SRichard Henderson### SVE Predicate Misc Group 4469e18d7a6SRichard Henderson 4479e18d7a6SRichard Henderson# SVE predicate test 4489e18d7a6SRichard HendersonPTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 4499e18d7a6SRichard Henderson 450028e2a7bSRichard Henderson# SVE predicate initialize 451028e2a7bSRichard HendersonPTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 452028e2a7bSRichard Henderson 453028e2a7bSRichard Henderson# SVE initialize FFR 454028e2a7bSRichard HendersonSETFFR 00100101 0010 1100 1001 0000 0000 0000 455028e2a7bSRichard Henderson 456028e2a7bSRichard Henderson# SVE zero predicate register 457028e2a7bSRichard HendersonPFALSE 00100101 0001 1000 1110 0100 0000 rd:4 458028e2a7bSRichard Henderson 459028e2a7bSRichard Henderson# SVE predicate read from FFR (predicated) 460028e2a7bSRichard HendersonRDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 461028e2a7bSRichard Henderson 462028e2a7bSRichard Henderson# SVE predicate read from FFR (unpredicated) 463028e2a7bSRichard HendersonRDFFR 00100101 0001 1001 1111 0000 0000 rd:4 464028e2a7bSRichard Henderson 465028e2a7bSRichard Henderson# SVE FFR write from predicate (WRFFR) 466028e2a7bSRichard HendersonWRFFR 00100101 0010 1000 1001 000 rn:4 00000 467028e2a7bSRichard Henderson 468028e2a7bSRichard Henderson# SVE predicate first active 469028e2a7bSRichard HendersonPFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 470028e2a7bSRichard Henderson 471028e2a7bSRichard Henderson# SVE predicate next active 472028e2a7bSRichard HendersonPNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn 473028e2a7bSRichard Henderson 474d1822297SRichard Henderson### SVE Memory - 32-bit Gather and Unsized Contiguous Group 475d1822297SRichard Henderson 476d1822297SRichard Henderson# SVE load predicate register 477d1822297SRichard HendersonLDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 478d1822297SRichard Henderson 479d1822297SRichard Henderson# SVE load vector register 480d1822297SRichard HendersonLDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 481