1 /* 2 * ARM helper routines 3 * 4 * Copyright (c) 2005-2007 CodeSourcery, LLC 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/main-loop.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "internals.h" 24 #include "cpu-features.h" 25 #include "exec/exec-all.h" 26 #include "exec/cpu_ldst.h" 27 #include "cpregs.h" 28 29 #define SIGNBIT (uint32_t)0x80000000 30 #define SIGNBIT64 ((uint64_t)1 << 63) 31 32 int exception_target_el(CPUARMState *env) 33 { 34 int target_el = MAX(1, arm_current_el(env)); 35 36 /* 37 * No such thing as secure EL1 if EL3 is aarch32, 38 * so update the target EL to EL3 in this case. 39 */ 40 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { 41 target_el = 3; 42 } 43 44 return target_el; 45 } 46 47 void raise_exception(CPUARMState *env, uint32_t excp, 48 uint32_t syndrome, uint32_t target_el) 49 { 50 CPUState *cs = env_cpu(env); 51 52 if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { 53 /* 54 * Redirect NS EL1 exceptions to NS EL2. These are reported with 55 * their original syndrome register value, with the exception of 56 * SIMD/FP access traps, which are reported as uncategorized 57 * (see DDI0478C.a D1.10.4) 58 */ 59 target_el = 2; 60 if (syn_get_ec(syndrome) == EC_ADVSIMDFPACCESSTRAP) { 61 syndrome = syn_uncategorized(); 62 } 63 } 64 65 assert(!excp_is_internal(excp)); 66 cs->exception_index = excp; 67 env->exception.syndrome = syndrome; 68 env->exception.target_el = target_el; 69 cpu_loop_exit(cs); 70 } 71 72 void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, 73 uint32_t target_el, uintptr_t ra) 74 { 75 CPUState *cs = env_cpu(env); 76 77 /* 78 * restore_state_to_opc() will set env->exception.syndrome, so 79 * we must restore CPU state here before setting the syndrome 80 * the caller passed us, and cannot use cpu_loop_exit_restore(). 81 */ 82 cpu_restore_state(cs, ra); 83 raise_exception(env, excp, syndrome, target_el); 84 } 85 86 uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, 87 uint64_t ireg, uint64_t def) 88 { 89 uint64_t tmp, val = 0; 90 uint32_t maxindex = ((desc & 3) + 1) * 8; 91 uint32_t base_reg = desc >> 2; 92 uint32_t shift, index, reg; 93 94 for (shift = 0; shift < 64; shift += 8) { 95 index = (ireg >> shift) & 0xff; 96 if (index < maxindex) { 97 reg = base_reg + (index >> 3); 98 tmp = *aa32_vfp_dreg(env, reg); 99 tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; 100 } else { 101 tmp = def & (0xffull << shift); 102 } 103 val |= tmp; 104 } 105 return val; 106 } 107 108 void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) 109 { 110 /* 111 * Perform the v8M stack limit check for SP updates from translated code, 112 * raising an exception if the limit is breached. 113 */ 114 if (newvalue < v7m_sp_limit(env)) { 115 /* 116 * Stack limit exceptions are a rare case, so rather than syncing 117 * PC/condbits before the call, we use raise_exception_ra() so 118 * that cpu_restore_state() will sort them out. 119 */ 120 raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); 121 } 122 } 123 124 /* Sign/zero extend */ 125 uint32_t HELPER(sxtb16)(uint32_t x) 126 { 127 uint32_t res; 128 res = (uint16_t)(int8_t)x; 129 res |= (uint32_t)(int8_t)(x >> 16) << 16; 130 return res; 131 } 132 133 static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) 134 { 135 /* 136 * Take a division-by-zero exception if necessary; otherwise return 137 * to get the usual non-trapping division behaviour (result of 0) 138 */ 139 if (arm_feature(env, ARM_FEATURE_M) 140 && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { 141 raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); 142 } 143 } 144 145 uint32_t HELPER(uxtb16)(uint32_t x) 146 { 147 uint32_t res; 148 res = (uint16_t)(uint8_t)x; 149 res |= (uint32_t)(uint8_t)(x >> 16) << 16; 150 return res; 151 } 152 153 int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) 154 { 155 if (den == 0) { 156 handle_possible_div0_trap(env, GETPC()); 157 return 0; 158 } 159 if (num == INT_MIN && den == -1) { 160 return INT_MIN; 161 } 162 return num / den; 163 } 164 165 uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) 166 { 167 if (den == 0) { 168 handle_possible_div0_trap(env, GETPC()); 169 return 0; 170 } 171 return num / den; 172 } 173 174 uint32_t HELPER(rbit)(uint32_t x) 175 { 176 return revbit32(x); 177 } 178 179 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) 180 { 181 uint32_t res = a + b; 182 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) 183 env->QF = 1; 184 return res; 185 } 186 187 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b) 188 { 189 uint32_t res = a + b; 190 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) { 191 env->QF = 1; 192 res = ~(((int32_t)a >> 31) ^ SIGNBIT); 193 } 194 return res; 195 } 196 197 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b) 198 { 199 uint32_t res = a - b; 200 if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) { 201 env->QF = 1; 202 res = ~(((int32_t)a >> 31) ^ SIGNBIT); 203 } 204 return res; 205 } 206 207 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) 208 { 209 uint32_t res = a + b; 210 if (res < a) { 211 env->QF = 1; 212 res = ~0; 213 } 214 return res; 215 } 216 217 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) 218 { 219 uint32_t res = a - b; 220 if (res > a) { 221 env->QF = 1; 222 res = 0; 223 } 224 return res; 225 } 226 227 /* Signed saturation. */ 228 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift) 229 { 230 int32_t top; 231 uint32_t mask; 232 233 top = val >> shift; 234 mask = (1u << shift) - 1; 235 if (top > 0) { 236 env->QF = 1; 237 return mask; 238 } else if (top < -1) { 239 env->QF = 1; 240 return ~mask; 241 } 242 return val; 243 } 244 245 /* Unsigned saturation. */ 246 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift) 247 { 248 uint32_t max; 249 250 max = (1u << shift) - 1; 251 if (val < 0) { 252 env->QF = 1; 253 return 0; 254 } else if (val > max) { 255 env->QF = 1; 256 return max; 257 } 258 return val; 259 } 260 261 /* Signed saturate. */ 262 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift) 263 { 264 return do_ssat(env, x, shift); 265 } 266 267 /* Dual halfword signed saturate. */ 268 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift) 269 { 270 uint32_t res; 271 272 res = (uint16_t)do_ssat(env, (int16_t)x, shift); 273 res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16; 274 return res; 275 } 276 277 /* Unsigned saturate. */ 278 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift) 279 { 280 return do_usat(env, x, shift); 281 } 282 283 /* Dual halfword unsigned saturate. */ 284 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) 285 { 286 uint32_t res; 287 288 res = (uint16_t)do_usat(env, (int16_t)x, shift); 289 res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16; 290 return res; 291 } 292 293 void HELPER(setend)(CPUARMState *env) 294 { 295 env->uncached_cpsr ^= CPSR_E; 296 arm_rebuild_hflags(env); 297 } 298 299 void HELPER(check_bxj_trap)(CPUARMState *env, uint32_t rm) 300 { 301 /* 302 * Only called if in NS EL0 or EL1 for a BXJ for a v7A CPU; 303 * check if HSTR.TJDBX means we need to trap to EL2. 304 */ 305 if (env->cp15.hstr_el2 & HSTR_TJDBX) { 306 /* 307 * We know the condition code check passed, so take the IMPDEF 308 * choice to always report CV=1 COND 0xe 309 */ 310 uint32_t syn = syn_bxjtrap(1, 0xe, rm); 311 raise_exception_ra(env, EXCP_HYP_TRAP, syn, 2, GETPC()); 312 } 313 } 314 315 #ifndef CONFIG_USER_ONLY 316 /* 317 * Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. 318 * The function returns the target EL (1-3) if the instruction is to be trapped; 319 * otherwise it returns 0 indicating it is not trapped. 320 * For a trap, *excp is updated with the EXCP_* trap type to use. 321 */ 322 static inline int check_wfx_trap(CPUARMState *env, bool is_wfe, uint32_t *excp) 323 { 324 int cur_el = arm_current_el(env); 325 uint64_t mask; 326 327 *excp = EXCP_UDEF; 328 329 if (arm_feature(env, ARM_FEATURE_M)) { 330 /* M profile cores can never trap WFI/WFE. */ 331 return 0; 332 } 333 334 /* If we are currently in EL0 then we need to check if SCTLR is set up for 335 * WFx instructions being trapped to EL1. These trap bits don't exist in v7. 336 */ 337 if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) { 338 mask = is_wfe ? SCTLR_nTWE : SCTLR_nTWI; 339 if (!(arm_sctlr(env, cur_el) & mask)) { 340 return exception_target_el(env); 341 } 342 } 343 344 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it 345 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the 346 * bits will be zero indicating no trap. 347 */ 348 if (cur_el < 2) { 349 mask = is_wfe ? HCR_TWE : HCR_TWI; 350 if (arm_hcr_el2_eff(env) & mask) { 351 return 2; 352 } 353 } 354 355 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */ 356 if (arm_feature(env, ARM_FEATURE_V8) && !arm_is_el3_or_mon(env)) { 357 mask = (is_wfe) ? SCR_TWE : SCR_TWI; 358 if (env->cp15.scr_el3 & mask) { 359 if (!arm_el_is_aa64(env, 3)) { 360 *excp = EXCP_MON_TRAP; 361 } 362 return 3; 363 } 364 } 365 366 return 0; 367 } 368 #endif 369 370 void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) 371 { 372 #ifdef CONFIG_USER_ONLY 373 /* 374 * WFI in the user-mode emulator is technically permitted but not 375 * something any real-world code would do. AArch64 Linux kernels 376 * trap it via SCTRL_EL1.nTWI and make it an (expensive) NOP; 377 * AArch32 kernels don't trap it so it will delay a bit. 378 * For QEMU, make it NOP here, because trying to raise EXCP_HLT 379 * would trigger an abort. 380 */ 381 return; 382 #else 383 CPUState *cs = env_cpu(env); 384 uint32_t excp; 385 int target_el = check_wfx_trap(env, false, &excp); 386 387 if (cpu_has_work(cs)) { 388 /* Don't bother to go into our "low power state" if 389 * we would just wake up immediately. 390 */ 391 return; 392 } 393 394 if (target_el) { 395 if (env->aarch64) { 396 env->pc -= insn_len; 397 } else { 398 env->regs[15] -= insn_len; 399 } 400 401 raise_exception(env, excp, syn_wfx(1, 0xe, 0, insn_len == 2), 402 target_el); 403 } 404 405 cs->exception_index = EXCP_HLT; 406 cs->halted = 1; 407 cpu_loop_exit(cs); 408 #endif 409 } 410 411 void HELPER(wfit)(CPUARMState *env, uint64_t timeout) 412 { 413 #ifdef CONFIG_USER_ONLY 414 /* 415 * WFI in the user-mode emulator is technically permitted but not 416 * something any real-world code would do. AArch64 Linux kernels 417 * trap it via SCTRL_EL1.nTWI and make it an (expensive) NOP; 418 * AArch32 kernels don't trap it so it will delay a bit. 419 * For QEMU, make it NOP here, because trying to raise EXCP_HLT 420 * would trigger an abort. 421 */ 422 return; 423 #else 424 ARMCPU *cpu = env_archcpu(env); 425 CPUState *cs = env_cpu(env); 426 uint32_t excp; 427 int target_el = check_wfx_trap(env, false, &excp); 428 /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */ 429 uint64_t cntval = gt_get_countervalue(env); 430 uint64_t offset = gt_virt_cnt_offset(env); 431 uint64_t cntvct = cntval - offset; 432 uint64_t nexttick; 433 434 if (cpu_has_work(cs) || cntvct >= timeout) { 435 /* 436 * Don't bother to go into our "low power state" if 437 * we would just wake up immediately. 438 */ 439 return; 440 } 441 442 if (target_el) { 443 env->pc -= 4; 444 raise_exception(env, excp, syn_wfx(1, 0xe, 0, false), target_el); 445 } 446 447 if (uadd64_overflow(timeout, offset, &nexttick)) { 448 nexttick = UINT64_MAX; 449 } 450 if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { 451 /* 452 * If the timeout is too long for the signed 64-bit range 453 * of a QEMUTimer, let it expire early. 454 */ 455 timer_mod_ns(cpu->wfxt_timer, INT64_MAX); 456 } else { 457 timer_mod(cpu->wfxt_timer, nexttick); 458 } 459 cs->exception_index = EXCP_HLT; 460 cs->halted = 1; 461 cpu_loop_exit(cs); 462 #endif 463 } 464 465 void HELPER(wfe)(CPUARMState *env) 466 { 467 /* This is a hint instruction that is semantically different 468 * from YIELD even though we currently implement it identically. 469 * Don't actually halt the CPU, just yield back to top 470 * level loop. This is not going into a "low power state" 471 * (ie halting until some event occurs), so we never take 472 * a configurable trap to a different exception level. 473 */ 474 HELPER(yield)(env); 475 } 476 477 void HELPER(yield)(CPUARMState *env) 478 { 479 CPUState *cs = env_cpu(env); 480 481 /* This is a non-trappable hint instruction that generally indicates 482 * that the guest is currently busy-looping. Yield control back to the 483 * top level loop so that a more deserving VCPU has a chance to run. 484 */ 485 cs->exception_index = EXCP_YIELD; 486 cpu_loop_exit(cs); 487 } 488 489 /* Raise an internal-to-QEMU exception. This is limited to only 490 * those EXCP values which are special cases for QEMU to interrupt 491 * execution and not to be used for exceptions which are passed to 492 * the guest (those must all have syndrome information and thus should 493 * use exception_with_syndrome*). 494 */ 495 void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) 496 { 497 CPUState *cs = env_cpu(env); 498 499 assert(excp_is_internal(excp)); 500 cs->exception_index = excp; 501 cpu_loop_exit(cs); 502 } 503 504 /* Raise an exception with the specified syndrome register value */ 505 void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, 506 uint32_t syndrome, uint32_t target_el) 507 { 508 raise_exception(env, excp, syndrome, target_el); 509 } 510 511 /* 512 * Raise an exception with the specified syndrome register value 513 * to the default target el. 514 */ 515 void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, 516 uint32_t syndrome) 517 { 518 raise_exception(env, excp, syndrome, exception_target_el(env)); 519 } 520 521 uint32_t HELPER(cpsr_read)(CPUARMState *env) 522 { 523 return cpsr_read(env) & ~CPSR_EXEC; 524 } 525 526 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) 527 { 528 cpsr_write(env, val, mask, CPSRWriteByInstr); 529 /* TODO: Not all cpsr bits are relevant to hflags. */ 530 arm_rebuild_hflags(env); 531 } 532 533 /* Write the CPSR for a 32-bit exception return */ 534 void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) 535 { 536 uint32_t mask; 537 538 bql_lock(); 539 arm_call_pre_el_change_hook(env_archcpu(env)); 540 bql_unlock(); 541 542 mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); 543 cpsr_write(env, val, mask, CPSRWriteExceptionReturn); 544 545 /* Generated code has already stored the new PC value, but 546 * without masking out its low bits, because which bits need 547 * masking depends on whether we're returning to Thumb or ARM 548 * state. Do the masking now. 549 */ 550 env->regs[15] &= (env->thumb ? ~1 : ~3); 551 arm_rebuild_hflags(env); 552 553 bql_lock(); 554 arm_call_el_change_hook(env_archcpu(env)); 555 bql_unlock(); 556 } 557 558 /* Access to user mode registers from privileged modes. */ 559 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno) 560 { 561 uint32_t val; 562 563 if (regno == 13) { 564 val = env->banked_r13[BANK_USRSYS]; 565 } else if (regno == 14) { 566 val = env->banked_r14[BANK_USRSYS]; 567 } else if (regno >= 8 568 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { 569 val = env->usr_regs[regno - 8]; 570 } else { 571 val = env->regs[regno]; 572 } 573 return val; 574 } 575 576 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val) 577 { 578 if (regno == 13) { 579 env->banked_r13[BANK_USRSYS] = val; 580 } else if (regno == 14) { 581 env->banked_r14[BANK_USRSYS] = val; 582 } else if (regno >= 8 583 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { 584 env->usr_regs[regno - 8] = val; 585 } else { 586 env->regs[regno] = val; 587 } 588 } 589 590 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) 591 { 592 if ((env->uncached_cpsr & CPSR_M) == mode) { 593 env->regs[13] = val; 594 } else { 595 env->banked_r13[bank_number(mode)] = val; 596 } 597 } 598 599 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) 600 { 601 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { 602 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF. 603 * Other UNPREDICTABLE and UNDEF cases were caught at translate time. 604 */ 605 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 606 exception_target_el(env)); 607 } 608 609 if ((env->uncached_cpsr & CPSR_M) == mode) { 610 return env->regs[13]; 611 } else { 612 return env->banked_r13[bank_number(mode)]; 613 } 614 } 615 616 static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, 617 uint32_t regno) 618 { 619 /* Raise an exception if the requested access is one of the UNPREDICTABLE 620 * cases; otherwise return. This broadly corresponds to the pseudocode 621 * BankedRegisterAccessValid() and SPSRAccessValid(), 622 * except that we have already handled some cases at translate time. 623 */ 624 int curmode = env->uncached_cpsr & CPSR_M; 625 626 if (tgtmode == ARM_CPU_MODE_HYP) { 627 /* 628 * Handle Hyp target regs first because some are special cases 629 * which don't want the usual "not accessible from tgtmode" check. 630 */ 631 switch (regno) { 632 case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */ 633 if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) { 634 goto undef; 635 } 636 break; 637 case 13: 638 if (curmode != ARM_CPU_MODE_MON) { 639 goto undef; 640 } 641 break; 642 default: 643 g_assert_not_reached(); 644 } 645 return; 646 } 647 648 if (curmode == tgtmode) { 649 goto undef; 650 } 651 652 if (tgtmode == ARM_CPU_MODE_USR) { 653 switch (regno) { 654 case 8 ... 12: 655 if (curmode != ARM_CPU_MODE_FIQ) { 656 goto undef; 657 } 658 break; 659 case 13: 660 if (curmode == ARM_CPU_MODE_SYS) { 661 goto undef; 662 } 663 break; 664 case 14: 665 if (curmode == ARM_CPU_MODE_HYP || curmode == ARM_CPU_MODE_SYS) { 666 goto undef; 667 } 668 break; 669 default: 670 break; 671 } 672 } 673 674 return; 675 676 undef: 677 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 678 exception_target_el(env)); 679 } 680 681 void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode, 682 uint32_t regno) 683 { 684 msr_mrs_banked_exc_checks(env, tgtmode, regno); 685 686 switch (regno) { 687 case 16: /* SPSRs */ 688 if (tgtmode == (env->uncached_cpsr & CPSR_M)) { 689 /* Only happens for SPSR_Hyp access in Hyp mode */ 690 env->spsr = value; 691 } else { 692 env->banked_spsr[bank_number(tgtmode)] = value; 693 } 694 break; 695 case 17: /* ELR_Hyp */ 696 env->elr_el[2] = value; 697 break; 698 case 13: 699 env->banked_r13[bank_number(tgtmode)] = value; 700 break; 701 case 14: 702 env->banked_r14[r14_bank_number(tgtmode)] = value; 703 break; 704 case 8 ... 12: 705 switch (tgtmode) { 706 case ARM_CPU_MODE_USR: 707 env->usr_regs[regno - 8] = value; 708 break; 709 case ARM_CPU_MODE_FIQ: 710 env->fiq_regs[regno - 8] = value; 711 break; 712 default: 713 g_assert_not_reached(); 714 } 715 break; 716 default: 717 g_assert_not_reached(); 718 } 719 } 720 721 uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno) 722 { 723 msr_mrs_banked_exc_checks(env, tgtmode, regno); 724 725 switch (regno) { 726 case 16: /* SPSRs */ 727 if (tgtmode == (env->uncached_cpsr & CPSR_M)) { 728 /* Only happens for SPSR_Hyp access in Hyp mode */ 729 return env->spsr; 730 } else { 731 return env->banked_spsr[bank_number(tgtmode)]; 732 } 733 case 17: /* ELR_Hyp */ 734 return env->elr_el[2]; 735 case 13: 736 return env->banked_r13[bank_number(tgtmode)]; 737 case 14: 738 return env->banked_r14[r14_bank_number(tgtmode)]; 739 case 8 ... 12: 740 switch (tgtmode) { 741 case ARM_CPU_MODE_USR: 742 return env->usr_regs[regno - 8]; 743 case ARM_CPU_MODE_FIQ: 744 return env->fiq_regs[regno - 8]; 745 default: 746 g_assert_not_reached(); 747 } 748 default: 749 g_assert_not_reached(); 750 } 751 } 752 753 const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, 754 uint32_t syndrome, uint32_t isread) 755 { 756 ARMCPU *cpu = env_archcpu(env); 757 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key); 758 CPAccessResult res = CP_ACCESS_OK; 759 int target_el; 760 uint32_t excp; 761 762 assert(ri != NULL); 763 764 if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 765 && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) { 766 res = CP_ACCESS_UNDEFINED; 767 goto fail; 768 } 769 770 if (ri->accessfn) { 771 res = ri->accessfn(env, ri, isread); 772 } 773 774 /* 775 * If the access function indicates a trap from EL0 to EL1 then 776 * that always takes priority over the HSTR_EL2 trap. (If it indicates 777 * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicates 778 * a trap to EL2, then the syndrome is the same either way so we don't 779 * care whether technically the architecture says that HSTR_EL2 trap or 780 * the other trap takes priority. So we take the "check HSTR_EL2" path 781 * for all of those cases.) 782 */ 783 if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) < 2) && 784 arm_current_el(env) == 0) { 785 goto fail; 786 } 787 788 /* 789 * HSTR_EL2 traps from EL1 are checked earlier, in generated code; 790 * we only need to check here for traps from EL0. 791 */ 792 if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 && 793 arm_is_el2_enabled(env) && 794 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 795 uint32_t mask = 1 << ri->crn; 796 797 if (ri->type & ARM_CP_64BIT) { 798 mask = 1 << ri->crm; 799 } 800 801 /* T4 and T14 are RES0 */ 802 mask &= ~((1 << 4) | (1 << 14)); 803 804 if (env->cp15.hstr_el2 & mask) { 805 res = CP_ACCESS_TRAP_EL2; 806 goto fail; 807 } 808 } 809 810 /* 811 * Fine-grained traps also are lower priority than undef-to-EL1, 812 * higher priority than trap-to-EL3, and we don't care about priority 813 * order with other EL2 traps because the syndrome value is the same. 814 */ 815 if (arm_fgt_active(env, arm_current_el(env))) { 816 uint64_t trapword = 0; 817 unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX); 818 unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS); 819 bool rev = FIELD_EX32(ri->fgt, FGT, REV); 820 bool nxs = FIELD_EX32(ri->fgt, FGT, NXS); 821 bool trapbit; 822 823 if (ri->fgt & FGT_EXEC) { 824 assert(idx < ARRAY_SIZE(env->cp15.fgt_exec)); 825 trapword = env->cp15.fgt_exec[idx]; 826 } else if (isread && (ri->fgt & FGT_R)) { 827 assert(idx < ARRAY_SIZE(env->cp15.fgt_read)); 828 trapword = env->cp15.fgt_read[idx]; 829 } else if (!isread && (ri->fgt & FGT_W)) { 830 assert(idx < ARRAY_SIZE(env->cp15.fgt_write)); 831 trapword = env->cp15.fgt_write[idx]; 832 } 833 834 if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) { 835 /* 836 * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for 837 * TLBI maintenance insns does *not* apply to the nXS variant. 838 */ 839 trapbit = 0; 840 } else { 841 trapbit = extract64(trapword, bitpos, 1); 842 } 843 if (trapbit != rev) { 844 res = CP_ACCESS_TRAP_EL2; 845 goto fail; 846 } 847 } 848 849 if (likely(res == CP_ACCESS_OK)) { 850 return ri; 851 } 852 853 fail: 854 excp = EXCP_UDEF; 855 switch (res) { 856 /* CP_ACCESS_TRAP* traps are always direct to a specified EL */ 857 case CP_ACCESS_TRAP_EL3: 858 /* 859 * If EL3 is AArch32 then there's no syndrome register; the cases 860 * where we would raise a SystemAccessTrap to AArch64 EL3 all become 861 * raising a Monitor trap exception. (Because there's no visible 862 * syndrome it doesn't matter what we pass to raise_exception().) 863 */ 864 if (!arm_el_is_aa64(env, 3)) { 865 excp = EXCP_MON_TRAP; 866 } 867 break; 868 case CP_ACCESS_TRAP_EL2: 869 case CP_ACCESS_TRAP_EL1: 870 break; 871 case CP_ACCESS_UNDEFINED: 872 /* CP_ACCESS_UNDEFINED is never direct to a specified EL */ 873 if (cpu_isar_feature(aa64_ids, cpu) && isread && 874 arm_cpreg_in_idspace(ri)) { 875 /* 876 * FEAT_IDST says this should be reported as EC_SYSTEMREGISTERTRAP, 877 * not EC_UNCATEGORIZED 878 */ 879 break; 880 } 881 syndrome = syn_uncategorized(); 882 break; 883 default: 884 g_assert_not_reached(); 885 } 886 887 target_el = res & CP_ACCESS_EL_MASK; 888 switch (target_el) { 889 case 0: 890 target_el = exception_target_el(env); 891 break; 892 case 1: 893 assert(arm_current_el(env) < 2); 894 break; 895 case 2: 896 assert(arm_current_el(env) != 3); 897 assert(arm_is_el2_enabled(env)); 898 break; 899 case 3: 900 assert(arm_feature(env, ARM_FEATURE_EL3)); 901 break; 902 default: 903 g_assert_not_reached(); 904 } 905 906 raise_exception(env, excp, syndrome, target_el); 907 } 908 909 const void *HELPER(lookup_cp_reg)(CPUARMState *env, uint32_t key) 910 { 911 ARMCPU *cpu = env_archcpu(env); 912 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key); 913 914 assert(ri != NULL); 915 return ri; 916 } 917 918 /* 919 * Test for HCR_EL2.TIDCP at EL1. 920 * Since implementation defined registers are rare, and within QEMU 921 * most of them are no-op, do not waste HFLAGS space for this and 922 * always use a helper. 923 */ 924 void HELPER(tidcp_el1)(CPUARMState *env, uint32_t syndrome) 925 { 926 if (arm_hcr_el2_eff(env) & HCR_TIDCP) { 927 raise_exception_ra(env, EXCP_UDEF, syndrome, 2, GETPC()); 928 } 929 } 930 931 /* 932 * Similarly, for FEAT_TIDCP1 at EL0. 933 * We have already checked for the presence of the feature. 934 */ 935 void HELPER(tidcp_el0)(CPUARMState *env, uint32_t syndrome) 936 { 937 /* See arm_sctlr(), but we also need the sctlr el. */ 938 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); 939 int target_el; 940 941 switch (mmu_idx) { 942 case ARMMMUIdx_E20_0: 943 target_el = 2; 944 break; 945 case ARMMMUIdx_E30_0: 946 target_el = 3; 947 break; 948 default: 949 target_el = 1; 950 break; 951 } 952 953 /* 954 * The bit is not valid unless the target el is aa64, but since the 955 * bit test is simpler perform that first and check validity after. 956 */ 957 if ((env->cp15.sctlr_el[target_el] & SCTLR_TIDCP) 958 && arm_el_is_aa64(env, target_el)) { 959 raise_exception_ra(env, EXCP_UDEF, syndrome, target_el, GETPC()); 960 } 961 } 962 963 void HELPER(set_cp_reg)(CPUARMState *env, const void *rip, uint32_t value) 964 { 965 const ARMCPRegInfo *ri = rip; 966 967 if (ri->type & ARM_CP_IO) { 968 bql_lock(); 969 ri->writefn(env, ri, value); 970 bql_unlock(); 971 } else { 972 ri->writefn(env, ri, value); 973 } 974 } 975 976 uint32_t HELPER(get_cp_reg)(CPUARMState *env, const void *rip) 977 { 978 const ARMCPRegInfo *ri = rip; 979 uint32_t res; 980 981 if (ri->type & ARM_CP_IO) { 982 bql_lock(); 983 res = ri->readfn(env, ri); 984 bql_unlock(); 985 } else { 986 res = ri->readfn(env, ri); 987 } 988 989 return res; 990 } 991 992 void HELPER(set_cp_reg64)(CPUARMState *env, const void *rip, uint64_t value) 993 { 994 const ARMCPRegInfo *ri = rip; 995 996 if (ri->type & ARM_CP_IO) { 997 bql_lock(); 998 ri->writefn(env, ri, value); 999 bql_unlock(); 1000 } else { 1001 ri->writefn(env, ri, value); 1002 } 1003 } 1004 1005 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, const void *rip) 1006 { 1007 const ARMCPRegInfo *ri = rip; 1008 uint64_t res; 1009 1010 if (ri->type & ARM_CP_IO) { 1011 bql_lock(); 1012 res = ri->readfn(env, ri); 1013 bql_unlock(); 1014 } else { 1015 res = ri->readfn(env, ri); 1016 } 1017 1018 return res; 1019 } 1020 1021 void HELPER(pre_hvc)(CPUARMState *env) 1022 { 1023 ARMCPU *cpu = env_archcpu(env); 1024 int cur_el = arm_current_el(env); 1025 /* FIXME: Use actual secure state. */ 1026 bool secure = false; 1027 bool undef; 1028 1029 if (arm_is_psci_call(cpu, EXCP_HVC)) { 1030 /* If PSCI is enabled and this looks like a valid PSCI call then 1031 * that overrides the architecturally mandated HVC behaviour. 1032 */ 1033 return; 1034 } 1035 1036 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1037 /* If EL2 doesn't exist, HVC always UNDEFs */ 1038 undef = true; 1039 } else if (arm_feature(env, ARM_FEATURE_EL3)) { 1040 /* EL3.HCE has priority over EL2.HCD. */ 1041 undef = !(env->cp15.scr_el3 & SCR_HCE); 1042 } else { 1043 undef = env->cp15.hcr_el2 & HCR_HCD; 1044 } 1045 1046 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state. 1047 * For ARMv8/AArch64, HVC is allowed in EL3. 1048 * Note that we've already trapped HVC from EL0 at translation 1049 * time. 1050 */ 1051 if (secure && (!is_a64(env) || cur_el == 1)) { 1052 undef = true; 1053 } 1054 1055 if (undef) { 1056 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 1057 exception_target_el(env)); 1058 } 1059 } 1060 1061 void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) 1062 { 1063 ARMCPU *cpu = env_archcpu(env); 1064 int cur_el = arm_current_el(env); 1065 bool secure = arm_is_secure(env); 1066 bool smd_flag = env->cp15.scr_el3 & SCR_SMD; 1067 1068 /* 1069 * SMC behaviour is summarized in the following table. 1070 * This helper handles the "Trap to EL2" and "Undef insn" cases. 1071 * The "Trap to EL3" and "PSCI call" cases are handled in the exception 1072 * helper. 1073 * 1074 * -> ARM_FEATURE_EL3 and !SMD 1075 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 1076 * 1077 * Conduit SMC, valid call Trap to EL2 PSCI Call 1078 * Conduit SMC, inval call Trap to EL2 Trap to EL3 1079 * Conduit not SMC Trap to EL2 Trap to EL3 1080 * 1081 * 1082 * -> ARM_FEATURE_EL3 and SMD 1083 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 1084 * 1085 * Conduit SMC, valid call Trap to EL2 PSCI Call 1086 * Conduit SMC, inval call Trap to EL2 Undef insn 1087 * Conduit not SMC Trap to EL2 Undef insn 1088 * 1089 * 1090 * -> !ARM_FEATURE_EL3 1091 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 1092 * 1093 * Conduit SMC, valid call Trap to EL2 PSCI Call 1094 * Conduit SMC, inval call Trap to EL2 Undef insn 1095 * Conduit not SMC Undef or trap[1] Undef insn 1096 * 1097 * [1] In this case: 1098 * - if HCR_EL2.NV == 1 we must trap to EL2 1099 * - if HCR_EL2.NV == 0 then newer architecture revisions permit 1100 * AArch64 (but not AArch32) to trap to EL2 as an IMPDEF choice 1101 * - otherwise we must UNDEF 1102 * We take the IMPDEF choice to always UNDEF if HCR_EL2.NV == 0. 1103 */ 1104 1105 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state. 1106 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization 1107 * extensions, SMD only applies to NS state. 1108 * On ARMv7 without the Virtualization extensions, the SMD bit 1109 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(), 1110 * so we need not special case this here. 1111 */ 1112 bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag 1113 : smd_flag && !secure; 1114 1115 if (!arm_feature(env, ARM_FEATURE_EL3) && 1116 !(arm_hcr_el2_eff(env) & HCR_NV) && 1117 cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { 1118 /* 1119 * If we have no EL3 then traditionally SMC always UNDEFs and can't be 1120 * trapped to EL2. For nested virtualization, SMC can be trapped to 1121 * the outer hypervisor. PSCI-via-SMC is a sort of ersatz EL3 1122 * firmware within QEMU, and we want an EL2 guest to be able 1123 * to forbid its EL1 from making PSCI calls into QEMU's 1124 * "firmware" via HCR.TSC, so for these purposes treat 1125 * PSCI-via-SMC as implying an EL3. 1126 * This handles the very last line of the previous table. 1127 */ 1128 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 1129 exception_target_el(env)); 1130 } 1131 1132 if (cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) { 1133 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. 1134 * We also want an EL2 guest to be able to forbid its EL1 from 1135 * making PSCI calls into QEMU's "firmware" via HCR.TSC. 1136 * This handles all the "Trap to EL2" cases of the previous table. 1137 */ 1138 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); 1139 } 1140 1141 /* Catch the two remaining "Undef insn" cases of the previous table: 1142 * - PSCI conduit is SMC but we don't have a valid PCSI call, 1143 * - We don't have EL3 or SMD is set. 1144 */ 1145 if (!arm_is_psci_call(cpu, EXCP_SMC) && 1146 (smd || !arm_feature(env, ARM_FEATURE_EL3))) { 1147 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 1148 exception_target_el(env)); 1149 } 1150 } 1151 1152 /* ??? Flag setting arithmetic is awkward because we need to do comparisons. 1153 The only way to do that in TCG is a conditional branch, which clobbers 1154 all our temporaries. For now implement these as helper functions. */ 1155 1156 /* Similarly for variable shift instructions. */ 1157 1158 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i) 1159 { 1160 int shift = i & 0xff; 1161 if (shift >= 32) { 1162 if (shift == 32) 1163 env->CF = x & 1; 1164 else 1165 env->CF = 0; 1166 return 0; 1167 } else if (shift != 0) { 1168 env->CF = (x >> (32 - shift)) & 1; 1169 return x << shift; 1170 } 1171 return x; 1172 } 1173 1174 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i) 1175 { 1176 int shift = i & 0xff; 1177 if (shift >= 32) { 1178 if (shift == 32) 1179 env->CF = (x >> 31) & 1; 1180 else 1181 env->CF = 0; 1182 return 0; 1183 } else if (shift != 0) { 1184 env->CF = (x >> (shift - 1)) & 1; 1185 return x >> shift; 1186 } 1187 return x; 1188 } 1189 1190 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i) 1191 { 1192 int shift = i & 0xff; 1193 if (shift >= 32) { 1194 env->CF = (x >> 31) & 1; 1195 return (int32_t)x >> 31; 1196 } else if (shift != 0) { 1197 env->CF = (x >> (shift - 1)) & 1; 1198 return (int32_t)x >> shift; 1199 } 1200 return x; 1201 } 1202 1203 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) 1204 { 1205 int shift1, shift; 1206 shift1 = i & 0xff; 1207 shift = shift1 & 0x1f; 1208 if (shift == 0) { 1209 if (shift1 != 0) 1210 env->CF = (x >> 31) & 1; 1211 return x; 1212 } else { 1213 env->CF = (x >> (shift - 1)) & 1; 1214 return ((uint32_t)x >> shift) | (x << (32 - shift)); 1215 } 1216 } 1217 1218 void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, 1219 uint32_t access_type, uint32_t mmu_idx, 1220 uint32_t size) 1221 { 1222 uint32_t in_page = -((uint32_t)ptr | TARGET_PAGE_SIZE); 1223 uintptr_t ra = GETPC(); 1224 1225 if (likely(size <= in_page)) { 1226 probe_access(env, ptr, size, access_type, mmu_idx, ra); 1227 } else { 1228 probe_access(env, ptr, in_page, access_type, mmu_idx, ra); 1229 probe_access(env, ptr + in_page, size - in_page, 1230 access_type, mmu_idx, ra); 1231 } 1232 } 1233 1234 /* 1235 * This function corresponds to AArch64.vESBOperation(). 1236 * Note that the AArch32 version is not functionally different. 1237 */ 1238 void HELPER(vesb)(CPUARMState *env) 1239 { 1240 /* 1241 * The EL2Enabled() check is done inside arm_hcr_el2_eff, 1242 * and will return HCR_EL2.VSE == 0, so nothing happens. 1243 */ 1244 uint64_t hcr = arm_hcr_el2_eff(env); 1245 bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO); 1246 bool pending = enabled && (hcr & HCR_VSE); 1247 bool masked = (env->daif & PSTATE_A); 1248 1249 /* If VSE pending and masked, defer the exception. */ 1250 if (pending && masked) { 1251 uint32_t syndrome; 1252 1253 if (arm_el_is_aa64(env, 1)) { 1254 /* Copy across IDS and ISS from VSESR. */ 1255 syndrome = env->cp15.vsesr_el2 & 0x1ffffff; 1256 } else { 1257 ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal }; 1258 1259 if (extended_addresses_enabled(env)) { 1260 syndrome = arm_fi_to_lfsc(&fi); 1261 } else { 1262 syndrome = arm_fi_to_sfsc(&fi); 1263 } 1264 /* Copy across AET and ExT from VSESR. */ 1265 syndrome |= env->cp15.vsesr_el2 & 0xd000; 1266 } 1267 1268 /* Set VDISR_EL2.A along with the syndrome. */ 1269 env->cp15.vdisr_el2 = syndrome | (1u << 31); 1270 1271 /* Clear pending virtual SError */ 1272 env->cp15.hcr_el2 &= ~HCR_VSE; 1273 cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); 1274 } 1275 } 1276