1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/exec-all.h" 27 #include "tcg/tcg.h" 28 29 static uint16_t mve_eci_mask(CPUARMState *env) 30 { 31 /* 32 * Return the mask of which elements in the MVE vector correspond 33 * to beats being executed. The mask has 1 bits for executed lanes 34 * and 0 bits where ECI says this beat was already executed. 35 */ 36 int eci; 37 38 if ((env->condexec_bits & 0xf) != 0) { 39 return 0xffff; 40 } 41 42 eci = env->condexec_bits >> 4; 43 switch (eci) { 44 case ECI_NONE: 45 return 0xffff; 46 case ECI_A0: 47 return 0xfff0; 48 case ECI_A0A1: 49 return 0xff00; 50 case ECI_A0A1A2: 51 case ECI_A0A1A2B0: 52 return 0xf000; 53 default: 54 g_assert_not_reached(); 55 } 56 } 57 58 static uint16_t mve_element_mask(CPUARMState *env) 59 { 60 /* 61 * Return the mask of which elements in the MVE vector should be 62 * updated. This is a combination of multiple things: 63 * (1) by default, we update every lane in the vector 64 * (2) VPT predication stores its state in the VPR register; 65 * (3) low-overhead-branch tail predication will mask out part 66 * the vector on the final iteration of the loop 67 * (4) if EPSR.ECI is set then we must execute only some beats 68 * of the insn 69 * We combine all these into a 16-bit result with the same semantics 70 * as VPR.P0: 0 to mask the lane, 1 if it is active. 71 * 8-bit vector ops will look at all bits of the result; 72 * 16-bit ops will look at bits 0, 2, 4, ...; 73 * 32-bit ops will look at bits 0, 4, 8 and 12. 74 * Compare pseudocode GetCurInstrBeat(), though that only returns 75 * the 4-bit slice of the mask corresponding to a single beat. 76 */ 77 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 78 79 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 80 mask |= 0xff; 81 } 82 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 83 mask |= 0xff00; 84 } 85 86 if (env->v7m.ltpsize < 4 && 87 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 88 /* 89 * Tail predication active, and this is the last loop iteration. 90 * The element size is (1 << ltpsize), and we only want to process 91 * loopcount elements, so we want to retain the least significant 92 * (loopcount * esize) predicate bits and zero out bits above that. 93 */ 94 int masklen = env->regs[14] << env->v7m.ltpsize; 95 assert(masklen <= 16); 96 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 97 mask &= ltpmask; 98 } 99 100 /* 101 * ECI bits indicate which beats are already executed; 102 * we handle this by effectively predicating them out. 103 */ 104 mask &= mve_eci_mask(env); 105 return mask; 106 } 107 108 static void mve_advance_vpt(CPUARMState *env) 109 { 110 /* Advance the VPT and ECI state if necessary */ 111 uint32_t vpr = env->v7m.vpr; 112 unsigned mask01, mask23; 113 uint16_t inv_mask; 114 uint16_t eci_mask = mve_eci_mask(env); 115 116 if ((env->condexec_bits & 0xf) == 0) { 117 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 118 (ECI_A0 << 4) : (ECI_NONE << 4); 119 } 120 121 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 122 /* VPT not enabled, nothing to do */ 123 return; 124 } 125 126 /* Invert P0 bits if needed, but only for beats we actually executed */ 127 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 128 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 129 /* Start by assuming we invert all bits corresponding to executed beats */ 130 inv_mask = eci_mask; 131 if (mask01 <= 8) { 132 /* MASK01 says don't invert low half of P0 */ 133 inv_mask &= ~0xff; 134 } 135 if (mask23 <= 8) { 136 /* MASK23 says don't invert high half of P0 */ 137 inv_mask &= ~0xff00; 138 } 139 vpr ^= inv_mask; 140 /* Only update MASK01 if beat 1 executed */ 141 if (eci_mask & 0xf0) { 142 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 143 } 144 /* Beat 3 always executes, so update MASK23 */ 145 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 146 env->v7m.vpr = vpr; 147 } 148 149 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 150 #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ 151 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 152 { \ 153 TYPE *d = vd; \ 154 uint16_t mask = mve_element_mask(env); \ 155 uint16_t eci_mask = mve_eci_mask(env); \ 156 unsigned b, e; \ 157 /* \ 158 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 159 * beats so we don't care if we update part of the dest and \ 160 * then take an exception. \ 161 */ \ 162 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 163 if (eci_mask & (1 << b)) { \ 164 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 165 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 166 } \ 167 addr += MSIZE; \ 168 } \ 169 mve_advance_vpt(env); \ 170 } 171 172 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ 173 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 174 { \ 175 TYPE *d = vd; \ 176 uint16_t mask = mve_element_mask(env); \ 177 unsigned b, e; \ 178 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 179 if (mask & (1 << b)) { \ 180 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 181 } \ 182 addr += MSIZE; \ 183 } \ 184 mve_advance_vpt(env); \ 185 } 186 187 DO_VLDR(vldrb, 1, ldub, 1, uint8_t) 188 DO_VLDR(vldrh, 2, lduw, 2, uint16_t) 189 DO_VLDR(vldrw, 4, ldl, 4, uint32_t) 190 191 DO_VSTR(vstrb, 1, stb, 1, uint8_t) 192 DO_VSTR(vstrh, 2, stw, 2, uint16_t) 193 DO_VSTR(vstrw, 4, stl, 4, uint32_t) 194 195 DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t) 196 DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t) 197 DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t) 198 DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t) 199 DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t) 200 DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t) 201 202 DO_VSTR(vstrb_h, 1, stb, 2, int16_t) 203 DO_VSTR(vstrb_w, 1, stb, 4, int32_t) 204 DO_VSTR(vstrh_w, 2, stw, 4, int32_t) 205 206 #undef DO_VLDR 207 #undef DO_VSTR 208 209 /* 210 * Gather loads/scatter stores. Here each element of Qm specifies 211 * an offset to use from the base register Rm. In the _os_ versions 212 * that offset is scaled by the element size. 213 * For loads, predicated lanes are zeroed instead of retaining 214 * their previous values. 215 */ 216 #define DO_VLDR_SG(OP, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN, WB) \ 217 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 218 uint32_t base) \ 219 { \ 220 TYPE *d = vd; \ 221 OFFTYPE *m = vm; \ 222 uint16_t mask = mve_element_mask(env); \ 223 uint16_t eci_mask = mve_eci_mask(env); \ 224 unsigned e; \ 225 uint32_t addr; \ 226 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 227 if (!(eci_mask & 1)) { \ 228 continue; \ 229 } \ 230 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 231 d[H##ESIZE(e)] = (mask & 1) ? \ 232 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 233 if (WB) { \ 234 m[H##ESIZE(e)] = addr; \ 235 } \ 236 } \ 237 mve_advance_vpt(env); \ 238 } 239 240 /* We know here TYPE is unsigned so always the same as the offset type */ 241 #define DO_VSTR_SG(OP, STTYPE, ESIZE, TYPE, ADDRFN, WB) \ 242 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 243 uint32_t base) \ 244 { \ 245 TYPE *d = vd; \ 246 TYPE *m = vm; \ 247 uint16_t mask = mve_element_mask(env); \ 248 uint16_t eci_mask = mve_eci_mask(env); \ 249 unsigned e; \ 250 uint32_t addr; \ 251 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 252 if (!(eci_mask & 1)) { \ 253 continue; \ 254 } \ 255 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 256 if (mask & 1) { \ 257 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 258 } \ 259 if (WB) { \ 260 m[H##ESIZE(e)] = addr; \ 261 } \ 262 } \ 263 mve_advance_vpt(env); \ 264 } 265 266 /* 267 * 64-bit accesses are slightly different: they are done as two 32-bit 268 * accesses, controlled by the predicate mask for the relevant beat, 269 * and with a single 32-bit offset in the first of the two Qm elements. 270 * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little). 271 * Address writeback happens on the odd beats and updates the address 272 * stored in the even-beat element. 273 */ 274 #define DO_VLDR64_SG(OP, ADDRFN, WB) \ 275 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 276 uint32_t base) \ 277 { \ 278 uint32_t *d = vd; \ 279 uint32_t *m = vm; \ 280 uint16_t mask = mve_element_mask(env); \ 281 uint16_t eci_mask = mve_eci_mask(env); \ 282 unsigned e; \ 283 uint32_t addr; \ 284 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 285 if (!(eci_mask & 1)) { \ 286 continue; \ 287 } \ 288 addr = ADDRFN(base, m[H4(e & ~1)]); \ 289 addr += 4 * (e & 1); \ 290 d[H4(e)] = (mask & 1) ? cpu_ldl_data_ra(env, addr, GETPC()) : 0; \ 291 if (WB && (e & 1)) { \ 292 m[H4(e & ~1)] = addr - 4; \ 293 } \ 294 } \ 295 mve_advance_vpt(env); \ 296 } 297 298 #define DO_VSTR64_SG(OP, ADDRFN, WB) \ 299 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 300 uint32_t base) \ 301 { \ 302 uint32_t *d = vd; \ 303 uint32_t *m = vm; \ 304 uint16_t mask = mve_element_mask(env); \ 305 uint16_t eci_mask = mve_eci_mask(env); \ 306 unsigned e; \ 307 uint32_t addr; \ 308 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 309 if (!(eci_mask & 1)) { \ 310 continue; \ 311 } \ 312 addr = ADDRFN(base, m[H4(e & ~1)]); \ 313 addr += 4 * (e & 1); \ 314 if (mask & 1) { \ 315 cpu_stl_data_ra(env, addr, d[H4(e)], GETPC()); \ 316 } \ 317 if (WB && (e & 1)) { \ 318 m[H4(e & ~1)] = addr - 4; \ 319 } \ 320 } \ 321 mve_advance_vpt(env); \ 322 } 323 324 #define ADDR_ADD(BASE, OFFSET) ((BASE) + (OFFSET)) 325 #define ADDR_ADD_OSH(BASE, OFFSET) ((BASE) + ((OFFSET) << 1)) 326 #define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2)) 327 #define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3)) 328 329 DO_VLDR_SG(vldrb_sg_sh, ldsb, 2, int16_t, uint16_t, ADDR_ADD, false) 330 DO_VLDR_SG(vldrb_sg_sw, ldsb, 4, int32_t, uint32_t, ADDR_ADD, false) 331 DO_VLDR_SG(vldrh_sg_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD, false) 332 333 DO_VLDR_SG(vldrb_sg_ub, ldub, 1, uint8_t, uint8_t, ADDR_ADD, false) 334 DO_VLDR_SG(vldrb_sg_uh, ldub, 2, uint16_t, uint16_t, ADDR_ADD, false) 335 DO_VLDR_SG(vldrb_sg_uw, ldub, 4, uint32_t, uint32_t, ADDR_ADD, false) 336 DO_VLDR_SG(vldrh_sg_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD, false) 337 DO_VLDR_SG(vldrh_sg_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD, false) 338 DO_VLDR_SG(vldrw_sg_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false) 339 DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) 340 341 DO_VLDR_SG(vldrh_sg_os_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD_OSH, false) 342 DO_VLDR_SG(vldrh_sg_os_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD_OSH, false) 343 DO_VLDR_SG(vldrh_sg_os_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD_OSH, false) 344 DO_VLDR_SG(vldrw_sg_os_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW, false) 345 DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) 346 347 DO_VSTR_SG(vstrb_sg_ub, stb, 1, uint8_t, ADDR_ADD, false) 348 DO_VSTR_SG(vstrb_sg_uh, stb, 2, uint16_t, ADDR_ADD, false) 349 DO_VSTR_SG(vstrb_sg_uw, stb, 4, uint32_t, ADDR_ADD, false) 350 DO_VSTR_SG(vstrh_sg_uh, stw, 2, uint16_t, ADDR_ADD, false) 351 DO_VSTR_SG(vstrh_sg_uw, stw, 4, uint32_t, ADDR_ADD, false) 352 DO_VSTR_SG(vstrw_sg_uw, stl, 4, uint32_t, ADDR_ADD, false) 353 DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) 354 355 DO_VSTR_SG(vstrh_sg_os_uh, stw, 2, uint16_t, ADDR_ADD_OSH, false) 356 DO_VSTR_SG(vstrh_sg_os_uw, stw, 4, uint32_t, ADDR_ADD_OSH, false) 357 DO_VSTR_SG(vstrw_sg_os_uw, stl, 4, uint32_t, ADDR_ADD_OSW, false) 358 DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) 359 360 DO_VLDR_SG(vldrw_sg_wb_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true) 361 DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) 362 DO_VSTR_SG(vstrw_sg_wb_uw, stl, 4, uint32_t, ADDR_ADD, true) 363 DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) 364 365 /* 366 * The mergemask(D, R, M) macro performs the operation "*D = R" but 367 * storing only the bytes which correspond to 1 bits in M, 368 * leaving other bytes in *D unchanged. We use _Generic 369 * to select the correct implementation based on the type of D. 370 */ 371 372 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 373 { 374 if (mask & 1) { 375 *d = r; 376 } 377 } 378 379 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 380 { 381 mergemask_ub((uint8_t *)d, r, mask); 382 } 383 384 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 385 { 386 uint16_t bmask = expand_pred_b_data[mask & 3]; 387 *d = (*d & ~bmask) | (r & bmask); 388 } 389 390 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 391 { 392 mergemask_uh((uint16_t *)d, r, mask); 393 } 394 395 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 396 { 397 uint32_t bmask = expand_pred_b_data[mask & 0xf]; 398 *d = (*d & ~bmask) | (r & bmask); 399 } 400 401 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 402 { 403 mergemask_uw((uint32_t *)d, r, mask); 404 } 405 406 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 407 { 408 uint64_t bmask = expand_pred_b_data[mask & 0xff]; 409 *d = (*d & ~bmask) | (r & bmask); 410 } 411 412 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 413 { 414 mergemask_uq((uint64_t *)d, r, mask); 415 } 416 417 #define mergemask(D, R, M) \ 418 _Generic(D, \ 419 uint8_t *: mergemask_ub, \ 420 int8_t *: mergemask_sb, \ 421 uint16_t *: mergemask_uh, \ 422 int16_t *: mergemask_sh, \ 423 uint32_t *: mergemask_uw, \ 424 int32_t *: mergemask_sw, \ 425 uint64_t *: mergemask_uq, \ 426 int64_t *: mergemask_sq)(D, R, M) 427 428 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 429 { 430 /* 431 * The generated code already replicated an 8 or 16 bit constant 432 * into the 32-bit value, so we only need to write the 32-bit 433 * value to all elements of the Qreg, allowing for predication. 434 */ 435 uint32_t *d = vd; 436 uint16_t mask = mve_element_mask(env); 437 unsigned e; 438 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 439 mergemask(&d[H4(e)], val, mask); 440 } 441 mve_advance_vpt(env); 442 } 443 444 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 445 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 446 { \ 447 TYPE *d = vd, *m = vm; \ 448 uint16_t mask = mve_element_mask(env); \ 449 unsigned e; \ 450 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 451 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 452 } \ 453 mve_advance_vpt(env); \ 454 } 455 456 #define DO_CLS_B(N) (clrsb32(N) - 24) 457 #define DO_CLS_H(N) (clrsb32(N) - 16) 458 459 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 460 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 461 DO_1OP(vclsw, 4, int32_t, clrsb32) 462 463 #define DO_CLZ_B(N) (clz32(N) - 24) 464 #define DO_CLZ_H(N) (clz32(N) - 16) 465 466 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 467 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 468 DO_1OP(vclzw, 4, uint32_t, clz32) 469 470 DO_1OP(vrev16b, 2, uint16_t, bswap16) 471 DO_1OP(vrev32b, 4, uint32_t, bswap32) 472 DO_1OP(vrev32h, 4, uint32_t, hswap32) 473 DO_1OP(vrev64b, 8, uint64_t, bswap64) 474 DO_1OP(vrev64h, 8, uint64_t, hswap64) 475 DO_1OP(vrev64w, 8, uint64_t, wswap64) 476 477 #define DO_NOT(N) (~(N)) 478 479 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 480 481 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 482 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 483 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 484 485 DO_1OP(vabsb, 1, int8_t, DO_ABS) 486 DO_1OP(vabsh, 2, int16_t, DO_ABS) 487 DO_1OP(vabsw, 4, int32_t, DO_ABS) 488 489 /* We can do these 64 bits at a time */ 490 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 491 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 492 493 #define DO_NEG(N) (-(N)) 494 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 495 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 496 497 DO_1OP(vnegb, 1, int8_t, DO_NEG) 498 DO_1OP(vnegh, 2, int16_t, DO_NEG) 499 DO_1OP(vnegw, 4, int32_t, DO_NEG) 500 501 /* We can do these 64 bits at a time */ 502 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 503 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 504 505 /* 506 * 1 operand immediates: Vda is destination and possibly also one source. 507 * All these insns work at 64-bit widths. 508 */ 509 #define DO_1OP_IMM(OP, FN) \ 510 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 511 { \ 512 uint64_t *da = vda; \ 513 uint16_t mask = mve_element_mask(env); \ 514 unsigned e; \ 515 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 516 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 517 } \ 518 mve_advance_vpt(env); \ 519 } 520 521 #define DO_MOVI(N, I) (I) 522 #define DO_ANDI(N, I) ((N) & (I)) 523 #define DO_ORRI(N, I) ((N) | (I)) 524 525 DO_1OP_IMM(vmovi, DO_MOVI) 526 DO_1OP_IMM(vandi, DO_ANDI) 527 DO_1OP_IMM(vorri, DO_ORRI) 528 529 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 530 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 531 void *vd, void *vn, void *vm) \ 532 { \ 533 TYPE *d = vd, *n = vn, *m = vm; \ 534 uint16_t mask = mve_element_mask(env); \ 535 unsigned e; \ 536 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 537 mergemask(&d[H##ESIZE(e)], \ 538 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 539 } \ 540 mve_advance_vpt(env); \ 541 } 542 543 /* provide unsigned 2-op helpers for all sizes */ 544 #define DO_2OP_U(OP, FN) \ 545 DO_2OP(OP##b, 1, uint8_t, FN) \ 546 DO_2OP(OP##h, 2, uint16_t, FN) \ 547 DO_2OP(OP##w, 4, uint32_t, FN) 548 549 /* provide signed 2-op helpers for all sizes */ 550 #define DO_2OP_S(OP, FN) \ 551 DO_2OP(OP##b, 1, int8_t, FN) \ 552 DO_2OP(OP##h, 2, int16_t, FN) \ 553 DO_2OP(OP##w, 4, int32_t, FN) 554 555 /* 556 * "Long" operations where two half-sized inputs (taken from either the 557 * top or the bottom of the input vector) produce a double-width result. 558 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 559 */ 560 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 561 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 562 { \ 563 LTYPE *d = vd; \ 564 TYPE *n = vn, *m = vm; \ 565 uint16_t mask = mve_element_mask(env); \ 566 unsigned le; \ 567 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 568 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 569 m[H##ESIZE(le * 2 + TOP)]); \ 570 mergemask(&d[H##LESIZE(le)], r, mask); \ 571 } \ 572 mve_advance_vpt(env); \ 573 } 574 575 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 576 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 577 { \ 578 TYPE *d = vd, *n = vn, *m = vm; \ 579 uint16_t mask = mve_element_mask(env); \ 580 unsigned e; \ 581 bool qc = false; \ 582 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 583 bool sat = false; \ 584 TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 585 mergemask(&d[H##ESIZE(e)], r, mask); \ 586 qc |= sat & mask & 1; \ 587 } \ 588 if (qc) { \ 589 env->vfp.qc[0] = qc; \ 590 } \ 591 mve_advance_vpt(env); \ 592 } 593 594 /* provide unsigned 2-op helpers for all sizes */ 595 #define DO_2OP_SAT_U(OP, FN) \ 596 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 597 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 598 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 599 600 /* provide signed 2-op helpers for all sizes */ 601 #define DO_2OP_SAT_S(OP, FN) \ 602 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 603 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 604 DO_2OP_SAT(OP##w, 4, int32_t, FN) 605 606 #define DO_AND(N, M) ((N) & (M)) 607 #define DO_BIC(N, M) ((N) & ~(M)) 608 #define DO_ORR(N, M) ((N) | (M)) 609 #define DO_ORN(N, M) ((N) | ~(M)) 610 #define DO_EOR(N, M) ((N) ^ (M)) 611 612 DO_2OP(vand, 8, uint64_t, DO_AND) 613 DO_2OP(vbic, 8, uint64_t, DO_BIC) 614 DO_2OP(vorr, 8, uint64_t, DO_ORR) 615 DO_2OP(vorn, 8, uint64_t, DO_ORN) 616 DO_2OP(veor, 8, uint64_t, DO_EOR) 617 618 #define DO_ADD(N, M) ((N) + (M)) 619 #define DO_SUB(N, M) ((N) - (M)) 620 #define DO_MUL(N, M) ((N) * (M)) 621 622 DO_2OP_U(vadd, DO_ADD) 623 DO_2OP_U(vsub, DO_SUB) 624 DO_2OP_U(vmul, DO_MUL) 625 626 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 627 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 628 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 629 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 630 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 631 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 632 633 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 634 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 635 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 636 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 637 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 638 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 639 640 /* 641 * Polynomial multiply. We can always do this generating 64 bits 642 * of the result at a time, so we don't need to use DO_2OP_L. 643 */ 644 #define VMULLPH_MASK 0x00ff00ff00ff00ffULL 645 #define VMULLPW_MASK 0x0000ffff0000ffffULL 646 #define DO_VMULLPBH(N, M) pmull_h((N) & VMULLPH_MASK, (M) & VMULLPH_MASK) 647 #define DO_VMULLPTH(N, M) DO_VMULLPBH((N) >> 8, (M) >> 8) 648 #define DO_VMULLPBW(N, M) pmull_w((N) & VMULLPW_MASK, (M) & VMULLPW_MASK) 649 #define DO_VMULLPTW(N, M) DO_VMULLPBW((N) >> 16, (M) >> 16) 650 651 DO_2OP(vmullpbh, 8, uint64_t, DO_VMULLPBH) 652 DO_2OP(vmullpth, 8, uint64_t, DO_VMULLPTH) 653 DO_2OP(vmullpbw, 8, uint64_t, DO_VMULLPBW) 654 DO_2OP(vmullptw, 8, uint64_t, DO_VMULLPTW) 655 656 /* 657 * Because the computation type is at least twice as large as required, 658 * these work for both signed and unsigned source types. 659 */ 660 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 661 { 662 return (n * m) >> 8; 663 } 664 665 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 666 { 667 return (n * m) >> 16; 668 } 669 670 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 671 { 672 return (n * m) >> 32; 673 } 674 675 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 676 { 677 return (n * m + (1U << 7)) >> 8; 678 } 679 680 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 681 { 682 return (n * m + (1U << 15)) >> 16; 683 } 684 685 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 686 { 687 return (n * m + (1U << 31)) >> 32; 688 } 689 690 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 691 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 692 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 693 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 694 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 695 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 696 697 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 698 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 699 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 700 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 701 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 702 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 703 704 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 705 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 706 707 DO_2OP_S(vmaxs, DO_MAX) 708 DO_2OP_U(vmaxu, DO_MAX) 709 DO_2OP_S(vmins, DO_MIN) 710 DO_2OP_U(vminu, DO_MIN) 711 712 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 713 714 DO_2OP_S(vabds, DO_ABD) 715 DO_2OP_U(vabdu, DO_ABD) 716 717 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 718 { 719 return ((uint64_t)n + m) >> 1; 720 } 721 722 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 723 { 724 return ((int64_t)n + m) >> 1; 725 } 726 727 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 728 { 729 return ((uint64_t)n - m) >> 1; 730 } 731 732 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 733 { 734 return ((int64_t)n - m) >> 1; 735 } 736 737 DO_2OP_S(vhadds, do_vhadd_s) 738 DO_2OP_U(vhaddu, do_vhadd_u) 739 DO_2OP_S(vhsubs, do_vhsub_s) 740 DO_2OP_U(vhsubu, do_vhsub_u) 741 742 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 743 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 744 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 745 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 746 747 DO_2OP_S(vshls, DO_VSHLS) 748 DO_2OP_U(vshlu, DO_VSHLU) 749 DO_2OP_S(vrshls, DO_VRSHLS) 750 DO_2OP_U(vrshlu, DO_VRSHLU) 751 752 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 753 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 754 755 DO_2OP_S(vrhadds, DO_RHADD_S) 756 DO_2OP_U(vrhaddu, DO_RHADD_U) 757 758 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 759 uint32_t inv, uint32_t carry_in, bool update_flags) 760 { 761 uint16_t mask = mve_element_mask(env); 762 unsigned e; 763 764 /* If any additions trigger, we will update flags. */ 765 if (mask & 0x1111) { 766 update_flags = true; 767 } 768 769 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 770 uint64_t r = carry_in; 771 r += n[H4(e)]; 772 r += m[H4(e)] ^ inv; 773 if (mask & 1) { 774 carry_in = r >> 32; 775 } 776 mergemask(&d[H4(e)], r, mask); 777 } 778 779 if (update_flags) { 780 /* Store C, clear NZV. */ 781 env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK; 782 env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C; 783 } 784 mve_advance_vpt(env); 785 } 786 787 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 788 { 789 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 790 do_vadc(env, vd, vn, vm, 0, carry_in, false); 791 } 792 793 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 794 { 795 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 796 do_vadc(env, vd, vn, vm, -1, carry_in, false); 797 } 798 799 800 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 801 { 802 do_vadc(env, vd, vn, vm, 0, 0, true); 803 } 804 805 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 806 { 807 do_vadc(env, vd, vn, vm, -1, 1, true); 808 } 809 810 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 811 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 812 { \ 813 TYPE *d = vd, *n = vn, *m = vm; \ 814 uint16_t mask = mve_element_mask(env); \ 815 unsigned e; \ 816 TYPE r[16 / ESIZE]; \ 817 /* Calculate all results first to avoid overwriting inputs */ \ 818 for (e = 0; e < 16 / ESIZE; e++) { \ 819 if (!(e & 1)) { \ 820 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 821 } else { \ 822 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 823 } \ 824 } \ 825 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 826 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 827 } \ 828 mve_advance_vpt(env); \ 829 } 830 831 #define DO_VCADD_ALL(OP, FN0, FN1) \ 832 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 833 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 834 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 835 836 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 837 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 838 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 839 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 840 841 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 842 { 843 if (val > max) { 844 *s = true; 845 return max; 846 } else if (val < min) { 847 *s = true; 848 return min; 849 } 850 return val; 851 } 852 853 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 854 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 855 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 856 857 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 858 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 859 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 860 861 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 862 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 863 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 864 865 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 866 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 867 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 868 869 /* 870 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 871 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 872 */ 873 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 874 INT8_MIN, INT8_MAX, s) 875 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 876 INT16_MIN, INT16_MAX, s) 877 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 878 INT32_MIN, INT32_MAX, s) 879 880 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 881 INT8_MIN, INT8_MAX, s) 882 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 883 INT16_MIN, INT16_MAX, s) 884 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 885 INT32_MIN, INT32_MAX, s) 886 887 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 888 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 889 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 890 891 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 892 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 893 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 894 895 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 896 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 897 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 898 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 899 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 900 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 901 902 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 903 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 904 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 905 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 906 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 907 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 908 909 /* 910 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 911 * and friends wanting a uint32_t* sat and our needing a bool*. 912 */ 913 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 914 ({ \ 915 uint32_t su32 = 0; \ 916 typeof(N) r = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 917 if (su32) { \ 918 *satp = true; \ 919 } \ 920 r; \ 921 }) 922 923 #define DO_SQSHL_OP(N, M, satp) \ 924 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 925 #define DO_UQSHL_OP(N, M, satp) \ 926 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 927 #define DO_SQRSHL_OP(N, M, satp) \ 928 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 929 #define DO_UQRSHL_OP(N, M, satp) \ 930 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 931 #define DO_SUQSHL_OP(N, M, satp) \ 932 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 933 934 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 935 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 936 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 937 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 938 939 /* 940 * Multiply add dual returning high half 941 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 942 * whether to add the rounding constant, and the pointer to the 943 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 944 * saturate to twice the input size and return the high half; or 945 * (A * B - C * D) etc for VQDMLSDH. 946 */ 947 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 948 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 949 void *vm) \ 950 { \ 951 TYPE *d = vd, *n = vn, *m = vm; \ 952 uint16_t mask = mve_element_mask(env); \ 953 unsigned e; \ 954 bool qc = false; \ 955 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 956 bool sat = false; \ 957 if ((e & 1) == XCHG) { \ 958 TYPE r = FN(n[H##ESIZE(e)], \ 959 m[H##ESIZE(e - XCHG)], \ 960 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 961 m[H##ESIZE(e + (1 - XCHG))], \ 962 ROUND, &sat); \ 963 mergemask(&d[H##ESIZE(e)], r, mask); \ 964 qc |= sat & mask & 1; \ 965 } \ 966 } \ 967 if (qc) { \ 968 env->vfp.qc[0] = qc; \ 969 } \ 970 mve_advance_vpt(env); \ 971 } 972 973 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 974 int round, bool *sat) 975 { 976 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 977 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 978 } 979 980 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 981 int round, bool *sat) 982 { 983 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 984 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 985 } 986 987 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 988 int round, bool *sat) 989 { 990 int64_t m1 = (int64_t)a * b; 991 int64_t m2 = (int64_t)c * d; 992 int64_t r; 993 /* 994 * Architecturally we should do the entire add, double, round 995 * and then check for saturation. We do three saturating adds, 996 * but we need to be careful about the order. If the first 997 * m1 + m2 saturates then it's impossible for the *2+rc to 998 * bring it back into the non-saturated range. However, if 999 * m1 + m2 is negative then it's possible that doing the doubling 1000 * would take the intermediate result below INT64_MAX and the 1001 * addition of the rounding constant then brings it back in range. 1002 * So we add half the rounding constant before doubling rather 1003 * than adding the rounding constant after the doubling. 1004 */ 1005 if (sadd64_overflow(m1, m2, &r) || 1006 sadd64_overflow(r, (round << 30), &r) || 1007 sadd64_overflow(r, r, &r)) { 1008 *sat = true; 1009 return r < 0 ? INT32_MAX : INT32_MIN; 1010 } 1011 return r >> 32; 1012 } 1013 1014 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1015 int round, bool *sat) 1016 { 1017 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 1018 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1019 } 1020 1021 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1022 int round, bool *sat) 1023 { 1024 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 1025 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1026 } 1027 1028 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1029 int round, bool *sat) 1030 { 1031 int64_t m1 = (int64_t)a * b; 1032 int64_t m2 = (int64_t)c * d; 1033 int64_t r; 1034 /* The same ordering issue as in do_vqdmladh_w applies here too */ 1035 if (ssub64_overflow(m1, m2, &r) || 1036 sadd64_overflow(r, (round << 30), &r) || 1037 sadd64_overflow(r, r, &r)) { 1038 *sat = true; 1039 return r < 0 ? INT32_MAX : INT32_MIN; 1040 } 1041 return r >> 32; 1042 } 1043 1044 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 1045 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 1046 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 1047 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 1048 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 1049 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 1050 1051 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 1052 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 1053 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 1054 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 1055 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 1056 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 1057 1058 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 1059 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 1060 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 1061 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 1062 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 1063 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 1064 1065 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 1066 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 1067 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 1068 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 1069 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 1070 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 1071 1072 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 1073 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1074 uint32_t rm) \ 1075 { \ 1076 TYPE *d = vd, *n = vn; \ 1077 TYPE m = rm; \ 1078 uint16_t mask = mve_element_mask(env); \ 1079 unsigned e; \ 1080 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1081 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 1082 } \ 1083 mve_advance_vpt(env); \ 1084 } 1085 1086 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 1087 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1088 uint32_t rm) \ 1089 { \ 1090 TYPE *d = vd, *n = vn; \ 1091 TYPE m = rm; \ 1092 uint16_t mask = mve_element_mask(env); \ 1093 unsigned e; \ 1094 bool qc = false; \ 1095 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1096 bool sat = false; \ 1097 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 1098 mask); \ 1099 qc |= sat & mask & 1; \ 1100 } \ 1101 if (qc) { \ 1102 env->vfp.qc[0] = qc; \ 1103 } \ 1104 mve_advance_vpt(env); \ 1105 } 1106 1107 /* "accumulating" version where FN takes d as well as n and m */ 1108 #define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1109 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1110 uint32_t rm) \ 1111 { \ 1112 TYPE *d = vd, *n = vn; \ 1113 TYPE m = rm; \ 1114 uint16_t mask = mve_element_mask(env); \ 1115 unsigned e; \ 1116 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1117 mergemask(&d[H##ESIZE(e)], \ 1118 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \ 1119 } \ 1120 mve_advance_vpt(env); \ 1121 } 1122 1123 #define DO_2OP_SAT_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1124 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1125 uint32_t rm) \ 1126 { \ 1127 TYPE *d = vd, *n = vn; \ 1128 TYPE m = rm; \ 1129 uint16_t mask = mve_element_mask(env); \ 1130 unsigned e; \ 1131 bool qc = false; \ 1132 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1133 bool sat = false; \ 1134 mergemask(&d[H##ESIZE(e)], \ 1135 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m, &sat), \ 1136 mask); \ 1137 qc |= sat & mask & 1; \ 1138 } \ 1139 if (qc) { \ 1140 env->vfp.qc[0] = qc; \ 1141 } \ 1142 mve_advance_vpt(env); \ 1143 } 1144 1145 /* provide unsigned 2-op scalar helpers for all sizes */ 1146 #define DO_2OP_SCALAR_U(OP, FN) \ 1147 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 1148 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 1149 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 1150 #define DO_2OP_SCALAR_S(OP, FN) \ 1151 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 1152 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 1153 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 1154 1155 #define DO_2OP_ACC_SCALAR_U(OP, FN) \ 1156 DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \ 1157 DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \ 1158 DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN) 1159 1160 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 1161 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 1162 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 1163 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 1164 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 1165 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 1166 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 1167 1168 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 1169 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 1170 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 1171 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 1172 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 1173 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 1174 1175 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 1176 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 1177 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 1178 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 1179 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 1180 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 1181 1182 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 1183 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 1184 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 1185 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 1186 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 1187 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 1188 1189 static int8_t do_vqdmlah_b(int8_t a, int8_t b, int8_t c, int round, bool *sat) 1190 { 1191 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 8) + (round << 7); 1192 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1193 } 1194 1195 static int16_t do_vqdmlah_h(int16_t a, int16_t b, int16_t c, 1196 int round, bool *sat) 1197 { 1198 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 16) + (round << 15); 1199 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1200 } 1201 1202 static int32_t do_vqdmlah_w(int32_t a, int32_t b, int32_t c, 1203 int round, bool *sat) 1204 { 1205 /* 1206 * Architecturally we should do the entire add, double, round 1207 * and then check for saturation. We do three saturating adds, 1208 * but we need to be careful about the order. If the first 1209 * m1 + m2 saturates then it's impossible for the *2+rc to 1210 * bring it back into the non-saturated range. However, if 1211 * m1 + m2 is negative then it's possible that doing the doubling 1212 * would take the intermediate result below INT64_MAX and the 1213 * addition of the rounding constant then brings it back in range. 1214 * So we add half the rounding constant and half the "c << esize" 1215 * before doubling rather than adding the rounding constant after 1216 * the doubling. 1217 */ 1218 int64_t m1 = (int64_t)a * b; 1219 int64_t m2 = (int64_t)c << 31; 1220 int64_t r; 1221 if (sadd64_overflow(m1, m2, &r) || 1222 sadd64_overflow(r, (round << 30), &r) || 1223 sadd64_overflow(r, r, &r)) { 1224 *sat = true; 1225 return r < 0 ? INT32_MAX : INT32_MIN; 1226 } 1227 return r >> 32; 1228 } 1229 1230 /* 1231 * The *MLAH insns are vector * scalar + vector; 1232 * the *MLASH insns are vector * vector + scalar 1233 */ 1234 #define DO_VQDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 0, S) 1235 #define DO_VQDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 0, S) 1236 #define DO_VQDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 0, S) 1237 #define DO_VQRDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 1, S) 1238 #define DO_VQRDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 1, S) 1239 #define DO_VQRDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 1, S) 1240 1241 #define DO_VQDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 0, S) 1242 #define DO_VQDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 0, S) 1243 #define DO_VQDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 0, S) 1244 #define DO_VQRDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 1, S) 1245 #define DO_VQRDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 1, S) 1246 #define DO_VQRDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 1, S) 1247 1248 DO_2OP_SAT_ACC_SCALAR(vqdmlahb, 1, int8_t, DO_VQDMLAH_B) 1249 DO_2OP_SAT_ACC_SCALAR(vqdmlahh, 2, int16_t, DO_VQDMLAH_H) 1250 DO_2OP_SAT_ACC_SCALAR(vqdmlahw, 4, int32_t, DO_VQDMLAH_W) 1251 DO_2OP_SAT_ACC_SCALAR(vqrdmlahb, 1, int8_t, DO_VQRDMLAH_B) 1252 DO_2OP_SAT_ACC_SCALAR(vqrdmlahh, 2, int16_t, DO_VQRDMLAH_H) 1253 DO_2OP_SAT_ACC_SCALAR(vqrdmlahw, 4, int32_t, DO_VQRDMLAH_W) 1254 1255 DO_2OP_SAT_ACC_SCALAR(vqdmlashb, 1, int8_t, DO_VQDMLASH_B) 1256 DO_2OP_SAT_ACC_SCALAR(vqdmlashh, 2, int16_t, DO_VQDMLASH_H) 1257 DO_2OP_SAT_ACC_SCALAR(vqdmlashw, 4, int32_t, DO_VQDMLASH_W) 1258 DO_2OP_SAT_ACC_SCALAR(vqrdmlashb, 1, int8_t, DO_VQRDMLASH_B) 1259 DO_2OP_SAT_ACC_SCALAR(vqrdmlashh, 2, int16_t, DO_VQRDMLASH_H) 1260 DO_2OP_SAT_ACC_SCALAR(vqrdmlashw, 4, int32_t, DO_VQRDMLASH_W) 1261 1262 /* Vector by scalar plus vector */ 1263 #define DO_VMLA(D, N, M) ((N) * (M) + (D)) 1264 1265 DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA) 1266 1267 /* Vector by vector plus scalar */ 1268 #define DO_VMLAS(D, N, M) ((N) * (D) + (M)) 1269 1270 DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS) 1271 1272 /* 1273 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 1274 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 1275 * SATMASK specifies which bits of the predicate mask matter for determining 1276 * whether to propagate a saturation indication into FPSCR.QC -- for 1277 * the 16x16->32 case we must check only the bit corresponding to the T or B 1278 * half that we used, but for the 32x32->64 case we propagate if the mask 1279 * bit is set for either half. 1280 */ 1281 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1282 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1283 uint32_t rm) \ 1284 { \ 1285 LTYPE *d = vd; \ 1286 TYPE *n = vn; \ 1287 TYPE m = rm; \ 1288 uint16_t mask = mve_element_mask(env); \ 1289 unsigned le; \ 1290 bool qc = false; \ 1291 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1292 bool sat = false; \ 1293 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 1294 mergemask(&d[H##LESIZE(le)], r, mask); \ 1295 qc |= sat && (mask & SATMASK); \ 1296 } \ 1297 if (qc) { \ 1298 env->vfp.qc[0] = qc; \ 1299 } \ 1300 mve_advance_vpt(env); \ 1301 } 1302 1303 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1304 { 1305 int64_t r = ((int64_t)n * m) * 2; 1306 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1307 } 1308 1309 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1310 { 1311 /* The multiply can't overflow, but the doubling might */ 1312 int64_t r = (int64_t)n * m; 1313 if (r > INT64_MAX / 2) { 1314 *sat = true; 1315 return INT64_MAX; 1316 } else if (r < INT64_MIN / 2) { 1317 *sat = true; 1318 return INT64_MIN; 1319 } else { 1320 return r * 2; 1321 } 1322 } 1323 1324 #define SATMASK16B 1 1325 #define SATMASK16T (1 << 2) 1326 #define SATMASK32 ((1 << 4) | 1) 1327 1328 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1329 do_qdmullh, SATMASK16B) 1330 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1331 do_qdmullw, SATMASK32) 1332 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1333 do_qdmullh, SATMASK16T) 1334 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1335 do_qdmullw, SATMASK32) 1336 1337 /* 1338 * Long saturating ops 1339 */ 1340 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1341 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1342 void *vm) \ 1343 { \ 1344 LTYPE *d = vd; \ 1345 TYPE *n = vn, *m = vm; \ 1346 uint16_t mask = mve_element_mask(env); \ 1347 unsigned le; \ 1348 bool qc = false; \ 1349 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1350 bool sat = false; \ 1351 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1352 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1353 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1354 qc |= sat && (mask & SATMASK); \ 1355 } \ 1356 if (qc) { \ 1357 env->vfp.qc[0] = qc; \ 1358 } \ 1359 mve_advance_vpt(env); \ 1360 } 1361 1362 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1363 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1364 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1365 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1366 1367 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1368 { 1369 m &= 0xff; 1370 if (m == 0) { 1371 return 0; 1372 } 1373 n = revbit8(n); 1374 if (m < 8) { 1375 n >>= 8 - m; 1376 } 1377 return n; 1378 } 1379 1380 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1381 { 1382 m &= 0xff; 1383 if (m == 0) { 1384 return 0; 1385 } 1386 n = revbit16(n); 1387 if (m < 16) { 1388 n >>= 16 - m; 1389 } 1390 return n; 1391 } 1392 1393 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1394 { 1395 m &= 0xff; 1396 if (m == 0) { 1397 return 0; 1398 } 1399 n = revbit32(n); 1400 if (m < 32) { 1401 n >>= 32 - m; 1402 } 1403 return n; 1404 } 1405 1406 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1407 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1408 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1409 1410 /* 1411 * Multiply add long dual accumulate ops. 1412 */ 1413 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1414 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1415 void *vm, uint64_t a) \ 1416 { \ 1417 uint16_t mask = mve_element_mask(env); \ 1418 unsigned e; \ 1419 TYPE *n = vn, *m = vm; \ 1420 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1421 if (mask & 1) { \ 1422 if (e & 1) { \ 1423 a ODDACC \ 1424 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1425 } else { \ 1426 a EVENACC \ 1427 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1428 } \ 1429 } \ 1430 } \ 1431 mve_advance_vpt(env); \ 1432 return a; \ 1433 } 1434 1435 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1436 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1437 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1438 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1439 1440 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1441 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1442 1443 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1444 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1445 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1446 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1447 1448 /* 1449 * Multiply add dual accumulate ops 1450 */ 1451 #define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1452 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1453 void *vm, uint32_t a) \ 1454 { \ 1455 uint16_t mask = mve_element_mask(env); \ 1456 unsigned e; \ 1457 TYPE *n = vn, *m = vm; \ 1458 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1459 if (mask & 1) { \ 1460 if (e & 1) { \ 1461 a ODDACC \ 1462 n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1463 } else { \ 1464 a EVENACC \ 1465 n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1466 } \ 1467 } \ 1468 } \ 1469 mve_advance_vpt(env); \ 1470 return a; \ 1471 } 1472 1473 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ 1474 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \ 1475 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \ 1476 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC) 1477 1478 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ 1479 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \ 1480 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \ 1481 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC) 1482 1483 DO_DAV_S(vmladavs, false, +=, +=) 1484 DO_DAV_U(vmladavu, false, +=, +=) 1485 DO_DAV_S(vmlsdav, false, +=, -=) 1486 DO_DAV_S(vmladavsx, true, +=, +=) 1487 DO_DAV_S(vmlsdavx, true, +=, -=) 1488 1489 /* 1490 * Rounding multiply add long dual accumulate high. In the pseudocode 1491 * this is implemented with a 72-bit internal accumulator value of which 1492 * the top 64 bits are returned. We optimize this to avoid having to 1493 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1494 * is squashed back into 64-bits after each beat. 1495 */ 1496 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1497 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1498 void *vm, uint64_t a) \ 1499 { \ 1500 uint16_t mask = mve_element_mask(env); \ 1501 unsigned e; \ 1502 TYPE *n = vn, *m = vm; \ 1503 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1504 if (mask & 1) { \ 1505 LTYPE mul; \ 1506 if (e & 1) { \ 1507 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1508 if (SUB) { \ 1509 mul = -mul; \ 1510 } \ 1511 } else { \ 1512 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1513 } \ 1514 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1515 a += mul; \ 1516 } \ 1517 } \ 1518 mve_advance_vpt(env); \ 1519 return a; \ 1520 } 1521 1522 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1523 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1524 1525 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1526 1527 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1528 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1529 1530 /* Vector add across vector */ 1531 #define DO_VADDV(OP, ESIZE, TYPE) \ 1532 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1533 uint32_t ra) \ 1534 { \ 1535 uint16_t mask = mve_element_mask(env); \ 1536 unsigned e; \ 1537 TYPE *m = vm; \ 1538 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1539 if (mask & 1) { \ 1540 ra += m[H##ESIZE(e)]; \ 1541 } \ 1542 } \ 1543 mve_advance_vpt(env); \ 1544 return ra; \ 1545 } \ 1546 1547 DO_VADDV(vaddvsb, 1, int8_t) 1548 DO_VADDV(vaddvsh, 2, int16_t) 1549 DO_VADDV(vaddvsw, 4, int32_t) 1550 DO_VADDV(vaddvub, 1, uint8_t) 1551 DO_VADDV(vaddvuh, 2, uint16_t) 1552 DO_VADDV(vaddvuw, 4, uint32_t) 1553 1554 /* 1555 * Vector max/min across vector. Unlike VADDV, we must 1556 * read ra as the element size, not its full width. 1557 * We work with int64_t internally for simplicity. 1558 */ 1559 #define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \ 1560 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1561 uint32_t ra_in) \ 1562 { \ 1563 uint16_t mask = mve_element_mask(env); \ 1564 unsigned e; \ 1565 TYPE *m = vm; \ 1566 int64_t ra = (RATYPE)ra_in; \ 1567 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1568 if (mask & 1) { \ 1569 ra = FN(ra, m[H##ESIZE(e)]); \ 1570 } \ 1571 } \ 1572 mve_advance_vpt(env); \ 1573 return ra; \ 1574 } \ 1575 1576 #define DO_VMAXMINV_U(INSN, FN) \ 1577 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \ 1578 DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \ 1579 DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN) 1580 #define DO_VMAXMINV_S(INSN, FN) \ 1581 DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \ 1582 DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \ 1583 DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN) 1584 1585 /* 1586 * Helpers for max and min of absolute values across vector: 1587 * note that we only take the absolute value of 'm', not 'n' 1588 */ 1589 static int64_t do_maxa(int64_t n, int64_t m) 1590 { 1591 if (m < 0) { 1592 m = -m; 1593 } 1594 return MAX(n, m); 1595 } 1596 1597 static int64_t do_mina(int64_t n, int64_t m) 1598 { 1599 if (m < 0) { 1600 m = -m; 1601 } 1602 return MIN(n, m); 1603 } 1604 1605 DO_VMAXMINV_S(vmaxvs, DO_MAX) 1606 DO_VMAXMINV_U(vmaxvu, DO_MAX) 1607 DO_VMAXMINV_S(vminvs, DO_MIN) 1608 DO_VMAXMINV_U(vminvu, DO_MIN) 1609 /* 1610 * VMAXAV, VMINAV treat the general purpose input as unsigned 1611 * and the vector elements as signed. 1612 */ 1613 DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa) 1614 DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa) 1615 DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa) 1616 DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) 1617 DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) 1618 DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) 1619 1620 #define DO_VABAV(OP, ESIZE, TYPE) \ 1621 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1622 void *vm, uint32_t ra) \ 1623 { \ 1624 uint16_t mask = mve_element_mask(env); \ 1625 unsigned e; \ 1626 TYPE *m = vm, *n = vn; \ 1627 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1628 if (mask & 1) { \ 1629 int64_t n0 = n[H##ESIZE(e)]; \ 1630 int64_t m0 = m[H##ESIZE(e)]; \ 1631 uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \ 1632 ra += r; \ 1633 } \ 1634 } \ 1635 mve_advance_vpt(env); \ 1636 return ra; \ 1637 } 1638 1639 DO_VABAV(vabavsb, 1, int8_t) 1640 DO_VABAV(vabavsh, 2, int16_t) 1641 DO_VABAV(vabavsw, 4, int32_t) 1642 DO_VABAV(vabavub, 1, uint8_t) 1643 DO_VABAV(vabavuh, 2, uint16_t) 1644 DO_VABAV(vabavuw, 4, uint32_t) 1645 1646 #define DO_VADDLV(OP, TYPE, LTYPE) \ 1647 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1648 uint64_t ra) \ 1649 { \ 1650 uint16_t mask = mve_element_mask(env); \ 1651 unsigned e; \ 1652 TYPE *m = vm; \ 1653 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1654 if (mask & 1) { \ 1655 ra += (LTYPE)m[H4(e)]; \ 1656 } \ 1657 } \ 1658 mve_advance_vpt(env); \ 1659 return ra; \ 1660 } \ 1661 1662 DO_VADDLV(vaddlv_s, int32_t, int64_t) 1663 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 1664 1665 /* Shifts by immediate */ 1666 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 1667 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1668 void *vm, uint32_t shift) \ 1669 { \ 1670 TYPE *d = vd, *m = vm; \ 1671 uint16_t mask = mve_element_mask(env); \ 1672 unsigned e; \ 1673 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1674 mergemask(&d[H##ESIZE(e)], \ 1675 FN(m[H##ESIZE(e)], shift), mask); \ 1676 } \ 1677 mve_advance_vpt(env); \ 1678 } 1679 1680 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 1681 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1682 void *vm, uint32_t shift) \ 1683 { \ 1684 TYPE *d = vd, *m = vm; \ 1685 uint16_t mask = mve_element_mask(env); \ 1686 unsigned e; \ 1687 bool qc = false; \ 1688 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1689 bool sat = false; \ 1690 mergemask(&d[H##ESIZE(e)], \ 1691 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 1692 qc |= sat & mask & 1; \ 1693 } \ 1694 if (qc) { \ 1695 env->vfp.qc[0] = qc; \ 1696 } \ 1697 mve_advance_vpt(env); \ 1698 } 1699 1700 /* provide unsigned 2-op shift helpers for all sizes */ 1701 #define DO_2SHIFT_U(OP, FN) \ 1702 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 1703 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 1704 DO_2SHIFT(OP##w, 4, uint32_t, FN) 1705 #define DO_2SHIFT_S(OP, FN) \ 1706 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 1707 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 1708 DO_2SHIFT(OP##w, 4, int32_t, FN) 1709 1710 #define DO_2SHIFT_SAT_U(OP, FN) \ 1711 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 1712 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 1713 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 1714 #define DO_2SHIFT_SAT_S(OP, FN) \ 1715 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 1716 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 1717 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 1718 1719 DO_2SHIFT_U(vshli_u, DO_VSHLU) 1720 DO_2SHIFT_S(vshli_s, DO_VSHLS) 1721 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 1722 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 1723 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 1724 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 1725 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 1726 DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP) 1727 DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP) 1728 1729 /* Shift-and-insert; we always work with 64 bits at a time */ 1730 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 1731 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1732 void *vm, uint32_t shift) \ 1733 { \ 1734 uint64_t *d = vd, *m = vm; \ 1735 uint16_t mask; \ 1736 uint64_t shiftmask; \ 1737 unsigned e; \ 1738 if (shift == ESIZE * 8) { \ 1739 /* \ 1740 * Only VSRI can shift by <dt>; it should mean "don't \ 1741 * update the destination". The generic logic can't handle \ 1742 * this because it would try to shift by an out-of-range \ 1743 * amount, so special case it here. \ 1744 */ \ 1745 goto done; \ 1746 } \ 1747 assert(shift < ESIZE * 8); \ 1748 mask = mve_element_mask(env); \ 1749 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 1750 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 1751 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 1752 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 1753 (d[H8(e)] & ~shiftmask); \ 1754 mergemask(&d[H8(e)], r, mask); \ 1755 } \ 1756 done: \ 1757 mve_advance_vpt(env); \ 1758 } 1759 1760 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 1761 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 1762 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 1763 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 1764 1765 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 1766 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 1767 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 1768 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 1769 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 1770 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 1771 1772 /* 1773 * Long shifts taking half-sized inputs from top or bottom of the input 1774 * vector and producing a double-width result. ESIZE, TYPE are for 1775 * the input, and LESIZE, LTYPE for the output. 1776 * Unlike the normal shift helpers, we do not handle negative shift counts, 1777 * because the long shift is strictly left-only. 1778 */ 1779 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 1780 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1781 void *vm, uint32_t shift) \ 1782 { \ 1783 LTYPE *d = vd; \ 1784 TYPE *m = vm; \ 1785 uint16_t mask = mve_element_mask(env); \ 1786 unsigned le; \ 1787 assert(shift <= 16); \ 1788 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1789 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 1790 mergemask(&d[H##LESIZE(le)], r, mask); \ 1791 } \ 1792 mve_advance_vpt(env); \ 1793 } 1794 1795 #define DO_VSHLL_ALL(OP, TOP) \ 1796 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 1797 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 1798 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 1799 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 1800 1801 DO_VSHLL_ALL(vshllb, false) 1802 DO_VSHLL_ALL(vshllt, true) 1803 1804 /* 1805 * Narrowing right shifts, taking a double sized input, shifting it 1806 * and putting the result in either the top or bottom half of the output. 1807 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 1808 */ 1809 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1810 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1811 void *vm, uint32_t shift) \ 1812 { \ 1813 LTYPE *m = vm; \ 1814 TYPE *d = vd; \ 1815 uint16_t mask = mve_element_mask(env); \ 1816 unsigned le; \ 1817 mask >>= ESIZE * TOP; \ 1818 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1819 TYPE r = FN(m[H##LESIZE(le)], shift); \ 1820 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1821 } \ 1822 mve_advance_vpt(env); \ 1823 } 1824 1825 #define DO_VSHRN_ALL(OP, FN) \ 1826 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 1827 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 1828 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 1829 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 1830 1831 static inline uint64_t do_urshr(uint64_t x, unsigned sh) 1832 { 1833 if (likely(sh < 64)) { 1834 return (x >> sh) + ((x >> (sh - 1)) & 1); 1835 } else if (sh == 64) { 1836 return x >> 63; 1837 } else { 1838 return 0; 1839 } 1840 } 1841 1842 static inline int64_t do_srshr(int64_t x, unsigned sh) 1843 { 1844 if (likely(sh < 64)) { 1845 return (x >> sh) + ((x >> (sh - 1)) & 1); 1846 } else { 1847 /* Rounding the sign bit always produces 0. */ 1848 return 0; 1849 } 1850 } 1851 1852 DO_VSHRN_ALL(vshrn, DO_SHR) 1853 DO_VSHRN_ALL(vrshrn, do_urshr) 1854 1855 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 1856 bool *satp) 1857 { 1858 if (val > max) { 1859 *satp = true; 1860 return max; 1861 } else if (val < min) { 1862 *satp = true; 1863 return min; 1864 } else { 1865 return val; 1866 } 1867 } 1868 1869 /* Saturating narrowing right shifts */ 1870 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1871 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1872 void *vm, uint32_t shift) \ 1873 { \ 1874 LTYPE *m = vm; \ 1875 TYPE *d = vd; \ 1876 uint16_t mask = mve_element_mask(env); \ 1877 bool qc = false; \ 1878 unsigned le; \ 1879 mask >>= ESIZE * TOP; \ 1880 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1881 bool sat = false; \ 1882 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 1883 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1884 qc |= sat & mask & 1; \ 1885 } \ 1886 if (qc) { \ 1887 env->vfp.qc[0] = qc; \ 1888 } \ 1889 mve_advance_vpt(env); \ 1890 } 1891 1892 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 1893 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 1894 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 1895 1896 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 1897 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 1898 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 1899 1900 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 1901 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 1902 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 1903 1904 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 1905 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 1906 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 1907 1908 #define DO_SHRN_SB(N, M, SATP) \ 1909 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 1910 #define DO_SHRN_UB(N, M, SATP) \ 1911 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1912 #define DO_SHRUN_B(N, M, SATP) \ 1913 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1914 1915 #define DO_SHRN_SH(N, M, SATP) \ 1916 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 1917 #define DO_SHRN_UH(N, M, SATP) \ 1918 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1919 #define DO_SHRUN_H(N, M, SATP) \ 1920 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1921 1922 #define DO_RSHRN_SB(N, M, SATP) \ 1923 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 1924 #define DO_RSHRN_UB(N, M, SATP) \ 1925 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 1926 #define DO_RSHRUN_B(N, M, SATP) \ 1927 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 1928 1929 #define DO_RSHRN_SH(N, M, SATP) \ 1930 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 1931 #define DO_RSHRN_UH(N, M, SATP) \ 1932 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 1933 #define DO_RSHRUN_H(N, M, SATP) \ 1934 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 1935 1936 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 1937 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 1938 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 1939 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 1940 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 1941 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 1942 1943 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 1944 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 1945 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 1946 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 1947 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 1948 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 1949 1950 #define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 1951 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 1952 { \ 1953 LTYPE *m = vm; \ 1954 TYPE *d = vd; \ 1955 uint16_t mask = mve_element_mask(env); \ 1956 unsigned le; \ 1957 mask >>= ESIZE * TOP; \ 1958 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1959 mergemask(&d[H##ESIZE(le * 2 + TOP)], \ 1960 m[H##LESIZE(le)], mask); \ 1961 } \ 1962 mve_advance_vpt(env); \ 1963 } 1964 1965 DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t) 1966 DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t) 1967 DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t) 1968 DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t) 1969 1970 #define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1971 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 1972 { \ 1973 LTYPE *m = vm; \ 1974 TYPE *d = vd; \ 1975 uint16_t mask = mve_element_mask(env); \ 1976 bool qc = false; \ 1977 unsigned le; \ 1978 mask >>= ESIZE * TOP; \ 1979 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1980 bool sat = false; \ 1981 TYPE r = FN(m[H##LESIZE(le)], &sat); \ 1982 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1983 qc |= sat & mask & 1; \ 1984 } \ 1985 if (qc) { \ 1986 env->vfp.qc[0] = qc; \ 1987 } \ 1988 mve_advance_vpt(env); \ 1989 } 1990 1991 #define DO_VMOVN_SAT_UB(BOP, TOP, FN) \ 1992 DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 1993 DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 1994 1995 #define DO_VMOVN_SAT_UH(BOP, TOP, FN) \ 1996 DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 1997 DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 1998 1999 #define DO_VMOVN_SAT_SB(BOP, TOP, FN) \ 2000 DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2001 DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2002 2003 #define DO_VMOVN_SAT_SH(BOP, TOP, FN) \ 2004 DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2005 DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2006 2007 #define DO_VQMOVN_SB(N, SATP) \ 2008 do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP) 2009 #define DO_VQMOVN_UB(N, SATP) \ 2010 do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP) 2011 #define DO_VQMOVUN_B(N, SATP) \ 2012 do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP) 2013 2014 #define DO_VQMOVN_SH(N, SATP) \ 2015 do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP) 2016 #define DO_VQMOVN_UH(N, SATP) \ 2017 do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP) 2018 #define DO_VQMOVUN_H(N, SATP) \ 2019 do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP) 2020 2021 DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB) 2022 DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH) 2023 DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB) 2024 DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH) 2025 DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B) 2026 DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H) 2027 2028 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 2029 uint32_t shift) 2030 { 2031 uint32_t *d = vd; 2032 uint16_t mask = mve_element_mask(env); 2033 unsigned e; 2034 uint32_t r; 2035 2036 /* 2037 * For each 32-bit element, we shift it left, bringing in the 2038 * low 'shift' bits of rdm at the bottom. Bits shifted out at 2039 * the top become the new rdm, if the predicate mask permits. 2040 * The final rdm value is returned to update the register. 2041 * shift == 0 here means "shift by 32 bits". 2042 */ 2043 if (shift == 0) { 2044 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2045 r = rdm; 2046 if (mask & 1) { 2047 rdm = d[H4(e)]; 2048 } 2049 mergemask(&d[H4(e)], r, mask); 2050 } 2051 } else { 2052 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 2053 2054 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2055 r = (d[H4(e)] << shift) | (rdm & shiftmask); 2056 if (mask & 1) { 2057 rdm = d[H4(e)] >> (32 - shift); 2058 } 2059 mergemask(&d[H4(e)], r, mask); 2060 } 2061 } 2062 mve_advance_vpt(env); 2063 return rdm; 2064 } 2065 2066 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2067 { 2068 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 2069 } 2070 2071 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 2072 { 2073 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 2074 } 2075 2076 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2077 { 2078 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 2079 } 2080 2081 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2082 { 2083 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 2084 } 2085 2086 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2087 { 2088 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 2089 } 2090 2091 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2092 { 2093 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 2094 } 2095 2096 /* Operate on 64-bit values, but saturate at 48 bits */ 2097 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 2098 bool round, uint32_t *sat) 2099 { 2100 int64_t val, extval; 2101 2102 if (shift <= -48) { 2103 /* Rounding the sign bit always produces 0. */ 2104 if (round) { 2105 return 0; 2106 } 2107 return src >> 63; 2108 } else if (shift < 0) { 2109 if (round) { 2110 src >>= -shift - 1; 2111 val = (src >> 1) + (src & 1); 2112 } else { 2113 val = src >> -shift; 2114 } 2115 extval = sextract64(val, 0, 48); 2116 if (!sat || val == extval) { 2117 return extval; 2118 } 2119 } else if (shift < 48) { 2120 int64_t extval = sextract64(src << shift, 0, 48); 2121 if (!sat || src == (extval >> shift)) { 2122 return extval; 2123 } 2124 } else if (!sat || src == 0) { 2125 return 0; 2126 } 2127 2128 *sat = 1; 2129 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 2130 } 2131 2132 /* Operate on 64-bit values, but saturate at 48 bits */ 2133 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 2134 bool round, uint32_t *sat) 2135 { 2136 uint64_t val, extval; 2137 2138 if (shift <= -(48 + round)) { 2139 return 0; 2140 } else if (shift < 0) { 2141 if (round) { 2142 val = src >> (-shift - 1); 2143 val = (val >> 1) + (val & 1); 2144 } else { 2145 val = src >> -shift; 2146 } 2147 extval = extract64(val, 0, 48); 2148 if (!sat || val == extval) { 2149 return extval; 2150 } 2151 } else if (shift < 48) { 2152 uint64_t extval = extract64(src << shift, 0, 48); 2153 if (!sat || src == (extval >> shift)) { 2154 return extval; 2155 } 2156 } else if (!sat || src == 0) { 2157 return 0; 2158 } 2159 2160 *sat = 1; 2161 return MAKE_64BIT_MASK(0, 48); 2162 } 2163 2164 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 2165 { 2166 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 2167 } 2168 2169 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 2170 { 2171 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 2172 } 2173 2174 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2175 { 2176 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2177 } 2178 2179 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2180 { 2181 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2182 } 2183 2184 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2185 { 2186 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 2187 } 2188 2189 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 2190 { 2191 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 2192 } 2193 2194 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \ 2195 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2196 uint32_t offset, uint32_t imm) \ 2197 { \ 2198 TYPE *d = vd; \ 2199 uint16_t mask = mve_element_mask(env); \ 2200 unsigned e; \ 2201 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2202 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2203 offset = FN(offset, imm); \ 2204 } \ 2205 mve_advance_vpt(env); \ 2206 return offset; \ 2207 } 2208 2209 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ 2210 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2211 uint32_t offset, uint32_t wrap, \ 2212 uint32_t imm) \ 2213 { \ 2214 TYPE *d = vd; \ 2215 uint16_t mask = mve_element_mask(env); \ 2216 unsigned e; \ 2217 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2218 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2219 offset = FN(offset, wrap, imm); \ 2220 } \ 2221 mve_advance_vpt(env); \ 2222 return offset; \ 2223 } 2224 2225 #define DO_VIDUP_ALL(OP, FN) \ 2226 DO_VIDUP(OP##b, 1, int8_t, FN) \ 2227 DO_VIDUP(OP##h, 2, int16_t, FN) \ 2228 DO_VIDUP(OP##w, 4, int32_t, FN) 2229 2230 #define DO_VIWDUP_ALL(OP, FN) \ 2231 DO_VIWDUP(OP##b, 1, int8_t, FN) \ 2232 DO_VIWDUP(OP##h, 2, int16_t, FN) \ 2233 DO_VIWDUP(OP##w, 4, int32_t, FN) 2234 2235 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2236 { 2237 offset += imm; 2238 if (offset == wrap) { 2239 offset = 0; 2240 } 2241 return offset; 2242 } 2243 2244 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2245 { 2246 if (offset == 0) { 2247 offset = wrap; 2248 } 2249 offset -= imm; 2250 return offset; 2251 } 2252 2253 DO_VIDUP_ALL(vidup, DO_ADD) 2254 DO_VIWDUP_ALL(viwdup, do_add_wrap) 2255 DO_VIWDUP_ALL(vdwdup, do_sub_wrap) 2256 2257 /* 2258 * Vector comparison. 2259 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. 2260 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. 2261 * P0 bits otherwise are updated with the results of the comparisons. 2262 * We must also keep unchanged the MASK fields at the top of v7m.vpr. 2263 */ 2264 #define DO_VCMP(OP, ESIZE, TYPE, FN) \ 2265 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 2266 { \ 2267 TYPE *n = vn, *m = vm; \ 2268 uint16_t mask = mve_element_mask(env); \ 2269 uint16_t eci_mask = mve_eci_mask(env); \ 2270 uint16_t beatpred = 0; \ 2271 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2272 unsigned e; \ 2273 for (e = 0; e < 16 / ESIZE; e++) { \ 2274 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ 2275 /* Comparison sets 0/1 bits for each byte in the element */ \ 2276 beatpred |= r * emask; \ 2277 emask <<= ESIZE; \ 2278 } \ 2279 beatpred &= mask; \ 2280 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2281 (beatpred & eci_mask); \ 2282 mve_advance_vpt(env); \ 2283 } 2284 2285 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ 2286 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 2287 uint32_t rm) \ 2288 { \ 2289 TYPE *n = vn; \ 2290 uint16_t mask = mve_element_mask(env); \ 2291 uint16_t eci_mask = mve_eci_mask(env); \ 2292 uint16_t beatpred = 0; \ 2293 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2294 unsigned e; \ 2295 for (e = 0; e < 16 / ESIZE; e++) { \ 2296 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \ 2297 /* Comparison sets 0/1 bits for each byte in the element */ \ 2298 beatpred |= r * emask; \ 2299 emask <<= ESIZE; \ 2300 } \ 2301 beatpred &= mask; \ 2302 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2303 (beatpred & eci_mask); \ 2304 mve_advance_vpt(env); \ 2305 } 2306 2307 #define DO_VCMP_S(OP, FN) \ 2308 DO_VCMP(OP##b, 1, int8_t, FN) \ 2309 DO_VCMP(OP##h, 2, int16_t, FN) \ 2310 DO_VCMP(OP##w, 4, int32_t, FN) \ 2311 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ 2312 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ 2313 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) 2314 2315 #define DO_VCMP_U(OP, FN) \ 2316 DO_VCMP(OP##b, 1, uint8_t, FN) \ 2317 DO_VCMP(OP##h, 2, uint16_t, FN) \ 2318 DO_VCMP(OP##w, 4, uint32_t, FN) \ 2319 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ 2320 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ 2321 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) 2322 2323 #define DO_EQ(N, M) ((N) == (M)) 2324 #define DO_NE(N, M) ((N) != (M)) 2325 #define DO_EQ(N, M) ((N) == (M)) 2326 #define DO_EQ(N, M) ((N) == (M)) 2327 #define DO_GE(N, M) ((N) >= (M)) 2328 #define DO_LT(N, M) ((N) < (M)) 2329 #define DO_GT(N, M) ((N) > (M)) 2330 #define DO_LE(N, M) ((N) <= (M)) 2331 2332 DO_VCMP_U(vcmpeq, DO_EQ) 2333 DO_VCMP_U(vcmpne, DO_NE) 2334 DO_VCMP_U(vcmpcs, DO_GE) 2335 DO_VCMP_U(vcmphi, DO_GT) 2336 DO_VCMP_S(vcmpge, DO_GE) 2337 DO_VCMP_S(vcmplt, DO_LT) 2338 DO_VCMP_S(vcmpgt, DO_GT) 2339 DO_VCMP_S(vcmple, DO_LE) 2340 2341 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) 2342 { 2343 /* 2344 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n] 2345 * but note that whether bytes are written to Qd is still subject 2346 * to (all forms of) predication in the usual way. 2347 */ 2348 uint64_t *d = vd, *n = vn, *m = vm; 2349 uint16_t mask = mve_element_mask(env); 2350 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 2351 unsigned e; 2352 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) { 2353 uint64_t r = m[H8(e)]; 2354 mergemask(&r, n[H8(e)], p0); 2355 mergemask(&d[H8(e)], r, mask); 2356 } 2357 mve_advance_vpt(env); 2358 } 2359 2360 void HELPER(mve_vpnot)(CPUARMState *env) 2361 { 2362 /* 2363 * P0 bits for unexecuted beats (where eci_mask is 0) are unchanged. 2364 * P0 bits for predicated lanes in executed bits (where mask is 0) are 0. 2365 * P0 bits otherwise are inverted. 2366 * (This is the same logic as VCMP.) 2367 * This insn is itself subject to predication and to beat-wise execution, 2368 * and after it executes VPT state advances in the usual way. 2369 */ 2370 uint16_t mask = mve_element_mask(env); 2371 uint16_t eci_mask = mve_eci_mask(env); 2372 uint16_t beatpred = ~env->v7m.vpr & mask; 2373 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask); 2374 mve_advance_vpt(env); 2375 } 2376 2377 /* 2378 * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed, 2379 * otherwise set according to value of Rn. The calculation of 2380 * newmask here works in the same way as the calculation of the 2381 * ltpmask in mve_element_mask(), but we have pre-calculated 2382 * the masklen in the generated code. 2383 */ 2384 void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen) 2385 { 2386 uint16_t mask = mve_element_mask(env); 2387 uint16_t eci_mask = mve_eci_mask(env); 2388 uint16_t newmask; 2389 2390 assert(masklen <= 16); 2391 newmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 2392 newmask &= mask; 2393 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask); 2394 mve_advance_vpt(env); 2395 } 2396 2397 #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ 2398 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2399 { \ 2400 TYPE *d = vd, *m = vm; \ 2401 uint16_t mask = mve_element_mask(env); \ 2402 unsigned e; \ 2403 bool qc = false; \ 2404 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2405 bool sat = false; \ 2406 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)], &sat), mask); \ 2407 qc |= sat & mask & 1; \ 2408 } \ 2409 if (qc) { \ 2410 env->vfp.qc[0] = qc; \ 2411 } \ 2412 mve_advance_vpt(env); \ 2413 } 2414 2415 #define DO_VQABS_B(N, SATP) \ 2416 do_sat_bhs(DO_ABS((int64_t)N), INT8_MIN, INT8_MAX, SATP) 2417 #define DO_VQABS_H(N, SATP) \ 2418 do_sat_bhs(DO_ABS((int64_t)N), INT16_MIN, INT16_MAX, SATP) 2419 #define DO_VQABS_W(N, SATP) \ 2420 do_sat_bhs(DO_ABS((int64_t)N), INT32_MIN, INT32_MAX, SATP) 2421 2422 #define DO_VQNEG_B(N, SATP) do_sat_bhs(-(int64_t)N, INT8_MIN, INT8_MAX, SATP) 2423 #define DO_VQNEG_H(N, SATP) do_sat_bhs(-(int64_t)N, INT16_MIN, INT16_MAX, SATP) 2424 #define DO_VQNEG_W(N, SATP) do_sat_bhs(-(int64_t)N, INT32_MIN, INT32_MAX, SATP) 2425 2426 DO_1OP_SAT(vqabsb, 1, int8_t, DO_VQABS_B) 2427 DO_1OP_SAT(vqabsh, 2, int16_t, DO_VQABS_H) 2428 DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W) 2429 2430 DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B) 2431 DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H) 2432 DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W) 2433 2434 /* 2435 * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its 2436 * absolute value; we then do an unsigned comparison. 2437 */ 2438 #define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \ 2439 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2440 { \ 2441 UTYPE *d = vd; \ 2442 STYPE *m = vm; \ 2443 uint16_t mask = mve_element_mask(env); \ 2444 unsigned e; \ 2445 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2446 UTYPE r = DO_ABS(m[H##ESIZE(e)]); \ 2447 r = FN(d[H##ESIZE(e)], r); \ 2448 mergemask(&d[H##ESIZE(e)], r, mask); \ 2449 } \ 2450 mve_advance_vpt(env); \ 2451 } 2452 2453 DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX) 2454 DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX) 2455 DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) 2456 DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) 2457 DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) 2458 DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) 2459