1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "accel/tcg/cpu-ldst.h" 26 #include "tcg/tcg.h" 27 #include "fpu/softfloat.h" 28 #include "crypto/clmul.h" 29 30 static uint16_t mve_eci_mask(CPUARMState *env) 31 { 32 /* 33 * Return the mask of which elements in the MVE vector correspond 34 * to beats being executed. The mask has 1 bits for executed lanes 35 * and 0 bits where ECI says this beat was already executed. 36 */ 37 int eci; 38 39 if ((env->condexec_bits & 0xf) != 0) { 40 return 0xffff; 41 } 42 43 eci = env->condexec_bits >> 4; 44 switch (eci) { 45 case ECI_NONE: 46 return 0xffff; 47 case ECI_A0: 48 return 0xfff0; 49 case ECI_A0A1: 50 return 0xff00; 51 case ECI_A0A1A2: 52 case ECI_A0A1A2B0: 53 return 0xf000; 54 default: 55 g_assert_not_reached(); 56 } 57 } 58 59 static uint16_t mve_element_mask(CPUARMState *env) 60 { 61 /* 62 * Return the mask of which elements in the MVE vector should be 63 * updated. This is a combination of multiple things: 64 * (1) by default, we update every lane in the vector 65 * (2) VPT predication stores its state in the VPR register; 66 * (3) low-overhead-branch tail predication will mask out part 67 * the vector on the final iteration of the loop 68 * (4) if EPSR.ECI is set then we must execute only some beats 69 * of the insn 70 * We combine all these into a 16-bit result with the same semantics 71 * as VPR.P0: 0 to mask the lane, 1 if it is active. 72 * 8-bit vector ops will look at all bits of the result; 73 * 16-bit ops will look at bits 0, 2, 4, ...; 74 * 32-bit ops will look at bits 0, 4, 8 and 12. 75 * Compare pseudocode GetCurInstrBeat(), though that only returns 76 * the 4-bit slice of the mask corresponding to a single beat. 77 */ 78 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 79 80 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 81 mask |= 0xff; 82 } 83 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 84 mask |= 0xff00; 85 } 86 87 if (env->v7m.ltpsize < 4 && 88 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 89 /* 90 * Tail predication active, and this is the last loop iteration. 91 * The element size is (1 << ltpsize), and we only want to process 92 * loopcount elements, so we want to retain the least significant 93 * (loopcount * esize) predicate bits and zero out bits above that. 94 */ 95 int masklen = env->regs[14] << env->v7m.ltpsize; 96 assert(masklen <= 16); 97 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 98 mask &= ltpmask; 99 } 100 101 /* 102 * ECI bits indicate which beats are already executed; 103 * we handle this by effectively predicating them out. 104 */ 105 mask &= mve_eci_mask(env); 106 return mask; 107 } 108 109 static void mve_advance_vpt(CPUARMState *env) 110 { 111 /* Advance the VPT and ECI state if necessary */ 112 uint32_t vpr = env->v7m.vpr; 113 unsigned mask01, mask23; 114 uint16_t inv_mask; 115 uint16_t eci_mask = mve_eci_mask(env); 116 117 if ((env->condexec_bits & 0xf) == 0) { 118 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 119 (ECI_A0 << 4) : (ECI_NONE << 4); 120 } 121 122 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 123 /* VPT not enabled, nothing to do */ 124 return; 125 } 126 127 /* Invert P0 bits if needed, but only for beats we actually executed */ 128 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 129 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 130 /* Start by assuming we invert all bits corresponding to executed beats */ 131 inv_mask = eci_mask; 132 if (mask01 <= 8) { 133 /* MASK01 says don't invert low half of P0 */ 134 inv_mask &= ~0xff; 135 } 136 if (mask23 <= 8) { 137 /* MASK23 says don't invert high half of P0 */ 138 inv_mask &= ~0xff00; 139 } 140 vpr ^= inv_mask; 141 /* Only update MASK01 if beat 1 executed */ 142 if (eci_mask & 0xf0) { 143 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 144 } 145 /* Beat 3 always executes, so update MASK23 */ 146 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 147 env->v7m.vpr = vpr; 148 } 149 150 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 151 #define DO_VLDR(OP, MFLAG, MSIZE, MTYPE, LDTYPE, ESIZE, TYPE) \ 152 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 153 { \ 154 TYPE *d = vd; \ 155 uint16_t mask = mve_element_mask(env); \ 156 uint16_t eci_mask = mve_eci_mask(env); \ 157 unsigned b, e; \ 158 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 159 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 160 /* \ 161 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 162 * beats so we don't care if we update part of the dest and \ 163 * then take an exception. \ 164 */ \ 165 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 166 if (eci_mask & (1 << b)) { \ 167 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 168 (MTYPE)cpu_##LDTYPE##_mmu(env, addr, oi, GETPC()) : 0;\ 169 } \ 170 addr += MSIZE; \ 171 } \ 172 mve_advance_vpt(env); \ 173 } 174 175 #define DO_VSTR(OP, MFLAG, MSIZE, STTYPE, ESIZE, TYPE) \ 176 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 177 { \ 178 TYPE *d = vd; \ 179 uint16_t mask = mve_element_mask(env); \ 180 unsigned b, e; \ 181 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 182 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 183 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 184 if (mask & (1 << b)) { \ 185 cpu_##STTYPE##_mmu(env, addr, d[H##ESIZE(e)], oi, GETPC()); \ 186 } \ 187 addr += MSIZE; \ 188 } \ 189 mve_advance_vpt(env); \ 190 } 191 192 DO_VLDR(vldrb, MO_UB, 1, uint8_t, ldb, 1, uint8_t) 193 DO_VLDR(vldrh, MO_TEUW, 2, uint16_t, ldw, 2, uint16_t) 194 DO_VLDR(vldrw, MO_TEUL, 4, uint32_t, ldl, 4, uint32_t) 195 196 DO_VSTR(vstrb, MO_UB, 1, stb, 1, uint8_t) 197 DO_VSTR(vstrh, MO_TEUW, 2, stw, 2, uint16_t) 198 DO_VSTR(vstrw, MO_TEUL, 4, stl, 4, uint32_t) 199 200 DO_VLDR(vldrb_sh, MO_SB, 1, int8_t, ldb, 2, int16_t) 201 DO_VLDR(vldrb_sw, MO_SB, 1, int8_t, ldb, 4, int32_t) 202 DO_VLDR(vldrb_uh, MO_UB, 1, uint8_t, ldb, 2, uint16_t) 203 DO_VLDR(vldrb_uw, MO_UB, 1, uint8_t, ldb, 4, uint32_t) 204 DO_VLDR(vldrh_sw, MO_TESW, 2, int16_t, ldw, 4, int32_t) 205 DO_VLDR(vldrh_uw, MO_TEUW, 2, uint16_t, ldw, 4, uint32_t) 206 207 DO_VSTR(vstrb_h, MO_UB, 1, stb, 2, int16_t) 208 DO_VSTR(vstrb_w, MO_UB, 1, stb, 4, int32_t) 209 DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) 210 211 #undef DO_VLDR 212 #undef DO_VSTR 213 214 /* 215 * Gather loads/scatter stores. Here each element of Qm specifies 216 * an offset to use from the base register Rm. In the _os_ versions 217 * that offset is scaled by the element size. 218 * For loads, predicated lanes are zeroed instead of retaining 219 * their previous values. 220 */ 221 #define DO_VLDR_SG(OP, MFLAG, MTYPE, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN, WB)\ 222 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 223 uint32_t base) \ 224 { \ 225 TYPE *d = vd; \ 226 OFFTYPE *m = vm; \ 227 uint16_t mask = mve_element_mask(env); \ 228 uint16_t eci_mask = mve_eci_mask(env); \ 229 unsigned e; \ 230 uint32_t addr; \ 231 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 232 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 233 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 234 if (!(eci_mask & 1)) { \ 235 continue; \ 236 } \ 237 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 238 d[H##ESIZE(e)] = (mask & 1) ? \ 239 (MTYPE)cpu_##LDTYPE##_mmu(env, addr, oi, GETPC()) : 0; \ 240 if (WB) { \ 241 m[H##ESIZE(e)] = addr; \ 242 } \ 243 } \ 244 mve_advance_vpt(env); \ 245 } 246 247 /* We know here TYPE is unsigned so always the same as the offset type */ 248 #define DO_VSTR_SG(OP, STTYPE, ESIZE, TYPE, ADDRFN, WB) \ 249 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 250 uint32_t base) \ 251 { \ 252 TYPE *d = vd; \ 253 TYPE *m = vm; \ 254 uint16_t mask = mve_element_mask(env); \ 255 uint16_t eci_mask = mve_eci_mask(env); \ 256 unsigned e; \ 257 uint32_t addr; \ 258 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 259 if (!(eci_mask & 1)) { \ 260 continue; \ 261 } \ 262 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 263 if (mask & 1) { \ 264 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 265 } \ 266 if (WB) { \ 267 m[H##ESIZE(e)] = addr; \ 268 } \ 269 } \ 270 mve_advance_vpt(env); \ 271 } 272 273 /* 274 * 64-bit accesses are slightly different: they are done as two 32-bit 275 * accesses, controlled by the predicate mask for the relevant beat, 276 * and with a single 32-bit offset in the first of the two Qm elements. 277 * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little). 278 * Address writeback happens on the odd beats and updates the address 279 * stored in the even-beat element. 280 */ 281 #define DO_VLDR64_SG(OP, ADDRFN, WB) \ 282 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 283 uint32_t base) \ 284 { \ 285 uint32_t *d = vd; \ 286 uint32_t *m = vm; \ 287 uint16_t mask = mve_element_mask(env); \ 288 uint16_t eci_mask = mve_eci_mask(env); \ 289 unsigned e; \ 290 uint32_t addr; \ 291 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 292 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 293 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 294 if (!(eci_mask & 1)) { \ 295 continue; \ 296 } \ 297 addr = ADDRFN(base, m[H4(e & ~1)]); \ 298 addr += 4 * (e & 1); \ 299 d[H4(e)] = (mask & 1) ? cpu_ldl_mmu(env, addr, oi, GETPC()) : 0; \ 300 if (WB && (e & 1)) { \ 301 m[H4(e & ~1)] = addr - 4; \ 302 } \ 303 } \ 304 mve_advance_vpt(env); \ 305 } 306 307 #define DO_VSTR64_SG(OP, ADDRFN, WB) \ 308 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 309 uint32_t base) \ 310 { \ 311 uint32_t *d = vd; \ 312 uint32_t *m = vm; \ 313 uint16_t mask = mve_element_mask(env); \ 314 uint16_t eci_mask = mve_eci_mask(env); \ 315 unsigned e; \ 316 uint32_t addr; \ 317 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 318 if (!(eci_mask & 1)) { \ 319 continue; \ 320 } \ 321 addr = ADDRFN(base, m[H4(e & ~1)]); \ 322 addr += 4 * (e & 1); \ 323 if (mask & 1) { \ 324 cpu_stl_data_ra(env, addr, d[H4(e)], GETPC()); \ 325 } \ 326 if (WB && (e & 1)) { \ 327 m[H4(e & ~1)] = addr - 4; \ 328 } \ 329 } \ 330 mve_advance_vpt(env); \ 331 } 332 333 #define ADDR_ADD(BASE, OFFSET) ((BASE) + (OFFSET)) 334 #define ADDR_ADD_OSH(BASE, OFFSET) ((BASE) + ((OFFSET) << 1)) 335 #define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2)) 336 #define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3)) 337 338 DO_VLDR_SG(vldrb_sg_sh, MO_SB, int8_t, ldb, 2, int16_t, uint16_t, ADDR_ADD, false) 339 DO_VLDR_SG(vldrb_sg_sw, MO_SB, int8_t, ldb, 4, int32_t, uint32_t, ADDR_ADD, false) 340 DO_VLDR_SG(vldrh_sg_sw, MO_TESW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_ADD, false) 341 342 DO_VLDR_SG(vldrb_sg_ub, MO_UB, uint8_t, ldb, 1, uint8_t, uint8_t, ADDR_ADD, false) 343 DO_VLDR_SG(vldrb_sg_uh, MO_UB, uint8_t, ldb, 2, uint16_t, uint16_t, ADDR_ADD, false) 344 DO_VLDR_SG(vldrb_sg_uw, MO_UB, uint8_t, ldb, 4, uint32_t, uint32_t, ADDR_ADD, false) 345 DO_VLDR_SG(vldrh_sg_uh, MO_TEUW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_ADD, false) 346 DO_VLDR_SG(vldrh_sg_uw, MO_TEUW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_ADD, false) 347 DO_VLDR_SG(vldrw_sg_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false) 348 DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) 349 350 DO_VLDR_SG(vldrh_sg_os_sw, MO_TESW, int16_t, ldw, 4, 351 int32_t, uint32_t, ADDR_ADD_OSH, false) 352 DO_VLDR_SG(vldrh_sg_os_uh, MO_TEUW, uint16_t, ldw, 2, 353 uint16_t, uint16_t, ADDR_ADD_OSH, false) 354 DO_VLDR_SG(vldrh_sg_os_uw, MO_TEUW, uint16_t, ldw, 4, 355 uint32_t, uint32_t, ADDR_ADD_OSH, false) 356 DO_VLDR_SG(vldrw_sg_os_uw, MO_TEUL, uint32_t, ldl, 4, 357 uint32_t, uint32_t, ADDR_ADD_OSW, false) 358 DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) 359 360 DO_VSTR_SG(vstrb_sg_ub, stb, 1, uint8_t, ADDR_ADD, false) 361 DO_VSTR_SG(vstrb_sg_uh, stb, 2, uint16_t, ADDR_ADD, false) 362 DO_VSTR_SG(vstrb_sg_uw, stb, 4, uint32_t, ADDR_ADD, false) 363 DO_VSTR_SG(vstrh_sg_uh, stw, 2, uint16_t, ADDR_ADD, false) 364 DO_VSTR_SG(vstrh_sg_uw, stw, 4, uint32_t, ADDR_ADD, false) 365 DO_VSTR_SG(vstrw_sg_uw, stl, 4, uint32_t, ADDR_ADD, false) 366 DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) 367 368 DO_VSTR_SG(vstrh_sg_os_uh, stw, 2, uint16_t, ADDR_ADD_OSH, false) 369 DO_VSTR_SG(vstrh_sg_os_uw, stw, 4, uint32_t, ADDR_ADD_OSH, false) 370 DO_VSTR_SG(vstrw_sg_os_uw, stl, 4, uint32_t, ADDR_ADD_OSW, false) 371 DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) 372 373 DO_VLDR_SG(vldrw_sg_wb_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true) 374 DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) 375 DO_VSTR_SG(vstrw_sg_wb_uw, stl, 4, uint32_t, ADDR_ADD, true) 376 DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) 377 378 /* 379 * Deinterleaving loads/interleaving stores. 380 * 381 * For these helpers we are passed the index of the first Qreg 382 * (VLD2/VST2 will also access Qn+1, VLD4/VST4 access Qn .. Qn+3) 383 * and the value of the base address register Rn. 384 * The helpers are specialized for pattern and element size, so 385 * for instance vld42h is VLD4 with pattern 2, element size MO_16. 386 * 387 * These insns are beatwise but not predicated, so we must honour ECI, 388 * but need not look at mve_element_mask(). 389 * 390 * The pseudocode implements these insns with multiple memory accesses 391 * of the element size, but rules R_VVVG and R_FXDM permit us to make 392 * one 32-bit memory access per beat. 393 */ 394 #define DO_VLD4B(OP, O1, O2, O3, O4) \ 395 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 396 uint32_t base) \ 397 { \ 398 int beat, e; \ 399 uint16_t mask = mve_eci_mask(env); \ 400 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 401 uint32_t addr, data; \ 402 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 403 if ((mask & 1) == 0) { \ 404 /* ECI says skip this beat */ \ 405 continue; \ 406 } \ 407 addr = base + off[beat] * 4; \ 408 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 409 for (e = 0; e < 4; e++, data >>= 8) { \ 410 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 411 qd[H1(off[beat])] = data; \ 412 } \ 413 } \ 414 } 415 416 #define DO_VLD4H(OP, O1, O2) \ 417 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 418 uint32_t base) \ 419 { \ 420 int beat; \ 421 uint16_t mask = mve_eci_mask(env); \ 422 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 423 uint32_t addr, data; \ 424 int y; /* y counts 0 2 0 2 */ \ 425 uint16_t *qd; \ 426 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 427 if ((mask & 1) == 0) { \ 428 /* ECI says skip this beat */ \ 429 continue; \ 430 } \ 431 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 432 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 433 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 434 qd[H2(off[beat])] = data; \ 435 data >>= 16; \ 436 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 437 qd[H2(off[beat])] = data; \ 438 } \ 439 } 440 441 #define DO_VLD4W(OP, O1, O2, O3, O4) \ 442 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 443 uint32_t base) \ 444 { \ 445 int beat; \ 446 uint16_t mask = mve_eci_mask(env); \ 447 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 448 uint32_t addr, data; \ 449 uint32_t *qd; \ 450 int y; \ 451 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 452 if ((mask & 1) == 0) { \ 453 /* ECI says skip this beat */ \ 454 continue; \ 455 } \ 456 addr = base + off[beat] * 4; \ 457 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 458 y = (beat + (O1 & 2)) & 3; \ 459 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 460 qd[H4(off[beat] >> 2)] = data; \ 461 } \ 462 } 463 464 DO_VLD4B(vld40b, 0, 1, 10, 11) 465 DO_VLD4B(vld41b, 2, 3, 12, 13) 466 DO_VLD4B(vld42b, 4, 5, 14, 15) 467 DO_VLD4B(vld43b, 6, 7, 8, 9) 468 469 DO_VLD4H(vld40h, 0, 5) 470 DO_VLD4H(vld41h, 1, 6) 471 DO_VLD4H(vld42h, 2, 7) 472 DO_VLD4H(vld43h, 3, 4) 473 474 DO_VLD4W(vld40w, 0, 1, 10, 11) 475 DO_VLD4W(vld41w, 2, 3, 12, 13) 476 DO_VLD4W(vld42w, 4, 5, 14, 15) 477 DO_VLD4W(vld43w, 6, 7, 8, 9) 478 479 #define DO_VLD2B(OP, O1, O2, O3, O4) \ 480 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 481 uint32_t base) \ 482 { \ 483 int beat, e; \ 484 uint16_t mask = mve_eci_mask(env); \ 485 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 486 uint32_t addr, data; \ 487 uint8_t *qd; \ 488 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 489 if ((mask & 1) == 0) { \ 490 /* ECI says skip this beat */ \ 491 continue; \ 492 } \ 493 addr = base + off[beat] * 2; \ 494 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 495 for (e = 0; e < 4; e++, data >>= 8) { \ 496 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 497 qd[H1(off[beat] + (e >> 1))] = data; \ 498 } \ 499 } \ 500 } 501 502 #define DO_VLD2H(OP, O1, O2, O3, O4) \ 503 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 504 uint32_t base) \ 505 { \ 506 int beat; \ 507 uint16_t mask = mve_eci_mask(env); \ 508 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 509 uint32_t addr, data; \ 510 int e; \ 511 uint16_t *qd; \ 512 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 513 if ((mask & 1) == 0) { \ 514 /* ECI says skip this beat */ \ 515 continue; \ 516 } \ 517 addr = base + off[beat] * 4; \ 518 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 519 for (e = 0; e < 2; e++, data >>= 16) { \ 520 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 521 qd[H2(off[beat])] = data; \ 522 } \ 523 } \ 524 } 525 526 #define DO_VLD2W(OP, O1, O2, O3, O4) \ 527 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 528 uint32_t base) \ 529 { \ 530 int beat; \ 531 uint16_t mask = mve_eci_mask(env); \ 532 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 533 uint32_t addr, data; \ 534 uint32_t *qd; \ 535 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 536 if ((mask & 1) == 0) { \ 537 /* ECI says skip this beat */ \ 538 continue; \ 539 } \ 540 addr = base + off[beat]; \ 541 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 542 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 543 qd[H4(off[beat] >> 3)] = data; \ 544 } \ 545 } 546 547 DO_VLD2B(vld20b, 0, 2, 12, 14) 548 DO_VLD2B(vld21b, 4, 6, 8, 10) 549 550 DO_VLD2H(vld20h, 0, 1, 6, 7) 551 DO_VLD2H(vld21h, 2, 3, 4, 5) 552 553 DO_VLD2W(vld20w, 0, 4, 24, 28) 554 DO_VLD2W(vld21w, 8, 12, 16, 20) 555 556 #define DO_VST4B(OP, O1, O2, O3, O4) \ 557 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 558 uint32_t base) \ 559 { \ 560 int beat, e; \ 561 uint16_t mask = mve_eci_mask(env); \ 562 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 563 uint32_t addr, data; \ 564 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 565 if ((mask & 1) == 0) { \ 566 /* ECI says skip this beat */ \ 567 continue; \ 568 } \ 569 addr = base + off[beat] * 4; \ 570 data = 0; \ 571 for (e = 3; e >= 0; e--) { \ 572 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 573 data = (data << 8) | qd[H1(off[beat])]; \ 574 } \ 575 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 576 } \ 577 } 578 579 #define DO_VST4H(OP, O1, O2) \ 580 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 581 uint32_t base) \ 582 { \ 583 int beat; \ 584 uint16_t mask = mve_eci_mask(env); \ 585 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 586 uint32_t addr, data; \ 587 int y; /* y counts 0 2 0 2 */ \ 588 uint16_t *qd; \ 589 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 590 if ((mask & 1) == 0) { \ 591 /* ECI says skip this beat */ \ 592 continue; \ 593 } \ 594 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 595 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 596 data = qd[H2(off[beat])]; \ 597 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 598 data |= qd[H2(off[beat])] << 16; \ 599 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 600 } \ 601 } 602 603 #define DO_VST4W(OP, O1, O2, O3, O4) \ 604 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 605 uint32_t base) \ 606 { \ 607 int beat; \ 608 uint16_t mask = mve_eci_mask(env); \ 609 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 610 uint32_t addr, data; \ 611 uint32_t *qd; \ 612 int y; \ 613 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 614 if ((mask & 1) == 0) { \ 615 /* ECI says skip this beat */ \ 616 continue; \ 617 } \ 618 addr = base + off[beat] * 4; \ 619 y = (beat + (O1 & 2)) & 3; \ 620 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 621 data = qd[H4(off[beat] >> 2)]; \ 622 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 623 } \ 624 } 625 626 DO_VST4B(vst40b, 0, 1, 10, 11) 627 DO_VST4B(vst41b, 2, 3, 12, 13) 628 DO_VST4B(vst42b, 4, 5, 14, 15) 629 DO_VST4B(vst43b, 6, 7, 8, 9) 630 631 DO_VST4H(vst40h, 0, 5) 632 DO_VST4H(vst41h, 1, 6) 633 DO_VST4H(vst42h, 2, 7) 634 DO_VST4H(vst43h, 3, 4) 635 636 DO_VST4W(vst40w, 0, 1, 10, 11) 637 DO_VST4W(vst41w, 2, 3, 12, 13) 638 DO_VST4W(vst42w, 4, 5, 14, 15) 639 DO_VST4W(vst43w, 6, 7, 8, 9) 640 641 #define DO_VST2B(OP, O1, O2, O3, O4) \ 642 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 643 uint32_t base) \ 644 { \ 645 int beat, e; \ 646 uint16_t mask = mve_eci_mask(env); \ 647 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 648 uint32_t addr, data; \ 649 uint8_t *qd; \ 650 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 651 if ((mask & 1) == 0) { \ 652 /* ECI says skip this beat */ \ 653 continue; \ 654 } \ 655 addr = base + off[beat] * 2; \ 656 data = 0; \ 657 for (e = 3; e >= 0; e--) { \ 658 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 659 data = (data << 8) | qd[H1(off[beat] + (e >> 1))]; \ 660 } \ 661 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 662 } \ 663 } 664 665 #define DO_VST2H(OP, O1, O2, O3, O4) \ 666 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 667 uint32_t base) \ 668 { \ 669 int beat; \ 670 uint16_t mask = mve_eci_mask(env); \ 671 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 672 uint32_t addr, data; \ 673 int e; \ 674 uint16_t *qd; \ 675 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 676 if ((mask & 1) == 0) { \ 677 /* ECI says skip this beat */ \ 678 continue; \ 679 } \ 680 addr = base + off[beat] * 4; \ 681 data = 0; \ 682 for (e = 1; e >= 0; e--) { \ 683 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 684 data = (data << 16) | qd[H2(off[beat])]; \ 685 } \ 686 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 687 } \ 688 } 689 690 #define DO_VST2W(OP, O1, O2, O3, O4) \ 691 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 692 uint32_t base) \ 693 { \ 694 int beat; \ 695 uint16_t mask = mve_eci_mask(env); \ 696 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 697 uint32_t addr, data; \ 698 uint32_t *qd; \ 699 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 700 if ((mask & 1) == 0) { \ 701 /* ECI says skip this beat */ \ 702 continue; \ 703 } \ 704 addr = base + off[beat]; \ 705 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 706 data = qd[H4(off[beat] >> 3)]; \ 707 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 708 } \ 709 } 710 711 DO_VST2B(vst20b, 0, 2, 12, 14) 712 DO_VST2B(vst21b, 4, 6, 8, 10) 713 714 DO_VST2H(vst20h, 0, 1, 6, 7) 715 DO_VST2H(vst21h, 2, 3, 4, 5) 716 717 DO_VST2W(vst20w, 0, 4, 24, 28) 718 DO_VST2W(vst21w, 8, 12, 16, 20) 719 720 /* 721 * The mergemask(D, R, M) macro performs the operation "*D = R" but 722 * storing only the bytes which correspond to 1 bits in M, 723 * leaving other bytes in *D unchanged. We use _Generic 724 * to select the correct implementation based on the type of D. 725 */ 726 727 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 728 { 729 if (mask & 1) { 730 *d = r; 731 } 732 } 733 734 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 735 { 736 mergemask_ub((uint8_t *)d, r, mask); 737 } 738 739 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 740 { 741 uint16_t bmask = expand_pred_b(mask); 742 *d = (*d & ~bmask) | (r & bmask); 743 } 744 745 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 746 { 747 mergemask_uh((uint16_t *)d, r, mask); 748 } 749 750 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 751 { 752 uint32_t bmask = expand_pred_b(mask); 753 *d = (*d & ~bmask) | (r & bmask); 754 } 755 756 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 757 { 758 mergemask_uw((uint32_t *)d, r, mask); 759 } 760 761 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 762 { 763 uint64_t bmask = expand_pred_b(mask); 764 *d = (*d & ~bmask) | (r & bmask); 765 } 766 767 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 768 { 769 mergemask_uq((uint64_t *)d, r, mask); 770 } 771 772 #define mergemask(D, R, M) \ 773 _Generic(D, \ 774 uint8_t *: mergemask_ub, \ 775 int8_t *: mergemask_sb, \ 776 uint16_t *: mergemask_uh, \ 777 int16_t *: mergemask_sh, \ 778 uint32_t *: mergemask_uw, \ 779 int32_t *: mergemask_sw, \ 780 uint64_t *: mergemask_uq, \ 781 int64_t *: mergemask_sq)(D, R, M) 782 783 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 784 { 785 /* 786 * The generated code already replicated an 8 or 16 bit constant 787 * into the 32-bit value, so we only need to write the 32-bit 788 * value to all elements of the Qreg, allowing for predication. 789 */ 790 uint32_t *d = vd; 791 uint16_t mask = mve_element_mask(env); 792 unsigned e; 793 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 794 mergemask(&d[H4(e)], val, mask); 795 } 796 mve_advance_vpt(env); 797 } 798 799 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 800 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 801 { \ 802 TYPE *d = vd, *m = vm; \ 803 uint16_t mask = mve_element_mask(env); \ 804 unsigned e; \ 805 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 806 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 807 } \ 808 mve_advance_vpt(env); \ 809 } 810 811 #define DO_CLS_B(N) (clrsb32(N) - 24) 812 #define DO_CLS_H(N) (clrsb32(N) - 16) 813 814 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 815 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 816 DO_1OP(vclsw, 4, int32_t, clrsb32) 817 818 #define DO_CLZ_B(N) (clz32(N) - 24) 819 #define DO_CLZ_H(N) (clz32(N) - 16) 820 821 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 822 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 823 DO_1OP(vclzw, 4, uint32_t, clz32) 824 825 DO_1OP(vrev16b, 2, uint16_t, bswap16) 826 DO_1OP(vrev32b, 4, uint32_t, bswap32) 827 DO_1OP(vrev32h, 4, uint32_t, hswap32) 828 DO_1OP(vrev64b, 8, uint64_t, bswap64) 829 DO_1OP(vrev64h, 8, uint64_t, hswap64) 830 DO_1OP(vrev64w, 8, uint64_t, wswap64) 831 832 #define DO_NOT(N) (~(N)) 833 834 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 835 836 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 837 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 838 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 839 840 DO_1OP(vabsb, 1, int8_t, DO_ABS) 841 DO_1OP(vabsh, 2, int16_t, DO_ABS) 842 DO_1OP(vabsw, 4, int32_t, DO_ABS) 843 844 /* We can do these 64 bits at a time */ 845 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 846 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 847 848 #define DO_NEG(N) (-(N)) 849 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 850 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 851 852 DO_1OP(vnegb, 1, int8_t, DO_NEG) 853 DO_1OP(vnegh, 2, int16_t, DO_NEG) 854 DO_1OP(vnegw, 4, int32_t, DO_NEG) 855 856 /* We can do these 64 bits at a time */ 857 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 858 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 859 860 /* 861 * 1 operand immediates: Vda is destination and possibly also one source. 862 * All these insns work at 64-bit widths. 863 */ 864 #define DO_1OP_IMM(OP, FN) \ 865 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 866 { \ 867 uint64_t *da = vda; \ 868 uint16_t mask = mve_element_mask(env); \ 869 unsigned e; \ 870 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 871 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 872 } \ 873 mve_advance_vpt(env); \ 874 } 875 876 #define DO_MOVI(N, I) (I) 877 #define DO_ANDI(N, I) ((N) & (I)) 878 #define DO_ORRI(N, I) ((N) | (I)) 879 880 DO_1OP_IMM(vmovi, DO_MOVI) 881 DO_1OP_IMM(vandi, DO_ANDI) 882 DO_1OP_IMM(vorri, DO_ORRI) 883 884 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 885 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 886 void *vd, void *vn, void *vm) \ 887 { \ 888 TYPE *d = vd, *n = vn, *m = vm; \ 889 uint16_t mask = mve_element_mask(env); \ 890 unsigned e; \ 891 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 892 mergemask(&d[H##ESIZE(e)], \ 893 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 894 } \ 895 mve_advance_vpt(env); \ 896 } 897 898 /* provide unsigned 2-op helpers for all sizes */ 899 #define DO_2OP_U(OP, FN) \ 900 DO_2OP(OP##b, 1, uint8_t, FN) \ 901 DO_2OP(OP##h, 2, uint16_t, FN) \ 902 DO_2OP(OP##w, 4, uint32_t, FN) 903 904 /* provide signed 2-op helpers for all sizes */ 905 #define DO_2OP_S(OP, FN) \ 906 DO_2OP(OP##b, 1, int8_t, FN) \ 907 DO_2OP(OP##h, 2, int16_t, FN) \ 908 DO_2OP(OP##w, 4, int32_t, FN) 909 910 /* 911 * "Long" operations where two half-sized inputs (taken from either the 912 * top or the bottom of the input vector) produce a double-width result. 913 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 914 */ 915 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 916 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 917 { \ 918 LTYPE *d = vd; \ 919 TYPE *n = vn, *m = vm; \ 920 uint16_t mask = mve_element_mask(env); \ 921 unsigned le; \ 922 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 923 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 924 m[H##ESIZE(le * 2 + TOP)]); \ 925 mergemask(&d[H##LESIZE(le)], r, mask); \ 926 } \ 927 mve_advance_vpt(env); \ 928 } 929 930 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 931 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 932 { \ 933 TYPE *d = vd, *n = vn, *m = vm; \ 934 uint16_t mask = mve_element_mask(env); \ 935 unsigned e; \ 936 bool qc = false; \ 937 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 938 bool sat = false; \ 939 TYPE r_ = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 940 mergemask(&d[H##ESIZE(e)], r_, mask); \ 941 qc |= sat & mask & 1; \ 942 } \ 943 if (qc) { \ 944 env->vfp.qc[0] = qc; \ 945 } \ 946 mve_advance_vpt(env); \ 947 } 948 949 /* provide unsigned 2-op helpers for all sizes */ 950 #define DO_2OP_SAT_U(OP, FN) \ 951 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 952 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 953 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 954 955 /* provide signed 2-op helpers for all sizes */ 956 #define DO_2OP_SAT_S(OP, FN) \ 957 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 958 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 959 DO_2OP_SAT(OP##w, 4, int32_t, FN) 960 961 #define DO_AND(N, M) ((N) & (M)) 962 #define DO_BIC(N, M) ((N) & ~(M)) 963 #define DO_ORR(N, M) ((N) | (M)) 964 #define DO_ORN(N, M) ((N) | ~(M)) 965 #define DO_EOR(N, M) ((N) ^ (M)) 966 967 DO_2OP(vand, 8, uint64_t, DO_AND) 968 DO_2OP(vbic, 8, uint64_t, DO_BIC) 969 DO_2OP(vorr, 8, uint64_t, DO_ORR) 970 DO_2OP(vorn, 8, uint64_t, DO_ORN) 971 DO_2OP(veor, 8, uint64_t, DO_EOR) 972 973 #define DO_ADD(N, M) ((N) + (M)) 974 #define DO_SUB(N, M) ((N) - (M)) 975 #define DO_MUL(N, M) ((N) * (M)) 976 977 DO_2OP_U(vadd, DO_ADD) 978 DO_2OP_U(vsub, DO_SUB) 979 DO_2OP_U(vmul, DO_MUL) 980 981 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 982 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 983 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 984 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 985 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 986 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 987 988 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 989 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 990 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 991 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 992 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 993 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 994 995 /* 996 * Polynomial multiply. We can always do this generating 64 bits 997 * of the result at a time, so we don't need to use DO_2OP_L. 998 */ 999 DO_2OP(vmullpbh, 8, uint64_t, clmul_8x4_even) 1000 DO_2OP(vmullpth, 8, uint64_t, clmul_8x4_odd) 1001 DO_2OP(vmullpbw, 8, uint64_t, clmul_16x2_even) 1002 DO_2OP(vmullptw, 8, uint64_t, clmul_16x2_odd) 1003 1004 /* 1005 * Because the computation type is at least twice as large as required, 1006 * these work for both signed and unsigned source types. 1007 */ 1008 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 1009 { 1010 return (n * m) >> 8; 1011 } 1012 1013 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 1014 { 1015 return (n * m) >> 16; 1016 } 1017 1018 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 1019 { 1020 return (n * m) >> 32; 1021 } 1022 1023 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 1024 { 1025 return (n * m + (1U << 7)) >> 8; 1026 } 1027 1028 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 1029 { 1030 return (n * m + (1U << 15)) >> 16; 1031 } 1032 1033 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 1034 { 1035 return (n * m + (1U << 31)) >> 32; 1036 } 1037 1038 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 1039 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 1040 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 1041 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 1042 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 1043 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 1044 1045 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 1046 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 1047 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 1048 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 1049 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 1050 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 1051 1052 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 1053 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 1054 1055 DO_2OP_S(vmaxs, DO_MAX) 1056 DO_2OP_U(vmaxu, DO_MAX) 1057 DO_2OP_S(vmins, DO_MIN) 1058 DO_2OP_U(vminu, DO_MIN) 1059 1060 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 1061 1062 DO_2OP_S(vabds, DO_ABD) 1063 DO_2OP_U(vabdu, DO_ABD) 1064 1065 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 1066 { 1067 return ((uint64_t)n + m) >> 1; 1068 } 1069 1070 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 1071 { 1072 return ((int64_t)n + m) >> 1; 1073 } 1074 1075 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 1076 { 1077 return ((uint64_t)n - m) >> 1; 1078 } 1079 1080 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 1081 { 1082 return ((int64_t)n - m) >> 1; 1083 } 1084 1085 DO_2OP_S(vhadds, do_vhadd_s) 1086 DO_2OP_U(vhaddu, do_vhadd_u) 1087 DO_2OP_S(vhsubs, do_vhsub_s) 1088 DO_2OP_U(vhsubu, do_vhsub_u) 1089 1090 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1091 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1092 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1093 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1094 1095 DO_2OP_S(vshls, DO_VSHLS) 1096 DO_2OP_U(vshlu, DO_VSHLU) 1097 DO_2OP_S(vrshls, DO_VRSHLS) 1098 DO_2OP_U(vrshlu, DO_VRSHLU) 1099 1100 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 1101 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 1102 1103 DO_2OP_S(vrhadds, DO_RHADD_S) 1104 DO_2OP_U(vrhaddu, DO_RHADD_U) 1105 1106 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 1107 uint32_t inv, uint32_t carry_in, bool update_flags) 1108 { 1109 uint16_t mask = mve_element_mask(env); 1110 unsigned e; 1111 1112 /* If any additions trigger, we will update flags. */ 1113 if (mask & 0x1111) { 1114 update_flags = true; 1115 } 1116 1117 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1118 uint64_t r = carry_in; 1119 r += n[H4(e)]; 1120 r += m[H4(e)] ^ inv; 1121 if (mask & 1) { 1122 carry_in = r >> 32; 1123 } 1124 mergemask(&d[H4(e)], r, mask); 1125 } 1126 1127 if (update_flags) { 1128 /* Store C, clear NZV. */ 1129 env->vfp.fpsr &= ~FPSR_NZCV_MASK; 1130 env->vfp.fpsr |= carry_in * FPSR_C; 1131 } 1132 mve_advance_vpt(env); 1133 } 1134 1135 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 1136 { 1137 bool carry_in = env->vfp.fpsr & FPSR_C; 1138 do_vadc(env, vd, vn, vm, 0, carry_in, false); 1139 } 1140 1141 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 1142 { 1143 bool carry_in = env->vfp.fpsr & FPSR_C; 1144 do_vadc(env, vd, vn, vm, -1, carry_in, false); 1145 } 1146 1147 1148 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 1149 { 1150 do_vadc(env, vd, vn, vm, 0, 0, true); 1151 } 1152 1153 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 1154 { 1155 do_vadc(env, vd, vn, vm, -1, 1, true); 1156 } 1157 1158 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 1159 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 1160 { \ 1161 TYPE *d = vd, *n = vn, *m = vm; \ 1162 uint16_t mask = mve_element_mask(env); \ 1163 unsigned e; \ 1164 TYPE r[16 / ESIZE]; \ 1165 /* Calculate all results first to avoid overwriting inputs */ \ 1166 for (e = 0; e < 16 / ESIZE; e++) { \ 1167 if (!(e & 1)) { \ 1168 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 1169 } else { \ 1170 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 1171 } \ 1172 } \ 1173 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1174 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 1175 } \ 1176 mve_advance_vpt(env); \ 1177 } 1178 1179 #define DO_VCADD_ALL(OP, FN0, FN1) \ 1180 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 1181 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 1182 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 1183 1184 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 1185 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 1186 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 1187 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 1188 1189 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 1190 { 1191 if (val > max) { 1192 *s = true; 1193 return max; 1194 } else if (val < min) { 1195 *s = true; 1196 return min; 1197 } 1198 return val; 1199 } 1200 1201 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 1202 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 1203 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 1204 1205 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 1206 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 1207 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 1208 1209 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 1210 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 1211 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 1212 1213 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 1214 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 1215 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 1216 1217 /* 1218 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 1219 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 1220 */ 1221 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 1222 INT8_MIN, INT8_MAX, s) 1223 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 1224 INT16_MIN, INT16_MAX, s) 1225 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 1226 INT32_MIN, INT32_MAX, s) 1227 1228 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 1229 INT8_MIN, INT8_MAX, s) 1230 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 1231 INT16_MIN, INT16_MAX, s) 1232 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 1233 INT32_MIN, INT32_MAX, s) 1234 1235 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 1236 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 1237 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 1238 1239 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 1240 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 1241 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 1242 1243 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 1244 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 1245 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 1246 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 1247 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 1248 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 1249 1250 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 1251 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 1252 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 1253 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 1254 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 1255 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 1256 1257 /* 1258 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 1259 * and friends wanting a uint32_t* sat and our needing a bool*. 1260 */ 1261 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 1262 ({ \ 1263 uint32_t su32 = 0; \ 1264 typeof(N) qrshl_ret = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 1265 if (su32) { \ 1266 *satp = true; \ 1267 } \ 1268 qrshl_ret; \ 1269 }) 1270 1271 #define DO_SQSHL_OP(N, M, satp) \ 1272 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 1273 #define DO_UQSHL_OP(N, M, satp) \ 1274 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 1275 #define DO_SQRSHL_OP(N, M, satp) \ 1276 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 1277 #define DO_UQRSHL_OP(N, M, satp) \ 1278 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 1279 #define DO_SUQSHL_OP(N, M, satp) \ 1280 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 1281 1282 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 1283 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 1284 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 1285 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 1286 1287 /* 1288 * Multiply add dual returning high half 1289 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 1290 * whether to add the rounding constant, and the pointer to the 1291 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 1292 * saturate to twice the input size and return the high half; or 1293 * (A * B - C * D) etc for VQDMLSDH. 1294 */ 1295 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 1296 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1297 void *vm) \ 1298 { \ 1299 TYPE *d = vd, *n = vn, *m = vm; \ 1300 uint16_t mask = mve_element_mask(env); \ 1301 unsigned e; \ 1302 bool qc = false; \ 1303 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1304 bool sat = false; \ 1305 if ((e & 1) == XCHG) { \ 1306 TYPE vqdmladh_ret = FN(n[H##ESIZE(e)], \ 1307 m[H##ESIZE(e - XCHG)], \ 1308 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 1309 m[H##ESIZE(e + (1 - XCHG))], \ 1310 ROUND, &sat); \ 1311 mergemask(&d[H##ESIZE(e)], vqdmladh_ret, mask); \ 1312 qc |= sat & mask & 1; \ 1313 } \ 1314 } \ 1315 if (qc) { \ 1316 env->vfp.qc[0] = qc; \ 1317 } \ 1318 mve_advance_vpt(env); \ 1319 } 1320 1321 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1322 int round, bool *sat) 1323 { 1324 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 1325 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1326 } 1327 1328 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1329 int round, bool *sat) 1330 { 1331 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 1332 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1333 } 1334 1335 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1336 int round, bool *sat) 1337 { 1338 int64_t m1 = (int64_t)a * b; 1339 int64_t m2 = (int64_t)c * d; 1340 int64_t r; 1341 /* 1342 * Architecturally we should do the entire add, double, round 1343 * and then check for saturation. We do three saturating adds, 1344 * but we need to be careful about the order. If the first 1345 * m1 + m2 saturates then it's impossible for the *2+rc to 1346 * bring it back into the non-saturated range. However, if 1347 * m1 + m2 is negative then it's possible that doing the doubling 1348 * would take the intermediate result below INT64_MAX and the 1349 * addition of the rounding constant then brings it back in range. 1350 * So we add half the rounding constant before doubling rather 1351 * than adding the rounding constant after the doubling. 1352 */ 1353 if (sadd64_overflow(m1, m2, &r) || 1354 sadd64_overflow(r, (round << 30), &r) || 1355 sadd64_overflow(r, r, &r)) { 1356 *sat = true; 1357 return r < 0 ? INT32_MAX : INT32_MIN; 1358 } 1359 return r >> 32; 1360 } 1361 1362 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1363 int round, bool *sat) 1364 { 1365 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 1366 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1367 } 1368 1369 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1370 int round, bool *sat) 1371 { 1372 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 1373 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1374 } 1375 1376 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1377 int round, bool *sat) 1378 { 1379 int64_t m1 = (int64_t)a * b; 1380 int64_t m2 = (int64_t)c * d; 1381 int64_t r; 1382 /* The same ordering issue as in do_vqdmladh_w applies here too */ 1383 if (ssub64_overflow(m1, m2, &r) || 1384 sadd64_overflow(r, (round << 30), &r) || 1385 sadd64_overflow(r, r, &r)) { 1386 *sat = true; 1387 return r < 0 ? INT32_MAX : INT32_MIN; 1388 } 1389 return r >> 32; 1390 } 1391 1392 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 1393 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 1394 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 1395 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 1396 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 1397 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 1398 1399 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 1400 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 1401 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 1402 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 1403 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 1404 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 1405 1406 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 1407 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 1408 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 1409 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 1410 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 1411 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 1412 1413 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 1414 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 1415 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 1416 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 1417 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 1418 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 1419 1420 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 1421 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1422 uint32_t rm) \ 1423 { \ 1424 TYPE *d = vd, *n = vn; \ 1425 TYPE m = rm; \ 1426 uint16_t mask = mve_element_mask(env); \ 1427 unsigned e; \ 1428 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1429 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 1430 } \ 1431 mve_advance_vpt(env); \ 1432 } 1433 1434 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 1435 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1436 uint32_t rm) \ 1437 { \ 1438 TYPE *d = vd, *n = vn; \ 1439 TYPE m = rm; \ 1440 uint16_t mask = mve_element_mask(env); \ 1441 unsigned e; \ 1442 bool qc = false; \ 1443 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1444 bool sat = false; \ 1445 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 1446 mask); \ 1447 qc |= sat & mask & 1; \ 1448 } \ 1449 if (qc) { \ 1450 env->vfp.qc[0] = qc; \ 1451 } \ 1452 mve_advance_vpt(env); \ 1453 } 1454 1455 /* "accumulating" version where FN takes d as well as n and m */ 1456 #define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1457 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1458 uint32_t rm) \ 1459 { \ 1460 TYPE *d = vd, *n = vn; \ 1461 TYPE m = rm; \ 1462 uint16_t mask = mve_element_mask(env); \ 1463 unsigned e; \ 1464 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1465 mergemask(&d[H##ESIZE(e)], \ 1466 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \ 1467 } \ 1468 mve_advance_vpt(env); \ 1469 } 1470 1471 #define DO_2OP_SAT_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1472 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1473 uint32_t rm) \ 1474 { \ 1475 TYPE *d = vd, *n = vn; \ 1476 TYPE m = rm; \ 1477 uint16_t mask = mve_element_mask(env); \ 1478 unsigned e; \ 1479 bool qc = false; \ 1480 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1481 bool sat = false; \ 1482 mergemask(&d[H##ESIZE(e)], \ 1483 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m, &sat), \ 1484 mask); \ 1485 qc |= sat & mask & 1; \ 1486 } \ 1487 if (qc) { \ 1488 env->vfp.qc[0] = qc; \ 1489 } \ 1490 mve_advance_vpt(env); \ 1491 } 1492 1493 /* provide unsigned 2-op scalar helpers for all sizes */ 1494 #define DO_2OP_SCALAR_U(OP, FN) \ 1495 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 1496 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 1497 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 1498 #define DO_2OP_SCALAR_S(OP, FN) \ 1499 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 1500 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 1501 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 1502 1503 #define DO_2OP_ACC_SCALAR_U(OP, FN) \ 1504 DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \ 1505 DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \ 1506 DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN) 1507 1508 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 1509 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 1510 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 1511 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 1512 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 1513 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 1514 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 1515 1516 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 1517 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 1518 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 1519 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 1520 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 1521 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 1522 1523 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 1524 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 1525 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 1526 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 1527 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 1528 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 1529 1530 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 1531 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 1532 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 1533 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 1534 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 1535 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 1536 1537 static int8_t do_vqdmlah_b(int8_t a, int8_t b, int8_t c, int round, bool *sat) 1538 { 1539 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 8) + (round << 7); 1540 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1541 } 1542 1543 static int16_t do_vqdmlah_h(int16_t a, int16_t b, int16_t c, 1544 int round, bool *sat) 1545 { 1546 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 16) + (round << 15); 1547 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1548 } 1549 1550 static int32_t do_vqdmlah_w(int32_t a, int32_t b, int32_t c, 1551 int round, bool *sat) 1552 { 1553 /* 1554 * Architecturally we should do the entire add, double, round 1555 * and then check for saturation. We do three saturating adds, 1556 * but we need to be careful about the order. If the first 1557 * m1 + m2 saturates then it's impossible for the *2+rc to 1558 * bring it back into the non-saturated range. However, if 1559 * m1 + m2 is negative then it's possible that doing the doubling 1560 * would take the intermediate result below INT64_MAX and the 1561 * addition of the rounding constant then brings it back in range. 1562 * So we add half the rounding constant and half the "c << esize" 1563 * before doubling rather than adding the rounding constant after 1564 * the doubling. 1565 */ 1566 int64_t m1 = (int64_t)a * b; 1567 int64_t m2 = (int64_t)c << 31; 1568 int64_t r; 1569 if (sadd64_overflow(m1, m2, &r) || 1570 sadd64_overflow(r, (round << 30), &r) || 1571 sadd64_overflow(r, r, &r)) { 1572 *sat = true; 1573 return r < 0 ? INT32_MAX : INT32_MIN; 1574 } 1575 return r >> 32; 1576 } 1577 1578 /* 1579 * The *MLAH insns are vector * scalar + vector; 1580 * the *MLASH insns are vector * vector + scalar 1581 */ 1582 #define DO_VQDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 0, S) 1583 #define DO_VQDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 0, S) 1584 #define DO_VQDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 0, S) 1585 #define DO_VQRDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 1, S) 1586 #define DO_VQRDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 1, S) 1587 #define DO_VQRDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 1, S) 1588 1589 #define DO_VQDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 0, S) 1590 #define DO_VQDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 0, S) 1591 #define DO_VQDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 0, S) 1592 #define DO_VQRDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 1, S) 1593 #define DO_VQRDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 1, S) 1594 #define DO_VQRDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 1, S) 1595 1596 DO_2OP_SAT_ACC_SCALAR(vqdmlahb, 1, int8_t, DO_VQDMLAH_B) 1597 DO_2OP_SAT_ACC_SCALAR(vqdmlahh, 2, int16_t, DO_VQDMLAH_H) 1598 DO_2OP_SAT_ACC_SCALAR(vqdmlahw, 4, int32_t, DO_VQDMLAH_W) 1599 DO_2OP_SAT_ACC_SCALAR(vqrdmlahb, 1, int8_t, DO_VQRDMLAH_B) 1600 DO_2OP_SAT_ACC_SCALAR(vqrdmlahh, 2, int16_t, DO_VQRDMLAH_H) 1601 DO_2OP_SAT_ACC_SCALAR(vqrdmlahw, 4, int32_t, DO_VQRDMLAH_W) 1602 1603 DO_2OP_SAT_ACC_SCALAR(vqdmlashb, 1, int8_t, DO_VQDMLASH_B) 1604 DO_2OP_SAT_ACC_SCALAR(vqdmlashh, 2, int16_t, DO_VQDMLASH_H) 1605 DO_2OP_SAT_ACC_SCALAR(vqdmlashw, 4, int32_t, DO_VQDMLASH_W) 1606 DO_2OP_SAT_ACC_SCALAR(vqrdmlashb, 1, int8_t, DO_VQRDMLASH_B) 1607 DO_2OP_SAT_ACC_SCALAR(vqrdmlashh, 2, int16_t, DO_VQRDMLASH_H) 1608 DO_2OP_SAT_ACC_SCALAR(vqrdmlashw, 4, int32_t, DO_VQRDMLASH_W) 1609 1610 /* Vector by scalar plus vector */ 1611 #define DO_VMLA(D, N, M) ((N) * (M) + (D)) 1612 1613 DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA) 1614 1615 /* Vector by vector plus scalar */ 1616 #define DO_VMLAS(D, N, M) ((N) * (D) + (M)) 1617 1618 DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS) 1619 1620 /* 1621 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 1622 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 1623 * SATMASK specifies which bits of the predicate mask matter for determining 1624 * whether to propagate a saturation indication into FPSCR.QC -- for 1625 * the 16x16->32 case we must check only the bit corresponding to the T or B 1626 * half that we used, but for the 32x32->64 case we propagate if the mask 1627 * bit is set for either half. 1628 */ 1629 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1630 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1631 uint32_t rm) \ 1632 { \ 1633 LTYPE *d = vd; \ 1634 TYPE *n = vn; \ 1635 TYPE m = rm; \ 1636 uint16_t mask = mve_element_mask(env); \ 1637 unsigned le; \ 1638 bool qc = false; \ 1639 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1640 bool sat = false; \ 1641 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 1642 mergemask(&d[H##LESIZE(le)], r, mask); \ 1643 qc |= sat && (mask & SATMASK); \ 1644 } \ 1645 if (qc) { \ 1646 env->vfp.qc[0] = qc; \ 1647 } \ 1648 mve_advance_vpt(env); \ 1649 } 1650 1651 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1652 { 1653 int64_t r = ((int64_t)n * m) * 2; 1654 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1655 } 1656 1657 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1658 { 1659 /* The multiply can't overflow, but the doubling might */ 1660 int64_t r = (int64_t)n * m; 1661 if (r > INT64_MAX / 2) { 1662 *sat = true; 1663 return INT64_MAX; 1664 } else if (r < INT64_MIN / 2) { 1665 *sat = true; 1666 return INT64_MIN; 1667 } else { 1668 return r * 2; 1669 } 1670 } 1671 1672 #define SATMASK16B 1 1673 #define SATMASK16T (1 << 2) 1674 #define SATMASK32 ((1 << 4) | 1) 1675 1676 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1677 do_qdmullh, SATMASK16B) 1678 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1679 do_qdmullw, SATMASK32) 1680 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1681 do_qdmullh, SATMASK16T) 1682 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1683 do_qdmullw, SATMASK32) 1684 1685 /* 1686 * Long saturating ops 1687 */ 1688 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1689 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1690 void *vm) \ 1691 { \ 1692 LTYPE *d = vd; \ 1693 TYPE *n = vn, *m = vm; \ 1694 uint16_t mask = mve_element_mask(env); \ 1695 unsigned le; \ 1696 bool qc = false; \ 1697 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1698 bool sat = false; \ 1699 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1700 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1701 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1702 qc |= sat && (mask & SATMASK); \ 1703 } \ 1704 if (qc) { \ 1705 env->vfp.qc[0] = qc; \ 1706 } \ 1707 mve_advance_vpt(env); \ 1708 } 1709 1710 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1711 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1712 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1713 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1714 1715 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1716 { 1717 m &= 0xff; 1718 if (m == 0) { 1719 return 0; 1720 } 1721 n = revbit8(n); 1722 if (m < 8) { 1723 n >>= 8 - m; 1724 } 1725 return n; 1726 } 1727 1728 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1729 { 1730 m &= 0xff; 1731 if (m == 0) { 1732 return 0; 1733 } 1734 n = revbit16(n); 1735 if (m < 16) { 1736 n >>= 16 - m; 1737 } 1738 return n; 1739 } 1740 1741 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1742 { 1743 m &= 0xff; 1744 if (m == 0) { 1745 return 0; 1746 } 1747 n = revbit32(n); 1748 if (m < 32) { 1749 n >>= 32 - m; 1750 } 1751 return n; 1752 } 1753 1754 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1755 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1756 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1757 1758 /* 1759 * Multiply add long dual accumulate ops. 1760 */ 1761 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1762 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1763 void *vm, uint64_t a) \ 1764 { \ 1765 uint16_t mask = mve_element_mask(env); \ 1766 unsigned e; \ 1767 TYPE *n = vn, *m = vm; \ 1768 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1769 if (mask & 1) { \ 1770 if (e & 1) { \ 1771 a ODDACC \ 1772 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1773 } else { \ 1774 a EVENACC \ 1775 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1776 } \ 1777 } \ 1778 } \ 1779 mve_advance_vpt(env); \ 1780 return a; \ 1781 } 1782 1783 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1784 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1785 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1786 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1787 1788 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1789 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1790 1791 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1792 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1793 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1794 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1795 1796 /* 1797 * Multiply add dual accumulate ops 1798 */ 1799 #define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1800 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1801 void *vm, uint32_t a) \ 1802 { \ 1803 uint16_t mask = mve_element_mask(env); \ 1804 unsigned e; \ 1805 TYPE *n = vn, *m = vm; \ 1806 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1807 if (mask & 1) { \ 1808 if (e & 1) { \ 1809 a ODDACC \ 1810 n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1811 } else { \ 1812 a EVENACC \ 1813 n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1814 } \ 1815 } \ 1816 } \ 1817 mve_advance_vpt(env); \ 1818 return a; \ 1819 } 1820 1821 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ 1822 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \ 1823 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \ 1824 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC) 1825 1826 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ 1827 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \ 1828 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \ 1829 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC) 1830 1831 DO_DAV_S(vmladavs, false, +=, +=) 1832 DO_DAV_U(vmladavu, false, +=, +=) 1833 DO_DAV_S(vmlsdav, false, +=, -=) 1834 DO_DAV_S(vmladavsx, true, +=, +=) 1835 DO_DAV_S(vmlsdavx, true, +=, -=) 1836 1837 /* 1838 * Rounding multiply add long dual accumulate high. In the pseudocode 1839 * this is implemented with a 72-bit internal accumulator value of which 1840 * the top 64 bits are returned. We optimize this to avoid having to 1841 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1842 * is squashed back into 64-bits after each beat. 1843 */ 1844 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1845 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1846 void *vm, uint64_t a) \ 1847 { \ 1848 uint16_t mask = mve_element_mask(env); \ 1849 unsigned e; \ 1850 TYPE *n = vn, *m = vm; \ 1851 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1852 if (mask & 1) { \ 1853 LTYPE mul; \ 1854 if (e & 1) { \ 1855 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1856 if (SUB) { \ 1857 mul = -mul; \ 1858 } \ 1859 } else { \ 1860 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1861 } \ 1862 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1863 a += mul; \ 1864 } \ 1865 } \ 1866 mve_advance_vpt(env); \ 1867 return a; \ 1868 } 1869 1870 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1871 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1872 1873 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1874 1875 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1876 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1877 1878 /* Vector add across vector */ 1879 #define DO_VADDV(OP, ESIZE, TYPE) \ 1880 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1881 uint32_t ra) \ 1882 { \ 1883 uint16_t mask = mve_element_mask(env); \ 1884 unsigned e; \ 1885 TYPE *m = vm; \ 1886 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1887 if (mask & 1) { \ 1888 ra += m[H##ESIZE(e)]; \ 1889 } \ 1890 } \ 1891 mve_advance_vpt(env); \ 1892 return ra; \ 1893 } \ 1894 1895 DO_VADDV(vaddvsb, 1, int8_t) 1896 DO_VADDV(vaddvsh, 2, int16_t) 1897 DO_VADDV(vaddvsw, 4, int32_t) 1898 DO_VADDV(vaddvub, 1, uint8_t) 1899 DO_VADDV(vaddvuh, 2, uint16_t) 1900 DO_VADDV(vaddvuw, 4, uint32_t) 1901 1902 /* 1903 * Vector max/min across vector. Unlike VADDV, we must 1904 * read ra as the element size, not its full width. 1905 * We work with int64_t internally for simplicity. 1906 */ 1907 #define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \ 1908 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1909 uint32_t ra_in) \ 1910 { \ 1911 uint16_t mask = mve_element_mask(env); \ 1912 unsigned e; \ 1913 TYPE *m = vm; \ 1914 int64_t ra = (RATYPE)ra_in; \ 1915 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1916 if (mask & 1) { \ 1917 ra = FN(ra, m[H##ESIZE(e)]); \ 1918 } \ 1919 } \ 1920 mve_advance_vpt(env); \ 1921 return ra; \ 1922 } \ 1923 1924 #define DO_VMAXMINV_U(INSN, FN) \ 1925 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \ 1926 DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \ 1927 DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN) 1928 #define DO_VMAXMINV_S(INSN, FN) \ 1929 DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \ 1930 DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \ 1931 DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN) 1932 1933 /* 1934 * Helpers for max and min of absolute values across vector: 1935 * note that we only take the absolute value of 'm', not 'n' 1936 */ 1937 static int64_t do_maxa(int64_t n, int64_t m) 1938 { 1939 if (m < 0) { 1940 m = -m; 1941 } 1942 return MAX(n, m); 1943 } 1944 1945 static int64_t do_mina(int64_t n, int64_t m) 1946 { 1947 if (m < 0) { 1948 m = -m; 1949 } 1950 return MIN(n, m); 1951 } 1952 1953 DO_VMAXMINV_S(vmaxvs, DO_MAX) 1954 DO_VMAXMINV_U(vmaxvu, DO_MAX) 1955 DO_VMAXMINV_S(vminvs, DO_MIN) 1956 DO_VMAXMINV_U(vminvu, DO_MIN) 1957 /* 1958 * VMAXAV, VMINAV treat the general purpose input as unsigned 1959 * and the vector elements as signed. 1960 */ 1961 DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa) 1962 DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa) 1963 DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa) 1964 DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) 1965 DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) 1966 DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) 1967 1968 #define DO_VABAV(OP, ESIZE, TYPE) \ 1969 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1970 void *vm, uint32_t ra) \ 1971 { \ 1972 uint16_t mask = mve_element_mask(env); \ 1973 unsigned e; \ 1974 TYPE *m = vm, *n = vn; \ 1975 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1976 if (mask & 1) { \ 1977 int64_t n0 = n[H##ESIZE(e)]; \ 1978 int64_t m0 = m[H##ESIZE(e)]; \ 1979 uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \ 1980 ra += r; \ 1981 } \ 1982 } \ 1983 mve_advance_vpt(env); \ 1984 return ra; \ 1985 } 1986 1987 DO_VABAV(vabavsb, 1, int8_t) 1988 DO_VABAV(vabavsh, 2, int16_t) 1989 DO_VABAV(vabavsw, 4, int32_t) 1990 DO_VABAV(vabavub, 1, uint8_t) 1991 DO_VABAV(vabavuh, 2, uint16_t) 1992 DO_VABAV(vabavuw, 4, uint32_t) 1993 1994 #define DO_VADDLV(OP, TYPE, LTYPE) \ 1995 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1996 uint64_t ra) \ 1997 { \ 1998 uint16_t mask = mve_element_mask(env); \ 1999 unsigned e; \ 2000 TYPE *m = vm; \ 2001 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 2002 if (mask & 1) { \ 2003 ra += (LTYPE)m[H4(e)]; \ 2004 } \ 2005 } \ 2006 mve_advance_vpt(env); \ 2007 return ra; \ 2008 } \ 2009 2010 DO_VADDLV(vaddlv_s, int32_t, int64_t) 2011 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 2012 2013 /* Shifts by immediate */ 2014 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 2015 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2016 void *vm, uint32_t shift) \ 2017 { \ 2018 TYPE *d = vd, *m = vm; \ 2019 uint16_t mask = mve_element_mask(env); \ 2020 unsigned e; \ 2021 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2022 mergemask(&d[H##ESIZE(e)], \ 2023 FN(m[H##ESIZE(e)], shift), mask); \ 2024 } \ 2025 mve_advance_vpt(env); \ 2026 } 2027 2028 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 2029 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2030 void *vm, uint32_t shift) \ 2031 { \ 2032 TYPE *d = vd, *m = vm; \ 2033 uint16_t mask = mve_element_mask(env); \ 2034 unsigned e; \ 2035 bool qc = false; \ 2036 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2037 bool sat = false; \ 2038 mergemask(&d[H##ESIZE(e)], \ 2039 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 2040 qc |= sat & mask & 1; \ 2041 } \ 2042 if (qc) { \ 2043 env->vfp.qc[0] = qc; \ 2044 } \ 2045 mve_advance_vpt(env); \ 2046 } 2047 2048 /* provide unsigned 2-op shift helpers for all sizes */ 2049 #define DO_2SHIFT_U(OP, FN) \ 2050 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 2051 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 2052 DO_2SHIFT(OP##w, 4, uint32_t, FN) 2053 #define DO_2SHIFT_S(OP, FN) \ 2054 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 2055 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 2056 DO_2SHIFT(OP##w, 4, int32_t, FN) 2057 2058 #define DO_2SHIFT_SAT_U(OP, FN) \ 2059 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 2060 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 2061 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 2062 #define DO_2SHIFT_SAT_S(OP, FN) \ 2063 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 2064 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 2065 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 2066 2067 DO_2SHIFT_U(vshli_u, DO_VSHLU) 2068 DO_2SHIFT_S(vshli_s, DO_VSHLS) 2069 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 2070 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 2071 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 2072 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 2073 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 2074 DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP) 2075 DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP) 2076 2077 /* Shift-and-insert; we always work with 64 bits at a time */ 2078 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 2079 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2080 void *vm, uint32_t shift) \ 2081 { \ 2082 uint64_t *d = vd, *m = vm; \ 2083 uint16_t mask; \ 2084 uint64_t shiftmask; \ 2085 unsigned e; \ 2086 if (shift == ESIZE * 8) { \ 2087 /* \ 2088 * Only VSRI can shift by <dt>; it should mean "don't \ 2089 * update the destination". The generic logic can't handle \ 2090 * this because it would try to shift by an out-of-range \ 2091 * amount, so special case it here. \ 2092 */ \ 2093 goto done; \ 2094 } \ 2095 assert(shift < ESIZE * 8); \ 2096 mask = mve_element_mask(env); \ 2097 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 2098 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 2099 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 2100 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 2101 (d[H8(e)] & ~shiftmask); \ 2102 mergemask(&d[H8(e)], r, mask); \ 2103 } \ 2104 done: \ 2105 mve_advance_vpt(env); \ 2106 } 2107 2108 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 2109 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 2110 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 2111 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 2112 2113 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 2114 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 2115 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 2116 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 2117 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 2118 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 2119 2120 /* 2121 * Long shifts taking half-sized inputs from top or bottom of the input 2122 * vector and producing a double-width result. ESIZE, TYPE are for 2123 * the input, and LESIZE, LTYPE for the output. 2124 * Unlike the normal shift helpers, we do not handle negative shift counts, 2125 * because the long shift is strictly left-only. 2126 */ 2127 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2128 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2129 void *vm, uint32_t shift) \ 2130 { \ 2131 LTYPE *d = vd; \ 2132 TYPE *m = vm; \ 2133 uint16_t mask = mve_element_mask(env); \ 2134 unsigned le; \ 2135 assert(shift <= 16); \ 2136 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2137 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 2138 mergemask(&d[H##LESIZE(le)], r, mask); \ 2139 } \ 2140 mve_advance_vpt(env); \ 2141 } 2142 2143 #define DO_VSHLL_ALL(OP, TOP) \ 2144 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 2145 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 2146 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 2147 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 2148 2149 DO_VSHLL_ALL(vshllb, false) 2150 DO_VSHLL_ALL(vshllt, true) 2151 2152 /* 2153 * Narrowing right shifts, taking a double sized input, shifting it 2154 * and putting the result in either the top or bottom half of the output. 2155 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 2156 */ 2157 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2158 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2159 void *vm, uint32_t shift) \ 2160 { \ 2161 LTYPE *m = vm; \ 2162 TYPE *d = vd; \ 2163 uint16_t mask = mve_element_mask(env); \ 2164 unsigned le; \ 2165 mask >>= ESIZE * TOP; \ 2166 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2167 TYPE r = FN(m[H##LESIZE(le)], shift); \ 2168 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2169 } \ 2170 mve_advance_vpt(env); \ 2171 } 2172 2173 #define DO_VSHRN_ALL(OP, FN) \ 2174 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 2175 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 2176 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 2177 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 2178 2179 static inline uint64_t do_urshr(uint64_t x, unsigned sh) 2180 { 2181 if (likely(sh < 64)) { 2182 return (x >> sh) + ((x >> (sh - 1)) & 1); 2183 } else if (sh == 64) { 2184 return x >> 63; 2185 } else { 2186 return 0; 2187 } 2188 } 2189 2190 static inline int64_t do_srshr(int64_t x, unsigned sh) 2191 { 2192 if (likely(sh < 64)) { 2193 return (x >> sh) + ((x >> (sh - 1)) & 1); 2194 } else { 2195 /* Rounding the sign bit always produces 0. */ 2196 return 0; 2197 } 2198 } 2199 2200 DO_VSHRN_ALL(vshrn, DO_SHR) 2201 DO_VSHRN_ALL(vrshrn, do_urshr) 2202 2203 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 2204 bool *satp) 2205 { 2206 if (val > max) { 2207 *satp = true; 2208 return max; 2209 } else if (val < min) { 2210 *satp = true; 2211 return min; 2212 } else { 2213 return val; 2214 } 2215 } 2216 2217 /* Saturating narrowing right shifts */ 2218 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2219 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2220 void *vm, uint32_t shift) \ 2221 { \ 2222 LTYPE *m = vm; \ 2223 TYPE *d = vd; \ 2224 uint16_t mask = mve_element_mask(env); \ 2225 bool qc = false; \ 2226 unsigned le; \ 2227 mask >>= ESIZE * TOP; \ 2228 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2229 bool sat = false; \ 2230 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 2231 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2232 qc |= sat & mask & 1; \ 2233 } \ 2234 if (qc) { \ 2235 env->vfp.qc[0] = qc; \ 2236 } \ 2237 mve_advance_vpt(env); \ 2238 } 2239 2240 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 2241 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2242 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2243 2244 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 2245 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2246 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2247 2248 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 2249 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2250 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2251 2252 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 2253 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2254 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2255 2256 #define DO_SHRN_SB(N, M, SATP) \ 2257 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 2258 #define DO_SHRN_UB(N, M, SATP) \ 2259 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2260 #define DO_SHRUN_B(N, M, SATP) \ 2261 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2262 2263 #define DO_SHRN_SH(N, M, SATP) \ 2264 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 2265 #define DO_SHRN_UH(N, M, SATP) \ 2266 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2267 #define DO_SHRUN_H(N, M, SATP) \ 2268 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2269 2270 #define DO_RSHRN_SB(N, M, SATP) \ 2271 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 2272 #define DO_RSHRN_UB(N, M, SATP) \ 2273 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 2274 #define DO_RSHRUN_B(N, M, SATP) \ 2275 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 2276 2277 #define DO_RSHRN_SH(N, M, SATP) \ 2278 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 2279 #define DO_RSHRN_UH(N, M, SATP) \ 2280 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 2281 #define DO_RSHRUN_H(N, M, SATP) \ 2282 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 2283 2284 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 2285 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 2286 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 2287 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 2288 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 2289 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 2290 2291 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 2292 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 2293 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 2294 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 2295 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 2296 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 2297 2298 #define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2299 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2300 { \ 2301 LTYPE *m = vm; \ 2302 TYPE *d = vd; \ 2303 uint16_t mask = mve_element_mask(env); \ 2304 unsigned le; \ 2305 mask >>= ESIZE * TOP; \ 2306 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2307 mergemask(&d[H##ESIZE(le * 2 + TOP)], \ 2308 m[H##LESIZE(le)], mask); \ 2309 } \ 2310 mve_advance_vpt(env); \ 2311 } 2312 2313 DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t) 2314 DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t) 2315 DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t) 2316 DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t) 2317 2318 #define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2319 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2320 { \ 2321 LTYPE *m = vm; \ 2322 TYPE *d = vd; \ 2323 uint16_t mask = mve_element_mask(env); \ 2324 bool qc = false; \ 2325 unsigned le; \ 2326 mask >>= ESIZE * TOP; \ 2327 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2328 bool sat = false; \ 2329 TYPE r = FN(m[H##LESIZE(le)], &sat); \ 2330 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2331 qc |= sat & mask & 1; \ 2332 } \ 2333 if (qc) { \ 2334 env->vfp.qc[0] = qc; \ 2335 } \ 2336 mve_advance_vpt(env); \ 2337 } 2338 2339 #define DO_VMOVN_SAT_UB(BOP, TOP, FN) \ 2340 DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2341 DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2342 2343 #define DO_VMOVN_SAT_UH(BOP, TOP, FN) \ 2344 DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2345 DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2346 2347 #define DO_VMOVN_SAT_SB(BOP, TOP, FN) \ 2348 DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2349 DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2350 2351 #define DO_VMOVN_SAT_SH(BOP, TOP, FN) \ 2352 DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2353 DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2354 2355 #define DO_VQMOVN_SB(N, SATP) \ 2356 do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP) 2357 #define DO_VQMOVN_UB(N, SATP) \ 2358 do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP) 2359 #define DO_VQMOVUN_B(N, SATP) \ 2360 do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP) 2361 2362 #define DO_VQMOVN_SH(N, SATP) \ 2363 do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP) 2364 #define DO_VQMOVN_UH(N, SATP) \ 2365 do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP) 2366 #define DO_VQMOVUN_H(N, SATP) \ 2367 do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP) 2368 2369 DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB) 2370 DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH) 2371 DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB) 2372 DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH) 2373 DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B) 2374 DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H) 2375 2376 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 2377 uint32_t shift) 2378 { 2379 uint32_t *d = vd; 2380 uint16_t mask = mve_element_mask(env); 2381 unsigned e; 2382 uint32_t r; 2383 2384 /* 2385 * For each 32-bit element, we shift it left, bringing in the 2386 * low 'shift' bits of rdm at the bottom. Bits shifted out at 2387 * the top become the new rdm, if the predicate mask permits. 2388 * The final rdm value is returned to update the register. 2389 * shift == 0 here means "shift by 32 bits". 2390 */ 2391 if (shift == 0) { 2392 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2393 r = rdm; 2394 if (mask & 1) { 2395 rdm = d[H4(e)]; 2396 } 2397 mergemask(&d[H4(e)], r, mask); 2398 } 2399 } else { 2400 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 2401 2402 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2403 r = (d[H4(e)] << shift) | (rdm & shiftmask); 2404 if (mask & 1) { 2405 rdm = d[H4(e)] >> (32 - shift); 2406 } 2407 mergemask(&d[H4(e)], r, mask); 2408 } 2409 } 2410 mve_advance_vpt(env); 2411 return rdm; 2412 } 2413 2414 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2415 { 2416 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 2417 } 2418 2419 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 2420 { 2421 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 2422 } 2423 2424 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2425 { 2426 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 2427 } 2428 2429 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2430 { 2431 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 2432 } 2433 2434 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2435 { 2436 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 2437 } 2438 2439 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2440 { 2441 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 2442 } 2443 2444 /* Operate on 64-bit values, but saturate at 48 bits */ 2445 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 2446 bool round, uint32_t *sat) 2447 { 2448 int64_t val, extval; 2449 2450 if (shift <= -48) { 2451 /* Rounding the sign bit always produces 0. */ 2452 if (round) { 2453 return 0; 2454 } 2455 return src >> 63; 2456 } else if (shift < 0) { 2457 if (round) { 2458 src >>= -shift - 1; 2459 val = (src >> 1) + (src & 1); 2460 } else { 2461 val = src >> -shift; 2462 } 2463 extval = sextract64(val, 0, 48); 2464 if (!sat || val == extval) { 2465 return extval; 2466 } 2467 } else if (shift < 48) { 2468 extval = sextract64(src << shift, 0, 48); 2469 if (!sat || src == (extval >> shift)) { 2470 return extval; 2471 } 2472 } else if (!sat || src == 0) { 2473 return 0; 2474 } 2475 2476 *sat = 1; 2477 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 2478 } 2479 2480 /* Operate on 64-bit values, but saturate at 48 bits */ 2481 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 2482 bool round, uint32_t *sat) 2483 { 2484 uint64_t val, extval; 2485 2486 if (shift <= -(48 + round)) { 2487 return 0; 2488 } else if (shift < 0) { 2489 if (round) { 2490 val = src >> (-shift - 1); 2491 val = (val >> 1) + (val & 1); 2492 } else { 2493 val = src >> -shift; 2494 } 2495 extval = extract64(val, 0, 48); 2496 if (!sat || val == extval) { 2497 return extval; 2498 } 2499 } else if (shift < 48) { 2500 extval = extract64(src << shift, 0, 48); 2501 if (!sat || src == (extval >> shift)) { 2502 return extval; 2503 } 2504 } else if (!sat || src == 0) { 2505 return 0; 2506 } 2507 2508 *sat = 1; 2509 return MAKE_64BIT_MASK(0, 48); 2510 } 2511 2512 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 2513 { 2514 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 2515 } 2516 2517 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 2518 { 2519 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 2520 } 2521 2522 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2523 { 2524 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2525 } 2526 2527 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2528 { 2529 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2530 } 2531 2532 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2533 { 2534 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 2535 } 2536 2537 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 2538 { 2539 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 2540 } 2541 2542 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \ 2543 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2544 uint32_t offset, uint32_t imm) \ 2545 { \ 2546 TYPE *d = vd; \ 2547 uint16_t mask = mve_element_mask(env); \ 2548 unsigned e; \ 2549 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2550 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2551 offset = FN(offset, imm); \ 2552 } \ 2553 mve_advance_vpt(env); \ 2554 return offset; \ 2555 } 2556 2557 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ 2558 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2559 uint32_t offset, uint32_t wrap, \ 2560 uint32_t imm) \ 2561 { \ 2562 TYPE *d = vd; \ 2563 uint16_t mask = mve_element_mask(env); \ 2564 unsigned e; \ 2565 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2566 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2567 offset = FN(offset, wrap, imm); \ 2568 } \ 2569 mve_advance_vpt(env); \ 2570 return offset; \ 2571 } 2572 2573 #define DO_VIDUP_ALL(OP, FN) \ 2574 DO_VIDUP(OP##b, 1, int8_t, FN) \ 2575 DO_VIDUP(OP##h, 2, int16_t, FN) \ 2576 DO_VIDUP(OP##w, 4, int32_t, FN) 2577 2578 #define DO_VIWDUP_ALL(OP, FN) \ 2579 DO_VIWDUP(OP##b, 1, int8_t, FN) \ 2580 DO_VIWDUP(OP##h, 2, int16_t, FN) \ 2581 DO_VIWDUP(OP##w, 4, int32_t, FN) 2582 2583 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2584 { 2585 offset += imm; 2586 if (offset == wrap) { 2587 offset = 0; 2588 } 2589 return offset; 2590 } 2591 2592 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2593 { 2594 if (offset == 0) { 2595 offset = wrap; 2596 } 2597 offset -= imm; 2598 return offset; 2599 } 2600 2601 DO_VIDUP_ALL(vidup, DO_ADD) 2602 DO_VIWDUP_ALL(viwdup, do_add_wrap) 2603 DO_VIWDUP_ALL(vdwdup, do_sub_wrap) 2604 2605 /* 2606 * Vector comparison. 2607 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. 2608 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. 2609 * P0 bits otherwise are updated with the results of the comparisons. 2610 * We must also keep unchanged the MASK fields at the top of v7m.vpr. 2611 */ 2612 #define DO_VCMP(OP, ESIZE, TYPE, FN) \ 2613 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 2614 { \ 2615 TYPE *n = vn, *m = vm; \ 2616 uint16_t mask = mve_element_mask(env); \ 2617 uint16_t eci_mask = mve_eci_mask(env); \ 2618 uint16_t beatpred = 0; \ 2619 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2620 unsigned e; \ 2621 for (e = 0; e < 16 / ESIZE; e++) { \ 2622 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ 2623 /* Comparison sets 0/1 bits for each byte in the element */ \ 2624 beatpred |= r * emask; \ 2625 emask <<= ESIZE; \ 2626 } \ 2627 beatpred &= mask; \ 2628 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2629 (beatpred & eci_mask); \ 2630 mve_advance_vpt(env); \ 2631 } 2632 2633 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ 2634 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 2635 uint32_t rm) \ 2636 { \ 2637 TYPE *n = vn; \ 2638 uint16_t mask = mve_element_mask(env); \ 2639 uint16_t eci_mask = mve_eci_mask(env); \ 2640 uint16_t beatpred = 0; \ 2641 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2642 unsigned e; \ 2643 for (e = 0; e < 16 / ESIZE; e++) { \ 2644 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \ 2645 /* Comparison sets 0/1 bits for each byte in the element */ \ 2646 beatpred |= r * emask; \ 2647 emask <<= ESIZE; \ 2648 } \ 2649 beatpred &= mask; \ 2650 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2651 (beatpred & eci_mask); \ 2652 mve_advance_vpt(env); \ 2653 } 2654 2655 #define DO_VCMP_S(OP, FN) \ 2656 DO_VCMP(OP##b, 1, int8_t, FN) \ 2657 DO_VCMP(OP##h, 2, int16_t, FN) \ 2658 DO_VCMP(OP##w, 4, int32_t, FN) \ 2659 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ 2660 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ 2661 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) 2662 2663 #define DO_VCMP_U(OP, FN) \ 2664 DO_VCMP(OP##b, 1, uint8_t, FN) \ 2665 DO_VCMP(OP##h, 2, uint16_t, FN) \ 2666 DO_VCMP(OP##w, 4, uint32_t, FN) \ 2667 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ 2668 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ 2669 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) 2670 2671 #define DO_EQ(N, M) ((N) == (M)) 2672 #define DO_NE(N, M) ((N) != (M)) 2673 #define DO_EQ(N, M) ((N) == (M)) 2674 #define DO_EQ(N, M) ((N) == (M)) 2675 #define DO_GE(N, M) ((N) >= (M)) 2676 #define DO_LT(N, M) ((N) < (M)) 2677 #define DO_GT(N, M) ((N) > (M)) 2678 #define DO_LE(N, M) ((N) <= (M)) 2679 2680 DO_VCMP_U(vcmpeq, DO_EQ) 2681 DO_VCMP_U(vcmpne, DO_NE) 2682 DO_VCMP_U(vcmpcs, DO_GE) 2683 DO_VCMP_U(vcmphi, DO_GT) 2684 DO_VCMP_S(vcmpge, DO_GE) 2685 DO_VCMP_S(vcmplt, DO_LT) 2686 DO_VCMP_S(vcmpgt, DO_GT) 2687 DO_VCMP_S(vcmple, DO_LE) 2688 2689 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) 2690 { 2691 /* 2692 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n] 2693 * but note that whether bytes are written to Qd is still subject 2694 * to (all forms of) predication in the usual way. 2695 */ 2696 uint64_t *d = vd, *n = vn, *m = vm; 2697 uint16_t mask = mve_element_mask(env); 2698 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 2699 unsigned e; 2700 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) { 2701 uint64_t r = m[H8(e)]; 2702 mergemask(&r, n[H8(e)], p0); 2703 mergemask(&d[H8(e)], r, mask); 2704 } 2705 mve_advance_vpt(env); 2706 } 2707 2708 void HELPER(mve_vpnot)(CPUARMState *env) 2709 { 2710 /* 2711 * P0 bits for unexecuted beats (where eci_mask is 0) are unchanged. 2712 * P0 bits for predicated lanes in executed bits (where mask is 0) are 0. 2713 * P0 bits otherwise are inverted. 2714 * (This is the same logic as VCMP.) 2715 * This insn is itself subject to predication and to beat-wise execution, 2716 * and after it executes VPT state advances in the usual way. 2717 */ 2718 uint16_t mask = mve_element_mask(env); 2719 uint16_t eci_mask = mve_eci_mask(env); 2720 uint16_t beatpred = ~env->v7m.vpr & mask; 2721 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask); 2722 mve_advance_vpt(env); 2723 } 2724 2725 /* 2726 * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed, 2727 * otherwise set according to value of Rn. The calculation of 2728 * newmask here works in the same way as the calculation of the 2729 * ltpmask in mve_element_mask(), but we have pre-calculated 2730 * the masklen in the generated code. 2731 */ 2732 void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen) 2733 { 2734 uint16_t mask = mve_element_mask(env); 2735 uint16_t eci_mask = mve_eci_mask(env); 2736 uint16_t newmask; 2737 2738 assert(masklen <= 16); 2739 newmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 2740 newmask &= mask; 2741 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask); 2742 mve_advance_vpt(env); 2743 } 2744 2745 #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ 2746 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2747 { \ 2748 TYPE *d = vd, *m = vm; \ 2749 uint16_t mask = mve_element_mask(env); \ 2750 unsigned e; \ 2751 bool qc = false; \ 2752 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2753 bool sat = false; \ 2754 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)], &sat), mask); \ 2755 qc |= sat & mask & 1; \ 2756 } \ 2757 if (qc) { \ 2758 env->vfp.qc[0] = qc; \ 2759 } \ 2760 mve_advance_vpt(env); \ 2761 } 2762 2763 #define DO_VQABS_B(N, SATP) \ 2764 do_sat_bhs(DO_ABS((int64_t)N), INT8_MIN, INT8_MAX, SATP) 2765 #define DO_VQABS_H(N, SATP) \ 2766 do_sat_bhs(DO_ABS((int64_t)N), INT16_MIN, INT16_MAX, SATP) 2767 #define DO_VQABS_W(N, SATP) \ 2768 do_sat_bhs(DO_ABS((int64_t)N), INT32_MIN, INT32_MAX, SATP) 2769 2770 #define DO_VQNEG_B(N, SATP) do_sat_bhs(-(int64_t)N, INT8_MIN, INT8_MAX, SATP) 2771 #define DO_VQNEG_H(N, SATP) do_sat_bhs(-(int64_t)N, INT16_MIN, INT16_MAX, SATP) 2772 #define DO_VQNEG_W(N, SATP) do_sat_bhs(-(int64_t)N, INT32_MIN, INT32_MAX, SATP) 2773 2774 DO_1OP_SAT(vqabsb, 1, int8_t, DO_VQABS_B) 2775 DO_1OP_SAT(vqabsh, 2, int16_t, DO_VQABS_H) 2776 DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W) 2777 2778 DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B) 2779 DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H) 2780 DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W) 2781 2782 /* 2783 * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its 2784 * absolute value; we then do an unsigned comparison. 2785 */ 2786 #define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \ 2787 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2788 { \ 2789 UTYPE *d = vd; \ 2790 STYPE *m = vm; \ 2791 uint16_t mask = mve_element_mask(env); \ 2792 unsigned e; \ 2793 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2794 UTYPE r = DO_ABS(m[H##ESIZE(e)]); \ 2795 r = FN(d[H##ESIZE(e)], r); \ 2796 mergemask(&d[H##ESIZE(e)], r, mask); \ 2797 } \ 2798 mve_advance_vpt(env); \ 2799 } 2800 2801 DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX) 2802 DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX) 2803 DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) 2804 DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) 2805 DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) 2806 DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) 2807 2808 /* 2809 * 2-operand floating point. Note that if an element is partially 2810 * predicated we must do the FP operation to update the non-predicated 2811 * bytes, but we must be careful to avoid updating the FP exception 2812 * state unless byte 0 of the element was unpredicated. 2813 */ 2814 #define DO_2OP_FP(OP, ESIZE, TYPE, FN) \ 2815 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2816 void *vd, void *vn, void *vm) \ 2817 { \ 2818 TYPE *d = vd, *n = vn, *m = vm; \ 2819 TYPE r; \ 2820 uint16_t mask = mve_element_mask(env); \ 2821 unsigned e; \ 2822 float_status *fpst; \ 2823 float_status scratch_fpst; \ 2824 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2825 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2826 continue; \ 2827 } \ 2828 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2829 if (!(mask & 1)) { \ 2830 /* We need the result but without updating flags */ \ 2831 scratch_fpst = *fpst; \ 2832 fpst = &scratch_fpst; \ 2833 } \ 2834 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 2835 mergemask(&d[H##ESIZE(e)], r, mask); \ 2836 } \ 2837 mve_advance_vpt(env); \ 2838 } 2839 2840 #define DO_2OP_FP_ALL(OP, FN) \ 2841 DO_2OP_FP(OP##h, 2, float16, float16_##FN) \ 2842 DO_2OP_FP(OP##s, 4, float32, float32_##FN) 2843 2844 DO_2OP_FP_ALL(vfadd, add) 2845 DO_2OP_FP_ALL(vfsub, sub) 2846 DO_2OP_FP_ALL(vfmul, mul) 2847 2848 static inline float16 float16_abd(float16 a, float16 b, float_status *s) 2849 { 2850 return float16_abs(float16_sub(a, b, s)); 2851 } 2852 2853 static inline float32 float32_abd(float32 a, float32 b, float_status *s) 2854 { 2855 return float32_abs(float32_sub(a, b, s)); 2856 } 2857 2858 DO_2OP_FP_ALL(vfabd, abd) 2859 DO_2OP_FP_ALL(vmaxnm, maxnum) 2860 DO_2OP_FP_ALL(vminnm, minnum) 2861 2862 static inline float16 float16_maxnuma(float16 a, float16 b, float_status *s) 2863 { 2864 return float16_maxnum(float16_abs(a), float16_abs(b), s); 2865 } 2866 2867 static inline float32 float32_maxnuma(float32 a, float32 b, float_status *s) 2868 { 2869 return float32_maxnum(float32_abs(a), float32_abs(b), s); 2870 } 2871 2872 static inline float16 float16_minnuma(float16 a, float16 b, float_status *s) 2873 { 2874 return float16_minnum(float16_abs(a), float16_abs(b), s); 2875 } 2876 2877 static inline float32 float32_minnuma(float32 a, float32 b, float_status *s) 2878 { 2879 return float32_minnum(float32_abs(a), float32_abs(b), s); 2880 } 2881 2882 DO_2OP_FP_ALL(vmaxnma, maxnuma) 2883 DO_2OP_FP_ALL(vminnma, minnuma) 2884 2885 #define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \ 2886 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2887 void *vd, void *vn, void *vm) \ 2888 { \ 2889 TYPE *d = vd, *n = vn, *m = vm; \ 2890 TYPE r[16 / ESIZE]; \ 2891 uint16_t tm, mask = mve_element_mask(env); \ 2892 unsigned e; \ 2893 float_status *fpst; \ 2894 float_status scratch_fpst; \ 2895 /* Calculate all results first to avoid overwriting inputs */ \ 2896 for (e = 0, tm = mask; e < 16 / ESIZE; e++, tm >>= ESIZE) { \ 2897 if ((tm & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2898 r[e] = 0; \ 2899 continue; \ 2900 } \ 2901 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2902 if (!(tm & 1)) { \ 2903 /* We need the result but without updating flags */ \ 2904 scratch_fpst = *fpst; \ 2905 fpst = &scratch_fpst; \ 2906 } \ 2907 if (!(e & 1)) { \ 2908 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)], fpst); \ 2909 } else { \ 2910 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)], fpst); \ 2911 } \ 2912 } \ 2913 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2914 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 2915 } \ 2916 mve_advance_vpt(env); \ 2917 } 2918 2919 DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, float16_add) 2920 DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add) 2921 DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub) 2922 DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) 2923 2924 #define DO_VFMA(OP, ESIZE, TYPE, CHS) \ 2925 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2926 void *vd, void *vn, void *vm) \ 2927 { \ 2928 TYPE *d = vd, *n = vn, *m = vm; \ 2929 TYPE r; \ 2930 uint16_t mask = mve_element_mask(env); \ 2931 unsigned e; \ 2932 float_status *fpst; \ 2933 float_status scratch_fpst; \ 2934 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2935 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2936 continue; \ 2937 } \ 2938 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2939 if (!(mask & 1)) { \ 2940 /* We need the result but without updating flags */ \ 2941 scratch_fpst = *fpst; \ 2942 fpst = &scratch_fpst; \ 2943 } \ 2944 r = n[H##ESIZE(e)]; \ 2945 if (CHS) { \ 2946 r = TYPE##_chs(r); \ 2947 } \ 2948 r = TYPE##_muladd(r, m[H##ESIZE(e)], d[H##ESIZE(e)], \ 2949 0, fpst); \ 2950 mergemask(&d[H##ESIZE(e)], r, mask); \ 2951 } \ 2952 mve_advance_vpt(env); \ 2953 } 2954 2955 DO_VFMA(vfmah, 2, float16, false) 2956 DO_VFMA(vfmas, 4, float32, false) 2957 DO_VFMA(vfmsh, 2, float16, true) 2958 DO_VFMA(vfmss, 4, float32, true) 2959 2960 #define DO_VCMLA(OP, ESIZE, TYPE, ROT, FN) \ 2961 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2962 void *vd, void *vn, void *vm) \ 2963 { \ 2964 TYPE *d = vd, *n = vn, *m = vm; \ 2965 TYPE r0, r1, e1, e2, e3, e4; \ 2966 uint16_t mask = mve_element_mask(env); \ 2967 unsigned e; \ 2968 float_status *fpst0, *fpst1; \ 2969 float_status scratch_fpst; \ 2970 /* We loop through pairs of elements at a time */ \ 2971 for (e = 0; e < 16 / ESIZE; e += 2, mask >>= ESIZE * 2) { \ 2972 if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) == 0) { \ 2973 continue; \ 2974 } \ 2975 fpst0 = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2976 fpst1 = fpst0; \ 2977 if (!(mask & 1)) { \ 2978 scratch_fpst = *fpst0; \ 2979 fpst0 = &scratch_fpst; \ 2980 } \ 2981 if (!(mask & (1 << ESIZE))) { \ 2982 scratch_fpst = *fpst1; \ 2983 fpst1 = &scratch_fpst; \ 2984 } \ 2985 switch (ROT) { \ 2986 case 0: \ 2987 e1 = m[H##ESIZE(e)]; \ 2988 e2 = n[H##ESIZE(e)]; \ 2989 e3 = m[H##ESIZE(e + 1)]; \ 2990 e4 = n[H##ESIZE(e)]; \ 2991 break; \ 2992 case 1: \ 2993 e1 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 2994 e2 = n[H##ESIZE(e + 1)]; \ 2995 e3 = m[H##ESIZE(e)]; \ 2996 e4 = n[H##ESIZE(e + 1)]; \ 2997 break; \ 2998 case 2: \ 2999 e1 = TYPE##_chs(m[H##ESIZE(e)]); \ 3000 e2 = n[H##ESIZE(e)]; \ 3001 e3 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 3002 e4 = n[H##ESIZE(e)]; \ 3003 break; \ 3004 case 3: \ 3005 e1 = m[H##ESIZE(e + 1)]; \ 3006 e2 = n[H##ESIZE(e + 1)]; \ 3007 e3 = TYPE##_chs(m[H##ESIZE(e)]); \ 3008 e4 = n[H##ESIZE(e + 1)]; \ 3009 break; \ 3010 default: \ 3011 g_assert_not_reached(); \ 3012 } \ 3013 r0 = FN(e2, e1, d[H##ESIZE(e)], fpst0); \ 3014 r1 = FN(e4, e3, d[H##ESIZE(e + 1)], fpst1); \ 3015 mergemask(&d[H##ESIZE(e)], r0, mask); \ 3016 mergemask(&d[H##ESIZE(e + 1)], r1, mask >> ESIZE); \ 3017 } \ 3018 mve_advance_vpt(env); \ 3019 } 3020 3021 #define DO_VCMULH(N, M, D, S) float16_mul(N, M, S) 3022 #define DO_VCMULS(N, M, D, S) float32_mul(N, M, S) 3023 3024 #define DO_VCMLAH(N, M, D, S) float16_muladd(N, M, D, 0, S) 3025 #define DO_VCMLAS(N, M, D, S) float32_muladd(N, M, D, 0, S) 3026 3027 DO_VCMLA(vcmul0h, 2, float16, 0, DO_VCMULH) 3028 DO_VCMLA(vcmul0s, 4, float32, 0, DO_VCMULS) 3029 DO_VCMLA(vcmul90h, 2, float16, 1, DO_VCMULH) 3030 DO_VCMLA(vcmul90s, 4, float32, 1, DO_VCMULS) 3031 DO_VCMLA(vcmul180h, 2, float16, 2, DO_VCMULH) 3032 DO_VCMLA(vcmul180s, 4, float32, 2, DO_VCMULS) 3033 DO_VCMLA(vcmul270h, 2, float16, 3, DO_VCMULH) 3034 DO_VCMLA(vcmul270s, 4, float32, 3, DO_VCMULS) 3035 3036 DO_VCMLA(vcmla0h, 2, float16, 0, DO_VCMLAH) 3037 DO_VCMLA(vcmla0s, 4, float32, 0, DO_VCMLAS) 3038 DO_VCMLA(vcmla90h, 2, float16, 1, DO_VCMLAH) 3039 DO_VCMLA(vcmla90s, 4, float32, 1, DO_VCMLAS) 3040 DO_VCMLA(vcmla180h, 2, float16, 2, DO_VCMLAH) 3041 DO_VCMLA(vcmla180s, 4, float32, 2, DO_VCMLAS) 3042 DO_VCMLA(vcmla270h, 2, float16, 3, DO_VCMLAH) 3043 DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) 3044 3045 #define DO_2OP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3046 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3047 void *vd, void *vn, uint32_t rm) \ 3048 { \ 3049 TYPE *d = vd, *n = vn; \ 3050 TYPE r, m = rm; \ 3051 uint16_t mask = mve_element_mask(env); \ 3052 unsigned e; \ 3053 float_status *fpst; \ 3054 float_status scratch_fpst; \ 3055 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3056 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3057 continue; \ 3058 } \ 3059 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3060 if (!(mask & 1)) { \ 3061 /* We need the result but without updating flags */ \ 3062 scratch_fpst = *fpst; \ 3063 fpst = &scratch_fpst; \ 3064 } \ 3065 r = FN(n[H##ESIZE(e)], m, fpst); \ 3066 mergemask(&d[H##ESIZE(e)], r, mask); \ 3067 } \ 3068 mve_advance_vpt(env); \ 3069 } 3070 3071 #define DO_2OP_FP_SCALAR_ALL(OP, FN) \ 3072 DO_2OP_FP_SCALAR(OP##h, 2, float16, float16_##FN) \ 3073 DO_2OP_FP_SCALAR(OP##s, 4, float32, float32_##FN) 3074 3075 DO_2OP_FP_SCALAR_ALL(vfadd_scalar, add) 3076 DO_2OP_FP_SCALAR_ALL(vfsub_scalar, sub) 3077 DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) 3078 3079 #define DO_2OP_FP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 3080 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3081 void *vd, void *vn, uint32_t rm) \ 3082 { \ 3083 TYPE *d = vd, *n = vn; \ 3084 TYPE r, m = rm; \ 3085 uint16_t mask = mve_element_mask(env); \ 3086 unsigned e; \ 3087 float_status *fpst; \ 3088 float_status scratch_fpst; \ 3089 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3090 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3091 continue; \ 3092 } \ 3093 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3094 if (!(mask & 1)) { \ 3095 /* We need the result but without updating flags */ \ 3096 scratch_fpst = *fpst; \ 3097 fpst = &scratch_fpst; \ 3098 } \ 3099 r = FN(n[H##ESIZE(e)], m, d[H##ESIZE(e)], 0, fpst); \ 3100 mergemask(&d[H##ESIZE(e)], r, mask); \ 3101 } \ 3102 mve_advance_vpt(env); \ 3103 } 3104 3105 /* VFMAS is vector * vector + scalar, so swap op2 and op3 */ 3106 #define DO_VFMAS_SCALARH(N, M, D, F, S) float16_muladd(N, D, M, F, S) 3107 #define DO_VFMAS_SCALARS(N, M, D, F, S) float32_muladd(N, D, M, F, S) 3108 3109 /* VFMA is vector * scalar + vector */ 3110 DO_2OP_FP_ACC_SCALAR(vfma_scalarh, 2, float16, float16_muladd) 3111 DO_2OP_FP_ACC_SCALAR(vfma_scalars, 4, float32, float32_muladd) 3112 DO_2OP_FP_ACC_SCALAR(vfmas_scalarh, 2, float16, DO_VFMAS_SCALARH) 3113 DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) 3114 3115 /* Floating point max/min across vector. */ 3116 #define DO_FP_VMAXMINV(OP, ESIZE, TYPE, ABS, FN) \ 3117 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 3118 uint32_t ra_in) \ 3119 { \ 3120 uint16_t mask = mve_element_mask(env); \ 3121 unsigned e; \ 3122 TYPE *m = vm; \ 3123 TYPE ra = (TYPE)ra_in; \ 3124 float_status *fpst = \ 3125 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3126 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3127 if (mask & 1) { \ 3128 TYPE v = m[H##ESIZE(e)]; \ 3129 if (TYPE##_is_signaling_nan(ra, fpst)) { \ 3130 ra = TYPE##_silence_nan(ra, fpst); \ 3131 float_raise(float_flag_invalid, fpst); \ 3132 } \ 3133 if (TYPE##_is_signaling_nan(v, fpst)) { \ 3134 v = TYPE##_silence_nan(v, fpst); \ 3135 float_raise(float_flag_invalid, fpst); \ 3136 } \ 3137 if (ABS) { \ 3138 v = TYPE##_abs(v); \ 3139 } \ 3140 ra = FN(ra, v, fpst); \ 3141 } \ 3142 } \ 3143 mve_advance_vpt(env); \ 3144 return ra; \ 3145 } \ 3146 3147 #define NOP(X) (X) 3148 3149 DO_FP_VMAXMINV(vmaxnmvh, 2, float16, false, float16_maxnum) 3150 DO_FP_VMAXMINV(vmaxnmvs, 4, float32, false, float32_maxnum) 3151 DO_FP_VMAXMINV(vminnmvh, 2, float16, false, float16_minnum) 3152 DO_FP_VMAXMINV(vminnmvs, 4, float32, false, float32_minnum) 3153 DO_FP_VMAXMINV(vmaxnmavh, 2, float16, true, float16_maxnum) 3154 DO_FP_VMAXMINV(vmaxnmavs, 4, float32, true, float32_maxnum) 3155 DO_FP_VMAXMINV(vminnmavh, 2, float16, true, float16_minnum) 3156 DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) 3157 3158 /* FP compares; note that all comparisons signal InvalidOp for QNaNs */ 3159 #define DO_VCMP_FP(OP, ESIZE, TYPE, FN) \ 3160 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 3161 { \ 3162 TYPE *n = vn, *m = vm; \ 3163 uint16_t mask = mve_element_mask(env); \ 3164 uint16_t eci_mask = mve_eci_mask(env); \ 3165 uint16_t beatpred = 0; \ 3166 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3167 unsigned e; \ 3168 float_status *fpst; \ 3169 float_status scratch_fpst; \ 3170 bool r; \ 3171 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3172 if ((mask & emask) == 0) { \ 3173 continue; \ 3174 } \ 3175 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3176 if (!(mask & (1 << (e * ESIZE)))) { \ 3177 /* We need the result but without updating flags */ \ 3178 scratch_fpst = *fpst; \ 3179 fpst = &scratch_fpst; \ 3180 } \ 3181 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 3182 /* Comparison sets 0/1 bits for each byte in the element */ \ 3183 beatpred |= r * emask; \ 3184 } \ 3185 beatpred &= mask; \ 3186 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3187 (beatpred & eci_mask); \ 3188 mve_advance_vpt(env); \ 3189 } 3190 3191 #define DO_VCMP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3192 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 3193 uint32_t rm) \ 3194 { \ 3195 TYPE *n = vn; \ 3196 uint16_t mask = mve_element_mask(env); \ 3197 uint16_t eci_mask = mve_eci_mask(env); \ 3198 uint16_t beatpred = 0; \ 3199 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3200 unsigned e; \ 3201 float_status *fpst; \ 3202 float_status scratch_fpst; \ 3203 bool r; \ 3204 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3205 if ((mask & emask) == 0) { \ 3206 continue; \ 3207 } \ 3208 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3209 if (!(mask & (1 << (e * ESIZE)))) { \ 3210 /* We need the result but without updating flags */ \ 3211 scratch_fpst = *fpst; \ 3212 fpst = &scratch_fpst; \ 3213 } \ 3214 r = FN(n[H##ESIZE(e)], (TYPE)rm, fpst); \ 3215 /* Comparison sets 0/1 bits for each byte in the element */ \ 3216 beatpred |= r * emask; \ 3217 } \ 3218 beatpred &= mask; \ 3219 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3220 (beatpred & eci_mask); \ 3221 mve_advance_vpt(env); \ 3222 } 3223 3224 #define DO_VCMP_FP_BOTH(VOP, SOP, ESIZE, TYPE, FN) \ 3225 DO_VCMP_FP(VOP, ESIZE, TYPE, FN) \ 3226 DO_VCMP_FP_SCALAR(SOP, ESIZE, TYPE, FN) 3227 3228 /* 3229 * Some care is needed here to get the correct result for the unordered case. 3230 * Architecturally EQ, GE and GT are defined to be false for unordered, but 3231 * the NE, LT and LE comparisons are defined as simple logical inverses of 3232 * EQ, GE and GT and so they must return true for unordered. The softfloat 3233 * comparison functions float*_{eq,le,lt} all return false for unordered. 3234 */ 3235 #define DO_GE16(X, Y, S) float16_le(Y, X, S) 3236 #define DO_GE32(X, Y, S) float32_le(Y, X, S) 3237 #define DO_GT16(X, Y, S) float16_lt(Y, X, S) 3238 #define DO_GT32(X, Y, S) float32_lt(Y, X, S) 3239 3240 DO_VCMP_FP_BOTH(vfcmpeqh, vfcmpeq_scalarh, 2, float16, float16_eq) 3241 DO_VCMP_FP_BOTH(vfcmpeqs, vfcmpeq_scalars, 4, float32, float32_eq) 3242 3243 DO_VCMP_FP_BOTH(vfcmpneh, vfcmpne_scalarh, 2, float16, !float16_eq) 3244 DO_VCMP_FP_BOTH(vfcmpnes, vfcmpne_scalars, 4, float32, !float32_eq) 3245 3246 DO_VCMP_FP_BOTH(vfcmpgeh, vfcmpge_scalarh, 2, float16, DO_GE16) 3247 DO_VCMP_FP_BOTH(vfcmpges, vfcmpge_scalars, 4, float32, DO_GE32) 3248 3249 DO_VCMP_FP_BOTH(vfcmplth, vfcmplt_scalarh, 2, float16, !DO_GE16) 3250 DO_VCMP_FP_BOTH(vfcmplts, vfcmplt_scalars, 4, float32, !DO_GE32) 3251 3252 DO_VCMP_FP_BOTH(vfcmpgth, vfcmpgt_scalarh, 2, float16, DO_GT16) 3253 DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float32, DO_GT32) 3254 3255 DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) 3256 DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) 3257 3258 #define DO_VCVT_FIXED(OP, ESIZE, TYPE, FN) \ 3259 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm, \ 3260 uint32_t shift) \ 3261 { \ 3262 TYPE *d = vd, *m = vm; \ 3263 TYPE r; \ 3264 uint16_t mask = mve_element_mask(env); \ 3265 unsigned e; \ 3266 float_status *fpst; \ 3267 float_status scratch_fpst; \ 3268 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3269 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3270 continue; \ 3271 } \ 3272 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3273 if (!(mask & 1)) { \ 3274 /* We need the result but without updating flags */ \ 3275 scratch_fpst = *fpst; \ 3276 fpst = &scratch_fpst; \ 3277 } \ 3278 r = FN(m[H##ESIZE(e)], shift, fpst); \ 3279 mergemask(&d[H##ESIZE(e)], r, mask); \ 3280 } \ 3281 mve_advance_vpt(env); \ 3282 } 3283 3284 DO_VCVT_FIXED(vcvt_sh, 2, int16_t, helper_vfp_shtoh) 3285 DO_VCVT_FIXED(vcvt_uh, 2, uint16_t, helper_vfp_uhtoh) 3286 DO_VCVT_FIXED(vcvt_hs, 2, int16_t, helper_vfp_toshh_round_to_zero) 3287 DO_VCVT_FIXED(vcvt_hu, 2, uint16_t, helper_vfp_touhh_round_to_zero) 3288 DO_VCVT_FIXED(vcvt_sf, 4, int32_t, helper_vfp_sltos) 3289 DO_VCVT_FIXED(vcvt_uf, 4, uint32_t, helper_vfp_ultos) 3290 DO_VCVT_FIXED(vcvt_fs, 4, int32_t, helper_vfp_tosls_round_to_zero) 3291 DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) 3292 3293 /* VCVT with specified rmode */ 3294 #define DO_VCVT_RMODE(OP, ESIZE, TYPE, FN) \ 3295 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3296 void *vd, void *vm, uint32_t rmode) \ 3297 { \ 3298 TYPE *d = vd, *m = vm; \ 3299 TYPE r; \ 3300 uint16_t mask = mve_element_mask(env); \ 3301 unsigned e; \ 3302 float_status *fpst; \ 3303 float_status scratch_fpst; \ 3304 float_status *base_fpst = \ 3305 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3306 uint32_t prev_rmode = get_float_rounding_mode(base_fpst); \ 3307 set_float_rounding_mode(rmode, base_fpst); \ 3308 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3309 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3310 continue; \ 3311 } \ 3312 fpst = base_fpst; \ 3313 if (!(mask & 1)) { \ 3314 /* We need the result but without updating flags */ \ 3315 scratch_fpst = *fpst; \ 3316 fpst = &scratch_fpst; \ 3317 } \ 3318 r = FN(m[H##ESIZE(e)], 0, fpst); \ 3319 mergemask(&d[H##ESIZE(e)], r, mask); \ 3320 } \ 3321 set_float_rounding_mode(prev_rmode, base_fpst); \ 3322 mve_advance_vpt(env); \ 3323 } 3324 3325 DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_toshh) 3326 DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) 3327 DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) 3328 DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) 3329 3330 #define DO_VRINT_RM_H(M, F, S) helper_rinth(M, S) 3331 #define DO_VRINT_RM_S(M, F, S) helper_rints(M, S) 3332 3333 DO_VCVT_RMODE(vrint_rm_h, 2, uint16_t, DO_VRINT_RM_H) 3334 DO_VCVT_RMODE(vrint_rm_s, 4, uint32_t, DO_VRINT_RM_S) 3335 3336 /* 3337 * VCVT between halfprec and singleprec. As usual for halfprec 3338 * conversions, FZ16 is ignored and AHP is observed. 3339 */ 3340 static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) 3341 { 3342 uint16_t *d = vd; 3343 uint32_t *m = vm; 3344 uint16_t r; 3345 uint16_t mask = mve_element_mask(env); 3346 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3347 unsigned e; 3348 float_status *fpst; 3349 float_status scratch_fpst; 3350 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3351 bool old_fz = get_flush_to_zero(base_fpst); 3352 set_flush_to_zero(false, base_fpst); 3353 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3354 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3355 continue; 3356 } 3357 fpst = base_fpst; 3358 if (!(mask & 1)) { 3359 /* We need the result but without updating flags */ 3360 scratch_fpst = *fpst; 3361 fpst = &scratch_fpst; 3362 } 3363 r = float32_to_float16(m[H4(e)], ieee, fpst); 3364 mergemask(&d[H2(e * 2 + top)], r, mask >> (top * 2)); 3365 } 3366 set_flush_to_zero(old_fz, base_fpst); 3367 mve_advance_vpt(env); 3368 } 3369 3370 static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) 3371 { 3372 uint32_t *d = vd; 3373 uint16_t *m = vm; 3374 uint32_t r; 3375 uint16_t mask = mve_element_mask(env); 3376 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3377 unsigned e; 3378 float_status *fpst; 3379 float_status scratch_fpst; 3380 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3381 bool old_fiz = get_flush_inputs_to_zero(base_fpst); 3382 set_flush_inputs_to_zero(false, base_fpst); 3383 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3384 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3385 continue; 3386 } 3387 fpst = base_fpst; 3388 if (!(mask & (1 << (top * 2)))) { 3389 /* We need the result but without updating flags */ 3390 scratch_fpst = *fpst; 3391 fpst = &scratch_fpst; 3392 } 3393 r = float16_to_float32(m[H2(e * 2 + top)], ieee, fpst); 3394 mergemask(&d[H4(e)], r, mask); 3395 } 3396 set_flush_inputs_to_zero(old_fiz, base_fpst); 3397 mve_advance_vpt(env); 3398 } 3399 3400 void HELPER(mve_vcvtb_sh)(CPUARMState *env, void *vd, void *vm) 3401 { 3402 do_vcvt_sh(env, vd, vm, 0); 3403 } 3404 void HELPER(mve_vcvtt_sh)(CPUARMState *env, void *vd, void *vm) 3405 { 3406 do_vcvt_sh(env, vd, vm, 1); 3407 } 3408 void HELPER(mve_vcvtb_hs)(CPUARMState *env, void *vd, void *vm) 3409 { 3410 do_vcvt_hs(env, vd, vm, 0); 3411 } 3412 void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) 3413 { 3414 do_vcvt_hs(env, vd, vm, 1); 3415 } 3416 3417 #define DO_1OP_FP(OP, ESIZE, TYPE, FN) \ 3418 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm) \ 3419 { \ 3420 TYPE *d = vd, *m = vm; \ 3421 TYPE r; \ 3422 uint16_t mask = mve_element_mask(env); \ 3423 unsigned e; \ 3424 float_status *fpst; \ 3425 float_status scratch_fpst; \ 3426 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3427 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3428 continue; \ 3429 } \ 3430 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3431 if (!(mask & 1)) { \ 3432 /* We need the result but without updating flags */ \ 3433 scratch_fpst = *fpst; \ 3434 fpst = &scratch_fpst; \ 3435 } \ 3436 r = FN(m[H##ESIZE(e)], fpst); \ 3437 mergemask(&d[H##ESIZE(e)], r, mask); \ 3438 } \ 3439 mve_advance_vpt(env); \ 3440 } 3441 3442 DO_1OP_FP(vrintx_h, 2, float16, float16_round_to_int) 3443 DO_1OP_FP(vrintx_s, 4, float32, float32_round_to_int) 3444