1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/exec-all.h" 27 #include "tcg/tcg.h" 28 29 static uint16_t mve_element_mask(CPUARMState *env) 30 { 31 /* 32 * Return the mask of which elements in the MVE vector should be 33 * updated. This is a combination of multiple things: 34 * (1) by default, we update every lane in the vector 35 * (2) VPT predication stores its state in the VPR register; 36 * (3) low-overhead-branch tail predication will mask out part 37 * the vector on the final iteration of the loop 38 * (4) if EPSR.ECI is set then we must execute only some beats 39 * of the insn 40 * We combine all these into a 16-bit result with the same semantics 41 * as VPR.P0: 0 to mask the lane, 1 if it is active. 42 * 8-bit vector ops will look at all bits of the result; 43 * 16-bit ops will look at bits 0, 2, 4, ...; 44 * 32-bit ops will look at bits 0, 4, 8 and 12. 45 * Compare pseudocode GetCurInstrBeat(), though that only returns 46 * the 4-bit slice of the mask corresponding to a single beat. 47 */ 48 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 49 50 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 51 mask |= 0xff; 52 } 53 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 54 mask |= 0xff00; 55 } 56 57 if (env->v7m.ltpsize < 4 && 58 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 59 /* 60 * Tail predication active, and this is the last loop iteration. 61 * The element size is (1 << ltpsize), and we only want to process 62 * loopcount elements, so we want to retain the least significant 63 * (loopcount * esize) predicate bits and zero out bits above that. 64 */ 65 int masklen = env->regs[14] << env->v7m.ltpsize; 66 assert(masklen <= 16); 67 mask &= MAKE_64BIT_MASK(0, masklen); 68 } 69 70 if ((env->condexec_bits & 0xf) == 0) { 71 /* 72 * ECI bits indicate which beats are already executed; 73 * we handle this by effectively predicating them out. 74 */ 75 int eci = env->condexec_bits >> 4; 76 switch (eci) { 77 case ECI_NONE: 78 break; 79 case ECI_A0: 80 mask &= 0xfff0; 81 break; 82 case ECI_A0A1: 83 mask &= 0xff00; 84 break; 85 case ECI_A0A1A2: 86 case ECI_A0A1A2B0: 87 mask &= 0xf000; 88 break; 89 default: 90 g_assert_not_reached(); 91 } 92 } 93 94 return mask; 95 } 96 97 static void mve_advance_vpt(CPUARMState *env) 98 { 99 /* Advance the VPT and ECI state if necessary */ 100 uint32_t vpr = env->v7m.vpr; 101 unsigned mask01, mask23; 102 103 if ((env->condexec_bits & 0xf) == 0) { 104 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 105 (ECI_A0 << 4) : (ECI_NONE << 4); 106 } 107 108 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 109 /* VPT not enabled, nothing to do */ 110 return; 111 } 112 113 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 114 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 115 if (mask01 > 8) { 116 /* high bit set, but not 0b1000: invert the relevant half of P0 */ 117 vpr ^= 0xff; 118 } 119 if (mask23 > 8) { 120 /* high bit set, but not 0b1000: invert the relevant half of P0 */ 121 vpr ^= 0xff00; 122 } 123 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 124 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 125 env->v7m.vpr = vpr; 126 } 127 128 129 #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ 130 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 131 { \ 132 TYPE *d = vd; \ 133 uint16_t mask = mve_element_mask(env); \ 134 unsigned b, e; \ 135 /* \ 136 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 137 * beats so we don't care if we update part of the dest and \ 138 * then take an exception. \ 139 */ \ 140 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 141 if (mask & (1 << b)) { \ 142 d[H##ESIZE(e)] = cpu_##LDTYPE##_data_ra(env, addr, GETPC()); \ 143 } \ 144 addr += MSIZE; \ 145 } \ 146 mve_advance_vpt(env); \ 147 } 148 149 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ 150 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 151 { \ 152 TYPE *d = vd; \ 153 uint16_t mask = mve_element_mask(env); \ 154 unsigned b, e; \ 155 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 156 if (mask & (1 << b)) { \ 157 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 158 } \ 159 addr += MSIZE; \ 160 } \ 161 mve_advance_vpt(env); \ 162 } 163 164 DO_VLDR(vldrb, 1, ldub, 1, uint8_t) 165 DO_VLDR(vldrh, 2, lduw, 2, uint16_t) 166 DO_VLDR(vldrw, 4, ldl, 4, uint32_t) 167 168 DO_VSTR(vstrb, 1, stb, 1, uint8_t) 169 DO_VSTR(vstrh, 2, stw, 2, uint16_t) 170 DO_VSTR(vstrw, 4, stl, 4, uint32_t) 171 172 DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t) 173 DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t) 174 DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t) 175 DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t) 176 DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t) 177 DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t) 178 179 DO_VSTR(vstrb_h, 1, stb, 2, int16_t) 180 DO_VSTR(vstrb_w, 1, stb, 4, int32_t) 181 DO_VSTR(vstrh_w, 2, stw, 4, int32_t) 182 183 #undef DO_VLDR 184 #undef DO_VSTR 185 186 /* 187 * The mergemask(D, R, M) macro performs the operation "*D = R" but 188 * storing only the bytes which correspond to 1 bits in M, 189 * leaving other bytes in *D unchanged. We use _Generic 190 * to select the correct implementation based on the type of D. 191 */ 192 193 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 194 { 195 if (mask & 1) { 196 *d = r; 197 } 198 } 199 200 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 201 { 202 mergemask_ub((uint8_t *)d, r, mask); 203 } 204 205 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 206 { 207 uint16_t bmask = expand_pred_b_data[mask & 3]; 208 *d = (*d & ~bmask) | (r & bmask); 209 } 210 211 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 212 { 213 mergemask_uh((uint16_t *)d, r, mask); 214 } 215 216 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 217 { 218 uint32_t bmask = expand_pred_b_data[mask & 0xf]; 219 *d = (*d & ~bmask) | (r & bmask); 220 } 221 222 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 223 { 224 mergemask_uw((uint32_t *)d, r, mask); 225 } 226 227 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 228 { 229 uint64_t bmask = expand_pred_b_data[mask & 0xff]; 230 *d = (*d & ~bmask) | (r & bmask); 231 } 232 233 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 234 { 235 mergemask_uq((uint64_t *)d, r, mask); 236 } 237 238 #define mergemask(D, R, M) \ 239 _Generic(D, \ 240 uint8_t *: mergemask_ub, \ 241 int8_t *: mergemask_sb, \ 242 uint16_t *: mergemask_uh, \ 243 int16_t *: mergemask_sh, \ 244 uint32_t *: mergemask_uw, \ 245 int32_t *: mergemask_sw, \ 246 uint64_t *: mergemask_uq, \ 247 int64_t *: mergemask_sq)(D, R, M) 248 249 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 250 { 251 /* 252 * The generated code already replicated an 8 or 16 bit constant 253 * into the 32-bit value, so we only need to write the 32-bit 254 * value to all elements of the Qreg, allowing for predication. 255 */ 256 uint32_t *d = vd; 257 uint16_t mask = mve_element_mask(env); 258 unsigned e; 259 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 260 mergemask(&d[H4(e)], val, mask); 261 } 262 mve_advance_vpt(env); 263 } 264 265 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 266 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 267 { \ 268 TYPE *d = vd, *m = vm; \ 269 uint16_t mask = mve_element_mask(env); \ 270 unsigned e; \ 271 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 272 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 273 } \ 274 mve_advance_vpt(env); \ 275 } 276 277 #define DO_CLS_B(N) (clrsb32(N) - 24) 278 #define DO_CLS_H(N) (clrsb32(N) - 16) 279 280 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 281 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 282 DO_1OP(vclsw, 4, int32_t, clrsb32) 283 284 #define DO_CLZ_B(N) (clz32(N) - 24) 285 #define DO_CLZ_H(N) (clz32(N) - 16) 286 287 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 288 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 289 DO_1OP(vclzw, 4, uint32_t, clz32) 290 291 DO_1OP(vrev16b, 2, uint16_t, bswap16) 292 DO_1OP(vrev32b, 4, uint32_t, bswap32) 293 DO_1OP(vrev32h, 4, uint32_t, hswap32) 294 DO_1OP(vrev64b, 8, uint64_t, bswap64) 295 DO_1OP(vrev64h, 8, uint64_t, hswap64) 296 DO_1OP(vrev64w, 8, uint64_t, wswap64) 297 298 #define DO_NOT(N) (~(N)) 299 300 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 301 302 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 303 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 304 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 305 306 DO_1OP(vabsb, 1, int8_t, DO_ABS) 307 DO_1OP(vabsh, 2, int16_t, DO_ABS) 308 DO_1OP(vabsw, 4, int32_t, DO_ABS) 309 310 /* We can do these 64 bits at a time */ 311 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 312 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 313 314 #define DO_NEG(N) (-(N)) 315 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 316 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 317 318 DO_1OP(vnegb, 1, int8_t, DO_NEG) 319 DO_1OP(vnegh, 2, int16_t, DO_NEG) 320 DO_1OP(vnegw, 4, int32_t, DO_NEG) 321 322 /* We can do these 64 bits at a time */ 323 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 324 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 325 326 /* 327 * 1 operand immediates: Vda is destination and possibly also one source. 328 * All these insns work at 64-bit widths. 329 */ 330 #define DO_1OP_IMM(OP, FN) \ 331 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 332 { \ 333 uint64_t *da = vda; \ 334 uint16_t mask = mve_element_mask(env); \ 335 unsigned e; \ 336 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 337 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 338 } \ 339 mve_advance_vpt(env); \ 340 } 341 342 #define DO_MOVI(N, I) (I) 343 #define DO_ANDI(N, I) ((N) & (I)) 344 #define DO_ORRI(N, I) ((N) | (I)) 345 346 DO_1OP_IMM(vmovi, DO_MOVI) 347 DO_1OP_IMM(vandi, DO_ANDI) 348 DO_1OP_IMM(vorri, DO_ORRI) 349 350 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 351 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 352 void *vd, void *vn, void *vm) \ 353 { \ 354 TYPE *d = vd, *n = vn, *m = vm; \ 355 uint16_t mask = mve_element_mask(env); \ 356 unsigned e; \ 357 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 358 mergemask(&d[H##ESIZE(e)], \ 359 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 360 } \ 361 mve_advance_vpt(env); \ 362 } 363 364 /* provide unsigned 2-op helpers for all sizes */ 365 #define DO_2OP_U(OP, FN) \ 366 DO_2OP(OP##b, 1, uint8_t, FN) \ 367 DO_2OP(OP##h, 2, uint16_t, FN) \ 368 DO_2OP(OP##w, 4, uint32_t, FN) 369 370 /* provide signed 2-op helpers for all sizes */ 371 #define DO_2OP_S(OP, FN) \ 372 DO_2OP(OP##b, 1, int8_t, FN) \ 373 DO_2OP(OP##h, 2, int16_t, FN) \ 374 DO_2OP(OP##w, 4, int32_t, FN) 375 376 /* 377 * "Long" operations where two half-sized inputs (taken from either the 378 * top or the bottom of the input vector) produce a double-width result. 379 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 380 */ 381 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 382 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 383 { \ 384 LTYPE *d = vd; \ 385 TYPE *n = vn, *m = vm; \ 386 uint16_t mask = mve_element_mask(env); \ 387 unsigned le; \ 388 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 389 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 390 m[H##ESIZE(le * 2 + TOP)]); \ 391 mergemask(&d[H##LESIZE(le)], r, mask); \ 392 } \ 393 mve_advance_vpt(env); \ 394 } 395 396 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 397 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 398 { \ 399 TYPE *d = vd, *n = vn, *m = vm; \ 400 uint16_t mask = mve_element_mask(env); \ 401 unsigned e; \ 402 bool qc = false; \ 403 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 404 bool sat = false; \ 405 TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 406 mergemask(&d[H##ESIZE(e)], r, mask); \ 407 qc |= sat & mask & 1; \ 408 } \ 409 if (qc) { \ 410 env->vfp.qc[0] = qc; \ 411 } \ 412 mve_advance_vpt(env); \ 413 } 414 415 /* provide unsigned 2-op helpers for all sizes */ 416 #define DO_2OP_SAT_U(OP, FN) \ 417 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 418 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 419 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 420 421 /* provide signed 2-op helpers for all sizes */ 422 #define DO_2OP_SAT_S(OP, FN) \ 423 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 424 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 425 DO_2OP_SAT(OP##w, 4, int32_t, FN) 426 427 #define DO_AND(N, M) ((N) & (M)) 428 #define DO_BIC(N, M) ((N) & ~(M)) 429 #define DO_ORR(N, M) ((N) | (M)) 430 #define DO_ORN(N, M) ((N) | ~(M)) 431 #define DO_EOR(N, M) ((N) ^ (M)) 432 433 DO_2OP(vand, 8, uint64_t, DO_AND) 434 DO_2OP(vbic, 8, uint64_t, DO_BIC) 435 DO_2OP(vorr, 8, uint64_t, DO_ORR) 436 DO_2OP(vorn, 8, uint64_t, DO_ORN) 437 DO_2OP(veor, 8, uint64_t, DO_EOR) 438 439 #define DO_ADD(N, M) ((N) + (M)) 440 #define DO_SUB(N, M) ((N) - (M)) 441 #define DO_MUL(N, M) ((N) * (M)) 442 443 DO_2OP_U(vadd, DO_ADD) 444 DO_2OP_U(vsub, DO_SUB) 445 DO_2OP_U(vmul, DO_MUL) 446 447 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 448 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 449 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 450 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 451 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 452 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 453 454 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 455 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 456 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 457 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 458 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 459 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 460 461 /* 462 * Because the computation type is at least twice as large as required, 463 * these work for both signed and unsigned source types. 464 */ 465 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 466 { 467 return (n * m) >> 8; 468 } 469 470 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 471 { 472 return (n * m) >> 16; 473 } 474 475 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 476 { 477 return (n * m) >> 32; 478 } 479 480 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 481 { 482 return (n * m + (1U << 7)) >> 8; 483 } 484 485 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 486 { 487 return (n * m + (1U << 15)) >> 16; 488 } 489 490 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 491 { 492 return (n * m + (1U << 31)) >> 32; 493 } 494 495 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 496 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 497 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 498 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 499 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 500 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 501 502 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 503 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 504 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 505 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 506 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 507 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 508 509 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 510 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 511 512 DO_2OP_S(vmaxs, DO_MAX) 513 DO_2OP_U(vmaxu, DO_MAX) 514 DO_2OP_S(vmins, DO_MIN) 515 DO_2OP_U(vminu, DO_MIN) 516 517 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 518 519 DO_2OP_S(vabds, DO_ABD) 520 DO_2OP_U(vabdu, DO_ABD) 521 522 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 523 { 524 return ((uint64_t)n + m) >> 1; 525 } 526 527 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 528 { 529 return ((int64_t)n + m) >> 1; 530 } 531 532 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 533 { 534 return ((uint64_t)n - m) >> 1; 535 } 536 537 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 538 { 539 return ((int64_t)n - m) >> 1; 540 } 541 542 DO_2OP_S(vhadds, do_vhadd_s) 543 DO_2OP_U(vhaddu, do_vhadd_u) 544 DO_2OP_S(vhsubs, do_vhsub_s) 545 DO_2OP_U(vhsubu, do_vhsub_u) 546 547 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 548 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 549 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 550 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 551 552 DO_2OP_S(vshls, DO_VSHLS) 553 DO_2OP_U(vshlu, DO_VSHLU) 554 DO_2OP_S(vrshls, DO_VRSHLS) 555 DO_2OP_U(vrshlu, DO_VRSHLU) 556 557 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 558 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 559 560 DO_2OP_S(vrhadds, DO_RHADD_S) 561 DO_2OP_U(vrhaddu, DO_RHADD_U) 562 563 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 564 uint32_t inv, uint32_t carry_in, bool update_flags) 565 { 566 uint16_t mask = mve_element_mask(env); 567 unsigned e; 568 569 /* If any additions trigger, we will update flags. */ 570 if (mask & 0x1111) { 571 update_flags = true; 572 } 573 574 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 575 uint64_t r = carry_in; 576 r += n[H4(e)]; 577 r += m[H4(e)] ^ inv; 578 if (mask & 1) { 579 carry_in = r >> 32; 580 } 581 mergemask(&d[H4(e)], r, mask); 582 } 583 584 if (update_flags) { 585 /* Store C, clear NZV. */ 586 env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK; 587 env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C; 588 } 589 mve_advance_vpt(env); 590 } 591 592 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 593 { 594 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 595 do_vadc(env, vd, vn, vm, 0, carry_in, false); 596 } 597 598 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 599 { 600 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 601 do_vadc(env, vd, vn, vm, -1, carry_in, false); 602 } 603 604 605 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 606 { 607 do_vadc(env, vd, vn, vm, 0, 0, true); 608 } 609 610 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 611 { 612 do_vadc(env, vd, vn, vm, -1, 1, true); 613 } 614 615 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 616 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 617 { \ 618 TYPE *d = vd, *n = vn, *m = vm; \ 619 uint16_t mask = mve_element_mask(env); \ 620 unsigned e; \ 621 TYPE r[16 / ESIZE]; \ 622 /* Calculate all results first to avoid overwriting inputs */ \ 623 for (e = 0; e < 16 / ESIZE; e++) { \ 624 if (!(e & 1)) { \ 625 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 626 } else { \ 627 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 628 } \ 629 } \ 630 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 631 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 632 } \ 633 mve_advance_vpt(env); \ 634 } 635 636 #define DO_VCADD_ALL(OP, FN0, FN1) \ 637 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 638 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 639 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 640 641 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 642 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 643 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 644 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 645 646 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 647 { 648 if (val > max) { 649 *s = true; 650 return max; 651 } else if (val < min) { 652 *s = true; 653 return min; 654 } 655 return val; 656 } 657 658 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 659 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 660 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 661 662 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 663 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 664 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 665 666 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 667 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 668 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 669 670 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 671 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 672 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 673 674 /* 675 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 676 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 677 */ 678 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 679 INT8_MIN, INT8_MAX, s) 680 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 681 INT16_MIN, INT16_MAX, s) 682 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 683 INT32_MIN, INT32_MAX, s) 684 685 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 686 INT8_MIN, INT8_MAX, s) 687 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 688 INT16_MIN, INT16_MAX, s) 689 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 690 INT32_MIN, INT32_MAX, s) 691 692 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 693 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 694 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 695 696 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 697 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 698 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 699 700 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 701 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 702 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 703 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 704 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 705 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 706 707 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 708 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 709 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 710 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 711 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 712 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 713 714 /* 715 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 716 * and friends wanting a uint32_t* sat and our needing a bool*. 717 */ 718 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 719 ({ \ 720 uint32_t su32 = 0; \ 721 typeof(N) r = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 722 if (su32) { \ 723 *satp = true; \ 724 } \ 725 r; \ 726 }) 727 728 #define DO_SQSHL_OP(N, M, satp) \ 729 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 730 #define DO_UQSHL_OP(N, M, satp) \ 731 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 732 #define DO_SQRSHL_OP(N, M, satp) \ 733 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 734 #define DO_UQRSHL_OP(N, M, satp) \ 735 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 736 737 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 738 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 739 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 740 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 741 742 /* 743 * Multiply add dual returning high half 744 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 745 * whether to add the rounding constant, and the pointer to the 746 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 747 * saturate to twice the input size and return the high half; or 748 * (A * B - C * D) etc for VQDMLSDH. 749 */ 750 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 751 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 752 void *vm) \ 753 { \ 754 TYPE *d = vd, *n = vn, *m = vm; \ 755 uint16_t mask = mve_element_mask(env); \ 756 unsigned e; \ 757 bool qc = false; \ 758 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 759 bool sat = false; \ 760 if ((e & 1) == XCHG) { \ 761 TYPE r = FN(n[H##ESIZE(e)], \ 762 m[H##ESIZE(e - XCHG)], \ 763 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 764 m[H##ESIZE(e + (1 - XCHG))], \ 765 ROUND, &sat); \ 766 mergemask(&d[H##ESIZE(e)], r, mask); \ 767 qc |= sat & mask & 1; \ 768 } \ 769 } \ 770 if (qc) { \ 771 env->vfp.qc[0] = qc; \ 772 } \ 773 mve_advance_vpt(env); \ 774 } 775 776 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 777 int round, bool *sat) 778 { 779 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 780 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 781 } 782 783 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 784 int round, bool *sat) 785 { 786 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 787 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 788 } 789 790 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 791 int round, bool *sat) 792 { 793 int64_t m1 = (int64_t)a * b; 794 int64_t m2 = (int64_t)c * d; 795 int64_t r; 796 /* 797 * Architecturally we should do the entire add, double, round 798 * and then check for saturation. We do three saturating adds, 799 * but we need to be careful about the order. If the first 800 * m1 + m2 saturates then it's impossible for the *2+rc to 801 * bring it back into the non-saturated range. However, if 802 * m1 + m2 is negative then it's possible that doing the doubling 803 * would take the intermediate result below INT64_MAX and the 804 * addition of the rounding constant then brings it back in range. 805 * So we add half the rounding constant before doubling rather 806 * than adding the rounding constant after the doubling. 807 */ 808 if (sadd64_overflow(m1, m2, &r) || 809 sadd64_overflow(r, (round << 30), &r) || 810 sadd64_overflow(r, r, &r)) { 811 *sat = true; 812 return r < 0 ? INT32_MAX : INT32_MIN; 813 } 814 return r >> 32; 815 } 816 817 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 818 int round, bool *sat) 819 { 820 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 821 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 822 } 823 824 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 825 int round, bool *sat) 826 { 827 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 828 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 829 } 830 831 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 832 int round, bool *sat) 833 { 834 int64_t m1 = (int64_t)a * b; 835 int64_t m2 = (int64_t)c * d; 836 int64_t r; 837 /* The same ordering issue as in do_vqdmladh_w applies here too */ 838 if (ssub64_overflow(m1, m2, &r) || 839 sadd64_overflow(r, (round << 30), &r) || 840 sadd64_overflow(r, r, &r)) { 841 *sat = true; 842 return r < 0 ? INT32_MAX : INT32_MIN; 843 } 844 return r >> 32; 845 } 846 847 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 848 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 849 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 850 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 851 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 852 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 853 854 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 855 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 856 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 857 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 858 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 859 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 860 861 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 862 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 863 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 864 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 865 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 866 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 867 868 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 869 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 870 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 871 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 872 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 873 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 874 875 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 876 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 877 uint32_t rm) \ 878 { \ 879 TYPE *d = vd, *n = vn; \ 880 TYPE m = rm; \ 881 uint16_t mask = mve_element_mask(env); \ 882 unsigned e; \ 883 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 884 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 885 } \ 886 mve_advance_vpt(env); \ 887 } 888 889 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 890 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 891 uint32_t rm) \ 892 { \ 893 TYPE *d = vd, *n = vn; \ 894 TYPE m = rm; \ 895 uint16_t mask = mve_element_mask(env); \ 896 unsigned e; \ 897 bool qc = false; \ 898 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 899 bool sat = false; \ 900 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 901 mask); \ 902 qc |= sat & mask & 1; \ 903 } \ 904 if (qc) { \ 905 env->vfp.qc[0] = qc; \ 906 } \ 907 mve_advance_vpt(env); \ 908 } 909 910 /* provide unsigned 2-op scalar helpers for all sizes */ 911 #define DO_2OP_SCALAR_U(OP, FN) \ 912 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 913 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 914 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 915 #define DO_2OP_SCALAR_S(OP, FN) \ 916 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 917 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 918 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 919 920 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 921 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 922 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 923 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 924 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 925 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 926 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 927 928 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 929 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 930 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 931 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 932 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 933 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 934 935 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 936 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 937 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 938 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 939 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 940 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 941 942 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 943 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 944 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 945 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 946 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 947 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 948 949 /* 950 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 951 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 952 * SATMASK specifies which bits of the predicate mask matter for determining 953 * whether to propagate a saturation indication into FPSCR.QC -- for 954 * the 16x16->32 case we must check only the bit corresponding to the T or B 955 * half that we used, but for the 32x32->64 case we propagate if the mask 956 * bit is set for either half. 957 */ 958 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 959 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 960 uint32_t rm) \ 961 { \ 962 LTYPE *d = vd; \ 963 TYPE *n = vn; \ 964 TYPE m = rm; \ 965 uint16_t mask = mve_element_mask(env); \ 966 unsigned le; \ 967 bool qc = false; \ 968 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 969 bool sat = false; \ 970 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 971 mergemask(&d[H##LESIZE(le)], r, mask); \ 972 qc |= sat && (mask & SATMASK); \ 973 } \ 974 if (qc) { \ 975 env->vfp.qc[0] = qc; \ 976 } \ 977 mve_advance_vpt(env); \ 978 } 979 980 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 981 { 982 int64_t r = ((int64_t)n * m) * 2; 983 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 984 } 985 986 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 987 { 988 /* The multiply can't overflow, but the doubling might */ 989 int64_t r = (int64_t)n * m; 990 if (r > INT64_MAX / 2) { 991 *sat = true; 992 return INT64_MAX; 993 } else if (r < INT64_MIN / 2) { 994 *sat = true; 995 return INT64_MIN; 996 } else { 997 return r * 2; 998 } 999 } 1000 1001 #define SATMASK16B 1 1002 #define SATMASK16T (1 << 2) 1003 #define SATMASK32 ((1 << 4) | 1) 1004 1005 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1006 do_qdmullh, SATMASK16B) 1007 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1008 do_qdmullw, SATMASK32) 1009 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1010 do_qdmullh, SATMASK16T) 1011 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1012 do_qdmullw, SATMASK32) 1013 1014 /* 1015 * Long saturating ops 1016 */ 1017 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1018 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1019 void *vm) \ 1020 { \ 1021 LTYPE *d = vd; \ 1022 TYPE *n = vn, *m = vm; \ 1023 uint16_t mask = mve_element_mask(env); \ 1024 unsigned le; \ 1025 bool qc = false; \ 1026 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1027 bool sat = false; \ 1028 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1029 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1030 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1031 qc |= sat && (mask & SATMASK); \ 1032 } \ 1033 if (qc) { \ 1034 env->vfp.qc[0] = qc; \ 1035 } \ 1036 mve_advance_vpt(env); \ 1037 } 1038 1039 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1040 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1041 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1042 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1043 1044 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1045 { 1046 m &= 0xff; 1047 if (m == 0) { 1048 return 0; 1049 } 1050 n = revbit8(n); 1051 if (m < 8) { 1052 n >>= 8 - m; 1053 } 1054 return n; 1055 } 1056 1057 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1058 { 1059 m &= 0xff; 1060 if (m == 0) { 1061 return 0; 1062 } 1063 n = revbit16(n); 1064 if (m < 16) { 1065 n >>= 16 - m; 1066 } 1067 return n; 1068 } 1069 1070 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1071 { 1072 m &= 0xff; 1073 if (m == 0) { 1074 return 0; 1075 } 1076 n = revbit32(n); 1077 if (m < 32) { 1078 n >>= 32 - m; 1079 } 1080 return n; 1081 } 1082 1083 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1084 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1085 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1086 1087 /* 1088 * Multiply add long dual accumulate ops. 1089 */ 1090 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1091 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1092 void *vm, uint64_t a) \ 1093 { \ 1094 uint16_t mask = mve_element_mask(env); \ 1095 unsigned e; \ 1096 TYPE *n = vn, *m = vm; \ 1097 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1098 if (mask & 1) { \ 1099 if (e & 1) { \ 1100 a ODDACC \ 1101 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1102 } else { \ 1103 a EVENACC \ 1104 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1105 } \ 1106 } \ 1107 } \ 1108 mve_advance_vpt(env); \ 1109 return a; \ 1110 } 1111 1112 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1113 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1114 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1115 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1116 1117 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1118 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1119 1120 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1121 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1122 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1123 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1124 1125 /* 1126 * Rounding multiply add long dual accumulate high. In the pseudocode 1127 * this is implemented with a 72-bit internal accumulator value of which 1128 * the top 64 bits are returned. We optimize this to avoid having to 1129 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1130 * is squashed back into 64-bits after each beat. 1131 */ 1132 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1133 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1134 void *vm, uint64_t a) \ 1135 { \ 1136 uint16_t mask = mve_element_mask(env); \ 1137 unsigned e; \ 1138 TYPE *n = vn, *m = vm; \ 1139 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1140 if (mask & 1) { \ 1141 LTYPE mul; \ 1142 if (e & 1) { \ 1143 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1144 if (SUB) { \ 1145 mul = -mul; \ 1146 } \ 1147 } else { \ 1148 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1149 } \ 1150 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1151 a += mul; \ 1152 } \ 1153 } \ 1154 mve_advance_vpt(env); \ 1155 return a; \ 1156 } 1157 1158 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1159 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1160 1161 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1162 1163 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1164 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1165 1166 /* Vector add across vector */ 1167 #define DO_VADDV(OP, ESIZE, TYPE) \ 1168 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1169 uint32_t ra) \ 1170 { \ 1171 uint16_t mask = mve_element_mask(env); \ 1172 unsigned e; \ 1173 TYPE *m = vm; \ 1174 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1175 if (mask & 1) { \ 1176 ra += m[H##ESIZE(e)]; \ 1177 } \ 1178 } \ 1179 mve_advance_vpt(env); \ 1180 return ra; \ 1181 } \ 1182 1183 DO_VADDV(vaddvsb, 1, uint8_t) 1184 DO_VADDV(vaddvsh, 2, uint16_t) 1185 DO_VADDV(vaddvsw, 4, uint32_t) 1186 DO_VADDV(vaddvub, 1, uint8_t) 1187 DO_VADDV(vaddvuh, 2, uint16_t) 1188 DO_VADDV(vaddvuw, 4, uint32_t) 1189