1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/exec-all.h" 27 #include "tcg/tcg.h" 28 29 static uint16_t mve_eci_mask(CPUARMState *env) 30 { 31 /* 32 * Return the mask of which elements in the MVE vector correspond 33 * to beats being executed. The mask has 1 bits for executed lanes 34 * and 0 bits where ECI says this beat was already executed. 35 */ 36 int eci; 37 38 if ((env->condexec_bits & 0xf) != 0) { 39 return 0xffff; 40 } 41 42 eci = env->condexec_bits >> 4; 43 switch (eci) { 44 case ECI_NONE: 45 return 0xffff; 46 case ECI_A0: 47 return 0xfff0; 48 case ECI_A0A1: 49 return 0xff00; 50 case ECI_A0A1A2: 51 case ECI_A0A1A2B0: 52 return 0xf000; 53 default: 54 g_assert_not_reached(); 55 } 56 } 57 58 static uint16_t mve_element_mask(CPUARMState *env) 59 { 60 /* 61 * Return the mask of which elements in the MVE vector should be 62 * updated. This is a combination of multiple things: 63 * (1) by default, we update every lane in the vector 64 * (2) VPT predication stores its state in the VPR register; 65 * (3) low-overhead-branch tail predication will mask out part 66 * the vector on the final iteration of the loop 67 * (4) if EPSR.ECI is set then we must execute only some beats 68 * of the insn 69 * We combine all these into a 16-bit result with the same semantics 70 * as VPR.P0: 0 to mask the lane, 1 if it is active. 71 * 8-bit vector ops will look at all bits of the result; 72 * 16-bit ops will look at bits 0, 2, 4, ...; 73 * 32-bit ops will look at bits 0, 4, 8 and 12. 74 * Compare pseudocode GetCurInstrBeat(), though that only returns 75 * the 4-bit slice of the mask corresponding to a single beat. 76 */ 77 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 78 79 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 80 mask |= 0xff; 81 } 82 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 83 mask |= 0xff00; 84 } 85 86 if (env->v7m.ltpsize < 4 && 87 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 88 /* 89 * Tail predication active, and this is the last loop iteration. 90 * The element size is (1 << ltpsize), and we only want to process 91 * loopcount elements, so we want to retain the least significant 92 * (loopcount * esize) predicate bits and zero out bits above that. 93 */ 94 int masklen = env->regs[14] << env->v7m.ltpsize; 95 assert(masklen <= 16); 96 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 97 mask &= ltpmask; 98 } 99 100 /* 101 * ECI bits indicate which beats are already executed; 102 * we handle this by effectively predicating them out. 103 */ 104 mask &= mve_eci_mask(env); 105 return mask; 106 } 107 108 static void mve_advance_vpt(CPUARMState *env) 109 { 110 /* Advance the VPT and ECI state if necessary */ 111 uint32_t vpr = env->v7m.vpr; 112 unsigned mask01, mask23; 113 uint16_t inv_mask; 114 uint16_t eci_mask = mve_eci_mask(env); 115 116 if ((env->condexec_bits & 0xf) == 0) { 117 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 118 (ECI_A0 << 4) : (ECI_NONE << 4); 119 } 120 121 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 122 /* VPT not enabled, nothing to do */ 123 return; 124 } 125 126 /* Invert P0 bits if needed, but only for beats we actually executed */ 127 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 128 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 129 /* Start by assuming we invert all bits corresponding to executed beats */ 130 inv_mask = eci_mask; 131 if (mask01 <= 8) { 132 /* MASK01 says don't invert low half of P0 */ 133 inv_mask &= ~0xff; 134 } 135 if (mask23 <= 8) { 136 /* MASK23 says don't invert high half of P0 */ 137 inv_mask &= ~0xff00; 138 } 139 vpr ^= inv_mask; 140 /* Only update MASK01 if beat 1 executed */ 141 if (eci_mask & 0xf0) { 142 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 143 } 144 /* Beat 3 always executes, so update MASK23 */ 145 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 146 env->v7m.vpr = vpr; 147 } 148 149 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 150 #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ 151 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 152 { \ 153 TYPE *d = vd; \ 154 uint16_t mask = mve_element_mask(env); \ 155 uint16_t eci_mask = mve_eci_mask(env); \ 156 unsigned b, e; \ 157 /* \ 158 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 159 * beats so we don't care if we update part of the dest and \ 160 * then take an exception. \ 161 */ \ 162 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 163 if (eci_mask & (1 << b)) { \ 164 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 165 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 166 } \ 167 addr += MSIZE; \ 168 } \ 169 mve_advance_vpt(env); \ 170 } 171 172 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ 173 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 174 { \ 175 TYPE *d = vd; \ 176 uint16_t mask = mve_element_mask(env); \ 177 unsigned b, e; \ 178 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 179 if (mask & (1 << b)) { \ 180 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 181 } \ 182 addr += MSIZE; \ 183 } \ 184 mve_advance_vpt(env); \ 185 } 186 187 DO_VLDR(vldrb, 1, ldub, 1, uint8_t) 188 DO_VLDR(vldrh, 2, lduw, 2, uint16_t) 189 DO_VLDR(vldrw, 4, ldl, 4, uint32_t) 190 191 DO_VSTR(vstrb, 1, stb, 1, uint8_t) 192 DO_VSTR(vstrh, 2, stw, 2, uint16_t) 193 DO_VSTR(vstrw, 4, stl, 4, uint32_t) 194 195 DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t) 196 DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t) 197 DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t) 198 DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t) 199 DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t) 200 DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t) 201 202 DO_VSTR(vstrb_h, 1, stb, 2, int16_t) 203 DO_VSTR(vstrb_w, 1, stb, 4, int32_t) 204 DO_VSTR(vstrh_w, 2, stw, 4, int32_t) 205 206 #undef DO_VLDR 207 #undef DO_VSTR 208 209 /* 210 * Gather loads/scatter stores. Here each element of Qm specifies 211 * an offset to use from the base register Rm. In the _os_ versions 212 * that offset is scaled by the element size. 213 * For loads, predicated lanes are zeroed instead of retaining 214 * their previous values. 215 */ 216 #define DO_VLDR_SG(OP, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN) \ 217 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 218 uint32_t base) \ 219 { \ 220 TYPE *d = vd; \ 221 OFFTYPE *m = vm; \ 222 uint16_t mask = mve_element_mask(env); \ 223 uint16_t eci_mask = mve_eci_mask(env); \ 224 unsigned e; \ 225 uint32_t addr; \ 226 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 227 if (!(eci_mask & 1)) { \ 228 continue; \ 229 } \ 230 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 231 d[H##ESIZE(e)] = (mask & 1) ? \ 232 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 233 } \ 234 mve_advance_vpt(env); \ 235 } 236 237 /* We know here TYPE is unsigned so always the same as the offset type */ 238 #define DO_VSTR_SG(OP, STTYPE, ESIZE, TYPE, ADDRFN) \ 239 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 240 uint32_t base) \ 241 { \ 242 TYPE *d = vd; \ 243 TYPE *m = vm; \ 244 uint16_t mask = mve_element_mask(env); \ 245 unsigned e; \ 246 uint32_t addr; \ 247 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 248 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 249 if (mask & 1) { \ 250 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 251 } \ 252 } \ 253 mve_advance_vpt(env); \ 254 } 255 256 /* 257 * 64-bit accesses are slightly different: they are done as two 32-bit 258 * accesses, controlled by the predicate mask for the relevant beat, 259 * and with a single 32-bit offset in the first of the two Qm elements. 260 * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little). 261 */ 262 #define DO_VLDR64_SG(OP, ADDRFN) \ 263 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 264 uint32_t base) \ 265 { \ 266 uint32_t *d = vd; \ 267 uint32_t *m = vm; \ 268 uint16_t mask = mve_element_mask(env); \ 269 uint16_t eci_mask = mve_eci_mask(env); \ 270 unsigned e; \ 271 uint32_t addr; \ 272 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 273 if (!(eci_mask & 1)) { \ 274 continue; \ 275 } \ 276 addr = ADDRFN(base, m[H4(e & ~1)]); \ 277 addr += 4 * (e & 1); \ 278 d[H4(e)] = (mask & 1) ? cpu_ldl_data_ra(env, addr, GETPC()) : 0; \ 279 } \ 280 mve_advance_vpt(env); \ 281 } 282 283 #define DO_VSTR64_SG(OP, ADDRFN) \ 284 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 285 uint32_t base) \ 286 { \ 287 uint32_t *d = vd; \ 288 uint32_t *m = vm; \ 289 uint16_t mask = mve_element_mask(env); \ 290 unsigned e; \ 291 uint32_t addr; \ 292 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 293 addr = ADDRFN(base, m[H4(e & ~1)]); \ 294 addr += 4 * (e & 1); \ 295 if (mask & 1) { \ 296 cpu_stl_data_ra(env, addr, d[H4(e)], GETPC()); \ 297 } \ 298 } \ 299 mve_advance_vpt(env); \ 300 } 301 302 #define ADDR_ADD(BASE, OFFSET) ((BASE) + (OFFSET)) 303 #define ADDR_ADD_OSH(BASE, OFFSET) ((BASE) + ((OFFSET) << 1)) 304 #define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2)) 305 #define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3)) 306 307 DO_VLDR_SG(vldrb_sg_sh, ldsb, 2, int16_t, uint16_t, ADDR_ADD) 308 DO_VLDR_SG(vldrb_sg_sw, ldsb, 4, int32_t, uint32_t, ADDR_ADD) 309 DO_VLDR_SG(vldrh_sg_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD) 310 311 DO_VLDR_SG(vldrb_sg_ub, ldub, 1, uint8_t, uint8_t, ADDR_ADD) 312 DO_VLDR_SG(vldrb_sg_uh, ldub, 2, uint16_t, uint16_t, ADDR_ADD) 313 DO_VLDR_SG(vldrb_sg_uw, ldub, 4, uint32_t, uint32_t, ADDR_ADD) 314 DO_VLDR_SG(vldrh_sg_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD) 315 DO_VLDR_SG(vldrh_sg_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD) 316 DO_VLDR_SG(vldrw_sg_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD) 317 DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD) 318 319 DO_VLDR_SG(vldrh_sg_os_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD_OSH) 320 DO_VLDR_SG(vldrh_sg_os_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD_OSH) 321 DO_VLDR_SG(vldrh_sg_os_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD_OSH) 322 DO_VLDR_SG(vldrw_sg_os_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW) 323 DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD) 324 325 DO_VSTR_SG(vstrb_sg_ub, stb, 1, uint8_t, ADDR_ADD) 326 DO_VSTR_SG(vstrb_sg_uh, stb, 2, uint16_t, ADDR_ADD) 327 DO_VSTR_SG(vstrb_sg_uw, stb, 4, uint32_t, ADDR_ADD) 328 DO_VSTR_SG(vstrh_sg_uh, stw, 2, uint16_t, ADDR_ADD) 329 DO_VSTR_SG(vstrh_sg_uw, stw, 4, uint32_t, ADDR_ADD) 330 DO_VSTR_SG(vstrw_sg_uw, stl, 4, uint32_t, ADDR_ADD) 331 DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD) 332 333 DO_VSTR_SG(vstrh_sg_os_uh, stw, 2, uint16_t, ADDR_ADD_OSH) 334 DO_VSTR_SG(vstrh_sg_os_uw, stw, 4, uint32_t, ADDR_ADD_OSH) 335 DO_VSTR_SG(vstrw_sg_os_uw, stl, 4, uint32_t, ADDR_ADD_OSW) 336 DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD) 337 338 /* 339 * The mergemask(D, R, M) macro performs the operation "*D = R" but 340 * storing only the bytes which correspond to 1 bits in M, 341 * leaving other bytes in *D unchanged. We use _Generic 342 * to select the correct implementation based on the type of D. 343 */ 344 345 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 346 { 347 if (mask & 1) { 348 *d = r; 349 } 350 } 351 352 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 353 { 354 mergemask_ub((uint8_t *)d, r, mask); 355 } 356 357 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 358 { 359 uint16_t bmask = expand_pred_b_data[mask & 3]; 360 *d = (*d & ~bmask) | (r & bmask); 361 } 362 363 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 364 { 365 mergemask_uh((uint16_t *)d, r, mask); 366 } 367 368 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 369 { 370 uint32_t bmask = expand_pred_b_data[mask & 0xf]; 371 *d = (*d & ~bmask) | (r & bmask); 372 } 373 374 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 375 { 376 mergemask_uw((uint32_t *)d, r, mask); 377 } 378 379 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 380 { 381 uint64_t bmask = expand_pred_b_data[mask & 0xff]; 382 *d = (*d & ~bmask) | (r & bmask); 383 } 384 385 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 386 { 387 mergemask_uq((uint64_t *)d, r, mask); 388 } 389 390 #define mergemask(D, R, M) \ 391 _Generic(D, \ 392 uint8_t *: mergemask_ub, \ 393 int8_t *: mergemask_sb, \ 394 uint16_t *: mergemask_uh, \ 395 int16_t *: mergemask_sh, \ 396 uint32_t *: mergemask_uw, \ 397 int32_t *: mergemask_sw, \ 398 uint64_t *: mergemask_uq, \ 399 int64_t *: mergemask_sq)(D, R, M) 400 401 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 402 { 403 /* 404 * The generated code already replicated an 8 or 16 bit constant 405 * into the 32-bit value, so we only need to write the 32-bit 406 * value to all elements of the Qreg, allowing for predication. 407 */ 408 uint32_t *d = vd; 409 uint16_t mask = mve_element_mask(env); 410 unsigned e; 411 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 412 mergemask(&d[H4(e)], val, mask); 413 } 414 mve_advance_vpt(env); 415 } 416 417 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 418 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 419 { \ 420 TYPE *d = vd, *m = vm; \ 421 uint16_t mask = mve_element_mask(env); \ 422 unsigned e; \ 423 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 424 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 425 } \ 426 mve_advance_vpt(env); \ 427 } 428 429 #define DO_CLS_B(N) (clrsb32(N) - 24) 430 #define DO_CLS_H(N) (clrsb32(N) - 16) 431 432 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 433 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 434 DO_1OP(vclsw, 4, int32_t, clrsb32) 435 436 #define DO_CLZ_B(N) (clz32(N) - 24) 437 #define DO_CLZ_H(N) (clz32(N) - 16) 438 439 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 440 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 441 DO_1OP(vclzw, 4, uint32_t, clz32) 442 443 DO_1OP(vrev16b, 2, uint16_t, bswap16) 444 DO_1OP(vrev32b, 4, uint32_t, bswap32) 445 DO_1OP(vrev32h, 4, uint32_t, hswap32) 446 DO_1OP(vrev64b, 8, uint64_t, bswap64) 447 DO_1OP(vrev64h, 8, uint64_t, hswap64) 448 DO_1OP(vrev64w, 8, uint64_t, wswap64) 449 450 #define DO_NOT(N) (~(N)) 451 452 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 453 454 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 455 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 456 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 457 458 DO_1OP(vabsb, 1, int8_t, DO_ABS) 459 DO_1OP(vabsh, 2, int16_t, DO_ABS) 460 DO_1OP(vabsw, 4, int32_t, DO_ABS) 461 462 /* We can do these 64 bits at a time */ 463 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 464 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 465 466 #define DO_NEG(N) (-(N)) 467 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 468 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 469 470 DO_1OP(vnegb, 1, int8_t, DO_NEG) 471 DO_1OP(vnegh, 2, int16_t, DO_NEG) 472 DO_1OP(vnegw, 4, int32_t, DO_NEG) 473 474 /* We can do these 64 bits at a time */ 475 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 476 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 477 478 /* 479 * 1 operand immediates: Vda is destination and possibly also one source. 480 * All these insns work at 64-bit widths. 481 */ 482 #define DO_1OP_IMM(OP, FN) \ 483 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 484 { \ 485 uint64_t *da = vda; \ 486 uint16_t mask = mve_element_mask(env); \ 487 unsigned e; \ 488 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 489 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 490 } \ 491 mve_advance_vpt(env); \ 492 } 493 494 #define DO_MOVI(N, I) (I) 495 #define DO_ANDI(N, I) ((N) & (I)) 496 #define DO_ORRI(N, I) ((N) | (I)) 497 498 DO_1OP_IMM(vmovi, DO_MOVI) 499 DO_1OP_IMM(vandi, DO_ANDI) 500 DO_1OP_IMM(vorri, DO_ORRI) 501 502 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 503 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 504 void *vd, void *vn, void *vm) \ 505 { \ 506 TYPE *d = vd, *n = vn, *m = vm; \ 507 uint16_t mask = mve_element_mask(env); \ 508 unsigned e; \ 509 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 510 mergemask(&d[H##ESIZE(e)], \ 511 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 512 } \ 513 mve_advance_vpt(env); \ 514 } 515 516 /* provide unsigned 2-op helpers for all sizes */ 517 #define DO_2OP_U(OP, FN) \ 518 DO_2OP(OP##b, 1, uint8_t, FN) \ 519 DO_2OP(OP##h, 2, uint16_t, FN) \ 520 DO_2OP(OP##w, 4, uint32_t, FN) 521 522 /* provide signed 2-op helpers for all sizes */ 523 #define DO_2OP_S(OP, FN) \ 524 DO_2OP(OP##b, 1, int8_t, FN) \ 525 DO_2OP(OP##h, 2, int16_t, FN) \ 526 DO_2OP(OP##w, 4, int32_t, FN) 527 528 /* 529 * "Long" operations where two half-sized inputs (taken from either the 530 * top or the bottom of the input vector) produce a double-width result. 531 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 532 */ 533 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 534 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 535 { \ 536 LTYPE *d = vd; \ 537 TYPE *n = vn, *m = vm; \ 538 uint16_t mask = mve_element_mask(env); \ 539 unsigned le; \ 540 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 541 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 542 m[H##ESIZE(le * 2 + TOP)]); \ 543 mergemask(&d[H##LESIZE(le)], r, mask); \ 544 } \ 545 mve_advance_vpt(env); \ 546 } 547 548 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 549 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 550 { \ 551 TYPE *d = vd, *n = vn, *m = vm; \ 552 uint16_t mask = mve_element_mask(env); \ 553 unsigned e; \ 554 bool qc = false; \ 555 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 556 bool sat = false; \ 557 TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 558 mergemask(&d[H##ESIZE(e)], r, mask); \ 559 qc |= sat & mask & 1; \ 560 } \ 561 if (qc) { \ 562 env->vfp.qc[0] = qc; \ 563 } \ 564 mve_advance_vpt(env); \ 565 } 566 567 /* provide unsigned 2-op helpers for all sizes */ 568 #define DO_2OP_SAT_U(OP, FN) \ 569 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 570 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 571 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 572 573 /* provide signed 2-op helpers for all sizes */ 574 #define DO_2OP_SAT_S(OP, FN) \ 575 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 576 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 577 DO_2OP_SAT(OP##w, 4, int32_t, FN) 578 579 #define DO_AND(N, M) ((N) & (M)) 580 #define DO_BIC(N, M) ((N) & ~(M)) 581 #define DO_ORR(N, M) ((N) | (M)) 582 #define DO_ORN(N, M) ((N) | ~(M)) 583 #define DO_EOR(N, M) ((N) ^ (M)) 584 585 DO_2OP(vand, 8, uint64_t, DO_AND) 586 DO_2OP(vbic, 8, uint64_t, DO_BIC) 587 DO_2OP(vorr, 8, uint64_t, DO_ORR) 588 DO_2OP(vorn, 8, uint64_t, DO_ORN) 589 DO_2OP(veor, 8, uint64_t, DO_EOR) 590 591 #define DO_ADD(N, M) ((N) + (M)) 592 #define DO_SUB(N, M) ((N) - (M)) 593 #define DO_MUL(N, M) ((N) * (M)) 594 595 DO_2OP_U(vadd, DO_ADD) 596 DO_2OP_U(vsub, DO_SUB) 597 DO_2OP_U(vmul, DO_MUL) 598 599 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 600 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 601 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 602 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 603 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 604 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 605 606 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 607 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 608 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 609 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 610 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 611 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 612 613 /* 614 * Polynomial multiply. We can always do this generating 64 bits 615 * of the result at a time, so we don't need to use DO_2OP_L. 616 */ 617 #define VMULLPH_MASK 0x00ff00ff00ff00ffULL 618 #define VMULLPW_MASK 0x0000ffff0000ffffULL 619 #define DO_VMULLPBH(N, M) pmull_h((N) & VMULLPH_MASK, (M) & VMULLPH_MASK) 620 #define DO_VMULLPTH(N, M) DO_VMULLPBH((N) >> 8, (M) >> 8) 621 #define DO_VMULLPBW(N, M) pmull_w((N) & VMULLPW_MASK, (M) & VMULLPW_MASK) 622 #define DO_VMULLPTW(N, M) DO_VMULLPBW((N) >> 16, (M) >> 16) 623 624 DO_2OP(vmullpbh, 8, uint64_t, DO_VMULLPBH) 625 DO_2OP(vmullpth, 8, uint64_t, DO_VMULLPTH) 626 DO_2OP(vmullpbw, 8, uint64_t, DO_VMULLPBW) 627 DO_2OP(vmullptw, 8, uint64_t, DO_VMULLPTW) 628 629 /* 630 * Because the computation type is at least twice as large as required, 631 * these work for both signed and unsigned source types. 632 */ 633 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 634 { 635 return (n * m) >> 8; 636 } 637 638 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 639 { 640 return (n * m) >> 16; 641 } 642 643 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 644 { 645 return (n * m) >> 32; 646 } 647 648 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 649 { 650 return (n * m + (1U << 7)) >> 8; 651 } 652 653 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 654 { 655 return (n * m + (1U << 15)) >> 16; 656 } 657 658 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 659 { 660 return (n * m + (1U << 31)) >> 32; 661 } 662 663 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 664 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 665 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 666 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 667 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 668 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 669 670 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 671 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 672 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 673 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 674 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 675 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 676 677 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 678 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 679 680 DO_2OP_S(vmaxs, DO_MAX) 681 DO_2OP_U(vmaxu, DO_MAX) 682 DO_2OP_S(vmins, DO_MIN) 683 DO_2OP_U(vminu, DO_MIN) 684 685 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 686 687 DO_2OP_S(vabds, DO_ABD) 688 DO_2OP_U(vabdu, DO_ABD) 689 690 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 691 { 692 return ((uint64_t)n + m) >> 1; 693 } 694 695 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 696 { 697 return ((int64_t)n + m) >> 1; 698 } 699 700 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 701 { 702 return ((uint64_t)n - m) >> 1; 703 } 704 705 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 706 { 707 return ((int64_t)n - m) >> 1; 708 } 709 710 DO_2OP_S(vhadds, do_vhadd_s) 711 DO_2OP_U(vhaddu, do_vhadd_u) 712 DO_2OP_S(vhsubs, do_vhsub_s) 713 DO_2OP_U(vhsubu, do_vhsub_u) 714 715 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 716 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 717 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 718 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 719 720 DO_2OP_S(vshls, DO_VSHLS) 721 DO_2OP_U(vshlu, DO_VSHLU) 722 DO_2OP_S(vrshls, DO_VRSHLS) 723 DO_2OP_U(vrshlu, DO_VRSHLU) 724 725 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 726 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 727 728 DO_2OP_S(vrhadds, DO_RHADD_S) 729 DO_2OP_U(vrhaddu, DO_RHADD_U) 730 731 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 732 uint32_t inv, uint32_t carry_in, bool update_flags) 733 { 734 uint16_t mask = mve_element_mask(env); 735 unsigned e; 736 737 /* If any additions trigger, we will update flags. */ 738 if (mask & 0x1111) { 739 update_flags = true; 740 } 741 742 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 743 uint64_t r = carry_in; 744 r += n[H4(e)]; 745 r += m[H4(e)] ^ inv; 746 if (mask & 1) { 747 carry_in = r >> 32; 748 } 749 mergemask(&d[H4(e)], r, mask); 750 } 751 752 if (update_flags) { 753 /* Store C, clear NZV. */ 754 env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK; 755 env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C; 756 } 757 mve_advance_vpt(env); 758 } 759 760 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 761 { 762 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 763 do_vadc(env, vd, vn, vm, 0, carry_in, false); 764 } 765 766 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 767 { 768 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 769 do_vadc(env, vd, vn, vm, -1, carry_in, false); 770 } 771 772 773 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 774 { 775 do_vadc(env, vd, vn, vm, 0, 0, true); 776 } 777 778 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 779 { 780 do_vadc(env, vd, vn, vm, -1, 1, true); 781 } 782 783 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 784 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 785 { \ 786 TYPE *d = vd, *n = vn, *m = vm; \ 787 uint16_t mask = mve_element_mask(env); \ 788 unsigned e; \ 789 TYPE r[16 / ESIZE]; \ 790 /* Calculate all results first to avoid overwriting inputs */ \ 791 for (e = 0; e < 16 / ESIZE; e++) { \ 792 if (!(e & 1)) { \ 793 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 794 } else { \ 795 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 796 } \ 797 } \ 798 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 799 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 800 } \ 801 mve_advance_vpt(env); \ 802 } 803 804 #define DO_VCADD_ALL(OP, FN0, FN1) \ 805 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 806 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 807 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 808 809 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 810 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 811 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 812 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 813 814 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 815 { 816 if (val > max) { 817 *s = true; 818 return max; 819 } else if (val < min) { 820 *s = true; 821 return min; 822 } 823 return val; 824 } 825 826 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 827 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 828 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 829 830 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 831 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 832 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 833 834 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 835 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 836 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 837 838 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 839 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 840 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 841 842 /* 843 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 844 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 845 */ 846 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 847 INT8_MIN, INT8_MAX, s) 848 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 849 INT16_MIN, INT16_MAX, s) 850 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 851 INT32_MIN, INT32_MAX, s) 852 853 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 854 INT8_MIN, INT8_MAX, s) 855 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 856 INT16_MIN, INT16_MAX, s) 857 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 858 INT32_MIN, INT32_MAX, s) 859 860 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 861 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 862 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 863 864 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 865 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 866 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 867 868 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 869 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 870 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 871 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 872 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 873 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 874 875 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 876 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 877 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 878 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 879 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 880 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 881 882 /* 883 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 884 * and friends wanting a uint32_t* sat and our needing a bool*. 885 */ 886 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 887 ({ \ 888 uint32_t su32 = 0; \ 889 typeof(N) r = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 890 if (su32) { \ 891 *satp = true; \ 892 } \ 893 r; \ 894 }) 895 896 #define DO_SQSHL_OP(N, M, satp) \ 897 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 898 #define DO_UQSHL_OP(N, M, satp) \ 899 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 900 #define DO_SQRSHL_OP(N, M, satp) \ 901 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 902 #define DO_UQRSHL_OP(N, M, satp) \ 903 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 904 #define DO_SUQSHL_OP(N, M, satp) \ 905 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 906 907 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 908 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 909 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 910 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 911 912 /* 913 * Multiply add dual returning high half 914 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 915 * whether to add the rounding constant, and the pointer to the 916 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 917 * saturate to twice the input size and return the high half; or 918 * (A * B - C * D) etc for VQDMLSDH. 919 */ 920 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 921 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 922 void *vm) \ 923 { \ 924 TYPE *d = vd, *n = vn, *m = vm; \ 925 uint16_t mask = mve_element_mask(env); \ 926 unsigned e; \ 927 bool qc = false; \ 928 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 929 bool sat = false; \ 930 if ((e & 1) == XCHG) { \ 931 TYPE r = FN(n[H##ESIZE(e)], \ 932 m[H##ESIZE(e - XCHG)], \ 933 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 934 m[H##ESIZE(e + (1 - XCHG))], \ 935 ROUND, &sat); \ 936 mergemask(&d[H##ESIZE(e)], r, mask); \ 937 qc |= sat & mask & 1; \ 938 } \ 939 } \ 940 if (qc) { \ 941 env->vfp.qc[0] = qc; \ 942 } \ 943 mve_advance_vpt(env); \ 944 } 945 946 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 947 int round, bool *sat) 948 { 949 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 950 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 951 } 952 953 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 954 int round, bool *sat) 955 { 956 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 957 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 958 } 959 960 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 961 int round, bool *sat) 962 { 963 int64_t m1 = (int64_t)a * b; 964 int64_t m2 = (int64_t)c * d; 965 int64_t r; 966 /* 967 * Architecturally we should do the entire add, double, round 968 * and then check for saturation. We do three saturating adds, 969 * but we need to be careful about the order. If the first 970 * m1 + m2 saturates then it's impossible for the *2+rc to 971 * bring it back into the non-saturated range. However, if 972 * m1 + m2 is negative then it's possible that doing the doubling 973 * would take the intermediate result below INT64_MAX and the 974 * addition of the rounding constant then brings it back in range. 975 * So we add half the rounding constant before doubling rather 976 * than adding the rounding constant after the doubling. 977 */ 978 if (sadd64_overflow(m1, m2, &r) || 979 sadd64_overflow(r, (round << 30), &r) || 980 sadd64_overflow(r, r, &r)) { 981 *sat = true; 982 return r < 0 ? INT32_MAX : INT32_MIN; 983 } 984 return r >> 32; 985 } 986 987 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 988 int round, bool *sat) 989 { 990 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 991 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 992 } 993 994 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 995 int round, bool *sat) 996 { 997 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 998 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 999 } 1000 1001 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1002 int round, bool *sat) 1003 { 1004 int64_t m1 = (int64_t)a * b; 1005 int64_t m2 = (int64_t)c * d; 1006 int64_t r; 1007 /* The same ordering issue as in do_vqdmladh_w applies here too */ 1008 if (ssub64_overflow(m1, m2, &r) || 1009 sadd64_overflow(r, (round << 30), &r) || 1010 sadd64_overflow(r, r, &r)) { 1011 *sat = true; 1012 return r < 0 ? INT32_MAX : INT32_MIN; 1013 } 1014 return r >> 32; 1015 } 1016 1017 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 1018 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 1019 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 1020 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 1021 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 1022 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 1023 1024 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 1025 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 1026 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 1027 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 1028 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 1029 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 1030 1031 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 1032 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 1033 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 1034 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 1035 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 1036 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 1037 1038 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 1039 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 1040 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 1041 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 1042 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 1043 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 1044 1045 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 1046 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1047 uint32_t rm) \ 1048 { \ 1049 TYPE *d = vd, *n = vn; \ 1050 TYPE m = rm; \ 1051 uint16_t mask = mve_element_mask(env); \ 1052 unsigned e; \ 1053 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1054 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 1055 } \ 1056 mve_advance_vpt(env); \ 1057 } 1058 1059 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 1060 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1061 uint32_t rm) \ 1062 { \ 1063 TYPE *d = vd, *n = vn; \ 1064 TYPE m = rm; \ 1065 uint16_t mask = mve_element_mask(env); \ 1066 unsigned e; \ 1067 bool qc = false; \ 1068 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1069 bool sat = false; \ 1070 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 1071 mask); \ 1072 qc |= sat & mask & 1; \ 1073 } \ 1074 if (qc) { \ 1075 env->vfp.qc[0] = qc; \ 1076 } \ 1077 mve_advance_vpt(env); \ 1078 } 1079 1080 /* "accumulating" version where FN takes d as well as n and m */ 1081 #define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1082 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1083 uint32_t rm) \ 1084 { \ 1085 TYPE *d = vd, *n = vn; \ 1086 TYPE m = rm; \ 1087 uint16_t mask = mve_element_mask(env); \ 1088 unsigned e; \ 1089 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1090 mergemask(&d[H##ESIZE(e)], \ 1091 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \ 1092 } \ 1093 mve_advance_vpt(env); \ 1094 } 1095 1096 #define DO_2OP_SAT_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1097 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1098 uint32_t rm) \ 1099 { \ 1100 TYPE *d = vd, *n = vn; \ 1101 TYPE m = rm; \ 1102 uint16_t mask = mve_element_mask(env); \ 1103 unsigned e; \ 1104 bool qc = false; \ 1105 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1106 bool sat = false; \ 1107 mergemask(&d[H##ESIZE(e)], \ 1108 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m, &sat), \ 1109 mask); \ 1110 qc |= sat & mask & 1; \ 1111 } \ 1112 if (qc) { \ 1113 env->vfp.qc[0] = qc; \ 1114 } \ 1115 mve_advance_vpt(env); \ 1116 } 1117 1118 /* provide unsigned 2-op scalar helpers for all sizes */ 1119 #define DO_2OP_SCALAR_U(OP, FN) \ 1120 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 1121 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 1122 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 1123 #define DO_2OP_SCALAR_S(OP, FN) \ 1124 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 1125 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 1126 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 1127 1128 #define DO_2OP_ACC_SCALAR_U(OP, FN) \ 1129 DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \ 1130 DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \ 1131 DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN) 1132 1133 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 1134 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 1135 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 1136 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 1137 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 1138 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 1139 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 1140 1141 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 1142 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 1143 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 1144 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 1145 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 1146 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 1147 1148 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 1149 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 1150 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 1151 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 1152 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 1153 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 1154 1155 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 1156 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 1157 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 1158 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 1159 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 1160 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 1161 1162 static int8_t do_vqdmlah_b(int8_t a, int8_t b, int8_t c, int round, bool *sat) 1163 { 1164 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 8) + (round << 7); 1165 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1166 } 1167 1168 static int16_t do_vqdmlah_h(int16_t a, int16_t b, int16_t c, 1169 int round, bool *sat) 1170 { 1171 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 16) + (round << 15); 1172 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1173 } 1174 1175 static int32_t do_vqdmlah_w(int32_t a, int32_t b, int32_t c, 1176 int round, bool *sat) 1177 { 1178 /* 1179 * Architecturally we should do the entire add, double, round 1180 * and then check for saturation. We do three saturating adds, 1181 * but we need to be careful about the order. If the first 1182 * m1 + m2 saturates then it's impossible for the *2+rc to 1183 * bring it back into the non-saturated range. However, if 1184 * m1 + m2 is negative then it's possible that doing the doubling 1185 * would take the intermediate result below INT64_MAX and the 1186 * addition of the rounding constant then brings it back in range. 1187 * So we add half the rounding constant and half the "c << esize" 1188 * before doubling rather than adding the rounding constant after 1189 * the doubling. 1190 */ 1191 int64_t m1 = (int64_t)a * b; 1192 int64_t m2 = (int64_t)c << 31; 1193 int64_t r; 1194 if (sadd64_overflow(m1, m2, &r) || 1195 sadd64_overflow(r, (round << 30), &r) || 1196 sadd64_overflow(r, r, &r)) { 1197 *sat = true; 1198 return r < 0 ? INT32_MAX : INT32_MIN; 1199 } 1200 return r >> 32; 1201 } 1202 1203 /* 1204 * The *MLAH insns are vector * scalar + vector; 1205 * the *MLASH insns are vector * vector + scalar 1206 */ 1207 #define DO_VQDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 0, S) 1208 #define DO_VQDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 0, S) 1209 #define DO_VQDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 0, S) 1210 #define DO_VQRDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 1, S) 1211 #define DO_VQRDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 1, S) 1212 #define DO_VQRDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 1, S) 1213 1214 #define DO_VQDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 0, S) 1215 #define DO_VQDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 0, S) 1216 #define DO_VQDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 0, S) 1217 #define DO_VQRDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 1, S) 1218 #define DO_VQRDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 1, S) 1219 #define DO_VQRDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 1, S) 1220 1221 DO_2OP_SAT_ACC_SCALAR(vqdmlahb, 1, int8_t, DO_VQDMLAH_B) 1222 DO_2OP_SAT_ACC_SCALAR(vqdmlahh, 2, int16_t, DO_VQDMLAH_H) 1223 DO_2OP_SAT_ACC_SCALAR(vqdmlahw, 4, int32_t, DO_VQDMLAH_W) 1224 DO_2OP_SAT_ACC_SCALAR(vqrdmlahb, 1, int8_t, DO_VQRDMLAH_B) 1225 DO_2OP_SAT_ACC_SCALAR(vqrdmlahh, 2, int16_t, DO_VQRDMLAH_H) 1226 DO_2OP_SAT_ACC_SCALAR(vqrdmlahw, 4, int32_t, DO_VQRDMLAH_W) 1227 1228 DO_2OP_SAT_ACC_SCALAR(vqdmlashb, 1, int8_t, DO_VQDMLASH_B) 1229 DO_2OP_SAT_ACC_SCALAR(vqdmlashh, 2, int16_t, DO_VQDMLASH_H) 1230 DO_2OP_SAT_ACC_SCALAR(vqdmlashw, 4, int32_t, DO_VQDMLASH_W) 1231 DO_2OP_SAT_ACC_SCALAR(vqrdmlashb, 1, int8_t, DO_VQRDMLASH_B) 1232 DO_2OP_SAT_ACC_SCALAR(vqrdmlashh, 2, int16_t, DO_VQRDMLASH_H) 1233 DO_2OP_SAT_ACC_SCALAR(vqrdmlashw, 4, int32_t, DO_VQRDMLASH_W) 1234 1235 /* Vector by scalar plus vector */ 1236 #define DO_VMLA(D, N, M) ((N) * (M) + (D)) 1237 1238 DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA) 1239 1240 /* Vector by vector plus scalar */ 1241 #define DO_VMLAS(D, N, M) ((N) * (D) + (M)) 1242 1243 DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS) 1244 1245 /* 1246 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 1247 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 1248 * SATMASK specifies which bits of the predicate mask matter for determining 1249 * whether to propagate a saturation indication into FPSCR.QC -- for 1250 * the 16x16->32 case we must check only the bit corresponding to the T or B 1251 * half that we used, but for the 32x32->64 case we propagate if the mask 1252 * bit is set for either half. 1253 */ 1254 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1255 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1256 uint32_t rm) \ 1257 { \ 1258 LTYPE *d = vd; \ 1259 TYPE *n = vn; \ 1260 TYPE m = rm; \ 1261 uint16_t mask = mve_element_mask(env); \ 1262 unsigned le; \ 1263 bool qc = false; \ 1264 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1265 bool sat = false; \ 1266 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 1267 mergemask(&d[H##LESIZE(le)], r, mask); \ 1268 qc |= sat && (mask & SATMASK); \ 1269 } \ 1270 if (qc) { \ 1271 env->vfp.qc[0] = qc; \ 1272 } \ 1273 mve_advance_vpt(env); \ 1274 } 1275 1276 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1277 { 1278 int64_t r = ((int64_t)n * m) * 2; 1279 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1280 } 1281 1282 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1283 { 1284 /* The multiply can't overflow, but the doubling might */ 1285 int64_t r = (int64_t)n * m; 1286 if (r > INT64_MAX / 2) { 1287 *sat = true; 1288 return INT64_MAX; 1289 } else if (r < INT64_MIN / 2) { 1290 *sat = true; 1291 return INT64_MIN; 1292 } else { 1293 return r * 2; 1294 } 1295 } 1296 1297 #define SATMASK16B 1 1298 #define SATMASK16T (1 << 2) 1299 #define SATMASK32 ((1 << 4) | 1) 1300 1301 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1302 do_qdmullh, SATMASK16B) 1303 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1304 do_qdmullw, SATMASK32) 1305 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1306 do_qdmullh, SATMASK16T) 1307 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1308 do_qdmullw, SATMASK32) 1309 1310 /* 1311 * Long saturating ops 1312 */ 1313 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1314 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1315 void *vm) \ 1316 { \ 1317 LTYPE *d = vd; \ 1318 TYPE *n = vn, *m = vm; \ 1319 uint16_t mask = mve_element_mask(env); \ 1320 unsigned le; \ 1321 bool qc = false; \ 1322 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1323 bool sat = false; \ 1324 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1325 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1326 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1327 qc |= sat && (mask & SATMASK); \ 1328 } \ 1329 if (qc) { \ 1330 env->vfp.qc[0] = qc; \ 1331 } \ 1332 mve_advance_vpt(env); \ 1333 } 1334 1335 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1336 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1337 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1338 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1339 1340 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1341 { 1342 m &= 0xff; 1343 if (m == 0) { 1344 return 0; 1345 } 1346 n = revbit8(n); 1347 if (m < 8) { 1348 n >>= 8 - m; 1349 } 1350 return n; 1351 } 1352 1353 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1354 { 1355 m &= 0xff; 1356 if (m == 0) { 1357 return 0; 1358 } 1359 n = revbit16(n); 1360 if (m < 16) { 1361 n >>= 16 - m; 1362 } 1363 return n; 1364 } 1365 1366 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1367 { 1368 m &= 0xff; 1369 if (m == 0) { 1370 return 0; 1371 } 1372 n = revbit32(n); 1373 if (m < 32) { 1374 n >>= 32 - m; 1375 } 1376 return n; 1377 } 1378 1379 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1380 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1381 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1382 1383 /* 1384 * Multiply add long dual accumulate ops. 1385 */ 1386 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1387 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1388 void *vm, uint64_t a) \ 1389 { \ 1390 uint16_t mask = mve_element_mask(env); \ 1391 unsigned e; \ 1392 TYPE *n = vn, *m = vm; \ 1393 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1394 if (mask & 1) { \ 1395 if (e & 1) { \ 1396 a ODDACC \ 1397 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1398 } else { \ 1399 a EVENACC \ 1400 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1401 } \ 1402 } \ 1403 } \ 1404 mve_advance_vpt(env); \ 1405 return a; \ 1406 } 1407 1408 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1409 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1410 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1411 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1412 1413 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1414 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1415 1416 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1417 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1418 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1419 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1420 1421 /* 1422 * Multiply add dual accumulate ops 1423 */ 1424 #define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1425 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1426 void *vm, uint32_t a) \ 1427 { \ 1428 uint16_t mask = mve_element_mask(env); \ 1429 unsigned e; \ 1430 TYPE *n = vn, *m = vm; \ 1431 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1432 if (mask & 1) { \ 1433 if (e & 1) { \ 1434 a ODDACC \ 1435 n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1436 } else { \ 1437 a EVENACC \ 1438 n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1439 } \ 1440 } \ 1441 } \ 1442 mve_advance_vpt(env); \ 1443 return a; \ 1444 } 1445 1446 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ 1447 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \ 1448 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \ 1449 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC) 1450 1451 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ 1452 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \ 1453 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \ 1454 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC) 1455 1456 DO_DAV_S(vmladavs, false, +=, +=) 1457 DO_DAV_U(vmladavu, false, +=, +=) 1458 DO_DAV_S(vmlsdav, false, +=, -=) 1459 DO_DAV_S(vmladavsx, true, +=, +=) 1460 DO_DAV_S(vmlsdavx, true, +=, -=) 1461 1462 /* 1463 * Rounding multiply add long dual accumulate high. In the pseudocode 1464 * this is implemented with a 72-bit internal accumulator value of which 1465 * the top 64 bits are returned. We optimize this to avoid having to 1466 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1467 * is squashed back into 64-bits after each beat. 1468 */ 1469 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1470 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1471 void *vm, uint64_t a) \ 1472 { \ 1473 uint16_t mask = mve_element_mask(env); \ 1474 unsigned e; \ 1475 TYPE *n = vn, *m = vm; \ 1476 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1477 if (mask & 1) { \ 1478 LTYPE mul; \ 1479 if (e & 1) { \ 1480 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1481 if (SUB) { \ 1482 mul = -mul; \ 1483 } \ 1484 } else { \ 1485 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1486 } \ 1487 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1488 a += mul; \ 1489 } \ 1490 } \ 1491 mve_advance_vpt(env); \ 1492 return a; \ 1493 } 1494 1495 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1496 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1497 1498 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1499 1500 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1501 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1502 1503 /* Vector add across vector */ 1504 #define DO_VADDV(OP, ESIZE, TYPE) \ 1505 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1506 uint32_t ra) \ 1507 { \ 1508 uint16_t mask = mve_element_mask(env); \ 1509 unsigned e; \ 1510 TYPE *m = vm; \ 1511 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1512 if (mask & 1) { \ 1513 ra += m[H##ESIZE(e)]; \ 1514 } \ 1515 } \ 1516 mve_advance_vpt(env); \ 1517 return ra; \ 1518 } \ 1519 1520 DO_VADDV(vaddvsb, 1, int8_t) 1521 DO_VADDV(vaddvsh, 2, int16_t) 1522 DO_VADDV(vaddvsw, 4, int32_t) 1523 DO_VADDV(vaddvub, 1, uint8_t) 1524 DO_VADDV(vaddvuh, 2, uint16_t) 1525 DO_VADDV(vaddvuw, 4, uint32_t) 1526 1527 /* 1528 * Vector max/min across vector. Unlike VADDV, we must 1529 * read ra as the element size, not its full width. 1530 * We work with int64_t internally for simplicity. 1531 */ 1532 #define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \ 1533 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1534 uint32_t ra_in) \ 1535 { \ 1536 uint16_t mask = mve_element_mask(env); \ 1537 unsigned e; \ 1538 TYPE *m = vm; \ 1539 int64_t ra = (RATYPE)ra_in; \ 1540 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1541 if (mask & 1) { \ 1542 ra = FN(ra, m[H##ESIZE(e)]); \ 1543 } \ 1544 } \ 1545 mve_advance_vpt(env); \ 1546 return ra; \ 1547 } \ 1548 1549 #define DO_VMAXMINV_U(INSN, FN) \ 1550 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \ 1551 DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \ 1552 DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN) 1553 #define DO_VMAXMINV_S(INSN, FN) \ 1554 DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \ 1555 DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \ 1556 DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN) 1557 1558 /* 1559 * Helpers for max and min of absolute values across vector: 1560 * note that we only take the absolute value of 'm', not 'n' 1561 */ 1562 static int64_t do_maxa(int64_t n, int64_t m) 1563 { 1564 if (m < 0) { 1565 m = -m; 1566 } 1567 return MAX(n, m); 1568 } 1569 1570 static int64_t do_mina(int64_t n, int64_t m) 1571 { 1572 if (m < 0) { 1573 m = -m; 1574 } 1575 return MIN(n, m); 1576 } 1577 1578 DO_VMAXMINV_S(vmaxvs, DO_MAX) 1579 DO_VMAXMINV_U(vmaxvu, DO_MAX) 1580 DO_VMAXMINV_S(vminvs, DO_MIN) 1581 DO_VMAXMINV_U(vminvu, DO_MIN) 1582 /* 1583 * VMAXAV, VMINAV treat the general purpose input as unsigned 1584 * and the vector elements as signed. 1585 */ 1586 DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa) 1587 DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa) 1588 DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa) 1589 DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) 1590 DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) 1591 DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) 1592 1593 #define DO_VABAV(OP, ESIZE, TYPE) \ 1594 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1595 void *vm, uint32_t ra) \ 1596 { \ 1597 uint16_t mask = mve_element_mask(env); \ 1598 unsigned e; \ 1599 TYPE *m = vm, *n = vn; \ 1600 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1601 if (mask & 1) { \ 1602 int64_t n0 = n[H##ESIZE(e)]; \ 1603 int64_t m0 = m[H##ESIZE(e)]; \ 1604 uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \ 1605 ra += r; \ 1606 } \ 1607 } \ 1608 mve_advance_vpt(env); \ 1609 return ra; \ 1610 } 1611 1612 DO_VABAV(vabavsb, 1, int8_t) 1613 DO_VABAV(vabavsh, 2, int16_t) 1614 DO_VABAV(vabavsw, 4, int32_t) 1615 DO_VABAV(vabavub, 1, uint8_t) 1616 DO_VABAV(vabavuh, 2, uint16_t) 1617 DO_VABAV(vabavuw, 4, uint32_t) 1618 1619 #define DO_VADDLV(OP, TYPE, LTYPE) \ 1620 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1621 uint64_t ra) \ 1622 { \ 1623 uint16_t mask = mve_element_mask(env); \ 1624 unsigned e; \ 1625 TYPE *m = vm; \ 1626 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1627 if (mask & 1) { \ 1628 ra += (LTYPE)m[H4(e)]; \ 1629 } \ 1630 } \ 1631 mve_advance_vpt(env); \ 1632 return ra; \ 1633 } \ 1634 1635 DO_VADDLV(vaddlv_s, int32_t, int64_t) 1636 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 1637 1638 /* Shifts by immediate */ 1639 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 1640 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1641 void *vm, uint32_t shift) \ 1642 { \ 1643 TYPE *d = vd, *m = vm; \ 1644 uint16_t mask = mve_element_mask(env); \ 1645 unsigned e; \ 1646 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1647 mergemask(&d[H##ESIZE(e)], \ 1648 FN(m[H##ESIZE(e)], shift), mask); \ 1649 } \ 1650 mve_advance_vpt(env); \ 1651 } 1652 1653 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 1654 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1655 void *vm, uint32_t shift) \ 1656 { \ 1657 TYPE *d = vd, *m = vm; \ 1658 uint16_t mask = mve_element_mask(env); \ 1659 unsigned e; \ 1660 bool qc = false; \ 1661 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1662 bool sat = false; \ 1663 mergemask(&d[H##ESIZE(e)], \ 1664 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 1665 qc |= sat & mask & 1; \ 1666 } \ 1667 if (qc) { \ 1668 env->vfp.qc[0] = qc; \ 1669 } \ 1670 mve_advance_vpt(env); \ 1671 } 1672 1673 /* provide unsigned 2-op shift helpers for all sizes */ 1674 #define DO_2SHIFT_U(OP, FN) \ 1675 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 1676 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 1677 DO_2SHIFT(OP##w, 4, uint32_t, FN) 1678 #define DO_2SHIFT_S(OP, FN) \ 1679 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 1680 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 1681 DO_2SHIFT(OP##w, 4, int32_t, FN) 1682 1683 #define DO_2SHIFT_SAT_U(OP, FN) \ 1684 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 1685 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 1686 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 1687 #define DO_2SHIFT_SAT_S(OP, FN) \ 1688 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 1689 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 1690 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 1691 1692 DO_2SHIFT_U(vshli_u, DO_VSHLU) 1693 DO_2SHIFT_S(vshli_s, DO_VSHLS) 1694 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 1695 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 1696 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 1697 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 1698 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 1699 DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP) 1700 DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP) 1701 1702 /* Shift-and-insert; we always work with 64 bits at a time */ 1703 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 1704 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1705 void *vm, uint32_t shift) \ 1706 { \ 1707 uint64_t *d = vd, *m = vm; \ 1708 uint16_t mask; \ 1709 uint64_t shiftmask; \ 1710 unsigned e; \ 1711 if (shift == ESIZE * 8) { \ 1712 /* \ 1713 * Only VSRI can shift by <dt>; it should mean "don't \ 1714 * update the destination". The generic logic can't handle \ 1715 * this because it would try to shift by an out-of-range \ 1716 * amount, so special case it here. \ 1717 */ \ 1718 goto done; \ 1719 } \ 1720 assert(shift < ESIZE * 8); \ 1721 mask = mve_element_mask(env); \ 1722 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 1723 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 1724 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 1725 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 1726 (d[H8(e)] & ~shiftmask); \ 1727 mergemask(&d[H8(e)], r, mask); \ 1728 } \ 1729 done: \ 1730 mve_advance_vpt(env); \ 1731 } 1732 1733 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 1734 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 1735 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 1736 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 1737 1738 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 1739 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 1740 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 1741 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 1742 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 1743 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 1744 1745 /* 1746 * Long shifts taking half-sized inputs from top or bottom of the input 1747 * vector and producing a double-width result. ESIZE, TYPE are for 1748 * the input, and LESIZE, LTYPE for the output. 1749 * Unlike the normal shift helpers, we do not handle negative shift counts, 1750 * because the long shift is strictly left-only. 1751 */ 1752 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 1753 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1754 void *vm, uint32_t shift) \ 1755 { \ 1756 LTYPE *d = vd; \ 1757 TYPE *m = vm; \ 1758 uint16_t mask = mve_element_mask(env); \ 1759 unsigned le; \ 1760 assert(shift <= 16); \ 1761 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1762 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 1763 mergemask(&d[H##LESIZE(le)], r, mask); \ 1764 } \ 1765 mve_advance_vpt(env); \ 1766 } 1767 1768 #define DO_VSHLL_ALL(OP, TOP) \ 1769 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 1770 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 1771 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 1772 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 1773 1774 DO_VSHLL_ALL(vshllb, false) 1775 DO_VSHLL_ALL(vshllt, true) 1776 1777 /* 1778 * Narrowing right shifts, taking a double sized input, shifting it 1779 * and putting the result in either the top or bottom half of the output. 1780 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 1781 */ 1782 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1783 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1784 void *vm, uint32_t shift) \ 1785 { \ 1786 LTYPE *m = vm; \ 1787 TYPE *d = vd; \ 1788 uint16_t mask = mve_element_mask(env); \ 1789 unsigned le; \ 1790 mask >>= ESIZE * TOP; \ 1791 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1792 TYPE r = FN(m[H##LESIZE(le)], shift); \ 1793 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1794 } \ 1795 mve_advance_vpt(env); \ 1796 } 1797 1798 #define DO_VSHRN_ALL(OP, FN) \ 1799 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 1800 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 1801 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 1802 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 1803 1804 static inline uint64_t do_urshr(uint64_t x, unsigned sh) 1805 { 1806 if (likely(sh < 64)) { 1807 return (x >> sh) + ((x >> (sh - 1)) & 1); 1808 } else if (sh == 64) { 1809 return x >> 63; 1810 } else { 1811 return 0; 1812 } 1813 } 1814 1815 static inline int64_t do_srshr(int64_t x, unsigned sh) 1816 { 1817 if (likely(sh < 64)) { 1818 return (x >> sh) + ((x >> (sh - 1)) & 1); 1819 } else { 1820 /* Rounding the sign bit always produces 0. */ 1821 return 0; 1822 } 1823 } 1824 1825 DO_VSHRN_ALL(vshrn, DO_SHR) 1826 DO_VSHRN_ALL(vrshrn, do_urshr) 1827 1828 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 1829 bool *satp) 1830 { 1831 if (val > max) { 1832 *satp = true; 1833 return max; 1834 } else if (val < min) { 1835 *satp = true; 1836 return min; 1837 } else { 1838 return val; 1839 } 1840 } 1841 1842 /* Saturating narrowing right shifts */ 1843 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1844 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1845 void *vm, uint32_t shift) \ 1846 { \ 1847 LTYPE *m = vm; \ 1848 TYPE *d = vd; \ 1849 uint16_t mask = mve_element_mask(env); \ 1850 bool qc = false; \ 1851 unsigned le; \ 1852 mask >>= ESIZE * TOP; \ 1853 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1854 bool sat = false; \ 1855 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 1856 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1857 qc |= sat & mask & 1; \ 1858 } \ 1859 if (qc) { \ 1860 env->vfp.qc[0] = qc; \ 1861 } \ 1862 mve_advance_vpt(env); \ 1863 } 1864 1865 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 1866 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 1867 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 1868 1869 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 1870 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 1871 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 1872 1873 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 1874 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 1875 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 1876 1877 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 1878 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 1879 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 1880 1881 #define DO_SHRN_SB(N, M, SATP) \ 1882 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 1883 #define DO_SHRN_UB(N, M, SATP) \ 1884 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1885 #define DO_SHRUN_B(N, M, SATP) \ 1886 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1887 1888 #define DO_SHRN_SH(N, M, SATP) \ 1889 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 1890 #define DO_SHRN_UH(N, M, SATP) \ 1891 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1892 #define DO_SHRUN_H(N, M, SATP) \ 1893 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1894 1895 #define DO_RSHRN_SB(N, M, SATP) \ 1896 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 1897 #define DO_RSHRN_UB(N, M, SATP) \ 1898 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 1899 #define DO_RSHRUN_B(N, M, SATP) \ 1900 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 1901 1902 #define DO_RSHRN_SH(N, M, SATP) \ 1903 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 1904 #define DO_RSHRN_UH(N, M, SATP) \ 1905 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 1906 #define DO_RSHRUN_H(N, M, SATP) \ 1907 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 1908 1909 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 1910 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 1911 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 1912 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 1913 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 1914 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 1915 1916 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 1917 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 1918 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 1919 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 1920 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 1921 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 1922 1923 #define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 1924 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 1925 { \ 1926 LTYPE *m = vm; \ 1927 TYPE *d = vd; \ 1928 uint16_t mask = mve_element_mask(env); \ 1929 unsigned le; \ 1930 mask >>= ESIZE * TOP; \ 1931 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1932 mergemask(&d[H##ESIZE(le * 2 + TOP)], \ 1933 m[H##LESIZE(le)], mask); \ 1934 } \ 1935 mve_advance_vpt(env); \ 1936 } 1937 1938 DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t) 1939 DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t) 1940 DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t) 1941 DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t) 1942 1943 #define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1944 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 1945 { \ 1946 LTYPE *m = vm; \ 1947 TYPE *d = vd; \ 1948 uint16_t mask = mve_element_mask(env); \ 1949 bool qc = false; \ 1950 unsigned le; \ 1951 mask >>= ESIZE * TOP; \ 1952 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1953 bool sat = false; \ 1954 TYPE r = FN(m[H##LESIZE(le)], &sat); \ 1955 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1956 qc |= sat & mask & 1; \ 1957 } \ 1958 if (qc) { \ 1959 env->vfp.qc[0] = qc; \ 1960 } \ 1961 mve_advance_vpt(env); \ 1962 } 1963 1964 #define DO_VMOVN_SAT_UB(BOP, TOP, FN) \ 1965 DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 1966 DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 1967 1968 #define DO_VMOVN_SAT_UH(BOP, TOP, FN) \ 1969 DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 1970 DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 1971 1972 #define DO_VMOVN_SAT_SB(BOP, TOP, FN) \ 1973 DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 1974 DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 1975 1976 #define DO_VMOVN_SAT_SH(BOP, TOP, FN) \ 1977 DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 1978 DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 1979 1980 #define DO_VQMOVN_SB(N, SATP) \ 1981 do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP) 1982 #define DO_VQMOVN_UB(N, SATP) \ 1983 do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP) 1984 #define DO_VQMOVUN_B(N, SATP) \ 1985 do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP) 1986 1987 #define DO_VQMOVN_SH(N, SATP) \ 1988 do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP) 1989 #define DO_VQMOVN_UH(N, SATP) \ 1990 do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP) 1991 #define DO_VQMOVUN_H(N, SATP) \ 1992 do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP) 1993 1994 DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB) 1995 DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH) 1996 DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB) 1997 DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH) 1998 DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B) 1999 DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H) 2000 2001 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 2002 uint32_t shift) 2003 { 2004 uint32_t *d = vd; 2005 uint16_t mask = mve_element_mask(env); 2006 unsigned e; 2007 uint32_t r; 2008 2009 /* 2010 * For each 32-bit element, we shift it left, bringing in the 2011 * low 'shift' bits of rdm at the bottom. Bits shifted out at 2012 * the top become the new rdm, if the predicate mask permits. 2013 * The final rdm value is returned to update the register. 2014 * shift == 0 here means "shift by 32 bits". 2015 */ 2016 if (shift == 0) { 2017 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2018 r = rdm; 2019 if (mask & 1) { 2020 rdm = d[H4(e)]; 2021 } 2022 mergemask(&d[H4(e)], r, mask); 2023 } 2024 } else { 2025 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 2026 2027 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2028 r = (d[H4(e)] << shift) | (rdm & shiftmask); 2029 if (mask & 1) { 2030 rdm = d[H4(e)] >> (32 - shift); 2031 } 2032 mergemask(&d[H4(e)], r, mask); 2033 } 2034 } 2035 mve_advance_vpt(env); 2036 return rdm; 2037 } 2038 2039 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2040 { 2041 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 2042 } 2043 2044 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 2045 { 2046 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 2047 } 2048 2049 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2050 { 2051 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 2052 } 2053 2054 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2055 { 2056 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 2057 } 2058 2059 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2060 { 2061 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 2062 } 2063 2064 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2065 { 2066 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 2067 } 2068 2069 /* Operate on 64-bit values, but saturate at 48 bits */ 2070 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 2071 bool round, uint32_t *sat) 2072 { 2073 int64_t val, extval; 2074 2075 if (shift <= -48) { 2076 /* Rounding the sign bit always produces 0. */ 2077 if (round) { 2078 return 0; 2079 } 2080 return src >> 63; 2081 } else if (shift < 0) { 2082 if (round) { 2083 src >>= -shift - 1; 2084 val = (src >> 1) + (src & 1); 2085 } else { 2086 val = src >> -shift; 2087 } 2088 extval = sextract64(val, 0, 48); 2089 if (!sat || val == extval) { 2090 return extval; 2091 } 2092 } else if (shift < 48) { 2093 int64_t extval = sextract64(src << shift, 0, 48); 2094 if (!sat || src == (extval >> shift)) { 2095 return extval; 2096 } 2097 } else if (!sat || src == 0) { 2098 return 0; 2099 } 2100 2101 *sat = 1; 2102 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 2103 } 2104 2105 /* Operate on 64-bit values, but saturate at 48 bits */ 2106 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 2107 bool round, uint32_t *sat) 2108 { 2109 uint64_t val, extval; 2110 2111 if (shift <= -(48 + round)) { 2112 return 0; 2113 } else if (shift < 0) { 2114 if (round) { 2115 val = src >> (-shift - 1); 2116 val = (val >> 1) + (val & 1); 2117 } else { 2118 val = src >> -shift; 2119 } 2120 extval = extract64(val, 0, 48); 2121 if (!sat || val == extval) { 2122 return extval; 2123 } 2124 } else if (shift < 48) { 2125 uint64_t extval = extract64(src << shift, 0, 48); 2126 if (!sat || src == (extval >> shift)) { 2127 return extval; 2128 } 2129 } else if (!sat || src == 0) { 2130 return 0; 2131 } 2132 2133 *sat = 1; 2134 return MAKE_64BIT_MASK(0, 48); 2135 } 2136 2137 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 2138 { 2139 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 2140 } 2141 2142 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 2143 { 2144 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 2145 } 2146 2147 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2148 { 2149 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2150 } 2151 2152 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2153 { 2154 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2155 } 2156 2157 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2158 { 2159 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 2160 } 2161 2162 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 2163 { 2164 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 2165 } 2166 2167 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \ 2168 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2169 uint32_t offset, uint32_t imm) \ 2170 { \ 2171 TYPE *d = vd; \ 2172 uint16_t mask = mve_element_mask(env); \ 2173 unsigned e; \ 2174 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2175 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2176 offset = FN(offset, imm); \ 2177 } \ 2178 mve_advance_vpt(env); \ 2179 return offset; \ 2180 } 2181 2182 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ 2183 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2184 uint32_t offset, uint32_t wrap, \ 2185 uint32_t imm) \ 2186 { \ 2187 TYPE *d = vd; \ 2188 uint16_t mask = mve_element_mask(env); \ 2189 unsigned e; \ 2190 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2191 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2192 offset = FN(offset, wrap, imm); \ 2193 } \ 2194 mve_advance_vpt(env); \ 2195 return offset; \ 2196 } 2197 2198 #define DO_VIDUP_ALL(OP, FN) \ 2199 DO_VIDUP(OP##b, 1, int8_t, FN) \ 2200 DO_VIDUP(OP##h, 2, int16_t, FN) \ 2201 DO_VIDUP(OP##w, 4, int32_t, FN) 2202 2203 #define DO_VIWDUP_ALL(OP, FN) \ 2204 DO_VIWDUP(OP##b, 1, int8_t, FN) \ 2205 DO_VIWDUP(OP##h, 2, int16_t, FN) \ 2206 DO_VIWDUP(OP##w, 4, int32_t, FN) 2207 2208 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2209 { 2210 offset += imm; 2211 if (offset == wrap) { 2212 offset = 0; 2213 } 2214 return offset; 2215 } 2216 2217 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2218 { 2219 if (offset == 0) { 2220 offset = wrap; 2221 } 2222 offset -= imm; 2223 return offset; 2224 } 2225 2226 DO_VIDUP_ALL(vidup, DO_ADD) 2227 DO_VIWDUP_ALL(viwdup, do_add_wrap) 2228 DO_VIWDUP_ALL(vdwdup, do_sub_wrap) 2229 2230 /* 2231 * Vector comparison. 2232 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. 2233 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. 2234 * P0 bits otherwise are updated with the results of the comparisons. 2235 * We must also keep unchanged the MASK fields at the top of v7m.vpr. 2236 */ 2237 #define DO_VCMP(OP, ESIZE, TYPE, FN) \ 2238 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 2239 { \ 2240 TYPE *n = vn, *m = vm; \ 2241 uint16_t mask = mve_element_mask(env); \ 2242 uint16_t eci_mask = mve_eci_mask(env); \ 2243 uint16_t beatpred = 0; \ 2244 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2245 unsigned e; \ 2246 for (e = 0; e < 16 / ESIZE; e++) { \ 2247 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ 2248 /* Comparison sets 0/1 bits for each byte in the element */ \ 2249 beatpred |= r * emask; \ 2250 emask <<= ESIZE; \ 2251 } \ 2252 beatpred &= mask; \ 2253 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2254 (beatpred & eci_mask); \ 2255 mve_advance_vpt(env); \ 2256 } 2257 2258 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ 2259 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 2260 uint32_t rm) \ 2261 { \ 2262 TYPE *n = vn; \ 2263 uint16_t mask = mve_element_mask(env); \ 2264 uint16_t eci_mask = mve_eci_mask(env); \ 2265 uint16_t beatpred = 0; \ 2266 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2267 unsigned e; \ 2268 for (e = 0; e < 16 / ESIZE; e++) { \ 2269 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \ 2270 /* Comparison sets 0/1 bits for each byte in the element */ \ 2271 beatpred |= r * emask; \ 2272 emask <<= ESIZE; \ 2273 } \ 2274 beatpred &= mask; \ 2275 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2276 (beatpred & eci_mask); \ 2277 mve_advance_vpt(env); \ 2278 } 2279 2280 #define DO_VCMP_S(OP, FN) \ 2281 DO_VCMP(OP##b, 1, int8_t, FN) \ 2282 DO_VCMP(OP##h, 2, int16_t, FN) \ 2283 DO_VCMP(OP##w, 4, int32_t, FN) \ 2284 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ 2285 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ 2286 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) 2287 2288 #define DO_VCMP_U(OP, FN) \ 2289 DO_VCMP(OP##b, 1, uint8_t, FN) \ 2290 DO_VCMP(OP##h, 2, uint16_t, FN) \ 2291 DO_VCMP(OP##w, 4, uint32_t, FN) \ 2292 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ 2293 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ 2294 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) 2295 2296 #define DO_EQ(N, M) ((N) == (M)) 2297 #define DO_NE(N, M) ((N) != (M)) 2298 #define DO_EQ(N, M) ((N) == (M)) 2299 #define DO_EQ(N, M) ((N) == (M)) 2300 #define DO_GE(N, M) ((N) >= (M)) 2301 #define DO_LT(N, M) ((N) < (M)) 2302 #define DO_GT(N, M) ((N) > (M)) 2303 #define DO_LE(N, M) ((N) <= (M)) 2304 2305 DO_VCMP_U(vcmpeq, DO_EQ) 2306 DO_VCMP_U(vcmpne, DO_NE) 2307 DO_VCMP_U(vcmpcs, DO_GE) 2308 DO_VCMP_U(vcmphi, DO_GT) 2309 DO_VCMP_S(vcmpge, DO_GE) 2310 DO_VCMP_S(vcmplt, DO_LT) 2311 DO_VCMP_S(vcmpgt, DO_GT) 2312 DO_VCMP_S(vcmple, DO_LE) 2313 2314 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) 2315 { 2316 /* 2317 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n] 2318 * but note that whether bytes are written to Qd is still subject 2319 * to (all forms of) predication in the usual way. 2320 */ 2321 uint64_t *d = vd, *n = vn, *m = vm; 2322 uint16_t mask = mve_element_mask(env); 2323 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 2324 unsigned e; 2325 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) { 2326 uint64_t r = m[H8(e)]; 2327 mergemask(&r, n[H8(e)], p0); 2328 mergemask(&d[H8(e)], r, mask); 2329 } 2330 mve_advance_vpt(env); 2331 } 2332 2333 void HELPER(mve_vpnot)(CPUARMState *env) 2334 { 2335 /* 2336 * P0 bits for unexecuted beats (where eci_mask is 0) are unchanged. 2337 * P0 bits for predicated lanes in executed bits (where mask is 0) are 0. 2338 * P0 bits otherwise are inverted. 2339 * (This is the same logic as VCMP.) 2340 * This insn is itself subject to predication and to beat-wise execution, 2341 * and after it executes VPT state advances in the usual way. 2342 */ 2343 uint16_t mask = mve_element_mask(env); 2344 uint16_t eci_mask = mve_eci_mask(env); 2345 uint16_t beatpred = ~env->v7m.vpr & mask; 2346 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask); 2347 mve_advance_vpt(env); 2348 } 2349 2350 /* 2351 * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed, 2352 * otherwise set according to value of Rn. The calculation of 2353 * newmask here works in the same way as the calculation of the 2354 * ltpmask in mve_element_mask(), but we have pre-calculated 2355 * the masklen in the generated code. 2356 */ 2357 void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen) 2358 { 2359 uint16_t mask = mve_element_mask(env); 2360 uint16_t eci_mask = mve_eci_mask(env); 2361 uint16_t newmask; 2362 2363 assert(masklen <= 16); 2364 newmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 2365 newmask &= mask; 2366 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask); 2367 mve_advance_vpt(env); 2368 } 2369 2370 #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ 2371 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2372 { \ 2373 TYPE *d = vd, *m = vm; \ 2374 uint16_t mask = mve_element_mask(env); \ 2375 unsigned e; \ 2376 bool qc = false; \ 2377 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2378 bool sat = false; \ 2379 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)], &sat), mask); \ 2380 qc |= sat & mask & 1; \ 2381 } \ 2382 if (qc) { \ 2383 env->vfp.qc[0] = qc; \ 2384 } \ 2385 mve_advance_vpt(env); \ 2386 } 2387 2388 #define DO_VQABS_B(N, SATP) \ 2389 do_sat_bhs(DO_ABS((int64_t)N), INT8_MIN, INT8_MAX, SATP) 2390 #define DO_VQABS_H(N, SATP) \ 2391 do_sat_bhs(DO_ABS((int64_t)N), INT16_MIN, INT16_MAX, SATP) 2392 #define DO_VQABS_W(N, SATP) \ 2393 do_sat_bhs(DO_ABS((int64_t)N), INT32_MIN, INT32_MAX, SATP) 2394 2395 #define DO_VQNEG_B(N, SATP) do_sat_bhs(-(int64_t)N, INT8_MIN, INT8_MAX, SATP) 2396 #define DO_VQNEG_H(N, SATP) do_sat_bhs(-(int64_t)N, INT16_MIN, INT16_MAX, SATP) 2397 #define DO_VQNEG_W(N, SATP) do_sat_bhs(-(int64_t)N, INT32_MIN, INT32_MAX, SATP) 2398 2399 DO_1OP_SAT(vqabsb, 1, int8_t, DO_VQABS_B) 2400 DO_1OP_SAT(vqabsh, 2, int16_t, DO_VQABS_H) 2401 DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W) 2402 2403 DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B) 2404 DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H) 2405 DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W) 2406 2407 /* 2408 * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its 2409 * absolute value; we then do an unsigned comparison. 2410 */ 2411 #define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \ 2412 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2413 { \ 2414 UTYPE *d = vd; \ 2415 STYPE *m = vm; \ 2416 uint16_t mask = mve_element_mask(env); \ 2417 unsigned e; \ 2418 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2419 UTYPE r = DO_ABS(m[H##ESIZE(e)]); \ 2420 r = FN(d[H##ESIZE(e)], r); \ 2421 mergemask(&d[H##ESIZE(e)], r, mask); \ 2422 } \ 2423 mve_advance_vpt(env); \ 2424 } 2425 2426 DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX) 2427 DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX) 2428 DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) 2429 DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) 2430 DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) 2431 DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) 2432