1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "accel/tcg/cpu-ldst.h" 26 #include "tcg/tcg.h" 27 #include "fpu/softfloat.h" 28 #include "crypto/clmul.h" 29 30 static uint16_t mve_eci_mask(CPUARMState *env) 31 { 32 /* 33 * Return the mask of which elements in the MVE vector correspond 34 * to beats being executed. The mask has 1 bits for executed lanes 35 * and 0 bits where ECI says this beat was already executed. 36 */ 37 int eci; 38 39 if ((env->condexec_bits & 0xf) != 0) { 40 return 0xffff; 41 } 42 43 eci = env->condexec_bits >> 4; 44 switch (eci) { 45 case ECI_NONE: 46 return 0xffff; 47 case ECI_A0: 48 return 0xfff0; 49 case ECI_A0A1: 50 return 0xff00; 51 case ECI_A0A1A2: 52 case ECI_A0A1A2B0: 53 return 0xf000; 54 default: 55 g_assert_not_reached(); 56 } 57 } 58 59 static uint16_t mve_element_mask(CPUARMState *env) 60 { 61 /* 62 * Return the mask of which elements in the MVE vector should be 63 * updated. This is a combination of multiple things: 64 * (1) by default, we update every lane in the vector 65 * (2) VPT predication stores its state in the VPR register; 66 * (3) low-overhead-branch tail predication will mask out part 67 * the vector on the final iteration of the loop 68 * (4) if EPSR.ECI is set then we must execute only some beats 69 * of the insn 70 * We combine all these into a 16-bit result with the same semantics 71 * as VPR.P0: 0 to mask the lane, 1 if it is active. 72 * 8-bit vector ops will look at all bits of the result; 73 * 16-bit ops will look at bits 0, 2, 4, ...; 74 * 32-bit ops will look at bits 0, 4, 8 and 12. 75 * Compare pseudocode GetCurInstrBeat(), though that only returns 76 * the 4-bit slice of the mask corresponding to a single beat. 77 */ 78 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 79 80 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 81 mask |= 0xff; 82 } 83 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 84 mask |= 0xff00; 85 } 86 87 if (env->v7m.ltpsize < 4 && 88 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 89 /* 90 * Tail predication active, and this is the last loop iteration. 91 * The element size is (1 << ltpsize), and we only want to process 92 * loopcount elements, so we want to retain the least significant 93 * (loopcount * esize) predicate bits and zero out bits above that. 94 */ 95 int masklen = env->regs[14] << env->v7m.ltpsize; 96 assert(masklen <= 16); 97 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 98 mask &= ltpmask; 99 } 100 101 /* 102 * ECI bits indicate which beats are already executed; 103 * we handle this by effectively predicating them out. 104 */ 105 mask &= mve_eci_mask(env); 106 return mask; 107 } 108 109 static void mve_advance_vpt(CPUARMState *env) 110 { 111 /* Advance the VPT and ECI state if necessary */ 112 uint32_t vpr = env->v7m.vpr; 113 unsigned mask01, mask23; 114 uint16_t inv_mask; 115 uint16_t eci_mask = mve_eci_mask(env); 116 117 if ((env->condexec_bits & 0xf) == 0) { 118 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 119 (ECI_A0 << 4) : (ECI_NONE << 4); 120 } 121 122 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 123 /* VPT not enabled, nothing to do */ 124 return; 125 } 126 127 /* Invert P0 bits if needed, but only for beats we actually executed */ 128 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 129 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 130 /* Start by assuming we invert all bits corresponding to executed beats */ 131 inv_mask = eci_mask; 132 if (mask01 <= 8) { 133 /* MASK01 says don't invert low half of P0 */ 134 inv_mask &= ~0xff; 135 } 136 if (mask23 <= 8) { 137 /* MASK23 says don't invert high half of P0 */ 138 inv_mask &= ~0xff00; 139 } 140 vpr ^= inv_mask; 141 /* Only update MASK01 if beat 1 executed */ 142 if (eci_mask & 0xf0) { 143 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 144 } 145 /* Beat 3 always executes, so update MASK23 */ 146 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 147 env->v7m.vpr = vpr; 148 } 149 150 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 151 #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ 152 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 153 { \ 154 TYPE *d = vd; \ 155 uint16_t mask = mve_element_mask(env); \ 156 uint16_t eci_mask = mve_eci_mask(env); \ 157 unsigned b, e; \ 158 /* \ 159 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 160 * beats so we don't care if we update part of the dest and \ 161 * then take an exception. \ 162 */ \ 163 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 164 if (eci_mask & (1 << b)) { \ 165 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 166 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 167 } \ 168 addr += MSIZE; \ 169 } \ 170 mve_advance_vpt(env); \ 171 } 172 173 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ 174 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 175 { \ 176 TYPE *d = vd; \ 177 uint16_t mask = mve_element_mask(env); \ 178 unsigned b, e; \ 179 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 180 if (mask & (1 << b)) { \ 181 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 182 } \ 183 addr += MSIZE; \ 184 } \ 185 mve_advance_vpt(env); \ 186 } 187 188 DO_VLDR(vldrb, 1, ldub, 1, uint8_t) 189 DO_VLDR(vldrh, 2, lduw, 2, uint16_t) 190 DO_VLDR(vldrw, 4, ldl, 4, uint32_t) 191 192 DO_VSTR(vstrb, 1, stb, 1, uint8_t) 193 DO_VSTR(vstrh, 2, stw, 2, uint16_t) 194 DO_VSTR(vstrw, 4, stl, 4, uint32_t) 195 196 DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t) 197 DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t) 198 DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t) 199 DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t) 200 DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t) 201 DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t) 202 203 DO_VSTR(vstrb_h, 1, stb, 2, int16_t) 204 DO_VSTR(vstrb_w, 1, stb, 4, int32_t) 205 DO_VSTR(vstrh_w, 2, stw, 4, int32_t) 206 207 #undef DO_VLDR 208 #undef DO_VSTR 209 210 /* 211 * Gather loads/scatter stores. Here each element of Qm specifies 212 * an offset to use from the base register Rm. In the _os_ versions 213 * that offset is scaled by the element size. 214 * For loads, predicated lanes are zeroed instead of retaining 215 * their previous values. 216 */ 217 #define DO_VLDR_SG(OP, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN, WB) \ 218 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 219 uint32_t base) \ 220 { \ 221 TYPE *d = vd; \ 222 OFFTYPE *m = vm; \ 223 uint16_t mask = mve_element_mask(env); \ 224 uint16_t eci_mask = mve_eci_mask(env); \ 225 unsigned e; \ 226 uint32_t addr; \ 227 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 228 if (!(eci_mask & 1)) { \ 229 continue; \ 230 } \ 231 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 232 d[H##ESIZE(e)] = (mask & 1) ? \ 233 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 234 if (WB) { \ 235 m[H##ESIZE(e)] = addr; \ 236 } \ 237 } \ 238 mve_advance_vpt(env); \ 239 } 240 241 /* We know here TYPE is unsigned so always the same as the offset type */ 242 #define DO_VSTR_SG(OP, STTYPE, ESIZE, TYPE, ADDRFN, WB) \ 243 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 244 uint32_t base) \ 245 { \ 246 TYPE *d = vd; \ 247 TYPE *m = vm; \ 248 uint16_t mask = mve_element_mask(env); \ 249 uint16_t eci_mask = mve_eci_mask(env); \ 250 unsigned e; \ 251 uint32_t addr; \ 252 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 253 if (!(eci_mask & 1)) { \ 254 continue; \ 255 } \ 256 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 257 if (mask & 1) { \ 258 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 259 } \ 260 if (WB) { \ 261 m[H##ESIZE(e)] = addr; \ 262 } \ 263 } \ 264 mve_advance_vpt(env); \ 265 } 266 267 /* 268 * 64-bit accesses are slightly different: they are done as two 32-bit 269 * accesses, controlled by the predicate mask for the relevant beat, 270 * and with a single 32-bit offset in the first of the two Qm elements. 271 * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little). 272 * Address writeback happens on the odd beats and updates the address 273 * stored in the even-beat element. 274 */ 275 #define DO_VLDR64_SG(OP, ADDRFN, WB) \ 276 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 277 uint32_t base) \ 278 { \ 279 uint32_t *d = vd; \ 280 uint32_t *m = vm; \ 281 uint16_t mask = mve_element_mask(env); \ 282 uint16_t eci_mask = mve_eci_mask(env); \ 283 unsigned e; \ 284 uint32_t addr; \ 285 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 286 if (!(eci_mask & 1)) { \ 287 continue; \ 288 } \ 289 addr = ADDRFN(base, m[H4(e & ~1)]); \ 290 addr += 4 * (e & 1); \ 291 d[H4(e)] = (mask & 1) ? cpu_ldl_data_ra(env, addr, GETPC()) : 0; \ 292 if (WB && (e & 1)) { \ 293 m[H4(e & ~1)] = addr - 4; \ 294 } \ 295 } \ 296 mve_advance_vpt(env); \ 297 } 298 299 #define DO_VSTR64_SG(OP, ADDRFN, WB) \ 300 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 301 uint32_t base) \ 302 { \ 303 uint32_t *d = vd; \ 304 uint32_t *m = vm; \ 305 uint16_t mask = mve_element_mask(env); \ 306 uint16_t eci_mask = mve_eci_mask(env); \ 307 unsigned e; \ 308 uint32_t addr; \ 309 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 310 if (!(eci_mask & 1)) { \ 311 continue; \ 312 } \ 313 addr = ADDRFN(base, m[H4(e & ~1)]); \ 314 addr += 4 * (e & 1); \ 315 if (mask & 1) { \ 316 cpu_stl_data_ra(env, addr, d[H4(e)], GETPC()); \ 317 } \ 318 if (WB && (e & 1)) { \ 319 m[H4(e & ~1)] = addr - 4; \ 320 } \ 321 } \ 322 mve_advance_vpt(env); \ 323 } 324 325 #define ADDR_ADD(BASE, OFFSET) ((BASE) + (OFFSET)) 326 #define ADDR_ADD_OSH(BASE, OFFSET) ((BASE) + ((OFFSET) << 1)) 327 #define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2)) 328 #define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3)) 329 330 DO_VLDR_SG(vldrb_sg_sh, ldsb, 2, int16_t, uint16_t, ADDR_ADD, false) 331 DO_VLDR_SG(vldrb_sg_sw, ldsb, 4, int32_t, uint32_t, ADDR_ADD, false) 332 DO_VLDR_SG(vldrh_sg_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD, false) 333 334 DO_VLDR_SG(vldrb_sg_ub, ldub, 1, uint8_t, uint8_t, ADDR_ADD, false) 335 DO_VLDR_SG(vldrb_sg_uh, ldub, 2, uint16_t, uint16_t, ADDR_ADD, false) 336 DO_VLDR_SG(vldrb_sg_uw, ldub, 4, uint32_t, uint32_t, ADDR_ADD, false) 337 DO_VLDR_SG(vldrh_sg_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD, false) 338 DO_VLDR_SG(vldrh_sg_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD, false) 339 DO_VLDR_SG(vldrw_sg_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false) 340 DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) 341 342 DO_VLDR_SG(vldrh_sg_os_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD_OSH, false) 343 DO_VLDR_SG(vldrh_sg_os_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD_OSH, false) 344 DO_VLDR_SG(vldrh_sg_os_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD_OSH, false) 345 DO_VLDR_SG(vldrw_sg_os_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW, false) 346 DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) 347 348 DO_VSTR_SG(vstrb_sg_ub, stb, 1, uint8_t, ADDR_ADD, false) 349 DO_VSTR_SG(vstrb_sg_uh, stb, 2, uint16_t, ADDR_ADD, false) 350 DO_VSTR_SG(vstrb_sg_uw, stb, 4, uint32_t, ADDR_ADD, false) 351 DO_VSTR_SG(vstrh_sg_uh, stw, 2, uint16_t, ADDR_ADD, false) 352 DO_VSTR_SG(vstrh_sg_uw, stw, 4, uint32_t, ADDR_ADD, false) 353 DO_VSTR_SG(vstrw_sg_uw, stl, 4, uint32_t, ADDR_ADD, false) 354 DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) 355 356 DO_VSTR_SG(vstrh_sg_os_uh, stw, 2, uint16_t, ADDR_ADD_OSH, false) 357 DO_VSTR_SG(vstrh_sg_os_uw, stw, 4, uint32_t, ADDR_ADD_OSH, false) 358 DO_VSTR_SG(vstrw_sg_os_uw, stl, 4, uint32_t, ADDR_ADD_OSW, false) 359 DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) 360 361 DO_VLDR_SG(vldrw_sg_wb_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true) 362 DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) 363 DO_VSTR_SG(vstrw_sg_wb_uw, stl, 4, uint32_t, ADDR_ADD, true) 364 DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) 365 366 /* 367 * Deinterleaving loads/interleaving stores. 368 * 369 * For these helpers we are passed the index of the first Qreg 370 * (VLD2/VST2 will also access Qn+1, VLD4/VST4 access Qn .. Qn+3) 371 * and the value of the base address register Rn. 372 * The helpers are specialized for pattern and element size, so 373 * for instance vld42h is VLD4 with pattern 2, element size MO_16. 374 * 375 * These insns are beatwise but not predicated, so we must honour ECI, 376 * but need not look at mve_element_mask(). 377 * 378 * The pseudocode implements these insns with multiple memory accesses 379 * of the element size, but rules R_VVVG and R_FXDM permit us to make 380 * one 32-bit memory access per beat. 381 */ 382 #define DO_VLD4B(OP, O1, O2, O3, O4) \ 383 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 384 uint32_t base) \ 385 { \ 386 int beat, e; \ 387 uint16_t mask = mve_eci_mask(env); \ 388 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 389 uint32_t addr, data; \ 390 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 391 if ((mask & 1) == 0) { \ 392 /* ECI says skip this beat */ \ 393 continue; \ 394 } \ 395 addr = base + off[beat] * 4; \ 396 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 397 for (e = 0; e < 4; e++, data >>= 8) { \ 398 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 399 qd[H1(off[beat])] = data; \ 400 } \ 401 } \ 402 } 403 404 #define DO_VLD4H(OP, O1, O2) \ 405 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 406 uint32_t base) \ 407 { \ 408 int beat; \ 409 uint16_t mask = mve_eci_mask(env); \ 410 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 411 uint32_t addr, data; \ 412 int y; /* y counts 0 2 0 2 */ \ 413 uint16_t *qd; \ 414 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 415 if ((mask & 1) == 0) { \ 416 /* ECI says skip this beat */ \ 417 continue; \ 418 } \ 419 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 420 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 421 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 422 qd[H2(off[beat])] = data; \ 423 data >>= 16; \ 424 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 425 qd[H2(off[beat])] = data; \ 426 } \ 427 } 428 429 #define DO_VLD4W(OP, O1, O2, O3, O4) \ 430 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 431 uint32_t base) \ 432 { \ 433 int beat; \ 434 uint16_t mask = mve_eci_mask(env); \ 435 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 436 uint32_t addr, data; \ 437 uint32_t *qd; \ 438 int y; \ 439 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 440 if ((mask & 1) == 0) { \ 441 /* ECI says skip this beat */ \ 442 continue; \ 443 } \ 444 addr = base + off[beat] * 4; \ 445 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 446 y = (beat + (O1 & 2)) & 3; \ 447 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 448 qd[H4(off[beat] >> 2)] = data; \ 449 } \ 450 } 451 452 DO_VLD4B(vld40b, 0, 1, 10, 11) 453 DO_VLD4B(vld41b, 2, 3, 12, 13) 454 DO_VLD4B(vld42b, 4, 5, 14, 15) 455 DO_VLD4B(vld43b, 6, 7, 8, 9) 456 457 DO_VLD4H(vld40h, 0, 5) 458 DO_VLD4H(vld41h, 1, 6) 459 DO_VLD4H(vld42h, 2, 7) 460 DO_VLD4H(vld43h, 3, 4) 461 462 DO_VLD4W(vld40w, 0, 1, 10, 11) 463 DO_VLD4W(vld41w, 2, 3, 12, 13) 464 DO_VLD4W(vld42w, 4, 5, 14, 15) 465 DO_VLD4W(vld43w, 6, 7, 8, 9) 466 467 #define DO_VLD2B(OP, O1, O2, O3, O4) \ 468 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 469 uint32_t base) \ 470 { \ 471 int beat, e; \ 472 uint16_t mask = mve_eci_mask(env); \ 473 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 474 uint32_t addr, data; \ 475 uint8_t *qd; \ 476 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 477 if ((mask & 1) == 0) { \ 478 /* ECI says skip this beat */ \ 479 continue; \ 480 } \ 481 addr = base + off[beat] * 2; \ 482 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 483 for (e = 0; e < 4; e++, data >>= 8) { \ 484 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 485 qd[H1(off[beat] + (e >> 1))] = data; \ 486 } \ 487 } \ 488 } 489 490 #define DO_VLD2H(OP, O1, O2, O3, O4) \ 491 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 492 uint32_t base) \ 493 { \ 494 int beat; \ 495 uint16_t mask = mve_eci_mask(env); \ 496 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 497 uint32_t addr, data; \ 498 int e; \ 499 uint16_t *qd; \ 500 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 501 if ((mask & 1) == 0) { \ 502 /* ECI says skip this beat */ \ 503 continue; \ 504 } \ 505 addr = base + off[beat] * 4; \ 506 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 507 for (e = 0; e < 2; e++, data >>= 16) { \ 508 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 509 qd[H2(off[beat])] = data; \ 510 } \ 511 } \ 512 } 513 514 #define DO_VLD2W(OP, O1, O2, O3, O4) \ 515 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 516 uint32_t base) \ 517 { \ 518 int beat; \ 519 uint16_t mask = mve_eci_mask(env); \ 520 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 521 uint32_t addr, data; \ 522 uint32_t *qd; \ 523 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 524 if ((mask & 1) == 0) { \ 525 /* ECI says skip this beat */ \ 526 continue; \ 527 } \ 528 addr = base + off[beat]; \ 529 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 530 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 531 qd[H4(off[beat] >> 3)] = data; \ 532 } \ 533 } 534 535 DO_VLD2B(vld20b, 0, 2, 12, 14) 536 DO_VLD2B(vld21b, 4, 6, 8, 10) 537 538 DO_VLD2H(vld20h, 0, 1, 6, 7) 539 DO_VLD2H(vld21h, 2, 3, 4, 5) 540 541 DO_VLD2W(vld20w, 0, 4, 24, 28) 542 DO_VLD2W(vld21w, 8, 12, 16, 20) 543 544 #define DO_VST4B(OP, O1, O2, O3, O4) \ 545 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 546 uint32_t base) \ 547 { \ 548 int beat, e; \ 549 uint16_t mask = mve_eci_mask(env); \ 550 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 551 uint32_t addr, data; \ 552 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 553 if ((mask & 1) == 0) { \ 554 /* ECI says skip this beat */ \ 555 continue; \ 556 } \ 557 addr = base + off[beat] * 4; \ 558 data = 0; \ 559 for (e = 3; e >= 0; e--) { \ 560 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 561 data = (data << 8) | qd[H1(off[beat])]; \ 562 } \ 563 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 564 } \ 565 } 566 567 #define DO_VST4H(OP, O1, O2) \ 568 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 569 uint32_t base) \ 570 { \ 571 int beat; \ 572 uint16_t mask = mve_eci_mask(env); \ 573 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 574 uint32_t addr, data; \ 575 int y; /* y counts 0 2 0 2 */ \ 576 uint16_t *qd; \ 577 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 578 if ((mask & 1) == 0) { \ 579 /* ECI says skip this beat */ \ 580 continue; \ 581 } \ 582 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 583 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 584 data = qd[H2(off[beat])]; \ 585 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 586 data |= qd[H2(off[beat])] << 16; \ 587 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 588 } \ 589 } 590 591 #define DO_VST4W(OP, O1, O2, O3, O4) \ 592 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 593 uint32_t base) \ 594 { \ 595 int beat; \ 596 uint16_t mask = mve_eci_mask(env); \ 597 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 598 uint32_t addr, data; \ 599 uint32_t *qd; \ 600 int y; \ 601 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 602 if ((mask & 1) == 0) { \ 603 /* ECI says skip this beat */ \ 604 continue; \ 605 } \ 606 addr = base + off[beat] * 4; \ 607 y = (beat + (O1 & 2)) & 3; \ 608 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 609 data = qd[H4(off[beat] >> 2)]; \ 610 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 611 } \ 612 } 613 614 DO_VST4B(vst40b, 0, 1, 10, 11) 615 DO_VST4B(vst41b, 2, 3, 12, 13) 616 DO_VST4B(vst42b, 4, 5, 14, 15) 617 DO_VST4B(vst43b, 6, 7, 8, 9) 618 619 DO_VST4H(vst40h, 0, 5) 620 DO_VST4H(vst41h, 1, 6) 621 DO_VST4H(vst42h, 2, 7) 622 DO_VST4H(vst43h, 3, 4) 623 624 DO_VST4W(vst40w, 0, 1, 10, 11) 625 DO_VST4W(vst41w, 2, 3, 12, 13) 626 DO_VST4W(vst42w, 4, 5, 14, 15) 627 DO_VST4W(vst43w, 6, 7, 8, 9) 628 629 #define DO_VST2B(OP, O1, O2, O3, O4) \ 630 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 631 uint32_t base) \ 632 { \ 633 int beat, e; \ 634 uint16_t mask = mve_eci_mask(env); \ 635 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 636 uint32_t addr, data; \ 637 uint8_t *qd; \ 638 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 639 if ((mask & 1) == 0) { \ 640 /* ECI says skip this beat */ \ 641 continue; \ 642 } \ 643 addr = base + off[beat] * 2; \ 644 data = 0; \ 645 for (e = 3; e >= 0; e--) { \ 646 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 647 data = (data << 8) | qd[H1(off[beat] + (e >> 1))]; \ 648 } \ 649 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 650 } \ 651 } 652 653 #define DO_VST2H(OP, O1, O2, O3, O4) \ 654 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 655 uint32_t base) \ 656 { \ 657 int beat; \ 658 uint16_t mask = mve_eci_mask(env); \ 659 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 660 uint32_t addr, data; \ 661 int e; \ 662 uint16_t *qd; \ 663 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 664 if ((mask & 1) == 0) { \ 665 /* ECI says skip this beat */ \ 666 continue; \ 667 } \ 668 addr = base + off[beat] * 4; \ 669 data = 0; \ 670 for (e = 1; e >= 0; e--) { \ 671 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 672 data = (data << 16) | qd[H2(off[beat])]; \ 673 } \ 674 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 675 } \ 676 } 677 678 #define DO_VST2W(OP, O1, O2, O3, O4) \ 679 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 680 uint32_t base) \ 681 { \ 682 int beat; \ 683 uint16_t mask = mve_eci_mask(env); \ 684 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 685 uint32_t addr, data; \ 686 uint32_t *qd; \ 687 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 688 if ((mask & 1) == 0) { \ 689 /* ECI says skip this beat */ \ 690 continue; \ 691 } \ 692 addr = base + off[beat]; \ 693 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 694 data = qd[H4(off[beat] >> 3)]; \ 695 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 696 } \ 697 } 698 699 DO_VST2B(vst20b, 0, 2, 12, 14) 700 DO_VST2B(vst21b, 4, 6, 8, 10) 701 702 DO_VST2H(vst20h, 0, 1, 6, 7) 703 DO_VST2H(vst21h, 2, 3, 4, 5) 704 705 DO_VST2W(vst20w, 0, 4, 24, 28) 706 DO_VST2W(vst21w, 8, 12, 16, 20) 707 708 /* 709 * The mergemask(D, R, M) macro performs the operation "*D = R" but 710 * storing only the bytes which correspond to 1 bits in M, 711 * leaving other bytes in *D unchanged. We use _Generic 712 * to select the correct implementation based on the type of D. 713 */ 714 715 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 716 { 717 if (mask & 1) { 718 *d = r; 719 } 720 } 721 722 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 723 { 724 mergemask_ub((uint8_t *)d, r, mask); 725 } 726 727 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 728 { 729 uint16_t bmask = expand_pred_b(mask); 730 *d = (*d & ~bmask) | (r & bmask); 731 } 732 733 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 734 { 735 mergemask_uh((uint16_t *)d, r, mask); 736 } 737 738 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 739 { 740 uint32_t bmask = expand_pred_b(mask); 741 *d = (*d & ~bmask) | (r & bmask); 742 } 743 744 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 745 { 746 mergemask_uw((uint32_t *)d, r, mask); 747 } 748 749 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 750 { 751 uint64_t bmask = expand_pred_b(mask); 752 *d = (*d & ~bmask) | (r & bmask); 753 } 754 755 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 756 { 757 mergemask_uq((uint64_t *)d, r, mask); 758 } 759 760 #define mergemask(D, R, M) \ 761 _Generic(D, \ 762 uint8_t *: mergemask_ub, \ 763 int8_t *: mergemask_sb, \ 764 uint16_t *: mergemask_uh, \ 765 int16_t *: mergemask_sh, \ 766 uint32_t *: mergemask_uw, \ 767 int32_t *: mergemask_sw, \ 768 uint64_t *: mergemask_uq, \ 769 int64_t *: mergemask_sq)(D, R, M) 770 771 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 772 { 773 /* 774 * The generated code already replicated an 8 or 16 bit constant 775 * into the 32-bit value, so we only need to write the 32-bit 776 * value to all elements of the Qreg, allowing for predication. 777 */ 778 uint32_t *d = vd; 779 uint16_t mask = mve_element_mask(env); 780 unsigned e; 781 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 782 mergemask(&d[H4(e)], val, mask); 783 } 784 mve_advance_vpt(env); 785 } 786 787 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 788 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 789 { \ 790 TYPE *d = vd, *m = vm; \ 791 uint16_t mask = mve_element_mask(env); \ 792 unsigned e; \ 793 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 794 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 795 } \ 796 mve_advance_vpt(env); \ 797 } 798 799 #define DO_CLS_B(N) (clrsb32(N) - 24) 800 #define DO_CLS_H(N) (clrsb32(N) - 16) 801 802 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 803 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 804 DO_1OP(vclsw, 4, int32_t, clrsb32) 805 806 #define DO_CLZ_B(N) (clz32(N) - 24) 807 #define DO_CLZ_H(N) (clz32(N) - 16) 808 809 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 810 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 811 DO_1OP(vclzw, 4, uint32_t, clz32) 812 813 DO_1OP(vrev16b, 2, uint16_t, bswap16) 814 DO_1OP(vrev32b, 4, uint32_t, bswap32) 815 DO_1OP(vrev32h, 4, uint32_t, hswap32) 816 DO_1OP(vrev64b, 8, uint64_t, bswap64) 817 DO_1OP(vrev64h, 8, uint64_t, hswap64) 818 DO_1OP(vrev64w, 8, uint64_t, wswap64) 819 820 #define DO_NOT(N) (~(N)) 821 822 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 823 824 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 825 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 826 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 827 828 DO_1OP(vabsb, 1, int8_t, DO_ABS) 829 DO_1OP(vabsh, 2, int16_t, DO_ABS) 830 DO_1OP(vabsw, 4, int32_t, DO_ABS) 831 832 /* We can do these 64 bits at a time */ 833 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 834 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 835 836 #define DO_NEG(N) (-(N)) 837 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 838 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 839 840 DO_1OP(vnegb, 1, int8_t, DO_NEG) 841 DO_1OP(vnegh, 2, int16_t, DO_NEG) 842 DO_1OP(vnegw, 4, int32_t, DO_NEG) 843 844 /* We can do these 64 bits at a time */ 845 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 846 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 847 848 /* 849 * 1 operand immediates: Vda is destination and possibly also one source. 850 * All these insns work at 64-bit widths. 851 */ 852 #define DO_1OP_IMM(OP, FN) \ 853 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 854 { \ 855 uint64_t *da = vda; \ 856 uint16_t mask = mve_element_mask(env); \ 857 unsigned e; \ 858 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 859 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 860 } \ 861 mve_advance_vpt(env); \ 862 } 863 864 #define DO_MOVI(N, I) (I) 865 #define DO_ANDI(N, I) ((N) & (I)) 866 #define DO_ORRI(N, I) ((N) | (I)) 867 868 DO_1OP_IMM(vmovi, DO_MOVI) 869 DO_1OP_IMM(vandi, DO_ANDI) 870 DO_1OP_IMM(vorri, DO_ORRI) 871 872 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 873 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 874 void *vd, void *vn, void *vm) \ 875 { \ 876 TYPE *d = vd, *n = vn, *m = vm; \ 877 uint16_t mask = mve_element_mask(env); \ 878 unsigned e; \ 879 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 880 mergemask(&d[H##ESIZE(e)], \ 881 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 882 } \ 883 mve_advance_vpt(env); \ 884 } 885 886 /* provide unsigned 2-op helpers for all sizes */ 887 #define DO_2OP_U(OP, FN) \ 888 DO_2OP(OP##b, 1, uint8_t, FN) \ 889 DO_2OP(OP##h, 2, uint16_t, FN) \ 890 DO_2OP(OP##w, 4, uint32_t, FN) 891 892 /* provide signed 2-op helpers for all sizes */ 893 #define DO_2OP_S(OP, FN) \ 894 DO_2OP(OP##b, 1, int8_t, FN) \ 895 DO_2OP(OP##h, 2, int16_t, FN) \ 896 DO_2OP(OP##w, 4, int32_t, FN) 897 898 /* 899 * "Long" operations where two half-sized inputs (taken from either the 900 * top or the bottom of the input vector) produce a double-width result. 901 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 902 */ 903 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 904 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 905 { \ 906 LTYPE *d = vd; \ 907 TYPE *n = vn, *m = vm; \ 908 uint16_t mask = mve_element_mask(env); \ 909 unsigned le; \ 910 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 911 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 912 m[H##ESIZE(le * 2 + TOP)]); \ 913 mergemask(&d[H##LESIZE(le)], r, mask); \ 914 } \ 915 mve_advance_vpt(env); \ 916 } 917 918 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 919 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 920 { \ 921 TYPE *d = vd, *n = vn, *m = vm; \ 922 uint16_t mask = mve_element_mask(env); \ 923 unsigned e; \ 924 bool qc = false; \ 925 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 926 bool sat = false; \ 927 TYPE r_ = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 928 mergemask(&d[H##ESIZE(e)], r_, mask); \ 929 qc |= sat & mask & 1; \ 930 } \ 931 if (qc) { \ 932 env->vfp.qc[0] = qc; \ 933 } \ 934 mve_advance_vpt(env); \ 935 } 936 937 /* provide unsigned 2-op helpers for all sizes */ 938 #define DO_2OP_SAT_U(OP, FN) \ 939 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 940 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 941 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 942 943 /* provide signed 2-op helpers for all sizes */ 944 #define DO_2OP_SAT_S(OP, FN) \ 945 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 946 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 947 DO_2OP_SAT(OP##w, 4, int32_t, FN) 948 949 #define DO_AND(N, M) ((N) & (M)) 950 #define DO_BIC(N, M) ((N) & ~(M)) 951 #define DO_ORR(N, M) ((N) | (M)) 952 #define DO_ORN(N, M) ((N) | ~(M)) 953 #define DO_EOR(N, M) ((N) ^ (M)) 954 955 DO_2OP(vand, 8, uint64_t, DO_AND) 956 DO_2OP(vbic, 8, uint64_t, DO_BIC) 957 DO_2OP(vorr, 8, uint64_t, DO_ORR) 958 DO_2OP(vorn, 8, uint64_t, DO_ORN) 959 DO_2OP(veor, 8, uint64_t, DO_EOR) 960 961 #define DO_ADD(N, M) ((N) + (M)) 962 #define DO_SUB(N, M) ((N) - (M)) 963 #define DO_MUL(N, M) ((N) * (M)) 964 965 DO_2OP_U(vadd, DO_ADD) 966 DO_2OP_U(vsub, DO_SUB) 967 DO_2OP_U(vmul, DO_MUL) 968 969 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 970 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 971 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 972 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 973 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 974 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 975 976 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 977 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 978 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 979 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 980 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 981 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 982 983 /* 984 * Polynomial multiply. We can always do this generating 64 bits 985 * of the result at a time, so we don't need to use DO_2OP_L. 986 */ 987 DO_2OP(vmullpbh, 8, uint64_t, clmul_8x4_even) 988 DO_2OP(vmullpth, 8, uint64_t, clmul_8x4_odd) 989 DO_2OP(vmullpbw, 8, uint64_t, clmul_16x2_even) 990 DO_2OP(vmullptw, 8, uint64_t, clmul_16x2_odd) 991 992 /* 993 * Because the computation type is at least twice as large as required, 994 * these work for both signed and unsigned source types. 995 */ 996 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 997 { 998 return (n * m) >> 8; 999 } 1000 1001 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 1002 { 1003 return (n * m) >> 16; 1004 } 1005 1006 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 1007 { 1008 return (n * m) >> 32; 1009 } 1010 1011 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 1012 { 1013 return (n * m + (1U << 7)) >> 8; 1014 } 1015 1016 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 1017 { 1018 return (n * m + (1U << 15)) >> 16; 1019 } 1020 1021 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 1022 { 1023 return (n * m + (1U << 31)) >> 32; 1024 } 1025 1026 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 1027 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 1028 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 1029 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 1030 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 1031 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 1032 1033 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 1034 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 1035 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 1036 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 1037 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 1038 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 1039 1040 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 1041 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 1042 1043 DO_2OP_S(vmaxs, DO_MAX) 1044 DO_2OP_U(vmaxu, DO_MAX) 1045 DO_2OP_S(vmins, DO_MIN) 1046 DO_2OP_U(vminu, DO_MIN) 1047 1048 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 1049 1050 DO_2OP_S(vabds, DO_ABD) 1051 DO_2OP_U(vabdu, DO_ABD) 1052 1053 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 1054 { 1055 return ((uint64_t)n + m) >> 1; 1056 } 1057 1058 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 1059 { 1060 return ((int64_t)n + m) >> 1; 1061 } 1062 1063 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 1064 { 1065 return ((uint64_t)n - m) >> 1; 1066 } 1067 1068 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 1069 { 1070 return ((int64_t)n - m) >> 1; 1071 } 1072 1073 DO_2OP_S(vhadds, do_vhadd_s) 1074 DO_2OP_U(vhaddu, do_vhadd_u) 1075 DO_2OP_S(vhsubs, do_vhsub_s) 1076 DO_2OP_U(vhsubu, do_vhsub_u) 1077 1078 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1079 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1080 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1081 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1082 1083 DO_2OP_S(vshls, DO_VSHLS) 1084 DO_2OP_U(vshlu, DO_VSHLU) 1085 DO_2OP_S(vrshls, DO_VRSHLS) 1086 DO_2OP_U(vrshlu, DO_VRSHLU) 1087 1088 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 1089 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 1090 1091 DO_2OP_S(vrhadds, DO_RHADD_S) 1092 DO_2OP_U(vrhaddu, DO_RHADD_U) 1093 1094 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 1095 uint32_t inv, uint32_t carry_in, bool update_flags) 1096 { 1097 uint16_t mask = mve_element_mask(env); 1098 unsigned e; 1099 1100 /* If any additions trigger, we will update flags. */ 1101 if (mask & 0x1111) { 1102 update_flags = true; 1103 } 1104 1105 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1106 uint64_t r = carry_in; 1107 r += n[H4(e)]; 1108 r += m[H4(e)] ^ inv; 1109 if (mask & 1) { 1110 carry_in = r >> 32; 1111 } 1112 mergemask(&d[H4(e)], r, mask); 1113 } 1114 1115 if (update_flags) { 1116 /* Store C, clear NZV. */ 1117 env->vfp.fpsr &= ~FPSR_NZCV_MASK; 1118 env->vfp.fpsr |= carry_in * FPSR_C; 1119 } 1120 mve_advance_vpt(env); 1121 } 1122 1123 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 1124 { 1125 bool carry_in = env->vfp.fpsr & FPSR_C; 1126 do_vadc(env, vd, vn, vm, 0, carry_in, false); 1127 } 1128 1129 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 1130 { 1131 bool carry_in = env->vfp.fpsr & FPSR_C; 1132 do_vadc(env, vd, vn, vm, -1, carry_in, false); 1133 } 1134 1135 1136 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 1137 { 1138 do_vadc(env, vd, vn, vm, 0, 0, true); 1139 } 1140 1141 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 1142 { 1143 do_vadc(env, vd, vn, vm, -1, 1, true); 1144 } 1145 1146 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 1147 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 1148 { \ 1149 TYPE *d = vd, *n = vn, *m = vm; \ 1150 uint16_t mask = mve_element_mask(env); \ 1151 unsigned e; \ 1152 TYPE r[16 / ESIZE]; \ 1153 /* Calculate all results first to avoid overwriting inputs */ \ 1154 for (e = 0; e < 16 / ESIZE; e++) { \ 1155 if (!(e & 1)) { \ 1156 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 1157 } else { \ 1158 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 1159 } \ 1160 } \ 1161 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1162 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 1163 } \ 1164 mve_advance_vpt(env); \ 1165 } 1166 1167 #define DO_VCADD_ALL(OP, FN0, FN1) \ 1168 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 1169 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 1170 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 1171 1172 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 1173 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 1174 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 1175 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 1176 1177 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 1178 { 1179 if (val > max) { 1180 *s = true; 1181 return max; 1182 } else if (val < min) { 1183 *s = true; 1184 return min; 1185 } 1186 return val; 1187 } 1188 1189 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 1190 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 1191 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 1192 1193 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 1194 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 1195 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 1196 1197 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 1198 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 1199 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 1200 1201 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 1202 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 1203 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 1204 1205 /* 1206 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 1207 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 1208 */ 1209 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 1210 INT8_MIN, INT8_MAX, s) 1211 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 1212 INT16_MIN, INT16_MAX, s) 1213 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 1214 INT32_MIN, INT32_MAX, s) 1215 1216 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 1217 INT8_MIN, INT8_MAX, s) 1218 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 1219 INT16_MIN, INT16_MAX, s) 1220 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 1221 INT32_MIN, INT32_MAX, s) 1222 1223 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 1224 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 1225 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 1226 1227 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 1228 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 1229 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 1230 1231 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 1232 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 1233 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 1234 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 1235 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 1236 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 1237 1238 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 1239 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 1240 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 1241 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 1242 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 1243 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 1244 1245 /* 1246 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 1247 * and friends wanting a uint32_t* sat and our needing a bool*. 1248 */ 1249 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 1250 ({ \ 1251 uint32_t su32 = 0; \ 1252 typeof(N) qrshl_ret = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 1253 if (su32) { \ 1254 *satp = true; \ 1255 } \ 1256 qrshl_ret; \ 1257 }) 1258 1259 #define DO_SQSHL_OP(N, M, satp) \ 1260 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 1261 #define DO_UQSHL_OP(N, M, satp) \ 1262 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 1263 #define DO_SQRSHL_OP(N, M, satp) \ 1264 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 1265 #define DO_UQRSHL_OP(N, M, satp) \ 1266 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 1267 #define DO_SUQSHL_OP(N, M, satp) \ 1268 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 1269 1270 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 1271 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 1272 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 1273 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 1274 1275 /* 1276 * Multiply add dual returning high half 1277 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 1278 * whether to add the rounding constant, and the pointer to the 1279 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 1280 * saturate to twice the input size and return the high half; or 1281 * (A * B - C * D) etc for VQDMLSDH. 1282 */ 1283 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 1284 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1285 void *vm) \ 1286 { \ 1287 TYPE *d = vd, *n = vn, *m = vm; \ 1288 uint16_t mask = mve_element_mask(env); \ 1289 unsigned e; \ 1290 bool qc = false; \ 1291 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1292 bool sat = false; \ 1293 if ((e & 1) == XCHG) { \ 1294 TYPE vqdmladh_ret = FN(n[H##ESIZE(e)], \ 1295 m[H##ESIZE(e - XCHG)], \ 1296 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 1297 m[H##ESIZE(e + (1 - XCHG))], \ 1298 ROUND, &sat); \ 1299 mergemask(&d[H##ESIZE(e)], vqdmladh_ret, mask); \ 1300 qc |= sat & mask & 1; \ 1301 } \ 1302 } \ 1303 if (qc) { \ 1304 env->vfp.qc[0] = qc; \ 1305 } \ 1306 mve_advance_vpt(env); \ 1307 } 1308 1309 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1310 int round, bool *sat) 1311 { 1312 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 1313 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1314 } 1315 1316 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1317 int round, bool *sat) 1318 { 1319 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 1320 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1321 } 1322 1323 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1324 int round, bool *sat) 1325 { 1326 int64_t m1 = (int64_t)a * b; 1327 int64_t m2 = (int64_t)c * d; 1328 int64_t r; 1329 /* 1330 * Architecturally we should do the entire add, double, round 1331 * and then check for saturation. We do three saturating adds, 1332 * but we need to be careful about the order. If the first 1333 * m1 + m2 saturates then it's impossible for the *2+rc to 1334 * bring it back into the non-saturated range. However, if 1335 * m1 + m2 is negative then it's possible that doing the doubling 1336 * would take the intermediate result below INT64_MAX and the 1337 * addition of the rounding constant then brings it back in range. 1338 * So we add half the rounding constant before doubling rather 1339 * than adding the rounding constant after the doubling. 1340 */ 1341 if (sadd64_overflow(m1, m2, &r) || 1342 sadd64_overflow(r, (round << 30), &r) || 1343 sadd64_overflow(r, r, &r)) { 1344 *sat = true; 1345 return r < 0 ? INT32_MAX : INT32_MIN; 1346 } 1347 return r >> 32; 1348 } 1349 1350 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1351 int round, bool *sat) 1352 { 1353 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 1354 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1355 } 1356 1357 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1358 int round, bool *sat) 1359 { 1360 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 1361 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1362 } 1363 1364 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1365 int round, bool *sat) 1366 { 1367 int64_t m1 = (int64_t)a * b; 1368 int64_t m2 = (int64_t)c * d; 1369 int64_t r; 1370 /* The same ordering issue as in do_vqdmladh_w applies here too */ 1371 if (ssub64_overflow(m1, m2, &r) || 1372 sadd64_overflow(r, (round << 30), &r) || 1373 sadd64_overflow(r, r, &r)) { 1374 *sat = true; 1375 return r < 0 ? INT32_MAX : INT32_MIN; 1376 } 1377 return r >> 32; 1378 } 1379 1380 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 1381 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 1382 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 1383 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 1384 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 1385 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 1386 1387 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 1388 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 1389 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 1390 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 1391 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 1392 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 1393 1394 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 1395 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 1396 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 1397 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 1398 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 1399 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 1400 1401 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 1402 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 1403 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 1404 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 1405 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 1406 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 1407 1408 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 1409 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1410 uint32_t rm) \ 1411 { \ 1412 TYPE *d = vd, *n = vn; \ 1413 TYPE m = rm; \ 1414 uint16_t mask = mve_element_mask(env); \ 1415 unsigned e; \ 1416 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1417 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 1418 } \ 1419 mve_advance_vpt(env); \ 1420 } 1421 1422 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 1423 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1424 uint32_t rm) \ 1425 { \ 1426 TYPE *d = vd, *n = vn; \ 1427 TYPE m = rm; \ 1428 uint16_t mask = mve_element_mask(env); \ 1429 unsigned e; \ 1430 bool qc = false; \ 1431 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1432 bool sat = false; \ 1433 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 1434 mask); \ 1435 qc |= sat & mask & 1; \ 1436 } \ 1437 if (qc) { \ 1438 env->vfp.qc[0] = qc; \ 1439 } \ 1440 mve_advance_vpt(env); \ 1441 } 1442 1443 /* "accumulating" version where FN takes d as well as n and m */ 1444 #define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1445 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1446 uint32_t rm) \ 1447 { \ 1448 TYPE *d = vd, *n = vn; \ 1449 TYPE m = rm; \ 1450 uint16_t mask = mve_element_mask(env); \ 1451 unsigned e; \ 1452 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1453 mergemask(&d[H##ESIZE(e)], \ 1454 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \ 1455 } \ 1456 mve_advance_vpt(env); \ 1457 } 1458 1459 #define DO_2OP_SAT_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1460 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1461 uint32_t rm) \ 1462 { \ 1463 TYPE *d = vd, *n = vn; \ 1464 TYPE m = rm; \ 1465 uint16_t mask = mve_element_mask(env); \ 1466 unsigned e; \ 1467 bool qc = false; \ 1468 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1469 bool sat = false; \ 1470 mergemask(&d[H##ESIZE(e)], \ 1471 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m, &sat), \ 1472 mask); \ 1473 qc |= sat & mask & 1; \ 1474 } \ 1475 if (qc) { \ 1476 env->vfp.qc[0] = qc; \ 1477 } \ 1478 mve_advance_vpt(env); \ 1479 } 1480 1481 /* provide unsigned 2-op scalar helpers for all sizes */ 1482 #define DO_2OP_SCALAR_U(OP, FN) \ 1483 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 1484 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 1485 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 1486 #define DO_2OP_SCALAR_S(OP, FN) \ 1487 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 1488 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 1489 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 1490 1491 #define DO_2OP_ACC_SCALAR_U(OP, FN) \ 1492 DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \ 1493 DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \ 1494 DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN) 1495 1496 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 1497 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 1498 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 1499 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 1500 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 1501 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 1502 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 1503 1504 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 1505 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 1506 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 1507 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 1508 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 1509 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 1510 1511 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 1512 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 1513 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 1514 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 1515 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 1516 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 1517 1518 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 1519 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 1520 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 1521 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 1522 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 1523 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 1524 1525 static int8_t do_vqdmlah_b(int8_t a, int8_t b, int8_t c, int round, bool *sat) 1526 { 1527 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 8) + (round << 7); 1528 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1529 } 1530 1531 static int16_t do_vqdmlah_h(int16_t a, int16_t b, int16_t c, 1532 int round, bool *sat) 1533 { 1534 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 16) + (round << 15); 1535 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1536 } 1537 1538 static int32_t do_vqdmlah_w(int32_t a, int32_t b, int32_t c, 1539 int round, bool *sat) 1540 { 1541 /* 1542 * Architecturally we should do the entire add, double, round 1543 * and then check for saturation. We do three saturating adds, 1544 * but we need to be careful about the order. If the first 1545 * m1 + m2 saturates then it's impossible for the *2+rc to 1546 * bring it back into the non-saturated range. However, if 1547 * m1 + m2 is negative then it's possible that doing the doubling 1548 * would take the intermediate result below INT64_MAX and the 1549 * addition of the rounding constant then brings it back in range. 1550 * So we add half the rounding constant and half the "c << esize" 1551 * before doubling rather than adding the rounding constant after 1552 * the doubling. 1553 */ 1554 int64_t m1 = (int64_t)a * b; 1555 int64_t m2 = (int64_t)c << 31; 1556 int64_t r; 1557 if (sadd64_overflow(m1, m2, &r) || 1558 sadd64_overflow(r, (round << 30), &r) || 1559 sadd64_overflow(r, r, &r)) { 1560 *sat = true; 1561 return r < 0 ? INT32_MAX : INT32_MIN; 1562 } 1563 return r >> 32; 1564 } 1565 1566 /* 1567 * The *MLAH insns are vector * scalar + vector; 1568 * the *MLASH insns are vector * vector + scalar 1569 */ 1570 #define DO_VQDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 0, S) 1571 #define DO_VQDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 0, S) 1572 #define DO_VQDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 0, S) 1573 #define DO_VQRDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 1, S) 1574 #define DO_VQRDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 1, S) 1575 #define DO_VQRDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 1, S) 1576 1577 #define DO_VQDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 0, S) 1578 #define DO_VQDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 0, S) 1579 #define DO_VQDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 0, S) 1580 #define DO_VQRDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 1, S) 1581 #define DO_VQRDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 1, S) 1582 #define DO_VQRDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 1, S) 1583 1584 DO_2OP_SAT_ACC_SCALAR(vqdmlahb, 1, int8_t, DO_VQDMLAH_B) 1585 DO_2OP_SAT_ACC_SCALAR(vqdmlahh, 2, int16_t, DO_VQDMLAH_H) 1586 DO_2OP_SAT_ACC_SCALAR(vqdmlahw, 4, int32_t, DO_VQDMLAH_W) 1587 DO_2OP_SAT_ACC_SCALAR(vqrdmlahb, 1, int8_t, DO_VQRDMLAH_B) 1588 DO_2OP_SAT_ACC_SCALAR(vqrdmlahh, 2, int16_t, DO_VQRDMLAH_H) 1589 DO_2OP_SAT_ACC_SCALAR(vqrdmlahw, 4, int32_t, DO_VQRDMLAH_W) 1590 1591 DO_2OP_SAT_ACC_SCALAR(vqdmlashb, 1, int8_t, DO_VQDMLASH_B) 1592 DO_2OP_SAT_ACC_SCALAR(vqdmlashh, 2, int16_t, DO_VQDMLASH_H) 1593 DO_2OP_SAT_ACC_SCALAR(vqdmlashw, 4, int32_t, DO_VQDMLASH_W) 1594 DO_2OP_SAT_ACC_SCALAR(vqrdmlashb, 1, int8_t, DO_VQRDMLASH_B) 1595 DO_2OP_SAT_ACC_SCALAR(vqrdmlashh, 2, int16_t, DO_VQRDMLASH_H) 1596 DO_2OP_SAT_ACC_SCALAR(vqrdmlashw, 4, int32_t, DO_VQRDMLASH_W) 1597 1598 /* Vector by scalar plus vector */ 1599 #define DO_VMLA(D, N, M) ((N) * (M) + (D)) 1600 1601 DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA) 1602 1603 /* Vector by vector plus scalar */ 1604 #define DO_VMLAS(D, N, M) ((N) * (D) + (M)) 1605 1606 DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS) 1607 1608 /* 1609 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 1610 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 1611 * SATMASK specifies which bits of the predicate mask matter for determining 1612 * whether to propagate a saturation indication into FPSCR.QC -- for 1613 * the 16x16->32 case we must check only the bit corresponding to the T or B 1614 * half that we used, but for the 32x32->64 case we propagate if the mask 1615 * bit is set for either half. 1616 */ 1617 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1618 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1619 uint32_t rm) \ 1620 { \ 1621 LTYPE *d = vd; \ 1622 TYPE *n = vn; \ 1623 TYPE m = rm; \ 1624 uint16_t mask = mve_element_mask(env); \ 1625 unsigned le; \ 1626 bool qc = false; \ 1627 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1628 bool sat = false; \ 1629 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 1630 mergemask(&d[H##LESIZE(le)], r, mask); \ 1631 qc |= sat && (mask & SATMASK); \ 1632 } \ 1633 if (qc) { \ 1634 env->vfp.qc[0] = qc; \ 1635 } \ 1636 mve_advance_vpt(env); \ 1637 } 1638 1639 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1640 { 1641 int64_t r = ((int64_t)n * m) * 2; 1642 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1643 } 1644 1645 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1646 { 1647 /* The multiply can't overflow, but the doubling might */ 1648 int64_t r = (int64_t)n * m; 1649 if (r > INT64_MAX / 2) { 1650 *sat = true; 1651 return INT64_MAX; 1652 } else if (r < INT64_MIN / 2) { 1653 *sat = true; 1654 return INT64_MIN; 1655 } else { 1656 return r * 2; 1657 } 1658 } 1659 1660 #define SATMASK16B 1 1661 #define SATMASK16T (1 << 2) 1662 #define SATMASK32 ((1 << 4) | 1) 1663 1664 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1665 do_qdmullh, SATMASK16B) 1666 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1667 do_qdmullw, SATMASK32) 1668 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1669 do_qdmullh, SATMASK16T) 1670 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1671 do_qdmullw, SATMASK32) 1672 1673 /* 1674 * Long saturating ops 1675 */ 1676 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1677 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1678 void *vm) \ 1679 { \ 1680 LTYPE *d = vd; \ 1681 TYPE *n = vn, *m = vm; \ 1682 uint16_t mask = mve_element_mask(env); \ 1683 unsigned le; \ 1684 bool qc = false; \ 1685 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1686 bool sat = false; \ 1687 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1688 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1689 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1690 qc |= sat && (mask & SATMASK); \ 1691 } \ 1692 if (qc) { \ 1693 env->vfp.qc[0] = qc; \ 1694 } \ 1695 mve_advance_vpt(env); \ 1696 } 1697 1698 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1699 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1700 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1701 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1702 1703 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1704 { 1705 m &= 0xff; 1706 if (m == 0) { 1707 return 0; 1708 } 1709 n = revbit8(n); 1710 if (m < 8) { 1711 n >>= 8 - m; 1712 } 1713 return n; 1714 } 1715 1716 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1717 { 1718 m &= 0xff; 1719 if (m == 0) { 1720 return 0; 1721 } 1722 n = revbit16(n); 1723 if (m < 16) { 1724 n >>= 16 - m; 1725 } 1726 return n; 1727 } 1728 1729 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1730 { 1731 m &= 0xff; 1732 if (m == 0) { 1733 return 0; 1734 } 1735 n = revbit32(n); 1736 if (m < 32) { 1737 n >>= 32 - m; 1738 } 1739 return n; 1740 } 1741 1742 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1743 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1744 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1745 1746 /* 1747 * Multiply add long dual accumulate ops. 1748 */ 1749 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1750 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1751 void *vm, uint64_t a) \ 1752 { \ 1753 uint16_t mask = mve_element_mask(env); \ 1754 unsigned e; \ 1755 TYPE *n = vn, *m = vm; \ 1756 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1757 if (mask & 1) { \ 1758 if (e & 1) { \ 1759 a ODDACC \ 1760 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1761 } else { \ 1762 a EVENACC \ 1763 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1764 } \ 1765 } \ 1766 } \ 1767 mve_advance_vpt(env); \ 1768 return a; \ 1769 } 1770 1771 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1772 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1773 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1774 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1775 1776 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1777 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1778 1779 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1780 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1781 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1782 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1783 1784 /* 1785 * Multiply add dual accumulate ops 1786 */ 1787 #define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1788 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1789 void *vm, uint32_t a) \ 1790 { \ 1791 uint16_t mask = mve_element_mask(env); \ 1792 unsigned e; \ 1793 TYPE *n = vn, *m = vm; \ 1794 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1795 if (mask & 1) { \ 1796 if (e & 1) { \ 1797 a ODDACC \ 1798 n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1799 } else { \ 1800 a EVENACC \ 1801 n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1802 } \ 1803 } \ 1804 } \ 1805 mve_advance_vpt(env); \ 1806 return a; \ 1807 } 1808 1809 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ 1810 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \ 1811 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \ 1812 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC) 1813 1814 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ 1815 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \ 1816 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \ 1817 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC) 1818 1819 DO_DAV_S(vmladavs, false, +=, +=) 1820 DO_DAV_U(vmladavu, false, +=, +=) 1821 DO_DAV_S(vmlsdav, false, +=, -=) 1822 DO_DAV_S(vmladavsx, true, +=, +=) 1823 DO_DAV_S(vmlsdavx, true, +=, -=) 1824 1825 /* 1826 * Rounding multiply add long dual accumulate high. In the pseudocode 1827 * this is implemented with a 72-bit internal accumulator value of which 1828 * the top 64 bits are returned. We optimize this to avoid having to 1829 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1830 * is squashed back into 64-bits after each beat. 1831 */ 1832 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1833 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1834 void *vm, uint64_t a) \ 1835 { \ 1836 uint16_t mask = mve_element_mask(env); \ 1837 unsigned e; \ 1838 TYPE *n = vn, *m = vm; \ 1839 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1840 if (mask & 1) { \ 1841 LTYPE mul; \ 1842 if (e & 1) { \ 1843 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1844 if (SUB) { \ 1845 mul = -mul; \ 1846 } \ 1847 } else { \ 1848 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1849 } \ 1850 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1851 a += mul; \ 1852 } \ 1853 } \ 1854 mve_advance_vpt(env); \ 1855 return a; \ 1856 } 1857 1858 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1859 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1860 1861 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1862 1863 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1864 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1865 1866 /* Vector add across vector */ 1867 #define DO_VADDV(OP, ESIZE, TYPE) \ 1868 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1869 uint32_t ra) \ 1870 { \ 1871 uint16_t mask = mve_element_mask(env); \ 1872 unsigned e; \ 1873 TYPE *m = vm; \ 1874 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1875 if (mask & 1) { \ 1876 ra += m[H##ESIZE(e)]; \ 1877 } \ 1878 } \ 1879 mve_advance_vpt(env); \ 1880 return ra; \ 1881 } \ 1882 1883 DO_VADDV(vaddvsb, 1, int8_t) 1884 DO_VADDV(vaddvsh, 2, int16_t) 1885 DO_VADDV(vaddvsw, 4, int32_t) 1886 DO_VADDV(vaddvub, 1, uint8_t) 1887 DO_VADDV(vaddvuh, 2, uint16_t) 1888 DO_VADDV(vaddvuw, 4, uint32_t) 1889 1890 /* 1891 * Vector max/min across vector. Unlike VADDV, we must 1892 * read ra as the element size, not its full width. 1893 * We work with int64_t internally for simplicity. 1894 */ 1895 #define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \ 1896 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1897 uint32_t ra_in) \ 1898 { \ 1899 uint16_t mask = mve_element_mask(env); \ 1900 unsigned e; \ 1901 TYPE *m = vm; \ 1902 int64_t ra = (RATYPE)ra_in; \ 1903 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1904 if (mask & 1) { \ 1905 ra = FN(ra, m[H##ESIZE(e)]); \ 1906 } \ 1907 } \ 1908 mve_advance_vpt(env); \ 1909 return ra; \ 1910 } \ 1911 1912 #define DO_VMAXMINV_U(INSN, FN) \ 1913 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \ 1914 DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \ 1915 DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN) 1916 #define DO_VMAXMINV_S(INSN, FN) \ 1917 DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \ 1918 DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \ 1919 DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN) 1920 1921 /* 1922 * Helpers for max and min of absolute values across vector: 1923 * note that we only take the absolute value of 'm', not 'n' 1924 */ 1925 static int64_t do_maxa(int64_t n, int64_t m) 1926 { 1927 if (m < 0) { 1928 m = -m; 1929 } 1930 return MAX(n, m); 1931 } 1932 1933 static int64_t do_mina(int64_t n, int64_t m) 1934 { 1935 if (m < 0) { 1936 m = -m; 1937 } 1938 return MIN(n, m); 1939 } 1940 1941 DO_VMAXMINV_S(vmaxvs, DO_MAX) 1942 DO_VMAXMINV_U(vmaxvu, DO_MAX) 1943 DO_VMAXMINV_S(vminvs, DO_MIN) 1944 DO_VMAXMINV_U(vminvu, DO_MIN) 1945 /* 1946 * VMAXAV, VMINAV treat the general purpose input as unsigned 1947 * and the vector elements as signed. 1948 */ 1949 DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa) 1950 DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa) 1951 DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa) 1952 DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) 1953 DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) 1954 DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) 1955 1956 #define DO_VABAV(OP, ESIZE, TYPE) \ 1957 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1958 void *vm, uint32_t ra) \ 1959 { \ 1960 uint16_t mask = mve_element_mask(env); \ 1961 unsigned e; \ 1962 TYPE *m = vm, *n = vn; \ 1963 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1964 if (mask & 1) { \ 1965 int64_t n0 = n[H##ESIZE(e)]; \ 1966 int64_t m0 = m[H##ESIZE(e)]; \ 1967 uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \ 1968 ra += r; \ 1969 } \ 1970 } \ 1971 mve_advance_vpt(env); \ 1972 return ra; \ 1973 } 1974 1975 DO_VABAV(vabavsb, 1, int8_t) 1976 DO_VABAV(vabavsh, 2, int16_t) 1977 DO_VABAV(vabavsw, 4, int32_t) 1978 DO_VABAV(vabavub, 1, uint8_t) 1979 DO_VABAV(vabavuh, 2, uint16_t) 1980 DO_VABAV(vabavuw, 4, uint32_t) 1981 1982 #define DO_VADDLV(OP, TYPE, LTYPE) \ 1983 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1984 uint64_t ra) \ 1985 { \ 1986 uint16_t mask = mve_element_mask(env); \ 1987 unsigned e; \ 1988 TYPE *m = vm; \ 1989 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1990 if (mask & 1) { \ 1991 ra += (LTYPE)m[H4(e)]; \ 1992 } \ 1993 } \ 1994 mve_advance_vpt(env); \ 1995 return ra; \ 1996 } \ 1997 1998 DO_VADDLV(vaddlv_s, int32_t, int64_t) 1999 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 2000 2001 /* Shifts by immediate */ 2002 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 2003 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2004 void *vm, uint32_t shift) \ 2005 { \ 2006 TYPE *d = vd, *m = vm; \ 2007 uint16_t mask = mve_element_mask(env); \ 2008 unsigned e; \ 2009 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2010 mergemask(&d[H##ESIZE(e)], \ 2011 FN(m[H##ESIZE(e)], shift), mask); \ 2012 } \ 2013 mve_advance_vpt(env); \ 2014 } 2015 2016 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 2017 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2018 void *vm, uint32_t shift) \ 2019 { \ 2020 TYPE *d = vd, *m = vm; \ 2021 uint16_t mask = mve_element_mask(env); \ 2022 unsigned e; \ 2023 bool qc = false; \ 2024 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2025 bool sat = false; \ 2026 mergemask(&d[H##ESIZE(e)], \ 2027 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 2028 qc |= sat & mask & 1; \ 2029 } \ 2030 if (qc) { \ 2031 env->vfp.qc[0] = qc; \ 2032 } \ 2033 mve_advance_vpt(env); \ 2034 } 2035 2036 /* provide unsigned 2-op shift helpers for all sizes */ 2037 #define DO_2SHIFT_U(OP, FN) \ 2038 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 2039 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 2040 DO_2SHIFT(OP##w, 4, uint32_t, FN) 2041 #define DO_2SHIFT_S(OP, FN) \ 2042 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 2043 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 2044 DO_2SHIFT(OP##w, 4, int32_t, FN) 2045 2046 #define DO_2SHIFT_SAT_U(OP, FN) \ 2047 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 2048 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 2049 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 2050 #define DO_2SHIFT_SAT_S(OP, FN) \ 2051 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 2052 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 2053 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 2054 2055 DO_2SHIFT_U(vshli_u, DO_VSHLU) 2056 DO_2SHIFT_S(vshli_s, DO_VSHLS) 2057 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 2058 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 2059 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 2060 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 2061 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 2062 DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP) 2063 DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP) 2064 2065 /* Shift-and-insert; we always work with 64 bits at a time */ 2066 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 2067 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2068 void *vm, uint32_t shift) \ 2069 { \ 2070 uint64_t *d = vd, *m = vm; \ 2071 uint16_t mask; \ 2072 uint64_t shiftmask; \ 2073 unsigned e; \ 2074 if (shift == ESIZE * 8) { \ 2075 /* \ 2076 * Only VSRI can shift by <dt>; it should mean "don't \ 2077 * update the destination". The generic logic can't handle \ 2078 * this because it would try to shift by an out-of-range \ 2079 * amount, so special case it here. \ 2080 */ \ 2081 goto done; \ 2082 } \ 2083 assert(shift < ESIZE * 8); \ 2084 mask = mve_element_mask(env); \ 2085 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 2086 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 2087 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 2088 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 2089 (d[H8(e)] & ~shiftmask); \ 2090 mergemask(&d[H8(e)], r, mask); \ 2091 } \ 2092 done: \ 2093 mve_advance_vpt(env); \ 2094 } 2095 2096 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 2097 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 2098 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 2099 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 2100 2101 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 2102 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 2103 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 2104 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 2105 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 2106 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 2107 2108 /* 2109 * Long shifts taking half-sized inputs from top or bottom of the input 2110 * vector and producing a double-width result. ESIZE, TYPE are for 2111 * the input, and LESIZE, LTYPE for the output. 2112 * Unlike the normal shift helpers, we do not handle negative shift counts, 2113 * because the long shift is strictly left-only. 2114 */ 2115 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2116 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2117 void *vm, uint32_t shift) \ 2118 { \ 2119 LTYPE *d = vd; \ 2120 TYPE *m = vm; \ 2121 uint16_t mask = mve_element_mask(env); \ 2122 unsigned le; \ 2123 assert(shift <= 16); \ 2124 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2125 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 2126 mergemask(&d[H##LESIZE(le)], r, mask); \ 2127 } \ 2128 mve_advance_vpt(env); \ 2129 } 2130 2131 #define DO_VSHLL_ALL(OP, TOP) \ 2132 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 2133 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 2134 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 2135 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 2136 2137 DO_VSHLL_ALL(vshllb, false) 2138 DO_VSHLL_ALL(vshllt, true) 2139 2140 /* 2141 * Narrowing right shifts, taking a double sized input, shifting it 2142 * and putting the result in either the top or bottom half of the output. 2143 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 2144 */ 2145 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2146 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2147 void *vm, uint32_t shift) \ 2148 { \ 2149 LTYPE *m = vm; \ 2150 TYPE *d = vd; \ 2151 uint16_t mask = mve_element_mask(env); \ 2152 unsigned le; \ 2153 mask >>= ESIZE * TOP; \ 2154 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2155 TYPE r = FN(m[H##LESIZE(le)], shift); \ 2156 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2157 } \ 2158 mve_advance_vpt(env); \ 2159 } 2160 2161 #define DO_VSHRN_ALL(OP, FN) \ 2162 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 2163 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 2164 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 2165 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 2166 2167 static inline uint64_t do_urshr(uint64_t x, unsigned sh) 2168 { 2169 if (likely(sh < 64)) { 2170 return (x >> sh) + ((x >> (sh - 1)) & 1); 2171 } else if (sh == 64) { 2172 return x >> 63; 2173 } else { 2174 return 0; 2175 } 2176 } 2177 2178 static inline int64_t do_srshr(int64_t x, unsigned sh) 2179 { 2180 if (likely(sh < 64)) { 2181 return (x >> sh) + ((x >> (sh - 1)) & 1); 2182 } else { 2183 /* Rounding the sign bit always produces 0. */ 2184 return 0; 2185 } 2186 } 2187 2188 DO_VSHRN_ALL(vshrn, DO_SHR) 2189 DO_VSHRN_ALL(vrshrn, do_urshr) 2190 2191 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 2192 bool *satp) 2193 { 2194 if (val > max) { 2195 *satp = true; 2196 return max; 2197 } else if (val < min) { 2198 *satp = true; 2199 return min; 2200 } else { 2201 return val; 2202 } 2203 } 2204 2205 /* Saturating narrowing right shifts */ 2206 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2207 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2208 void *vm, uint32_t shift) \ 2209 { \ 2210 LTYPE *m = vm; \ 2211 TYPE *d = vd; \ 2212 uint16_t mask = mve_element_mask(env); \ 2213 bool qc = false; \ 2214 unsigned le; \ 2215 mask >>= ESIZE * TOP; \ 2216 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2217 bool sat = false; \ 2218 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 2219 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2220 qc |= sat & mask & 1; \ 2221 } \ 2222 if (qc) { \ 2223 env->vfp.qc[0] = qc; \ 2224 } \ 2225 mve_advance_vpt(env); \ 2226 } 2227 2228 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 2229 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2230 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2231 2232 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 2233 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2234 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2235 2236 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 2237 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2238 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2239 2240 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 2241 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2242 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2243 2244 #define DO_SHRN_SB(N, M, SATP) \ 2245 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 2246 #define DO_SHRN_UB(N, M, SATP) \ 2247 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2248 #define DO_SHRUN_B(N, M, SATP) \ 2249 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2250 2251 #define DO_SHRN_SH(N, M, SATP) \ 2252 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 2253 #define DO_SHRN_UH(N, M, SATP) \ 2254 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2255 #define DO_SHRUN_H(N, M, SATP) \ 2256 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2257 2258 #define DO_RSHRN_SB(N, M, SATP) \ 2259 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 2260 #define DO_RSHRN_UB(N, M, SATP) \ 2261 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 2262 #define DO_RSHRUN_B(N, M, SATP) \ 2263 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 2264 2265 #define DO_RSHRN_SH(N, M, SATP) \ 2266 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 2267 #define DO_RSHRN_UH(N, M, SATP) \ 2268 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 2269 #define DO_RSHRUN_H(N, M, SATP) \ 2270 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 2271 2272 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 2273 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 2274 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 2275 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 2276 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 2277 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 2278 2279 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 2280 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 2281 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 2282 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 2283 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 2284 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 2285 2286 #define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2287 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2288 { \ 2289 LTYPE *m = vm; \ 2290 TYPE *d = vd; \ 2291 uint16_t mask = mve_element_mask(env); \ 2292 unsigned le; \ 2293 mask >>= ESIZE * TOP; \ 2294 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2295 mergemask(&d[H##ESIZE(le * 2 + TOP)], \ 2296 m[H##LESIZE(le)], mask); \ 2297 } \ 2298 mve_advance_vpt(env); \ 2299 } 2300 2301 DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t) 2302 DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t) 2303 DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t) 2304 DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t) 2305 2306 #define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2307 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2308 { \ 2309 LTYPE *m = vm; \ 2310 TYPE *d = vd; \ 2311 uint16_t mask = mve_element_mask(env); \ 2312 bool qc = false; \ 2313 unsigned le; \ 2314 mask >>= ESIZE * TOP; \ 2315 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2316 bool sat = false; \ 2317 TYPE r = FN(m[H##LESIZE(le)], &sat); \ 2318 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2319 qc |= sat & mask & 1; \ 2320 } \ 2321 if (qc) { \ 2322 env->vfp.qc[0] = qc; \ 2323 } \ 2324 mve_advance_vpt(env); \ 2325 } 2326 2327 #define DO_VMOVN_SAT_UB(BOP, TOP, FN) \ 2328 DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2329 DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2330 2331 #define DO_VMOVN_SAT_UH(BOP, TOP, FN) \ 2332 DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2333 DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2334 2335 #define DO_VMOVN_SAT_SB(BOP, TOP, FN) \ 2336 DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2337 DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2338 2339 #define DO_VMOVN_SAT_SH(BOP, TOP, FN) \ 2340 DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2341 DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2342 2343 #define DO_VQMOVN_SB(N, SATP) \ 2344 do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP) 2345 #define DO_VQMOVN_UB(N, SATP) \ 2346 do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP) 2347 #define DO_VQMOVUN_B(N, SATP) \ 2348 do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP) 2349 2350 #define DO_VQMOVN_SH(N, SATP) \ 2351 do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP) 2352 #define DO_VQMOVN_UH(N, SATP) \ 2353 do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP) 2354 #define DO_VQMOVUN_H(N, SATP) \ 2355 do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP) 2356 2357 DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB) 2358 DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH) 2359 DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB) 2360 DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH) 2361 DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B) 2362 DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H) 2363 2364 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 2365 uint32_t shift) 2366 { 2367 uint32_t *d = vd; 2368 uint16_t mask = mve_element_mask(env); 2369 unsigned e; 2370 uint32_t r; 2371 2372 /* 2373 * For each 32-bit element, we shift it left, bringing in the 2374 * low 'shift' bits of rdm at the bottom. Bits shifted out at 2375 * the top become the new rdm, if the predicate mask permits. 2376 * The final rdm value is returned to update the register. 2377 * shift == 0 here means "shift by 32 bits". 2378 */ 2379 if (shift == 0) { 2380 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2381 r = rdm; 2382 if (mask & 1) { 2383 rdm = d[H4(e)]; 2384 } 2385 mergemask(&d[H4(e)], r, mask); 2386 } 2387 } else { 2388 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 2389 2390 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2391 r = (d[H4(e)] << shift) | (rdm & shiftmask); 2392 if (mask & 1) { 2393 rdm = d[H4(e)] >> (32 - shift); 2394 } 2395 mergemask(&d[H4(e)], r, mask); 2396 } 2397 } 2398 mve_advance_vpt(env); 2399 return rdm; 2400 } 2401 2402 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2403 { 2404 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 2405 } 2406 2407 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 2408 { 2409 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 2410 } 2411 2412 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2413 { 2414 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 2415 } 2416 2417 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2418 { 2419 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 2420 } 2421 2422 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2423 { 2424 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 2425 } 2426 2427 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2428 { 2429 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 2430 } 2431 2432 /* Operate on 64-bit values, but saturate at 48 bits */ 2433 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 2434 bool round, uint32_t *sat) 2435 { 2436 int64_t val, extval; 2437 2438 if (shift <= -48) { 2439 /* Rounding the sign bit always produces 0. */ 2440 if (round) { 2441 return 0; 2442 } 2443 return src >> 63; 2444 } else if (shift < 0) { 2445 if (round) { 2446 src >>= -shift - 1; 2447 val = (src >> 1) + (src & 1); 2448 } else { 2449 val = src >> -shift; 2450 } 2451 extval = sextract64(val, 0, 48); 2452 if (!sat || val == extval) { 2453 return extval; 2454 } 2455 } else if (shift < 48) { 2456 extval = sextract64(src << shift, 0, 48); 2457 if (!sat || src == (extval >> shift)) { 2458 return extval; 2459 } 2460 } else if (!sat || src == 0) { 2461 return 0; 2462 } 2463 2464 *sat = 1; 2465 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 2466 } 2467 2468 /* Operate on 64-bit values, but saturate at 48 bits */ 2469 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 2470 bool round, uint32_t *sat) 2471 { 2472 uint64_t val, extval; 2473 2474 if (shift <= -(48 + round)) { 2475 return 0; 2476 } else if (shift < 0) { 2477 if (round) { 2478 val = src >> (-shift - 1); 2479 val = (val >> 1) + (val & 1); 2480 } else { 2481 val = src >> -shift; 2482 } 2483 extval = extract64(val, 0, 48); 2484 if (!sat || val == extval) { 2485 return extval; 2486 } 2487 } else if (shift < 48) { 2488 extval = extract64(src << shift, 0, 48); 2489 if (!sat || src == (extval >> shift)) { 2490 return extval; 2491 } 2492 } else if (!sat || src == 0) { 2493 return 0; 2494 } 2495 2496 *sat = 1; 2497 return MAKE_64BIT_MASK(0, 48); 2498 } 2499 2500 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 2501 { 2502 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 2503 } 2504 2505 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 2506 { 2507 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 2508 } 2509 2510 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2511 { 2512 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2513 } 2514 2515 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2516 { 2517 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2518 } 2519 2520 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2521 { 2522 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 2523 } 2524 2525 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 2526 { 2527 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 2528 } 2529 2530 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \ 2531 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2532 uint32_t offset, uint32_t imm) \ 2533 { \ 2534 TYPE *d = vd; \ 2535 uint16_t mask = mve_element_mask(env); \ 2536 unsigned e; \ 2537 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2538 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2539 offset = FN(offset, imm); \ 2540 } \ 2541 mve_advance_vpt(env); \ 2542 return offset; \ 2543 } 2544 2545 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ 2546 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2547 uint32_t offset, uint32_t wrap, \ 2548 uint32_t imm) \ 2549 { \ 2550 TYPE *d = vd; \ 2551 uint16_t mask = mve_element_mask(env); \ 2552 unsigned e; \ 2553 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2554 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2555 offset = FN(offset, wrap, imm); \ 2556 } \ 2557 mve_advance_vpt(env); \ 2558 return offset; \ 2559 } 2560 2561 #define DO_VIDUP_ALL(OP, FN) \ 2562 DO_VIDUP(OP##b, 1, int8_t, FN) \ 2563 DO_VIDUP(OP##h, 2, int16_t, FN) \ 2564 DO_VIDUP(OP##w, 4, int32_t, FN) 2565 2566 #define DO_VIWDUP_ALL(OP, FN) \ 2567 DO_VIWDUP(OP##b, 1, int8_t, FN) \ 2568 DO_VIWDUP(OP##h, 2, int16_t, FN) \ 2569 DO_VIWDUP(OP##w, 4, int32_t, FN) 2570 2571 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2572 { 2573 offset += imm; 2574 if (offset == wrap) { 2575 offset = 0; 2576 } 2577 return offset; 2578 } 2579 2580 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2581 { 2582 if (offset == 0) { 2583 offset = wrap; 2584 } 2585 offset -= imm; 2586 return offset; 2587 } 2588 2589 DO_VIDUP_ALL(vidup, DO_ADD) 2590 DO_VIWDUP_ALL(viwdup, do_add_wrap) 2591 DO_VIWDUP_ALL(vdwdup, do_sub_wrap) 2592 2593 /* 2594 * Vector comparison. 2595 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. 2596 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. 2597 * P0 bits otherwise are updated with the results of the comparisons. 2598 * We must also keep unchanged the MASK fields at the top of v7m.vpr. 2599 */ 2600 #define DO_VCMP(OP, ESIZE, TYPE, FN) \ 2601 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 2602 { \ 2603 TYPE *n = vn, *m = vm; \ 2604 uint16_t mask = mve_element_mask(env); \ 2605 uint16_t eci_mask = mve_eci_mask(env); \ 2606 uint16_t beatpred = 0; \ 2607 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2608 unsigned e; \ 2609 for (e = 0; e < 16 / ESIZE; e++) { \ 2610 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ 2611 /* Comparison sets 0/1 bits for each byte in the element */ \ 2612 beatpred |= r * emask; \ 2613 emask <<= ESIZE; \ 2614 } \ 2615 beatpred &= mask; \ 2616 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2617 (beatpred & eci_mask); \ 2618 mve_advance_vpt(env); \ 2619 } 2620 2621 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ 2622 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 2623 uint32_t rm) \ 2624 { \ 2625 TYPE *n = vn; \ 2626 uint16_t mask = mve_element_mask(env); \ 2627 uint16_t eci_mask = mve_eci_mask(env); \ 2628 uint16_t beatpred = 0; \ 2629 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2630 unsigned e; \ 2631 for (e = 0; e < 16 / ESIZE; e++) { \ 2632 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \ 2633 /* Comparison sets 0/1 bits for each byte in the element */ \ 2634 beatpred |= r * emask; \ 2635 emask <<= ESIZE; \ 2636 } \ 2637 beatpred &= mask; \ 2638 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2639 (beatpred & eci_mask); \ 2640 mve_advance_vpt(env); \ 2641 } 2642 2643 #define DO_VCMP_S(OP, FN) \ 2644 DO_VCMP(OP##b, 1, int8_t, FN) \ 2645 DO_VCMP(OP##h, 2, int16_t, FN) \ 2646 DO_VCMP(OP##w, 4, int32_t, FN) \ 2647 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ 2648 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ 2649 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) 2650 2651 #define DO_VCMP_U(OP, FN) \ 2652 DO_VCMP(OP##b, 1, uint8_t, FN) \ 2653 DO_VCMP(OP##h, 2, uint16_t, FN) \ 2654 DO_VCMP(OP##w, 4, uint32_t, FN) \ 2655 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ 2656 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ 2657 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) 2658 2659 #define DO_EQ(N, M) ((N) == (M)) 2660 #define DO_NE(N, M) ((N) != (M)) 2661 #define DO_EQ(N, M) ((N) == (M)) 2662 #define DO_EQ(N, M) ((N) == (M)) 2663 #define DO_GE(N, M) ((N) >= (M)) 2664 #define DO_LT(N, M) ((N) < (M)) 2665 #define DO_GT(N, M) ((N) > (M)) 2666 #define DO_LE(N, M) ((N) <= (M)) 2667 2668 DO_VCMP_U(vcmpeq, DO_EQ) 2669 DO_VCMP_U(vcmpne, DO_NE) 2670 DO_VCMP_U(vcmpcs, DO_GE) 2671 DO_VCMP_U(vcmphi, DO_GT) 2672 DO_VCMP_S(vcmpge, DO_GE) 2673 DO_VCMP_S(vcmplt, DO_LT) 2674 DO_VCMP_S(vcmpgt, DO_GT) 2675 DO_VCMP_S(vcmple, DO_LE) 2676 2677 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) 2678 { 2679 /* 2680 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n] 2681 * but note that whether bytes are written to Qd is still subject 2682 * to (all forms of) predication in the usual way. 2683 */ 2684 uint64_t *d = vd, *n = vn, *m = vm; 2685 uint16_t mask = mve_element_mask(env); 2686 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 2687 unsigned e; 2688 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) { 2689 uint64_t r = m[H8(e)]; 2690 mergemask(&r, n[H8(e)], p0); 2691 mergemask(&d[H8(e)], r, mask); 2692 } 2693 mve_advance_vpt(env); 2694 } 2695 2696 void HELPER(mve_vpnot)(CPUARMState *env) 2697 { 2698 /* 2699 * P0 bits for unexecuted beats (where eci_mask is 0) are unchanged. 2700 * P0 bits for predicated lanes in executed bits (where mask is 0) are 0. 2701 * P0 bits otherwise are inverted. 2702 * (This is the same logic as VCMP.) 2703 * This insn is itself subject to predication and to beat-wise execution, 2704 * and after it executes VPT state advances in the usual way. 2705 */ 2706 uint16_t mask = mve_element_mask(env); 2707 uint16_t eci_mask = mve_eci_mask(env); 2708 uint16_t beatpred = ~env->v7m.vpr & mask; 2709 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask); 2710 mve_advance_vpt(env); 2711 } 2712 2713 /* 2714 * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed, 2715 * otherwise set according to value of Rn. The calculation of 2716 * newmask here works in the same way as the calculation of the 2717 * ltpmask in mve_element_mask(), but we have pre-calculated 2718 * the masklen in the generated code. 2719 */ 2720 void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen) 2721 { 2722 uint16_t mask = mve_element_mask(env); 2723 uint16_t eci_mask = mve_eci_mask(env); 2724 uint16_t newmask; 2725 2726 assert(masklen <= 16); 2727 newmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 2728 newmask &= mask; 2729 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask); 2730 mve_advance_vpt(env); 2731 } 2732 2733 #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ 2734 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2735 { \ 2736 TYPE *d = vd, *m = vm; \ 2737 uint16_t mask = mve_element_mask(env); \ 2738 unsigned e; \ 2739 bool qc = false; \ 2740 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2741 bool sat = false; \ 2742 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)], &sat), mask); \ 2743 qc |= sat & mask & 1; \ 2744 } \ 2745 if (qc) { \ 2746 env->vfp.qc[0] = qc; \ 2747 } \ 2748 mve_advance_vpt(env); \ 2749 } 2750 2751 #define DO_VQABS_B(N, SATP) \ 2752 do_sat_bhs(DO_ABS((int64_t)N), INT8_MIN, INT8_MAX, SATP) 2753 #define DO_VQABS_H(N, SATP) \ 2754 do_sat_bhs(DO_ABS((int64_t)N), INT16_MIN, INT16_MAX, SATP) 2755 #define DO_VQABS_W(N, SATP) \ 2756 do_sat_bhs(DO_ABS((int64_t)N), INT32_MIN, INT32_MAX, SATP) 2757 2758 #define DO_VQNEG_B(N, SATP) do_sat_bhs(-(int64_t)N, INT8_MIN, INT8_MAX, SATP) 2759 #define DO_VQNEG_H(N, SATP) do_sat_bhs(-(int64_t)N, INT16_MIN, INT16_MAX, SATP) 2760 #define DO_VQNEG_W(N, SATP) do_sat_bhs(-(int64_t)N, INT32_MIN, INT32_MAX, SATP) 2761 2762 DO_1OP_SAT(vqabsb, 1, int8_t, DO_VQABS_B) 2763 DO_1OP_SAT(vqabsh, 2, int16_t, DO_VQABS_H) 2764 DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W) 2765 2766 DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B) 2767 DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H) 2768 DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W) 2769 2770 /* 2771 * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its 2772 * absolute value; we then do an unsigned comparison. 2773 */ 2774 #define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \ 2775 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2776 { \ 2777 UTYPE *d = vd; \ 2778 STYPE *m = vm; \ 2779 uint16_t mask = mve_element_mask(env); \ 2780 unsigned e; \ 2781 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2782 UTYPE r = DO_ABS(m[H##ESIZE(e)]); \ 2783 r = FN(d[H##ESIZE(e)], r); \ 2784 mergemask(&d[H##ESIZE(e)], r, mask); \ 2785 } \ 2786 mve_advance_vpt(env); \ 2787 } 2788 2789 DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX) 2790 DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX) 2791 DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) 2792 DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) 2793 DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) 2794 DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) 2795 2796 /* 2797 * 2-operand floating point. Note that if an element is partially 2798 * predicated we must do the FP operation to update the non-predicated 2799 * bytes, but we must be careful to avoid updating the FP exception 2800 * state unless byte 0 of the element was unpredicated. 2801 */ 2802 #define DO_2OP_FP(OP, ESIZE, TYPE, FN) \ 2803 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2804 void *vd, void *vn, void *vm) \ 2805 { \ 2806 TYPE *d = vd, *n = vn, *m = vm; \ 2807 TYPE r; \ 2808 uint16_t mask = mve_element_mask(env); \ 2809 unsigned e; \ 2810 float_status *fpst; \ 2811 float_status scratch_fpst; \ 2812 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2813 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2814 continue; \ 2815 } \ 2816 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2817 if (!(mask & 1)) { \ 2818 /* We need the result but without updating flags */ \ 2819 scratch_fpst = *fpst; \ 2820 fpst = &scratch_fpst; \ 2821 } \ 2822 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 2823 mergemask(&d[H##ESIZE(e)], r, mask); \ 2824 } \ 2825 mve_advance_vpt(env); \ 2826 } 2827 2828 #define DO_2OP_FP_ALL(OP, FN) \ 2829 DO_2OP_FP(OP##h, 2, float16, float16_##FN) \ 2830 DO_2OP_FP(OP##s, 4, float32, float32_##FN) 2831 2832 DO_2OP_FP_ALL(vfadd, add) 2833 DO_2OP_FP_ALL(vfsub, sub) 2834 DO_2OP_FP_ALL(vfmul, mul) 2835 2836 static inline float16 float16_abd(float16 a, float16 b, float_status *s) 2837 { 2838 return float16_abs(float16_sub(a, b, s)); 2839 } 2840 2841 static inline float32 float32_abd(float32 a, float32 b, float_status *s) 2842 { 2843 return float32_abs(float32_sub(a, b, s)); 2844 } 2845 2846 DO_2OP_FP_ALL(vfabd, abd) 2847 DO_2OP_FP_ALL(vmaxnm, maxnum) 2848 DO_2OP_FP_ALL(vminnm, minnum) 2849 2850 static inline float16 float16_maxnuma(float16 a, float16 b, float_status *s) 2851 { 2852 return float16_maxnum(float16_abs(a), float16_abs(b), s); 2853 } 2854 2855 static inline float32 float32_maxnuma(float32 a, float32 b, float_status *s) 2856 { 2857 return float32_maxnum(float32_abs(a), float32_abs(b), s); 2858 } 2859 2860 static inline float16 float16_minnuma(float16 a, float16 b, float_status *s) 2861 { 2862 return float16_minnum(float16_abs(a), float16_abs(b), s); 2863 } 2864 2865 static inline float32 float32_minnuma(float32 a, float32 b, float_status *s) 2866 { 2867 return float32_minnum(float32_abs(a), float32_abs(b), s); 2868 } 2869 2870 DO_2OP_FP_ALL(vmaxnma, maxnuma) 2871 DO_2OP_FP_ALL(vminnma, minnuma) 2872 2873 #define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \ 2874 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2875 void *vd, void *vn, void *vm) \ 2876 { \ 2877 TYPE *d = vd, *n = vn, *m = vm; \ 2878 TYPE r[16 / ESIZE]; \ 2879 uint16_t tm, mask = mve_element_mask(env); \ 2880 unsigned e; \ 2881 float_status *fpst; \ 2882 float_status scratch_fpst; \ 2883 /* Calculate all results first to avoid overwriting inputs */ \ 2884 for (e = 0, tm = mask; e < 16 / ESIZE; e++, tm >>= ESIZE) { \ 2885 if ((tm & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2886 r[e] = 0; \ 2887 continue; \ 2888 } \ 2889 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2890 if (!(tm & 1)) { \ 2891 /* We need the result but without updating flags */ \ 2892 scratch_fpst = *fpst; \ 2893 fpst = &scratch_fpst; \ 2894 } \ 2895 if (!(e & 1)) { \ 2896 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)], fpst); \ 2897 } else { \ 2898 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)], fpst); \ 2899 } \ 2900 } \ 2901 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2902 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 2903 } \ 2904 mve_advance_vpt(env); \ 2905 } 2906 2907 DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, float16_add) 2908 DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add) 2909 DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub) 2910 DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) 2911 2912 #define DO_VFMA(OP, ESIZE, TYPE, CHS) \ 2913 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2914 void *vd, void *vn, void *vm) \ 2915 { \ 2916 TYPE *d = vd, *n = vn, *m = vm; \ 2917 TYPE r; \ 2918 uint16_t mask = mve_element_mask(env); \ 2919 unsigned e; \ 2920 float_status *fpst; \ 2921 float_status scratch_fpst; \ 2922 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2923 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2924 continue; \ 2925 } \ 2926 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2927 if (!(mask & 1)) { \ 2928 /* We need the result but without updating flags */ \ 2929 scratch_fpst = *fpst; \ 2930 fpst = &scratch_fpst; \ 2931 } \ 2932 r = n[H##ESIZE(e)]; \ 2933 if (CHS) { \ 2934 r = TYPE##_chs(r); \ 2935 } \ 2936 r = TYPE##_muladd(r, m[H##ESIZE(e)], d[H##ESIZE(e)], \ 2937 0, fpst); \ 2938 mergemask(&d[H##ESIZE(e)], r, mask); \ 2939 } \ 2940 mve_advance_vpt(env); \ 2941 } 2942 2943 DO_VFMA(vfmah, 2, float16, false) 2944 DO_VFMA(vfmas, 4, float32, false) 2945 DO_VFMA(vfmsh, 2, float16, true) 2946 DO_VFMA(vfmss, 4, float32, true) 2947 2948 #define DO_VCMLA(OP, ESIZE, TYPE, ROT, FN) \ 2949 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2950 void *vd, void *vn, void *vm) \ 2951 { \ 2952 TYPE *d = vd, *n = vn, *m = vm; \ 2953 TYPE r0, r1, e1, e2, e3, e4; \ 2954 uint16_t mask = mve_element_mask(env); \ 2955 unsigned e; \ 2956 float_status *fpst0, *fpst1; \ 2957 float_status scratch_fpst; \ 2958 /* We loop through pairs of elements at a time */ \ 2959 for (e = 0; e < 16 / ESIZE; e += 2, mask >>= ESIZE * 2) { \ 2960 if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) == 0) { \ 2961 continue; \ 2962 } \ 2963 fpst0 = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2964 fpst1 = fpst0; \ 2965 if (!(mask & 1)) { \ 2966 scratch_fpst = *fpst0; \ 2967 fpst0 = &scratch_fpst; \ 2968 } \ 2969 if (!(mask & (1 << ESIZE))) { \ 2970 scratch_fpst = *fpst1; \ 2971 fpst1 = &scratch_fpst; \ 2972 } \ 2973 switch (ROT) { \ 2974 case 0: \ 2975 e1 = m[H##ESIZE(e)]; \ 2976 e2 = n[H##ESIZE(e)]; \ 2977 e3 = m[H##ESIZE(e + 1)]; \ 2978 e4 = n[H##ESIZE(e)]; \ 2979 break; \ 2980 case 1: \ 2981 e1 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 2982 e2 = n[H##ESIZE(e + 1)]; \ 2983 e3 = m[H##ESIZE(e)]; \ 2984 e4 = n[H##ESIZE(e + 1)]; \ 2985 break; \ 2986 case 2: \ 2987 e1 = TYPE##_chs(m[H##ESIZE(e)]); \ 2988 e2 = n[H##ESIZE(e)]; \ 2989 e3 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 2990 e4 = n[H##ESIZE(e)]; \ 2991 break; \ 2992 case 3: \ 2993 e1 = m[H##ESIZE(e + 1)]; \ 2994 e2 = n[H##ESIZE(e + 1)]; \ 2995 e3 = TYPE##_chs(m[H##ESIZE(e)]); \ 2996 e4 = n[H##ESIZE(e + 1)]; \ 2997 break; \ 2998 default: \ 2999 g_assert_not_reached(); \ 3000 } \ 3001 r0 = FN(e2, e1, d[H##ESIZE(e)], fpst0); \ 3002 r1 = FN(e4, e3, d[H##ESIZE(e + 1)], fpst1); \ 3003 mergemask(&d[H##ESIZE(e)], r0, mask); \ 3004 mergemask(&d[H##ESIZE(e + 1)], r1, mask >> ESIZE); \ 3005 } \ 3006 mve_advance_vpt(env); \ 3007 } 3008 3009 #define DO_VCMULH(N, M, D, S) float16_mul(N, M, S) 3010 #define DO_VCMULS(N, M, D, S) float32_mul(N, M, S) 3011 3012 #define DO_VCMLAH(N, M, D, S) float16_muladd(N, M, D, 0, S) 3013 #define DO_VCMLAS(N, M, D, S) float32_muladd(N, M, D, 0, S) 3014 3015 DO_VCMLA(vcmul0h, 2, float16, 0, DO_VCMULH) 3016 DO_VCMLA(vcmul0s, 4, float32, 0, DO_VCMULS) 3017 DO_VCMLA(vcmul90h, 2, float16, 1, DO_VCMULH) 3018 DO_VCMLA(vcmul90s, 4, float32, 1, DO_VCMULS) 3019 DO_VCMLA(vcmul180h, 2, float16, 2, DO_VCMULH) 3020 DO_VCMLA(vcmul180s, 4, float32, 2, DO_VCMULS) 3021 DO_VCMLA(vcmul270h, 2, float16, 3, DO_VCMULH) 3022 DO_VCMLA(vcmul270s, 4, float32, 3, DO_VCMULS) 3023 3024 DO_VCMLA(vcmla0h, 2, float16, 0, DO_VCMLAH) 3025 DO_VCMLA(vcmla0s, 4, float32, 0, DO_VCMLAS) 3026 DO_VCMLA(vcmla90h, 2, float16, 1, DO_VCMLAH) 3027 DO_VCMLA(vcmla90s, 4, float32, 1, DO_VCMLAS) 3028 DO_VCMLA(vcmla180h, 2, float16, 2, DO_VCMLAH) 3029 DO_VCMLA(vcmla180s, 4, float32, 2, DO_VCMLAS) 3030 DO_VCMLA(vcmla270h, 2, float16, 3, DO_VCMLAH) 3031 DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) 3032 3033 #define DO_2OP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3034 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3035 void *vd, void *vn, uint32_t rm) \ 3036 { \ 3037 TYPE *d = vd, *n = vn; \ 3038 TYPE r, m = rm; \ 3039 uint16_t mask = mve_element_mask(env); \ 3040 unsigned e; \ 3041 float_status *fpst; \ 3042 float_status scratch_fpst; \ 3043 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3044 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3045 continue; \ 3046 } \ 3047 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3048 if (!(mask & 1)) { \ 3049 /* We need the result but without updating flags */ \ 3050 scratch_fpst = *fpst; \ 3051 fpst = &scratch_fpst; \ 3052 } \ 3053 r = FN(n[H##ESIZE(e)], m, fpst); \ 3054 mergemask(&d[H##ESIZE(e)], r, mask); \ 3055 } \ 3056 mve_advance_vpt(env); \ 3057 } 3058 3059 #define DO_2OP_FP_SCALAR_ALL(OP, FN) \ 3060 DO_2OP_FP_SCALAR(OP##h, 2, float16, float16_##FN) \ 3061 DO_2OP_FP_SCALAR(OP##s, 4, float32, float32_##FN) 3062 3063 DO_2OP_FP_SCALAR_ALL(vfadd_scalar, add) 3064 DO_2OP_FP_SCALAR_ALL(vfsub_scalar, sub) 3065 DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) 3066 3067 #define DO_2OP_FP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 3068 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3069 void *vd, void *vn, uint32_t rm) \ 3070 { \ 3071 TYPE *d = vd, *n = vn; \ 3072 TYPE r, m = rm; \ 3073 uint16_t mask = mve_element_mask(env); \ 3074 unsigned e; \ 3075 float_status *fpst; \ 3076 float_status scratch_fpst; \ 3077 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3078 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3079 continue; \ 3080 } \ 3081 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3082 if (!(mask & 1)) { \ 3083 /* We need the result but without updating flags */ \ 3084 scratch_fpst = *fpst; \ 3085 fpst = &scratch_fpst; \ 3086 } \ 3087 r = FN(n[H##ESIZE(e)], m, d[H##ESIZE(e)], 0, fpst); \ 3088 mergemask(&d[H##ESIZE(e)], r, mask); \ 3089 } \ 3090 mve_advance_vpt(env); \ 3091 } 3092 3093 /* VFMAS is vector * vector + scalar, so swap op2 and op3 */ 3094 #define DO_VFMAS_SCALARH(N, M, D, F, S) float16_muladd(N, D, M, F, S) 3095 #define DO_VFMAS_SCALARS(N, M, D, F, S) float32_muladd(N, D, M, F, S) 3096 3097 /* VFMA is vector * scalar + vector */ 3098 DO_2OP_FP_ACC_SCALAR(vfma_scalarh, 2, float16, float16_muladd) 3099 DO_2OP_FP_ACC_SCALAR(vfma_scalars, 4, float32, float32_muladd) 3100 DO_2OP_FP_ACC_SCALAR(vfmas_scalarh, 2, float16, DO_VFMAS_SCALARH) 3101 DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) 3102 3103 /* Floating point max/min across vector. */ 3104 #define DO_FP_VMAXMINV(OP, ESIZE, TYPE, ABS, FN) \ 3105 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 3106 uint32_t ra_in) \ 3107 { \ 3108 uint16_t mask = mve_element_mask(env); \ 3109 unsigned e; \ 3110 TYPE *m = vm; \ 3111 TYPE ra = (TYPE)ra_in; \ 3112 float_status *fpst = \ 3113 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3114 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3115 if (mask & 1) { \ 3116 TYPE v = m[H##ESIZE(e)]; \ 3117 if (TYPE##_is_signaling_nan(ra, fpst)) { \ 3118 ra = TYPE##_silence_nan(ra, fpst); \ 3119 float_raise(float_flag_invalid, fpst); \ 3120 } \ 3121 if (TYPE##_is_signaling_nan(v, fpst)) { \ 3122 v = TYPE##_silence_nan(v, fpst); \ 3123 float_raise(float_flag_invalid, fpst); \ 3124 } \ 3125 if (ABS) { \ 3126 v = TYPE##_abs(v); \ 3127 } \ 3128 ra = FN(ra, v, fpst); \ 3129 } \ 3130 } \ 3131 mve_advance_vpt(env); \ 3132 return ra; \ 3133 } \ 3134 3135 #define NOP(X) (X) 3136 3137 DO_FP_VMAXMINV(vmaxnmvh, 2, float16, false, float16_maxnum) 3138 DO_FP_VMAXMINV(vmaxnmvs, 4, float32, false, float32_maxnum) 3139 DO_FP_VMAXMINV(vminnmvh, 2, float16, false, float16_minnum) 3140 DO_FP_VMAXMINV(vminnmvs, 4, float32, false, float32_minnum) 3141 DO_FP_VMAXMINV(vmaxnmavh, 2, float16, true, float16_maxnum) 3142 DO_FP_VMAXMINV(vmaxnmavs, 4, float32, true, float32_maxnum) 3143 DO_FP_VMAXMINV(vminnmavh, 2, float16, true, float16_minnum) 3144 DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) 3145 3146 /* FP compares; note that all comparisons signal InvalidOp for QNaNs */ 3147 #define DO_VCMP_FP(OP, ESIZE, TYPE, FN) \ 3148 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 3149 { \ 3150 TYPE *n = vn, *m = vm; \ 3151 uint16_t mask = mve_element_mask(env); \ 3152 uint16_t eci_mask = mve_eci_mask(env); \ 3153 uint16_t beatpred = 0; \ 3154 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3155 unsigned e; \ 3156 float_status *fpst; \ 3157 float_status scratch_fpst; \ 3158 bool r; \ 3159 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3160 if ((mask & emask) == 0) { \ 3161 continue; \ 3162 } \ 3163 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3164 if (!(mask & (1 << (e * ESIZE)))) { \ 3165 /* We need the result but without updating flags */ \ 3166 scratch_fpst = *fpst; \ 3167 fpst = &scratch_fpst; \ 3168 } \ 3169 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 3170 /* Comparison sets 0/1 bits for each byte in the element */ \ 3171 beatpred |= r * emask; \ 3172 } \ 3173 beatpred &= mask; \ 3174 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3175 (beatpred & eci_mask); \ 3176 mve_advance_vpt(env); \ 3177 } 3178 3179 #define DO_VCMP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3180 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 3181 uint32_t rm) \ 3182 { \ 3183 TYPE *n = vn; \ 3184 uint16_t mask = mve_element_mask(env); \ 3185 uint16_t eci_mask = mve_eci_mask(env); \ 3186 uint16_t beatpred = 0; \ 3187 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3188 unsigned e; \ 3189 float_status *fpst; \ 3190 float_status scratch_fpst; \ 3191 bool r; \ 3192 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3193 if ((mask & emask) == 0) { \ 3194 continue; \ 3195 } \ 3196 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3197 if (!(mask & (1 << (e * ESIZE)))) { \ 3198 /* We need the result but without updating flags */ \ 3199 scratch_fpst = *fpst; \ 3200 fpst = &scratch_fpst; \ 3201 } \ 3202 r = FN(n[H##ESIZE(e)], (TYPE)rm, fpst); \ 3203 /* Comparison sets 0/1 bits for each byte in the element */ \ 3204 beatpred |= r * emask; \ 3205 } \ 3206 beatpred &= mask; \ 3207 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3208 (beatpred & eci_mask); \ 3209 mve_advance_vpt(env); \ 3210 } 3211 3212 #define DO_VCMP_FP_BOTH(VOP, SOP, ESIZE, TYPE, FN) \ 3213 DO_VCMP_FP(VOP, ESIZE, TYPE, FN) \ 3214 DO_VCMP_FP_SCALAR(SOP, ESIZE, TYPE, FN) 3215 3216 /* 3217 * Some care is needed here to get the correct result for the unordered case. 3218 * Architecturally EQ, GE and GT are defined to be false for unordered, but 3219 * the NE, LT and LE comparisons are defined as simple logical inverses of 3220 * EQ, GE and GT and so they must return true for unordered. The softfloat 3221 * comparison functions float*_{eq,le,lt} all return false for unordered. 3222 */ 3223 #define DO_GE16(X, Y, S) float16_le(Y, X, S) 3224 #define DO_GE32(X, Y, S) float32_le(Y, X, S) 3225 #define DO_GT16(X, Y, S) float16_lt(Y, X, S) 3226 #define DO_GT32(X, Y, S) float32_lt(Y, X, S) 3227 3228 DO_VCMP_FP_BOTH(vfcmpeqh, vfcmpeq_scalarh, 2, float16, float16_eq) 3229 DO_VCMP_FP_BOTH(vfcmpeqs, vfcmpeq_scalars, 4, float32, float32_eq) 3230 3231 DO_VCMP_FP_BOTH(vfcmpneh, vfcmpne_scalarh, 2, float16, !float16_eq) 3232 DO_VCMP_FP_BOTH(vfcmpnes, vfcmpne_scalars, 4, float32, !float32_eq) 3233 3234 DO_VCMP_FP_BOTH(vfcmpgeh, vfcmpge_scalarh, 2, float16, DO_GE16) 3235 DO_VCMP_FP_BOTH(vfcmpges, vfcmpge_scalars, 4, float32, DO_GE32) 3236 3237 DO_VCMP_FP_BOTH(vfcmplth, vfcmplt_scalarh, 2, float16, !DO_GE16) 3238 DO_VCMP_FP_BOTH(vfcmplts, vfcmplt_scalars, 4, float32, !DO_GE32) 3239 3240 DO_VCMP_FP_BOTH(vfcmpgth, vfcmpgt_scalarh, 2, float16, DO_GT16) 3241 DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float32, DO_GT32) 3242 3243 DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) 3244 DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) 3245 3246 #define DO_VCVT_FIXED(OP, ESIZE, TYPE, FN) \ 3247 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm, \ 3248 uint32_t shift) \ 3249 { \ 3250 TYPE *d = vd, *m = vm; \ 3251 TYPE r; \ 3252 uint16_t mask = mve_element_mask(env); \ 3253 unsigned e; \ 3254 float_status *fpst; \ 3255 float_status scratch_fpst; \ 3256 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3257 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3258 continue; \ 3259 } \ 3260 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3261 if (!(mask & 1)) { \ 3262 /* We need the result but without updating flags */ \ 3263 scratch_fpst = *fpst; \ 3264 fpst = &scratch_fpst; \ 3265 } \ 3266 r = FN(m[H##ESIZE(e)], shift, fpst); \ 3267 mergemask(&d[H##ESIZE(e)], r, mask); \ 3268 } \ 3269 mve_advance_vpt(env); \ 3270 } 3271 3272 DO_VCVT_FIXED(vcvt_sh, 2, int16_t, helper_vfp_shtoh) 3273 DO_VCVT_FIXED(vcvt_uh, 2, uint16_t, helper_vfp_uhtoh) 3274 DO_VCVT_FIXED(vcvt_hs, 2, int16_t, helper_vfp_toshh_round_to_zero) 3275 DO_VCVT_FIXED(vcvt_hu, 2, uint16_t, helper_vfp_touhh_round_to_zero) 3276 DO_VCVT_FIXED(vcvt_sf, 4, int32_t, helper_vfp_sltos) 3277 DO_VCVT_FIXED(vcvt_uf, 4, uint32_t, helper_vfp_ultos) 3278 DO_VCVT_FIXED(vcvt_fs, 4, int32_t, helper_vfp_tosls_round_to_zero) 3279 DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) 3280 3281 /* VCVT with specified rmode */ 3282 #define DO_VCVT_RMODE(OP, ESIZE, TYPE, FN) \ 3283 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3284 void *vd, void *vm, uint32_t rmode) \ 3285 { \ 3286 TYPE *d = vd, *m = vm; \ 3287 TYPE r; \ 3288 uint16_t mask = mve_element_mask(env); \ 3289 unsigned e; \ 3290 float_status *fpst; \ 3291 float_status scratch_fpst; \ 3292 float_status *base_fpst = \ 3293 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3294 uint32_t prev_rmode = get_float_rounding_mode(base_fpst); \ 3295 set_float_rounding_mode(rmode, base_fpst); \ 3296 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3297 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3298 continue; \ 3299 } \ 3300 fpst = base_fpst; \ 3301 if (!(mask & 1)) { \ 3302 /* We need the result but without updating flags */ \ 3303 scratch_fpst = *fpst; \ 3304 fpst = &scratch_fpst; \ 3305 } \ 3306 r = FN(m[H##ESIZE(e)], 0, fpst); \ 3307 mergemask(&d[H##ESIZE(e)], r, mask); \ 3308 } \ 3309 set_float_rounding_mode(prev_rmode, base_fpst); \ 3310 mve_advance_vpt(env); \ 3311 } 3312 3313 DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_toshh) 3314 DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) 3315 DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) 3316 DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) 3317 3318 #define DO_VRINT_RM_H(M, F, S) helper_rinth(M, S) 3319 #define DO_VRINT_RM_S(M, F, S) helper_rints(M, S) 3320 3321 DO_VCVT_RMODE(vrint_rm_h, 2, uint16_t, DO_VRINT_RM_H) 3322 DO_VCVT_RMODE(vrint_rm_s, 4, uint32_t, DO_VRINT_RM_S) 3323 3324 /* 3325 * VCVT between halfprec and singleprec. As usual for halfprec 3326 * conversions, FZ16 is ignored and AHP is observed. 3327 */ 3328 static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) 3329 { 3330 uint16_t *d = vd; 3331 uint32_t *m = vm; 3332 uint16_t r; 3333 uint16_t mask = mve_element_mask(env); 3334 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3335 unsigned e; 3336 float_status *fpst; 3337 float_status scratch_fpst; 3338 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3339 bool old_fz = get_flush_to_zero(base_fpst); 3340 set_flush_to_zero(false, base_fpst); 3341 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3342 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3343 continue; 3344 } 3345 fpst = base_fpst; 3346 if (!(mask & 1)) { 3347 /* We need the result but without updating flags */ 3348 scratch_fpst = *fpst; 3349 fpst = &scratch_fpst; 3350 } 3351 r = float32_to_float16(m[H4(e)], ieee, fpst); 3352 mergemask(&d[H2(e * 2 + top)], r, mask >> (top * 2)); 3353 } 3354 set_flush_to_zero(old_fz, base_fpst); 3355 mve_advance_vpt(env); 3356 } 3357 3358 static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) 3359 { 3360 uint32_t *d = vd; 3361 uint16_t *m = vm; 3362 uint32_t r; 3363 uint16_t mask = mve_element_mask(env); 3364 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3365 unsigned e; 3366 float_status *fpst; 3367 float_status scratch_fpst; 3368 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3369 bool old_fiz = get_flush_inputs_to_zero(base_fpst); 3370 set_flush_inputs_to_zero(false, base_fpst); 3371 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3372 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3373 continue; 3374 } 3375 fpst = base_fpst; 3376 if (!(mask & (1 << (top * 2)))) { 3377 /* We need the result but without updating flags */ 3378 scratch_fpst = *fpst; 3379 fpst = &scratch_fpst; 3380 } 3381 r = float16_to_float32(m[H2(e * 2 + top)], ieee, fpst); 3382 mergemask(&d[H4(e)], r, mask); 3383 } 3384 set_flush_inputs_to_zero(old_fiz, base_fpst); 3385 mve_advance_vpt(env); 3386 } 3387 3388 void HELPER(mve_vcvtb_sh)(CPUARMState *env, void *vd, void *vm) 3389 { 3390 do_vcvt_sh(env, vd, vm, 0); 3391 } 3392 void HELPER(mve_vcvtt_sh)(CPUARMState *env, void *vd, void *vm) 3393 { 3394 do_vcvt_sh(env, vd, vm, 1); 3395 } 3396 void HELPER(mve_vcvtb_hs)(CPUARMState *env, void *vd, void *vm) 3397 { 3398 do_vcvt_hs(env, vd, vm, 0); 3399 } 3400 void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) 3401 { 3402 do_vcvt_hs(env, vd, vm, 1); 3403 } 3404 3405 #define DO_1OP_FP(OP, ESIZE, TYPE, FN) \ 3406 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm) \ 3407 { \ 3408 TYPE *d = vd, *m = vm; \ 3409 TYPE r; \ 3410 uint16_t mask = mve_element_mask(env); \ 3411 unsigned e; \ 3412 float_status *fpst; \ 3413 float_status scratch_fpst; \ 3414 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3415 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3416 continue; \ 3417 } \ 3418 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3419 if (!(mask & 1)) { \ 3420 /* We need the result but without updating flags */ \ 3421 scratch_fpst = *fpst; \ 3422 fpst = &scratch_fpst; \ 3423 } \ 3424 r = FN(m[H##ESIZE(e)], fpst); \ 3425 mergemask(&d[H##ESIZE(e)], r, mask); \ 3426 } \ 3427 mve_advance_vpt(env); \ 3428 } 3429 3430 DO_1OP_FP(vrintx_h, 2, float16, float16_round_to_int) 3431 DO_1OP_FP(vrintx_s, 4, float32, float32_round_to_int) 3432