1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/exec-all.h" 27 #include "tcg/tcg.h" 28 29 static uint16_t mve_eci_mask(CPUARMState *env) 30 { 31 /* 32 * Return the mask of which elements in the MVE vector correspond 33 * to beats being executed. The mask has 1 bits for executed lanes 34 * and 0 bits where ECI says this beat was already executed. 35 */ 36 int eci; 37 38 if ((env->condexec_bits & 0xf) != 0) { 39 return 0xffff; 40 } 41 42 eci = env->condexec_bits >> 4; 43 switch (eci) { 44 case ECI_NONE: 45 return 0xffff; 46 case ECI_A0: 47 return 0xfff0; 48 case ECI_A0A1: 49 return 0xff00; 50 case ECI_A0A1A2: 51 case ECI_A0A1A2B0: 52 return 0xf000; 53 default: 54 g_assert_not_reached(); 55 } 56 } 57 58 static uint16_t mve_element_mask(CPUARMState *env) 59 { 60 /* 61 * Return the mask of which elements in the MVE vector should be 62 * updated. This is a combination of multiple things: 63 * (1) by default, we update every lane in the vector 64 * (2) VPT predication stores its state in the VPR register; 65 * (3) low-overhead-branch tail predication will mask out part 66 * the vector on the final iteration of the loop 67 * (4) if EPSR.ECI is set then we must execute only some beats 68 * of the insn 69 * We combine all these into a 16-bit result with the same semantics 70 * as VPR.P0: 0 to mask the lane, 1 if it is active. 71 * 8-bit vector ops will look at all bits of the result; 72 * 16-bit ops will look at bits 0, 2, 4, ...; 73 * 32-bit ops will look at bits 0, 4, 8 and 12. 74 * Compare pseudocode GetCurInstrBeat(), though that only returns 75 * the 4-bit slice of the mask corresponding to a single beat. 76 */ 77 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 78 79 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 80 mask |= 0xff; 81 } 82 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 83 mask |= 0xff00; 84 } 85 86 if (env->v7m.ltpsize < 4 && 87 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 88 /* 89 * Tail predication active, and this is the last loop iteration. 90 * The element size is (1 << ltpsize), and we only want to process 91 * loopcount elements, so we want to retain the least significant 92 * (loopcount * esize) predicate bits and zero out bits above that. 93 */ 94 int masklen = env->regs[14] << env->v7m.ltpsize; 95 assert(masklen <= 16); 96 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 97 mask &= ltpmask; 98 } 99 100 /* 101 * ECI bits indicate which beats are already executed; 102 * we handle this by effectively predicating them out. 103 */ 104 mask &= mve_eci_mask(env); 105 return mask; 106 } 107 108 static void mve_advance_vpt(CPUARMState *env) 109 { 110 /* Advance the VPT and ECI state if necessary */ 111 uint32_t vpr = env->v7m.vpr; 112 unsigned mask01, mask23; 113 uint16_t inv_mask; 114 uint16_t eci_mask = mve_eci_mask(env); 115 116 if ((env->condexec_bits & 0xf) == 0) { 117 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 118 (ECI_A0 << 4) : (ECI_NONE << 4); 119 } 120 121 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 122 /* VPT not enabled, nothing to do */ 123 return; 124 } 125 126 /* Invert P0 bits if needed, but only for beats we actually executed */ 127 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 128 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 129 /* Start by assuming we invert all bits corresponding to executed beats */ 130 inv_mask = eci_mask; 131 if (mask01 <= 8) { 132 /* MASK01 says don't invert low half of P0 */ 133 inv_mask &= ~0xff; 134 } 135 if (mask23 <= 8) { 136 /* MASK23 says don't invert high half of P0 */ 137 inv_mask &= ~0xff00; 138 } 139 vpr ^= inv_mask; 140 /* Only update MASK01 if beat 1 executed */ 141 if (eci_mask & 0xf0) { 142 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 143 } 144 /* Beat 3 always executes, so update MASK23 */ 145 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 146 env->v7m.vpr = vpr; 147 } 148 149 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 150 #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ 151 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 152 { \ 153 TYPE *d = vd; \ 154 uint16_t mask = mve_element_mask(env); \ 155 uint16_t eci_mask = mve_eci_mask(env); \ 156 unsigned b, e; \ 157 /* \ 158 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 159 * beats so we don't care if we update part of the dest and \ 160 * then take an exception. \ 161 */ \ 162 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 163 if (eci_mask & (1 << b)) { \ 164 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 165 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 166 } \ 167 addr += MSIZE; \ 168 } \ 169 mve_advance_vpt(env); \ 170 } 171 172 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ 173 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 174 { \ 175 TYPE *d = vd; \ 176 uint16_t mask = mve_element_mask(env); \ 177 unsigned b, e; \ 178 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 179 if (mask & (1 << b)) { \ 180 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 181 } \ 182 addr += MSIZE; \ 183 } \ 184 mve_advance_vpt(env); \ 185 } 186 187 DO_VLDR(vldrb, 1, ldub, 1, uint8_t) 188 DO_VLDR(vldrh, 2, lduw, 2, uint16_t) 189 DO_VLDR(vldrw, 4, ldl, 4, uint32_t) 190 191 DO_VSTR(vstrb, 1, stb, 1, uint8_t) 192 DO_VSTR(vstrh, 2, stw, 2, uint16_t) 193 DO_VSTR(vstrw, 4, stl, 4, uint32_t) 194 195 DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t) 196 DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t) 197 DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t) 198 DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t) 199 DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t) 200 DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t) 201 202 DO_VSTR(vstrb_h, 1, stb, 2, int16_t) 203 DO_VSTR(vstrb_w, 1, stb, 4, int32_t) 204 DO_VSTR(vstrh_w, 2, stw, 4, int32_t) 205 206 #undef DO_VLDR 207 #undef DO_VSTR 208 209 /* 210 * The mergemask(D, R, M) macro performs the operation "*D = R" but 211 * storing only the bytes which correspond to 1 bits in M, 212 * leaving other bytes in *D unchanged. We use _Generic 213 * to select the correct implementation based on the type of D. 214 */ 215 216 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 217 { 218 if (mask & 1) { 219 *d = r; 220 } 221 } 222 223 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 224 { 225 mergemask_ub((uint8_t *)d, r, mask); 226 } 227 228 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 229 { 230 uint16_t bmask = expand_pred_b_data[mask & 3]; 231 *d = (*d & ~bmask) | (r & bmask); 232 } 233 234 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 235 { 236 mergemask_uh((uint16_t *)d, r, mask); 237 } 238 239 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 240 { 241 uint32_t bmask = expand_pred_b_data[mask & 0xf]; 242 *d = (*d & ~bmask) | (r & bmask); 243 } 244 245 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 246 { 247 mergemask_uw((uint32_t *)d, r, mask); 248 } 249 250 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 251 { 252 uint64_t bmask = expand_pred_b_data[mask & 0xff]; 253 *d = (*d & ~bmask) | (r & bmask); 254 } 255 256 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 257 { 258 mergemask_uq((uint64_t *)d, r, mask); 259 } 260 261 #define mergemask(D, R, M) \ 262 _Generic(D, \ 263 uint8_t *: mergemask_ub, \ 264 int8_t *: mergemask_sb, \ 265 uint16_t *: mergemask_uh, \ 266 int16_t *: mergemask_sh, \ 267 uint32_t *: mergemask_uw, \ 268 int32_t *: mergemask_sw, \ 269 uint64_t *: mergemask_uq, \ 270 int64_t *: mergemask_sq)(D, R, M) 271 272 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 273 { 274 /* 275 * The generated code already replicated an 8 or 16 bit constant 276 * into the 32-bit value, so we only need to write the 32-bit 277 * value to all elements of the Qreg, allowing for predication. 278 */ 279 uint32_t *d = vd; 280 uint16_t mask = mve_element_mask(env); 281 unsigned e; 282 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 283 mergemask(&d[H4(e)], val, mask); 284 } 285 mve_advance_vpt(env); 286 } 287 288 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 289 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 290 { \ 291 TYPE *d = vd, *m = vm; \ 292 uint16_t mask = mve_element_mask(env); \ 293 unsigned e; \ 294 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 295 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 296 } \ 297 mve_advance_vpt(env); \ 298 } 299 300 #define DO_CLS_B(N) (clrsb32(N) - 24) 301 #define DO_CLS_H(N) (clrsb32(N) - 16) 302 303 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 304 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 305 DO_1OP(vclsw, 4, int32_t, clrsb32) 306 307 #define DO_CLZ_B(N) (clz32(N) - 24) 308 #define DO_CLZ_H(N) (clz32(N) - 16) 309 310 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 311 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 312 DO_1OP(vclzw, 4, uint32_t, clz32) 313 314 DO_1OP(vrev16b, 2, uint16_t, bswap16) 315 DO_1OP(vrev32b, 4, uint32_t, bswap32) 316 DO_1OP(vrev32h, 4, uint32_t, hswap32) 317 DO_1OP(vrev64b, 8, uint64_t, bswap64) 318 DO_1OP(vrev64h, 8, uint64_t, hswap64) 319 DO_1OP(vrev64w, 8, uint64_t, wswap64) 320 321 #define DO_NOT(N) (~(N)) 322 323 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 324 325 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 326 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 327 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 328 329 DO_1OP(vabsb, 1, int8_t, DO_ABS) 330 DO_1OP(vabsh, 2, int16_t, DO_ABS) 331 DO_1OP(vabsw, 4, int32_t, DO_ABS) 332 333 /* We can do these 64 bits at a time */ 334 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 335 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 336 337 #define DO_NEG(N) (-(N)) 338 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 339 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 340 341 DO_1OP(vnegb, 1, int8_t, DO_NEG) 342 DO_1OP(vnegh, 2, int16_t, DO_NEG) 343 DO_1OP(vnegw, 4, int32_t, DO_NEG) 344 345 /* We can do these 64 bits at a time */ 346 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 347 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 348 349 /* 350 * 1 operand immediates: Vda is destination and possibly also one source. 351 * All these insns work at 64-bit widths. 352 */ 353 #define DO_1OP_IMM(OP, FN) \ 354 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 355 { \ 356 uint64_t *da = vda; \ 357 uint16_t mask = mve_element_mask(env); \ 358 unsigned e; \ 359 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 360 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 361 } \ 362 mve_advance_vpt(env); \ 363 } 364 365 #define DO_MOVI(N, I) (I) 366 #define DO_ANDI(N, I) ((N) & (I)) 367 #define DO_ORRI(N, I) ((N) | (I)) 368 369 DO_1OP_IMM(vmovi, DO_MOVI) 370 DO_1OP_IMM(vandi, DO_ANDI) 371 DO_1OP_IMM(vorri, DO_ORRI) 372 373 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 374 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 375 void *vd, void *vn, void *vm) \ 376 { \ 377 TYPE *d = vd, *n = vn, *m = vm; \ 378 uint16_t mask = mve_element_mask(env); \ 379 unsigned e; \ 380 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 381 mergemask(&d[H##ESIZE(e)], \ 382 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 383 } \ 384 mve_advance_vpt(env); \ 385 } 386 387 /* provide unsigned 2-op helpers for all sizes */ 388 #define DO_2OP_U(OP, FN) \ 389 DO_2OP(OP##b, 1, uint8_t, FN) \ 390 DO_2OP(OP##h, 2, uint16_t, FN) \ 391 DO_2OP(OP##w, 4, uint32_t, FN) 392 393 /* provide signed 2-op helpers for all sizes */ 394 #define DO_2OP_S(OP, FN) \ 395 DO_2OP(OP##b, 1, int8_t, FN) \ 396 DO_2OP(OP##h, 2, int16_t, FN) \ 397 DO_2OP(OP##w, 4, int32_t, FN) 398 399 /* 400 * "Long" operations where two half-sized inputs (taken from either the 401 * top or the bottom of the input vector) produce a double-width result. 402 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 403 */ 404 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 405 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 406 { \ 407 LTYPE *d = vd; \ 408 TYPE *n = vn, *m = vm; \ 409 uint16_t mask = mve_element_mask(env); \ 410 unsigned le; \ 411 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 412 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 413 m[H##ESIZE(le * 2 + TOP)]); \ 414 mergemask(&d[H##LESIZE(le)], r, mask); \ 415 } \ 416 mve_advance_vpt(env); \ 417 } 418 419 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 420 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 421 { \ 422 TYPE *d = vd, *n = vn, *m = vm; \ 423 uint16_t mask = mve_element_mask(env); \ 424 unsigned e; \ 425 bool qc = false; \ 426 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 427 bool sat = false; \ 428 TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 429 mergemask(&d[H##ESIZE(e)], r, mask); \ 430 qc |= sat & mask & 1; \ 431 } \ 432 if (qc) { \ 433 env->vfp.qc[0] = qc; \ 434 } \ 435 mve_advance_vpt(env); \ 436 } 437 438 /* provide unsigned 2-op helpers for all sizes */ 439 #define DO_2OP_SAT_U(OP, FN) \ 440 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 441 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 442 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 443 444 /* provide signed 2-op helpers for all sizes */ 445 #define DO_2OP_SAT_S(OP, FN) \ 446 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 447 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 448 DO_2OP_SAT(OP##w, 4, int32_t, FN) 449 450 #define DO_AND(N, M) ((N) & (M)) 451 #define DO_BIC(N, M) ((N) & ~(M)) 452 #define DO_ORR(N, M) ((N) | (M)) 453 #define DO_ORN(N, M) ((N) | ~(M)) 454 #define DO_EOR(N, M) ((N) ^ (M)) 455 456 DO_2OP(vand, 8, uint64_t, DO_AND) 457 DO_2OP(vbic, 8, uint64_t, DO_BIC) 458 DO_2OP(vorr, 8, uint64_t, DO_ORR) 459 DO_2OP(vorn, 8, uint64_t, DO_ORN) 460 DO_2OP(veor, 8, uint64_t, DO_EOR) 461 462 #define DO_ADD(N, M) ((N) + (M)) 463 #define DO_SUB(N, M) ((N) - (M)) 464 #define DO_MUL(N, M) ((N) * (M)) 465 466 DO_2OP_U(vadd, DO_ADD) 467 DO_2OP_U(vsub, DO_SUB) 468 DO_2OP_U(vmul, DO_MUL) 469 470 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 471 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 472 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 473 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 474 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 475 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 476 477 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 478 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 479 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 480 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 481 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 482 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 483 484 /* 485 * Polynomial multiply. We can always do this generating 64 bits 486 * of the result at a time, so we don't need to use DO_2OP_L. 487 */ 488 #define VMULLPH_MASK 0x00ff00ff00ff00ffULL 489 #define VMULLPW_MASK 0x0000ffff0000ffffULL 490 #define DO_VMULLPBH(N, M) pmull_h((N) & VMULLPH_MASK, (M) & VMULLPH_MASK) 491 #define DO_VMULLPTH(N, M) DO_VMULLPBH((N) >> 8, (M) >> 8) 492 #define DO_VMULLPBW(N, M) pmull_w((N) & VMULLPW_MASK, (M) & VMULLPW_MASK) 493 #define DO_VMULLPTW(N, M) DO_VMULLPBW((N) >> 16, (M) >> 16) 494 495 DO_2OP(vmullpbh, 8, uint64_t, DO_VMULLPBH) 496 DO_2OP(vmullpth, 8, uint64_t, DO_VMULLPTH) 497 DO_2OP(vmullpbw, 8, uint64_t, DO_VMULLPBW) 498 DO_2OP(vmullptw, 8, uint64_t, DO_VMULLPTW) 499 500 /* 501 * Because the computation type is at least twice as large as required, 502 * these work for both signed and unsigned source types. 503 */ 504 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 505 { 506 return (n * m) >> 8; 507 } 508 509 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 510 { 511 return (n * m) >> 16; 512 } 513 514 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 515 { 516 return (n * m) >> 32; 517 } 518 519 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 520 { 521 return (n * m + (1U << 7)) >> 8; 522 } 523 524 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 525 { 526 return (n * m + (1U << 15)) >> 16; 527 } 528 529 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 530 { 531 return (n * m + (1U << 31)) >> 32; 532 } 533 534 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 535 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 536 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 537 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 538 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 539 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 540 541 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 542 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 543 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 544 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 545 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 546 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 547 548 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 549 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 550 551 DO_2OP_S(vmaxs, DO_MAX) 552 DO_2OP_U(vmaxu, DO_MAX) 553 DO_2OP_S(vmins, DO_MIN) 554 DO_2OP_U(vminu, DO_MIN) 555 556 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 557 558 DO_2OP_S(vabds, DO_ABD) 559 DO_2OP_U(vabdu, DO_ABD) 560 561 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 562 { 563 return ((uint64_t)n + m) >> 1; 564 } 565 566 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 567 { 568 return ((int64_t)n + m) >> 1; 569 } 570 571 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 572 { 573 return ((uint64_t)n - m) >> 1; 574 } 575 576 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 577 { 578 return ((int64_t)n - m) >> 1; 579 } 580 581 DO_2OP_S(vhadds, do_vhadd_s) 582 DO_2OP_U(vhaddu, do_vhadd_u) 583 DO_2OP_S(vhsubs, do_vhsub_s) 584 DO_2OP_U(vhsubu, do_vhsub_u) 585 586 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 587 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 588 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 589 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 590 591 DO_2OP_S(vshls, DO_VSHLS) 592 DO_2OP_U(vshlu, DO_VSHLU) 593 DO_2OP_S(vrshls, DO_VRSHLS) 594 DO_2OP_U(vrshlu, DO_VRSHLU) 595 596 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 597 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 598 599 DO_2OP_S(vrhadds, DO_RHADD_S) 600 DO_2OP_U(vrhaddu, DO_RHADD_U) 601 602 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 603 uint32_t inv, uint32_t carry_in, bool update_flags) 604 { 605 uint16_t mask = mve_element_mask(env); 606 unsigned e; 607 608 /* If any additions trigger, we will update flags. */ 609 if (mask & 0x1111) { 610 update_flags = true; 611 } 612 613 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 614 uint64_t r = carry_in; 615 r += n[H4(e)]; 616 r += m[H4(e)] ^ inv; 617 if (mask & 1) { 618 carry_in = r >> 32; 619 } 620 mergemask(&d[H4(e)], r, mask); 621 } 622 623 if (update_flags) { 624 /* Store C, clear NZV. */ 625 env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK; 626 env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C; 627 } 628 mve_advance_vpt(env); 629 } 630 631 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 632 { 633 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 634 do_vadc(env, vd, vn, vm, 0, carry_in, false); 635 } 636 637 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 638 { 639 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 640 do_vadc(env, vd, vn, vm, -1, carry_in, false); 641 } 642 643 644 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 645 { 646 do_vadc(env, vd, vn, vm, 0, 0, true); 647 } 648 649 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 650 { 651 do_vadc(env, vd, vn, vm, -1, 1, true); 652 } 653 654 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 655 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 656 { \ 657 TYPE *d = vd, *n = vn, *m = vm; \ 658 uint16_t mask = mve_element_mask(env); \ 659 unsigned e; \ 660 TYPE r[16 / ESIZE]; \ 661 /* Calculate all results first to avoid overwriting inputs */ \ 662 for (e = 0; e < 16 / ESIZE; e++) { \ 663 if (!(e & 1)) { \ 664 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 665 } else { \ 666 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 667 } \ 668 } \ 669 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 670 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 671 } \ 672 mve_advance_vpt(env); \ 673 } 674 675 #define DO_VCADD_ALL(OP, FN0, FN1) \ 676 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 677 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 678 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 679 680 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 681 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 682 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 683 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 684 685 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 686 { 687 if (val > max) { 688 *s = true; 689 return max; 690 } else if (val < min) { 691 *s = true; 692 return min; 693 } 694 return val; 695 } 696 697 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 698 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 699 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 700 701 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 702 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 703 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 704 705 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 706 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 707 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 708 709 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 710 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 711 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 712 713 /* 714 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 715 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 716 */ 717 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 718 INT8_MIN, INT8_MAX, s) 719 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 720 INT16_MIN, INT16_MAX, s) 721 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 722 INT32_MIN, INT32_MAX, s) 723 724 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 725 INT8_MIN, INT8_MAX, s) 726 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 727 INT16_MIN, INT16_MAX, s) 728 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 729 INT32_MIN, INT32_MAX, s) 730 731 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 732 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 733 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 734 735 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 736 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 737 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 738 739 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 740 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 741 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 742 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 743 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 744 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 745 746 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 747 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 748 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 749 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 750 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 751 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 752 753 /* 754 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 755 * and friends wanting a uint32_t* sat and our needing a bool*. 756 */ 757 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 758 ({ \ 759 uint32_t su32 = 0; \ 760 typeof(N) r = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 761 if (su32) { \ 762 *satp = true; \ 763 } \ 764 r; \ 765 }) 766 767 #define DO_SQSHL_OP(N, M, satp) \ 768 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 769 #define DO_UQSHL_OP(N, M, satp) \ 770 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 771 #define DO_SQRSHL_OP(N, M, satp) \ 772 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 773 #define DO_UQRSHL_OP(N, M, satp) \ 774 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 775 #define DO_SUQSHL_OP(N, M, satp) \ 776 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 777 778 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 779 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 780 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 781 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 782 783 /* 784 * Multiply add dual returning high half 785 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 786 * whether to add the rounding constant, and the pointer to the 787 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 788 * saturate to twice the input size and return the high half; or 789 * (A * B - C * D) etc for VQDMLSDH. 790 */ 791 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 792 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 793 void *vm) \ 794 { \ 795 TYPE *d = vd, *n = vn, *m = vm; \ 796 uint16_t mask = mve_element_mask(env); \ 797 unsigned e; \ 798 bool qc = false; \ 799 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 800 bool sat = false; \ 801 if ((e & 1) == XCHG) { \ 802 TYPE r = FN(n[H##ESIZE(e)], \ 803 m[H##ESIZE(e - XCHG)], \ 804 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 805 m[H##ESIZE(e + (1 - XCHG))], \ 806 ROUND, &sat); \ 807 mergemask(&d[H##ESIZE(e)], r, mask); \ 808 qc |= sat & mask & 1; \ 809 } \ 810 } \ 811 if (qc) { \ 812 env->vfp.qc[0] = qc; \ 813 } \ 814 mve_advance_vpt(env); \ 815 } 816 817 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 818 int round, bool *sat) 819 { 820 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 821 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 822 } 823 824 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 825 int round, bool *sat) 826 { 827 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 828 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 829 } 830 831 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 832 int round, bool *sat) 833 { 834 int64_t m1 = (int64_t)a * b; 835 int64_t m2 = (int64_t)c * d; 836 int64_t r; 837 /* 838 * Architecturally we should do the entire add, double, round 839 * and then check for saturation. We do three saturating adds, 840 * but we need to be careful about the order. If the first 841 * m1 + m2 saturates then it's impossible for the *2+rc to 842 * bring it back into the non-saturated range. However, if 843 * m1 + m2 is negative then it's possible that doing the doubling 844 * would take the intermediate result below INT64_MAX and the 845 * addition of the rounding constant then brings it back in range. 846 * So we add half the rounding constant before doubling rather 847 * than adding the rounding constant after the doubling. 848 */ 849 if (sadd64_overflow(m1, m2, &r) || 850 sadd64_overflow(r, (round << 30), &r) || 851 sadd64_overflow(r, r, &r)) { 852 *sat = true; 853 return r < 0 ? INT32_MAX : INT32_MIN; 854 } 855 return r >> 32; 856 } 857 858 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 859 int round, bool *sat) 860 { 861 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 862 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 863 } 864 865 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 866 int round, bool *sat) 867 { 868 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 869 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 870 } 871 872 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 873 int round, bool *sat) 874 { 875 int64_t m1 = (int64_t)a * b; 876 int64_t m2 = (int64_t)c * d; 877 int64_t r; 878 /* The same ordering issue as in do_vqdmladh_w applies here too */ 879 if (ssub64_overflow(m1, m2, &r) || 880 sadd64_overflow(r, (round << 30), &r) || 881 sadd64_overflow(r, r, &r)) { 882 *sat = true; 883 return r < 0 ? INT32_MAX : INT32_MIN; 884 } 885 return r >> 32; 886 } 887 888 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 889 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 890 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 891 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 892 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 893 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 894 895 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 896 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 897 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 898 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 899 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 900 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 901 902 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 903 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 904 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 905 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 906 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 907 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 908 909 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 910 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 911 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 912 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 913 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 914 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 915 916 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 917 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 918 uint32_t rm) \ 919 { \ 920 TYPE *d = vd, *n = vn; \ 921 TYPE m = rm; \ 922 uint16_t mask = mve_element_mask(env); \ 923 unsigned e; \ 924 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 925 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 926 } \ 927 mve_advance_vpt(env); \ 928 } 929 930 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 931 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 932 uint32_t rm) \ 933 { \ 934 TYPE *d = vd, *n = vn; \ 935 TYPE m = rm; \ 936 uint16_t mask = mve_element_mask(env); \ 937 unsigned e; \ 938 bool qc = false; \ 939 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 940 bool sat = false; \ 941 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 942 mask); \ 943 qc |= sat & mask & 1; \ 944 } \ 945 if (qc) { \ 946 env->vfp.qc[0] = qc; \ 947 } \ 948 mve_advance_vpt(env); \ 949 } 950 951 /* "accumulating" version where FN takes d as well as n and m */ 952 #define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 953 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 954 uint32_t rm) \ 955 { \ 956 TYPE *d = vd, *n = vn; \ 957 TYPE m = rm; \ 958 uint16_t mask = mve_element_mask(env); \ 959 unsigned e; \ 960 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 961 mergemask(&d[H##ESIZE(e)], \ 962 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \ 963 } \ 964 mve_advance_vpt(env); \ 965 } 966 967 /* provide unsigned 2-op scalar helpers for all sizes */ 968 #define DO_2OP_SCALAR_U(OP, FN) \ 969 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 970 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 971 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 972 #define DO_2OP_SCALAR_S(OP, FN) \ 973 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 974 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 975 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 976 977 #define DO_2OP_ACC_SCALAR_U(OP, FN) \ 978 DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \ 979 DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \ 980 DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN) 981 982 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 983 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 984 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 985 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 986 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 987 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 988 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 989 990 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 991 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 992 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 993 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 994 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 995 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 996 997 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 998 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 999 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 1000 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 1001 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 1002 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 1003 1004 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 1005 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 1006 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 1007 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 1008 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 1009 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 1010 1011 /* Vector by scalar plus vector */ 1012 #define DO_VMLA(D, N, M) ((N) * (M) + (D)) 1013 1014 DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA) 1015 1016 /* Vector by vector plus scalar */ 1017 #define DO_VMLAS(D, N, M) ((N) * (D) + (M)) 1018 1019 DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS) 1020 1021 /* 1022 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 1023 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 1024 * SATMASK specifies which bits of the predicate mask matter for determining 1025 * whether to propagate a saturation indication into FPSCR.QC -- for 1026 * the 16x16->32 case we must check only the bit corresponding to the T or B 1027 * half that we used, but for the 32x32->64 case we propagate if the mask 1028 * bit is set for either half. 1029 */ 1030 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1031 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1032 uint32_t rm) \ 1033 { \ 1034 LTYPE *d = vd; \ 1035 TYPE *n = vn; \ 1036 TYPE m = rm; \ 1037 uint16_t mask = mve_element_mask(env); \ 1038 unsigned le; \ 1039 bool qc = false; \ 1040 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1041 bool sat = false; \ 1042 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 1043 mergemask(&d[H##LESIZE(le)], r, mask); \ 1044 qc |= sat && (mask & SATMASK); \ 1045 } \ 1046 if (qc) { \ 1047 env->vfp.qc[0] = qc; \ 1048 } \ 1049 mve_advance_vpt(env); \ 1050 } 1051 1052 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1053 { 1054 int64_t r = ((int64_t)n * m) * 2; 1055 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1056 } 1057 1058 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1059 { 1060 /* The multiply can't overflow, but the doubling might */ 1061 int64_t r = (int64_t)n * m; 1062 if (r > INT64_MAX / 2) { 1063 *sat = true; 1064 return INT64_MAX; 1065 } else if (r < INT64_MIN / 2) { 1066 *sat = true; 1067 return INT64_MIN; 1068 } else { 1069 return r * 2; 1070 } 1071 } 1072 1073 #define SATMASK16B 1 1074 #define SATMASK16T (1 << 2) 1075 #define SATMASK32 ((1 << 4) | 1) 1076 1077 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1078 do_qdmullh, SATMASK16B) 1079 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1080 do_qdmullw, SATMASK32) 1081 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1082 do_qdmullh, SATMASK16T) 1083 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1084 do_qdmullw, SATMASK32) 1085 1086 /* 1087 * Long saturating ops 1088 */ 1089 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1090 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1091 void *vm) \ 1092 { \ 1093 LTYPE *d = vd; \ 1094 TYPE *n = vn, *m = vm; \ 1095 uint16_t mask = mve_element_mask(env); \ 1096 unsigned le; \ 1097 bool qc = false; \ 1098 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1099 bool sat = false; \ 1100 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1101 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1102 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1103 qc |= sat && (mask & SATMASK); \ 1104 } \ 1105 if (qc) { \ 1106 env->vfp.qc[0] = qc; \ 1107 } \ 1108 mve_advance_vpt(env); \ 1109 } 1110 1111 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1112 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1113 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1114 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1115 1116 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1117 { 1118 m &= 0xff; 1119 if (m == 0) { 1120 return 0; 1121 } 1122 n = revbit8(n); 1123 if (m < 8) { 1124 n >>= 8 - m; 1125 } 1126 return n; 1127 } 1128 1129 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1130 { 1131 m &= 0xff; 1132 if (m == 0) { 1133 return 0; 1134 } 1135 n = revbit16(n); 1136 if (m < 16) { 1137 n >>= 16 - m; 1138 } 1139 return n; 1140 } 1141 1142 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1143 { 1144 m &= 0xff; 1145 if (m == 0) { 1146 return 0; 1147 } 1148 n = revbit32(n); 1149 if (m < 32) { 1150 n >>= 32 - m; 1151 } 1152 return n; 1153 } 1154 1155 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1156 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1157 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1158 1159 /* 1160 * Multiply add long dual accumulate ops. 1161 */ 1162 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1163 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1164 void *vm, uint64_t a) \ 1165 { \ 1166 uint16_t mask = mve_element_mask(env); \ 1167 unsigned e; \ 1168 TYPE *n = vn, *m = vm; \ 1169 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1170 if (mask & 1) { \ 1171 if (e & 1) { \ 1172 a ODDACC \ 1173 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1174 } else { \ 1175 a EVENACC \ 1176 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1177 } \ 1178 } \ 1179 } \ 1180 mve_advance_vpt(env); \ 1181 return a; \ 1182 } 1183 1184 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1185 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1186 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1187 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1188 1189 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1190 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1191 1192 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1193 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1194 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1195 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1196 1197 /* 1198 * Multiply add dual accumulate ops 1199 */ 1200 #define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1201 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1202 void *vm, uint32_t a) \ 1203 { \ 1204 uint16_t mask = mve_element_mask(env); \ 1205 unsigned e; \ 1206 TYPE *n = vn, *m = vm; \ 1207 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1208 if (mask & 1) { \ 1209 if (e & 1) { \ 1210 a ODDACC \ 1211 n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1212 } else { \ 1213 a EVENACC \ 1214 n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1215 } \ 1216 } \ 1217 } \ 1218 mve_advance_vpt(env); \ 1219 return a; \ 1220 } 1221 1222 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ 1223 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \ 1224 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \ 1225 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC) 1226 1227 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ 1228 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \ 1229 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \ 1230 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC) 1231 1232 DO_DAV_S(vmladavs, false, +=, +=) 1233 DO_DAV_U(vmladavu, false, +=, +=) 1234 DO_DAV_S(vmlsdav, false, +=, -=) 1235 DO_DAV_S(vmladavsx, true, +=, +=) 1236 DO_DAV_S(vmlsdavx, true, +=, -=) 1237 1238 /* 1239 * Rounding multiply add long dual accumulate high. In the pseudocode 1240 * this is implemented with a 72-bit internal accumulator value of which 1241 * the top 64 bits are returned. We optimize this to avoid having to 1242 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1243 * is squashed back into 64-bits after each beat. 1244 */ 1245 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1246 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1247 void *vm, uint64_t a) \ 1248 { \ 1249 uint16_t mask = mve_element_mask(env); \ 1250 unsigned e; \ 1251 TYPE *n = vn, *m = vm; \ 1252 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1253 if (mask & 1) { \ 1254 LTYPE mul; \ 1255 if (e & 1) { \ 1256 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1257 if (SUB) { \ 1258 mul = -mul; \ 1259 } \ 1260 } else { \ 1261 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1262 } \ 1263 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1264 a += mul; \ 1265 } \ 1266 } \ 1267 mve_advance_vpt(env); \ 1268 return a; \ 1269 } 1270 1271 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1272 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1273 1274 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1275 1276 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1277 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1278 1279 /* Vector add across vector */ 1280 #define DO_VADDV(OP, ESIZE, TYPE) \ 1281 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1282 uint32_t ra) \ 1283 { \ 1284 uint16_t mask = mve_element_mask(env); \ 1285 unsigned e; \ 1286 TYPE *m = vm; \ 1287 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1288 if (mask & 1) { \ 1289 ra += m[H##ESIZE(e)]; \ 1290 } \ 1291 } \ 1292 mve_advance_vpt(env); \ 1293 return ra; \ 1294 } \ 1295 1296 DO_VADDV(vaddvsb, 1, int8_t) 1297 DO_VADDV(vaddvsh, 2, int16_t) 1298 DO_VADDV(vaddvsw, 4, int32_t) 1299 DO_VADDV(vaddvub, 1, uint8_t) 1300 DO_VADDV(vaddvuh, 2, uint16_t) 1301 DO_VADDV(vaddvuw, 4, uint32_t) 1302 1303 /* 1304 * Vector max/min across vector. Unlike VADDV, we must 1305 * read ra as the element size, not its full width. 1306 * We work with int64_t internally for simplicity. 1307 */ 1308 #define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \ 1309 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1310 uint32_t ra_in) \ 1311 { \ 1312 uint16_t mask = mve_element_mask(env); \ 1313 unsigned e; \ 1314 TYPE *m = vm; \ 1315 int64_t ra = (RATYPE)ra_in; \ 1316 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1317 if (mask & 1) { \ 1318 ra = FN(ra, m[H##ESIZE(e)]); \ 1319 } \ 1320 } \ 1321 mve_advance_vpt(env); \ 1322 return ra; \ 1323 } \ 1324 1325 #define DO_VMAXMINV_U(INSN, FN) \ 1326 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \ 1327 DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \ 1328 DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN) 1329 #define DO_VMAXMINV_S(INSN, FN) \ 1330 DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \ 1331 DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \ 1332 DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN) 1333 1334 /* 1335 * Helpers for max and min of absolute values across vector: 1336 * note that we only take the absolute value of 'm', not 'n' 1337 */ 1338 static int64_t do_maxa(int64_t n, int64_t m) 1339 { 1340 if (m < 0) { 1341 m = -m; 1342 } 1343 return MAX(n, m); 1344 } 1345 1346 static int64_t do_mina(int64_t n, int64_t m) 1347 { 1348 if (m < 0) { 1349 m = -m; 1350 } 1351 return MIN(n, m); 1352 } 1353 1354 DO_VMAXMINV_S(vmaxvs, DO_MAX) 1355 DO_VMAXMINV_U(vmaxvu, DO_MAX) 1356 DO_VMAXMINV_S(vminvs, DO_MIN) 1357 DO_VMAXMINV_U(vminvu, DO_MIN) 1358 /* 1359 * VMAXAV, VMINAV treat the general purpose input as unsigned 1360 * and the vector elements as signed. 1361 */ 1362 DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa) 1363 DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa) 1364 DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa) 1365 DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) 1366 DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) 1367 DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) 1368 1369 #define DO_VABAV(OP, ESIZE, TYPE) \ 1370 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1371 void *vm, uint32_t ra) \ 1372 { \ 1373 uint16_t mask = mve_element_mask(env); \ 1374 unsigned e; \ 1375 TYPE *m = vm, *n = vn; \ 1376 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1377 if (mask & 1) { \ 1378 int64_t n0 = n[H##ESIZE(e)]; \ 1379 int64_t m0 = m[H##ESIZE(e)]; \ 1380 uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \ 1381 ra += r; \ 1382 } \ 1383 } \ 1384 mve_advance_vpt(env); \ 1385 return ra; \ 1386 } 1387 1388 DO_VABAV(vabavsb, 1, int8_t) 1389 DO_VABAV(vabavsh, 2, int16_t) 1390 DO_VABAV(vabavsw, 4, int32_t) 1391 DO_VABAV(vabavub, 1, uint8_t) 1392 DO_VABAV(vabavuh, 2, uint16_t) 1393 DO_VABAV(vabavuw, 4, uint32_t) 1394 1395 #define DO_VADDLV(OP, TYPE, LTYPE) \ 1396 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1397 uint64_t ra) \ 1398 { \ 1399 uint16_t mask = mve_element_mask(env); \ 1400 unsigned e; \ 1401 TYPE *m = vm; \ 1402 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1403 if (mask & 1) { \ 1404 ra += (LTYPE)m[H4(e)]; \ 1405 } \ 1406 } \ 1407 mve_advance_vpt(env); \ 1408 return ra; \ 1409 } \ 1410 1411 DO_VADDLV(vaddlv_s, int32_t, int64_t) 1412 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 1413 1414 /* Shifts by immediate */ 1415 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 1416 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1417 void *vm, uint32_t shift) \ 1418 { \ 1419 TYPE *d = vd, *m = vm; \ 1420 uint16_t mask = mve_element_mask(env); \ 1421 unsigned e; \ 1422 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1423 mergemask(&d[H##ESIZE(e)], \ 1424 FN(m[H##ESIZE(e)], shift), mask); \ 1425 } \ 1426 mve_advance_vpt(env); \ 1427 } 1428 1429 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 1430 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1431 void *vm, uint32_t shift) \ 1432 { \ 1433 TYPE *d = vd, *m = vm; \ 1434 uint16_t mask = mve_element_mask(env); \ 1435 unsigned e; \ 1436 bool qc = false; \ 1437 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1438 bool sat = false; \ 1439 mergemask(&d[H##ESIZE(e)], \ 1440 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 1441 qc |= sat & mask & 1; \ 1442 } \ 1443 if (qc) { \ 1444 env->vfp.qc[0] = qc; \ 1445 } \ 1446 mve_advance_vpt(env); \ 1447 } 1448 1449 /* provide unsigned 2-op shift helpers for all sizes */ 1450 #define DO_2SHIFT_U(OP, FN) \ 1451 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 1452 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 1453 DO_2SHIFT(OP##w, 4, uint32_t, FN) 1454 #define DO_2SHIFT_S(OP, FN) \ 1455 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 1456 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 1457 DO_2SHIFT(OP##w, 4, int32_t, FN) 1458 1459 #define DO_2SHIFT_SAT_U(OP, FN) \ 1460 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 1461 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 1462 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 1463 #define DO_2SHIFT_SAT_S(OP, FN) \ 1464 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 1465 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 1466 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 1467 1468 DO_2SHIFT_U(vshli_u, DO_VSHLU) 1469 DO_2SHIFT_S(vshli_s, DO_VSHLS) 1470 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 1471 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 1472 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 1473 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 1474 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 1475 DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP) 1476 DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP) 1477 1478 /* Shift-and-insert; we always work with 64 bits at a time */ 1479 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 1480 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1481 void *vm, uint32_t shift) \ 1482 { \ 1483 uint64_t *d = vd, *m = vm; \ 1484 uint16_t mask; \ 1485 uint64_t shiftmask; \ 1486 unsigned e; \ 1487 if (shift == ESIZE * 8) { \ 1488 /* \ 1489 * Only VSRI can shift by <dt>; it should mean "don't \ 1490 * update the destination". The generic logic can't handle \ 1491 * this because it would try to shift by an out-of-range \ 1492 * amount, so special case it here. \ 1493 */ \ 1494 goto done; \ 1495 } \ 1496 assert(shift < ESIZE * 8); \ 1497 mask = mve_element_mask(env); \ 1498 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 1499 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 1500 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 1501 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 1502 (d[H8(e)] & ~shiftmask); \ 1503 mergemask(&d[H8(e)], r, mask); \ 1504 } \ 1505 done: \ 1506 mve_advance_vpt(env); \ 1507 } 1508 1509 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 1510 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 1511 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 1512 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 1513 1514 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 1515 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 1516 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 1517 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 1518 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 1519 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 1520 1521 /* 1522 * Long shifts taking half-sized inputs from top or bottom of the input 1523 * vector and producing a double-width result. ESIZE, TYPE are for 1524 * the input, and LESIZE, LTYPE for the output. 1525 * Unlike the normal shift helpers, we do not handle negative shift counts, 1526 * because the long shift is strictly left-only. 1527 */ 1528 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 1529 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1530 void *vm, uint32_t shift) \ 1531 { \ 1532 LTYPE *d = vd; \ 1533 TYPE *m = vm; \ 1534 uint16_t mask = mve_element_mask(env); \ 1535 unsigned le; \ 1536 assert(shift <= 16); \ 1537 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1538 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 1539 mergemask(&d[H##LESIZE(le)], r, mask); \ 1540 } \ 1541 mve_advance_vpt(env); \ 1542 } 1543 1544 #define DO_VSHLL_ALL(OP, TOP) \ 1545 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 1546 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 1547 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 1548 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 1549 1550 DO_VSHLL_ALL(vshllb, false) 1551 DO_VSHLL_ALL(vshllt, true) 1552 1553 /* 1554 * Narrowing right shifts, taking a double sized input, shifting it 1555 * and putting the result in either the top or bottom half of the output. 1556 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 1557 */ 1558 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1559 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1560 void *vm, uint32_t shift) \ 1561 { \ 1562 LTYPE *m = vm; \ 1563 TYPE *d = vd; \ 1564 uint16_t mask = mve_element_mask(env); \ 1565 unsigned le; \ 1566 mask >>= ESIZE * TOP; \ 1567 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1568 TYPE r = FN(m[H##LESIZE(le)], shift); \ 1569 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1570 } \ 1571 mve_advance_vpt(env); \ 1572 } 1573 1574 #define DO_VSHRN_ALL(OP, FN) \ 1575 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 1576 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 1577 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 1578 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 1579 1580 static inline uint64_t do_urshr(uint64_t x, unsigned sh) 1581 { 1582 if (likely(sh < 64)) { 1583 return (x >> sh) + ((x >> (sh - 1)) & 1); 1584 } else if (sh == 64) { 1585 return x >> 63; 1586 } else { 1587 return 0; 1588 } 1589 } 1590 1591 static inline int64_t do_srshr(int64_t x, unsigned sh) 1592 { 1593 if (likely(sh < 64)) { 1594 return (x >> sh) + ((x >> (sh - 1)) & 1); 1595 } else { 1596 /* Rounding the sign bit always produces 0. */ 1597 return 0; 1598 } 1599 } 1600 1601 DO_VSHRN_ALL(vshrn, DO_SHR) 1602 DO_VSHRN_ALL(vrshrn, do_urshr) 1603 1604 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 1605 bool *satp) 1606 { 1607 if (val > max) { 1608 *satp = true; 1609 return max; 1610 } else if (val < min) { 1611 *satp = true; 1612 return min; 1613 } else { 1614 return val; 1615 } 1616 } 1617 1618 /* Saturating narrowing right shifts */ 1619 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1620 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1621 void *vm, uint32_t shift) \ 1622 { \ 1623 LTYPE *m = vm; \ 1624 TYPE *d = vd; \ 1625 uint16_t mask = mve_element_mask(env); \ 1626 bool qc = false; \ 1627 unsigned le; \ 1628 mask >>= ESIZE * TOP; \ 1629 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1630 bool sat = false; \ 1631 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 1632 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1633 qc |= sat & mask & 1; \ 1634 } \ 1635 if (qc) { \ 1636 env->vfp.qc[0] = qc; \ 1637 } \ 1638 mve_advance_vpt(env); \ 1639 } 1640 1641 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 1642 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 1643 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 1644 1645 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 1646 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 1647 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 1648 1649 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 1650 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 1651 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 1652 1653 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 1654 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 1655 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 1656 1657 #define DO_SHRN_SB(N, M, SATP) \ 1658 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 1659 #define DO_SHRN_UB(N, M, SATP) \ 1660 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1661 #define DO_SHRUN_B(N, M, SATP) \ 1662 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1663 1664 #define DO_SHRN_SH(N, M, SATP) \ 1665 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 1666 #define DO_SHRN_UH(N, M, SATP) \ 1667 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1668 #define DO_SHRUN_H(N, M, SATP) \ 1669 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1670 1671 #define DO_RSHRN_SB(N, M, SATP) \ 1672 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 1673 #define DO_RSHRN_UB(N, M, SATP) \ 1674 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 1675 #define DO_RSHRUN_B(N, M, SATP) \ 1676 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 1677 1678 #define DO_RSHRN_SH(N, M, SATP) \ 1679 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 1680 #define DO_RSHRN_UH(N, M, SATP) \ 1681 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 1682 #define DO_RSHRUN_H(N, M, SATP) \ 1683 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 1684 1685 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 1686 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 1687 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 1688 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 1689 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 1690 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 1691 1692 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 1693 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 1694 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 1695 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 1696 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 1697 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 1698 1699 #define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 1700 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 1701 { \ 1702 LTYPE *m = vm; \ 1703 TYPE *d = vd; \ 1704 uint16_t mask = mve_element_mask(env); \ 1705 unsigned le; \ 1706 mask >>= ESIZE * TOP; \ 1707 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1708 mergemask(&d[H##ESIZE(le * 2 + TOP)], \ 1709 m[H##LESIZE(le)], mask); \ 1710 } \ 1711 mve_advance_vpt(env); \ 1712 } 1713 1714 DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t) 1715 DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t) 1716 DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t) 1717 DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t) 1718 1719 #define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1720 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 1721 { \ 1722 LTYPE *m = vm; \ 1723 TYPE *d = vd; \ 1724 uint16_t mask = mve_element_mask(env); \ 1725 bool qc = false; \ 1726 unsigned le; \ 1727 mask >>= ESIZE * TOP; \ 1728 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1729 bool sat = false; \ 1730 TYPE r = FN(m[H##LESIZE(le)], &sat); \ 1731 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1732 qc |= sat & mask & 1; \ 1733 } \ 1734 if (qc) { \ 1735 env->vfp.qc[0] = qc; \ 1736 } \ 1737 mve_advance_vpt(env); \ 1738 } 1739 1740 #define DO_VMOVN_SAT_UB(BOP, TOP, FN) \ 1741 DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 1742 DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 1743 1744 #define DO_VMOVN_SAT_UH(BOP, TOP, FN) \ 1745 DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 1746 DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 1747 1748 #define DO_VMOVN_SAT_SB(BOP, TOP, FN) \ 1749 DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 1750 DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 1751 1752 #define DO_VMOVN_SAT_SH(BOP, TOP, FN) \ 1753 DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 1754 DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 1755 1756 #define DO_VQMOVN_SB(N, SATP) \ 1757 do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP) 1758 #define DO_VQMOVN_UB(N, SATP) \ 1759 do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP) 1760 #define DO_VQMOVUN_B(N, SATP) \ 1761 do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP) 1762 1763 #define DO_VQMOVN_SH(N, SATP) \ 1764 do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP) 1765 #define DO_VQMOVN_UH(N, SATP) \ 1766 do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP) 1767 #define DO_VQMOVUN_H(N, SATP) \ 1768 do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP) 1769 1770 DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB) 1771 DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH) 1772 DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB) 1773 DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH) 1774 DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B) 1775 DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H) 1776 1777 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 1778 uint32_t shift) 1779 { 1780 uint32_t *d = vd; 1781 uint16_t mask = mve_element_mask(env); 1782 unsigned e; 1783 uint32_t r; 1784 1785 /* 1786 * For each 32-bit element, we shift it left, bringing in the 1787 * low 'shift' bits of rdm at the bottom. Bits shifted out at 1788 * the top become the new rdm, if the predicate mask permits. 1789 * The final rdm value is returned to update the register. 1790 * shift == 0 here means "shift by 32 bits". 1791 */ 1792 if (shift == 0) { 1793 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1794 r = rdm; 1795 if (mask & 1) { 1796 rdm = d[H4(e)]; 1797 } 1798 mergemask(&d[H4(e)], r, mask); 1799 } 1800 } else { 1801 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 1802 1803 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1804 r = (d[H4(e)] << shift) | (rdm & shiftmask); 1805 if (mask & 1) { 1806 rdm = d[H4(e)] >> (32 - shift); 1807 } 1808 mergemask(&d[H4(e)], r, mask); 1809 } 1810 } 1811 mve_advance_vpt(env); 1812 return rdm; 1813 } 1814 1815 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 1816 { 1817 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 1818 } 1819 1820 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 1821 { 1822 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 1823 } 1824 1825 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 1826 { 1827 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 1828 } 1829 1830 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 1831 { 1832 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 1833 } 1834 1835 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 1836 { 1837 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 1838 } 1839 1840 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 1841 { 1842 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 1843 } 1844 1845 /* Operate on 64-bit values, but saturate at 48 bits */ 1846 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 1847 bool round, uint32_t *sat) 1848 { 1849 int64_t val, extval; 1850 1851 if (shift <= -48) { 1852 /* Rounding the sign bit always produces 0. */ 1853 if (round) { 1854 return 0; 1855 } 1856 return src >> 63; 1857 } else if (shift < 0) { 1858 if (round) { 1859 src >>= -shift - 1; 1860 val = (src >> 1) + (src & 1); 1861 } else { 1862 val = src >> -shift; 1863 } 1864 extval = sextract64(val, 0, 48); 1865 if (!sat || val == extval) { 1866 return extval; 1867 } 1868 } else if (shift < 48) { 1869 int64_t extval = sextract64(src << shift, 0, 48); 1870 if (!sat || src == (extval >> shift)) { 1871 return extval; 1872 } 1873 } else if (!sat || src == 0) { 1874 return 0; 1875 } 1876 1877 *sat = 1; 1878 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 1879 } 1880 1881 /* Operate on 64-bit values, but saturate at 48 bits */ 1882 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 1883 bool round, uint32_t *sat) 1884 { 1885 uint64_t val, extval; 1886 1887 if (shift <= -(48 + round)) { 1888 return 0; 1889 } else if (shift < 0) { 1890 if (round) { 1891 val = src >> (-shift - 1); 1892 val = (val >> 1) + (val & 1); 1893 } else { 1894 val = src >> -shift; 1895 } 1896 extval = extract64(val, 0, 48); 1897 if (!sat || val == extval) { 1898 return extval; 1899 } 1900 } else if (shift < 48) { 1901 uint64_t extval = extract64(src << shift, 0, 48); 1902 if (!sat || src == (extval >> shift)) { 1903 return extval; 1904 } 1905 } else if (!sat || src == 0) { 1906 return 0; 1907 } 1908 1909 *sat = 1; 1910 return MAKE_64BIT_MASK(0, 48); 1911 } 1912 1913 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 1914 { 1915 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 1916 } 1917 1918 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 1919 { 1920 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 1921 } 1922 1923 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 1924 { 1925 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 1926 } 1927 1928 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 1929 { 1930 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 1931 } 1932 1933 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 1934 { 1935 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 1936 } 1937 1938 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 1939 { 1940 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 1941 } 1942 1943 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \ 1944 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 1945 uint32_t offset, uint32_t imm) \ 1946 { \ 1947 TYPE *d = vd; \ 1948 uint16_t mask = mve_element_mask(env); \ 1949 unsigned e; \ 1950 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1951 mergemask(&d[H##ESIZE(e)], offset, mask); \ 1952 offset = FN(offset, imm); \ 1953 } \ 1954 mve_advance_vpt(env); \ 1955 return offset; \ 1956 } 1957 1958 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ 1959 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 1960 uint32_t offset, uint32_t wrap, \ 1961 uint32_t imm) \ 1962 { \ 1963 TYPE *d = vd; \ 1964 uint16_t mask = mve_element_mask(env); \ 1965 unsigned e; \ 1966 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1967 mergemask(&d[H##ESIZE(e)], offset, mask); \ 1968 offset = FN(offset, wrap, imm); \ 1969 } \ 1970 mve_advance_vpt(env); \ 1971 return offset; \ 1972 } 1973 1974 #define DO_VIDUP_ALL(OP, FN) \ 1975 DO_VIDUP(OP##b, 1, int8_t, FN) \ 1976 DO_VIDUP(OP##h, 2, int16_t, FN) \ 1977 DO_VIDUP(OP##w, 4, int32_t, FN) 1978 1979 #define DO_VIWDUP_ALL(OP, FN) \ 1980 DO_VIWDUP(OP##b, 1, int8_t, FN) \ 1981 DO_VIWDUP(OP##h, 2, int16_t, FN) \ 1982 DO_VIWDUP(OP##w, 4, int32_t, FN) 1983 1984 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 1985 { 1986 offset += imm; 1987 if (offset == wrap) { 1988 offset = 0; 1989 } 1990 return offset; 1991 } 1992 1993 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 1994 { 1995 if (offset == 0) { 1996 offset = wrap; 1997 } 1998 offset -= imm; 1999 return offset; 2000 } 2001 2002 DO_VIDUP_ALL(vidup, DO_ADD) 2003 DO_VIWDUP_ALL(viwdup, do_add_wrap) 2004 DO_VIWDUP_ALL(vdwdup, do_sub_wrap) 2005 2006 /* 2007 * Vector comparison. 2008 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. 2009 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. 2010 * P0 bits otherwise are updated with the results of the comparisons. 2011 * We must also keep unchanged the MASK fields at the top of v7m.vpr. 2012 */ 2013 #define DO_VCMP(OP, ESIZE, TYPE, FN) \ 2014 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 2015 { \ 2016 TYPE *n = vn, *m = vm; \ 2017 uint16_t mask = mve_element_mask(env); \ 2018 uint16_t eci_mask = mve_eci_mask(env); \ 2019 uint16_t beatpred = 0; \ 2020 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2021 unsigned e; \ 2022 for (e = 0; e < 16 / ESIZE; e++) { \ 2023 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ 2024 /* Comparison sets 0/1 bits for each byte in the element */ \ 2025 beatpred |= r * emask; \ 2026 emask <<= ESIZE; \ 2027 } \ 2028 beatpred &= mask; \ 2029 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2030 (beatpred & eci_mask); \ 2031 mve_advance_vpt(env); \ 2032 } 2033 2034 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ 2035 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 2036 uint32_t rm) \ 2037 { \ 2038 TYPE *n = vn; \ 2039 uint16_t mask = mve_element_mask(env); \ 2040 uint16_t eci_mask = mve_eci_mask(env); \ 2041 uint16_t beatpred = 0; \ 2042 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2043 unsigned e; \ 2044 for (e = 0; e < 16 / ESIZE; e++) { \ 2045 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \ 2046 /* Comparison sets 0/1 bits for each byte in the element */ \ 2047 beatpred |= r * emask; \ 2048 emask <<= ESIZE; \ 2049 } \ 2050 beatpred &= mask; \ 2051 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2052 (beatpred & eci_mask); \ 2053 mve_advance_vpt(env); \ 2054 } 2055 2056 #define DO_VCMP_S(OP, FN) \ 2057 DO_VCMP(OP##b, 1, int8_t, FN) \ 2058 DO_VCMP(OP##h, 2, int16_t, FN) \ 2059 DO_VCMP(OP##w, 4, int32_t, FN) \ 2060 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ 2061 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ 2062 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) 2063 2064 #define DO_VCMP_U(OP, FN) \ 2065 DO_VCMP(OP##b, 1, uint8_t, FN) \ 2066 DO_VCMP(OP##h, 2, uint16_t, FN) \ 2067 DO_VCMP(OP##w, 4, uint32_t, FN) \ 2068 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ 2069 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ 2070 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) 2071 2072 #define DO_EQ(N, M) ((N) == (M)) 2073 #define DO_NE(N, M) ((N) != (M)) 2074 #define DO_EQ(N, M) ((N) == (M)) 2075 #define DO_EQ(N, M) ((N) == (M)) 2076 #define DO_GE(N, M) ((N) >= (M)) 2077 #define DO_LT(N, M) ((N) < (M)) 2078 #define DO_GT(N, M) ((N) > (M)) 2079 #define DO_LE(N, M) ((N) <= (M)) 2080 2081 DO_VCMP_U(vcmpeq, DO_EQ) 2082 DO_VCMP_U(vcmpne, DO_NE) 2083 DO_VCMP_U(vcmpcs, DO_GE) 2084 DO_VCMP_U(vcmphi, DO_GT) 2085 DO_VCMP_S(vcmpge, DO_GE) 2086 DO_VCMP_S(vcmplt, DO_LT) 2087 DO_VCMP_S(vcmpgt, DO_GT) 2088 DO_VCMP_S(vcmple, DO_LE) 2089 2090 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) 2091 { 2092 /* 2093 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n] 2094 * but note that whether bytes are written to Qd is still subject 2095 * to (all forms of) predication in the usual way. 2096 */ 2097 uint64_t *d = vd, *n = vn, *m = vm; 2098 uint16_t mask = mve_element_mask(env); 2099 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 2100 unsigned e; 2101 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) { 2102 uint64_t r = m[H8(e)]; 2103 mergemask(&r, n[H8(e)], p0); 2104 mergemask(&d[H8(e)], r, mask); 2105 } 2106 mve_advance_vpt(env); 2107 } 2108