1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/exec-all.h" 27 #include "tcg/tcg.h" 28 29 static uint16_t mve_eci_mask(CPUARMState *env) 30 { 31 /* 32 * Return the mask of which elements in the MVE vector correspond 33 * to beats being executed. The mask has 1 bits for executed lanes 34 * and 0 bits where ECI says this beat was already executed. 35 */ 36 int eci; 37 38 if ((env->condexec_bits & 0xf) != 0) { 39 return 0xffff; 40 } 41 42 eci = env->condexec_bits >> 4; 43 switch (eci) { 44 case ECI_NONE: 45 return 0xffff; 46 case ECI_A0: 47 return 0xfff0; 48 case ECI_A0A1: 49 return 0xff00; 50 case ECI_A0A1A2: 51 case ECI_A0A1A2B0: 52 return 0xf000; 53 default: 54 g_assert_not_reached(); 55 } 56 } 57 58 static uint16_t mve_element_mask(CPUARMState *env) 59 { 60 /* 61 * Return the mask of which elements in the MVE vector should be 62 * updated. This is a combination of multiple things: 63 * (1) by default, we update every lane in the vector 64 * (2) VPT predication stores its state in the VPR register; 65 * (3) low-overhead-branch tail predication will mask out part 66 * the vector on the final iteration of the loop 67 * (4) if EPSR.ECI is set then we must execute only some beats 68 * of the insn 69 * We combine all these into a 16-bit result with the same semantics 70 * as VPR.P0: 0 to mask the lane, 1 if it is active. 71 * 8-bit vector ops will look at all bits of the result; 72 * 16-bit ops will look at bits 0, 2, 4, ...; 73 * 32-bit ops will look at bits 0, 4, 8 and 12. 74 * Compare pseudocode GetCurInstrBeat(), though that only returns 75 * the 4-bit slice of the mask corresponding to a single beat. 76 */ 77 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 78 79 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 80 mask |= 0xff; 81 } 82 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 83 mask |= 0xff00; 84 } 85 86 if (env->v7m.ltpsize < 4 && 87 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 88 /* 89 * Tail predication active, and this is the last loop iteration. 90 * The element size is (1 << ltpsize), and we only want to process 91 * loopcount elements, so we want to retain the least significant 92 * (loopcount * esize) predicate bits and zero out bits above that. 93 */ 94 int masklen = env->regs[14] << env->v7m.ltpsize; 95 assert(masklen <= 16); 96 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 97 mask &= ltpmask; 98 } 99 100 /* 101 * ECI bits indicate which beats are already executed; 102 * we handle this by effectively predicating them out. 103 */ 104 mask &= mve_eci_mask(env); 105 return mask; 106 } 107 108 static void mve_advance_vpt(CPUARMState *env) 109 { 110 /* Advance the VPT and ECI state if necessary */ 111 uint32_t vpr = env->v7m.vpr; 112 unsigned mask01, mask23; 113 uint16_t inv_mask; 114 uint16_t eci_mask = mve_eci_mask(env); 115 116 if ((env->condexec_bits & 0xf) == 0) { 117 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 118 (ECI_A0 << 4) : (ECI_NONE << 4); 119 } 120 121 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 122 /* VPT not enabled, nothing to do */ 123 return; 124 } 125 126 /* Invert P0 bits if needed, but only for beats we actually executed */ 127 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 128 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 129 /* Start by assuming we invert all bits corresponding to executed beats */ 130 inv_mask = eci_mask; 131 if (mask01 <= 8) { 132 /* MASK01 says don't invert low half of P0 */ 133 inv_mask &= ~0xff; 134 } 135 if (mask23 <= 8) { 136 /* MASK23 says don't invert high half of P0 */ 137 inv_mask &= ~0xff00; 138 } 139 vpr ^= inv_mask; 140 /* Only update MASK01 if beat 1 executed */ 141 if (eci_mask & 0xf0) { 142 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 143 } 144 /* Beat 3 always executes, so update MASK23 */ 145 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 146 env->v7m.vpr = vpr; 147 } 148 149 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 150 #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ 151 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 152 { \ 153 TYPE *d = vd; \ 154 uint16_t mask = mve_element_mask(env); \ 155 uint16_t eci_mask = mve_eci_mask(env); \ 156 unsigned b, e; \ 157 /* \ 158 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 159 * beats so we don't care if we update part of the dest and \ 160 * then take an exception. \ 161 */ \ 162 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 163 if (eci_mask & (1 << b)) { \ 164 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 165 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 166 } \ 167 addr += MSIZE; \ 168 } \ 169 mve_advance_vpt(env); \ 170 } 171 172 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ 173 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 174 { \ 175 TYPE *d = vd; \ 176 uint16_t mask = mve_element_mask(env); \ 177 unsigned b, e; \ 178 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 179 if (mask & (1 << b)) { \ 180 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 181 } \ 182 addr += MSIZE; \ 183 } \ 184 mve_advance_vpt(env); \ 185 } 186 187 DO_VLDR(vldrb, 1, ldub, 1, uint8_t) 188 DO_VLDR(vldrh, 2, lduw, 2, uint16_t) 189 DO_VLDR(vldrw, 4, ldl, 4, uint32_t) 190 191 DO_VSTR(vstrb, 1, stb, 1, uint8_t) 192 DO_VSTR(vstrh, 2, stw, 2, uint16_t) 193 DO_VSTR(vstrw, 4, stl, 4, uint32_t) 194 195 DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t) 196 DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t) 197 DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t) 198 DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t) 199 DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t) 200 DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t) 201 202 DO_VSTR(vstrb_h, 1, stb, 2, int16_t) 203 DO_VSTR(vstrb_w, 1, stb, 4, int32_t) 204 DO_VSTR(vstrh_w, 2, stw, 4, int32_t) 205 206 #undef DO_VLDR 207 #undef DO_VSTR 208 209 /* 210 * The mergemask(D, R, M) macro performs the operation "*D = R" but 211 * storing only the bytes which correspond to 1 bits in M, 212 * leaving other bytes in *D unchanged. We use _Generic 213 * to select the correct implementation based on the type of D. 214 */ 215 216 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 217 { 218 if (mask & 1) { 219 *d = r; 220 } 221 } 222 223 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 224 { 225 mergemask_ub((uint8_t *)d, r, mask); 226 } 227 228 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 229 { 230 uint16_t bmask = expand_pred_b_data[mask & 3]; 231 *d = (*d & ~bmask) | (r & bmask); 232 } 233 234 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 235 { 236 mergemask_uh((uint16_t *)d, r, mask); 237 } 238 239 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 240 { 241 uint32_t bmask = expand_pred_b_data[mask & 0xf]; 242 *d = (*d & ~bmask) | (r & bmask); 243 } 244 245 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 246 { 247 mergemask_uw((uint32_t *)d, r, mask); 248 } 249 250 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 251 { 252 uint64_t bmask = expand_pred_b_data[mask & 0xff]; 253 *d = (*d & ~bmask) | (r & bmask); 254 } 255 256 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 257 { 258 mergemask_uq((uint64_t *)d, r, mask); 259 } 260 261 #define mergemask(D, R, M) \ 262 _Generic(D, \ 263 uint8_t *: mergemask_ub, \ 264 int8_t *: mergemask_sb, \ 265 uint16_t *: mergemask_uh, \ 266 int16_t *: mergemask_sh, \ 267 uint32_t *: mergemask_uw, \ 268 int32_t *: mergemask_sw, \ 269 uint64_t *: mergemask_uq, \ 270 int64_t *: mergemask_sq)(D, R, M) 271 272 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 273 { 274 /* 275 * The generated code already replicated an 8 or 16 bit constant 276 * into the 32-bit value, so we only need to write the 32-bit 277 * value to all elements of the Qreg, allowing for predication. 278 */ 279 uint32_t *d = vd; 280 uint16_t mask = mve_element_mask(env); 281 unsigned e; 282 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 283 mergemask(&d[H4(e)], val, mask); 284 } 285 mve_advance_vpt(env); 286 } 287 288 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 289 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 290 { \ 291 TYPE *d = vd, *m = vm; \ 292 uint16_t mask = mve_element_mask(env); \ 293 unsigned e; \ 294 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 295 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 296 } \ 297 mve_advance_vpt(env); \ 298 } 299 300 #define DO_CLS_B(N) (clrsb32(N) - 24) 301 #define DO_CLS_H(N) (clrsb32(N) - 16) 302 303 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 304 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 305 DO_1OP(vclsw, 4, int32_t, clrsb32) 306 307 #define DO_CLZ_B(N) (clz32(N) - 24) 308 #define DO_CLZ_H(N) (clz32(N) - 16) 309 310 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 311 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 312 DO_1OP(vclzw, 4, uint32_t, clz32) 313 314 DO_1OP(vrev16b, 2, uint16_t, bswap16) 315 DO_1OP(vrev32b, 4, uint32_t, bswap32) 316 DO_1OP(vrev32h, 4, uint32_t, hswap32) 317 DO_1OP(vrev64b, 8, uint64_t, bswap64) 318 DO_1OP(vrev64h, 8, uint64_t, hswap64) 319 DO_1OP(vrev64w, 8, uint64_t, wswap64) 320 321 #define DO_NOT(N) (~(N)) 322 323 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 324 325 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 326 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 327 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 328 329 DO_1OP(vabsb, 1, int8_t, DO_ABS) 330 DO_1OP(vabsh, 2, int16_t, DO_ABS) 331 DO_1OP(vabsw, 4, int32_t, DO_ABS) 332 333 /* We can do these 64 bits at a time */ 334 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 335 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 336 337 #define DO_NEG(N) (-(N)) 338 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 339 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 340 341 DO_1OP(vnegb, 1, int8_t, DO_NEG) 342 DO_1OP(vnegh, 2, int16_t, DO_NEG) 343 DO_1OP(vnegw, 4, int32_t, DO_NEG) 344 345 /* We can do these 64 bits at a time */ 346 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 347 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 348 349 /* 350 * 1 operand immediates: Vda is destination and possibly also one source. 351 * All these insns work at 64-bit widths. 352 */ 353 #define DO_1OP_IMM(OP, FN) \ 354 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 355 { \ 356 uint64_t *da = vda; \ 357 uint16_t mask = mve_element_mask(env); \ 358 unsigned e; \ 359 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 360 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 361 } \ 362 mve_advance_vpt(env); \ 363 } 364 365 #define DO_MOVI(N, I) (I) 366 #define DO_ANDI(N, I) ((N) & (I)) 367 #define DO_ORRI(N, I) ((N) | (I)) 368 369 DO_1OP_IMM(vmovi, DO_MOVI) 370 DO_1OP_IMM(vandi, DO_ANDI) 371 DO_1OP_IMM(vorri, DO_ORRI) 372 373 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 374 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 375 void *vd, void *vn, void *vm) \ 376 { \ 377 TYPE *d = vd, *n = vn, *m = vm; \ 378 uint16_t mask = mve_element_mask(env); \ 379 unsigned e; \ 380 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 381 mergemask(&d[H##ESIZE(e)], \ 382 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 383 } \ 384 mve_advance_vpt(env); \ 385 } 386 387 /* provide unsigned 2-op helpers for all sizes */ 388 #define DO_2OP_U(OP, FN) \ 389 DO_2OP(OP##b, 1, uint8_t, FN) \ 390 DO_2OP(OP##h, 2, uint16_t, FN) \ 391 DO_2OP(OP##w, 4, uint32_t, FN) 392 393 /* provide signed 2-op helpers for all sizes */ 394 #define DO_2OP_S(OP, FN) \ 395 DO_2OP(OP##b, 1, int8_t, FN) \ 396 DO_2OP(OP##h, 2, int16_t, FN) \ 397 DO_2OP(OP##w, 4, int32_t, FN) 398 399 /* 400 * "Long" operations where two half-sized inputs (taken from either the 401 * top or the bottom of the input vector) produce a double-width result. 402 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 403 */ 404 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 405 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 406 { \ 407 LTYPE *d = vd; \ 408 TYPE *n = vn, *m = vm; \ 409 uint16_t mask = mve_element_mask(env); \ 410 unsigned le; \ 411 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 412 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 413 m[H##ESIZE(le * 2 + TOP)]); \ 414 mergemask(&d[H##LESIZE(le)], r, mask); \ 415 } \ 416 mve_advance_vpt(env); \ 417 } 418 419 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 420 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 421 { \ 422 TYPE *d = vd, *n = vn, *m = vm; \ 423 uint16_t mask = mve_element_mask(env); \ 424 unsigned e; \ 425 bool qc = false; \ 426 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 427 bool sat = false; \ 428 TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 429 mergemask(&d[H##ESIZE(e)], r, mask); \ 430 qc |= sat & mask & 1; \ 431 } \ 432 if (qc) { \ 433 env->vfp.qc[0] = qc; \ 434 } \ 435 mve_advance_vpt(env); \ 436 } 437 438 /* provide unsigned 2-op helpers for all sizes */ 439 #define DO_2OP_SAT_U(OP, FN) \ 440 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 441 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 442 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 443 444 /* provide signed 2-op helpers for all sizes */ 445 #define DO_2OP_SAT_S(OP, FN) \ 446 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 447 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 448 DO_2OP_SAT(OP##w, 4, int32_t, FN) 449 450 #define DO_AND(N, M) ((N) & (M)) 451 #define DO_BIC(N, M) ((N) & ~(M)) 452 #define DO_ORR(N, M) ((N) | (M)) 453 #define DO_ORN(N, M) ((N) | ~(M)) 454 #define DO_EOR(N, M) ((N) ^ (M)) 455 456 DO_2OP(vand, 8, uint64_t, DO_AND) 457 DO_2OP(vbic, 8, uint64_t, DO_BIC) 458 DO_2OP(vorr, 8, uint64_t, DO_ORR) 459 DO_2OP(vorn, 8, uint64_t, DO_ORN) 460 DO_2OP(veor, 8, uint64_t, DO_EOR) 461 462 #define DO_ADD(N, M) ((N) + (M)) 463 #define DO_SUB(N, M) ((N) - (M)) 464 #define DO_MUL(N, M) ((N) * (M)) 465 466 DO_2OP_U(vadd, DO_ADD) 467 DO_2OP_U(vsub, DO_SUB) 468 DO_2OP_U(vmul, DO_MUL) 469 470 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 471 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 472 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 473 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 474 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 475 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 476 477 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 478 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 479 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 480 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 481 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 482 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 483 484 /* 485 * Polynomial multiply. We can always do this generating 64 bits 486 * of the result at a time, so we don't need to use DO_2OP_L. 487 */ 488 #define VMULLPH_MASK 0x00ff00ff00ff00ffULL 489 #define VMULLPW_MASK 0x0000ffff0000ffffULL 490 #define DO_VMULLPBH(N, M) pmull_h((N) & VMULLPH_MASK, (M) & VMULLPH_MASK) 491 #define DO_VMULLPTH(N, M) DO_VMULLPBH((N) >> 8, (M) >> 8) 492 #define DO_VMULLPBW(N, M) pmull_w((N) & VMULLPW_MASK, (M) & VMULLPW_MASK) 493 #define DO_VMULLPTW(N, M) DO_VMULLPBW((N) >> 16, (M) >> 16) 494 495 DO_2OP(vmullpbh, 8, uint64_t, DO_VMULLPBH) 496 DO_2OP(vmullpth, 8, uint64_t, DO_VMULLPTH) 497 DO_2OP(vmullpbw, 8, uint64_t, DO_VMULLPBW) 498 DO_2OP(vmullptw, 8, uint64_t, DO_VMULLPTW) 499 500 /* 501 * Because the computation type is at least twice as large as required, 502 * these work for both signed and unsigned source types. 503 */ 504 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 505 { 506 return (n * m) >> 8; 507 } 508 509 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 510 { 511 return (n * m) >> 16; 512 } 513 514 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 515 { 516 return (n * m) >> 32; 517 } 518 519 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 520 { 521 return (n * m + (1U << 7)) >> 8; 522 } 523 524 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 525 { 526 return (n * m + (1U << 15)) >> 16; 527 } 528 529 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 530 { 531 return (n * m + (1U << 31)) >> 32; 532 } 533 534 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 535 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 536 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 537 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 538 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 539 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 540 541 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 542 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 543 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 544 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 545 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 546 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 547 548 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 549 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 550 551 DO_2OP_S(vmaxs, DO_MAX) 552 DO_2OP_U(vmaxu, DO_MAX) 553 DO_2OP_S(vmins, DO_MIN) 554 DO_2OP_U(vminu, DO_MIN) 555 556 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 557 558 DO_2OP_S(vabds, DO_ABD) 559 DO_2OP_U(vabdu, DO_ABD) 560 561 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 562 { 563 return ((uint64_t)n + m) >> 1; 564 } 565 566 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 567 { 568 return ((int64_t)n + m) >> 1; 569 } 570 571 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 572 { 573 return ((uint64_t)n - m) >> 1; 574 } 575 576 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 577 { 578 return ((int64_t)n - m) >> 1; 579 } 580 581 DO_2OP_S(vhadds, do_vhadd_s) 582 DO_2OP_U(vhaddu, do_vhadd_u) 583 DO_2OP_S(vhsubs, do_vhsub_s) 584 DO_2OP_U(vhsubu, do_vhsub_u) 585 586 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 587 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 588 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 589 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 590 591 DO_2OP_S(vshls, DO_VSHLS) 592 DO_2OP_U(vshlu, DO_VSHLU) 593 DO_2OP_S(vrshls, DO_VRSHLS) 594 DO_2OP_U(vrshlu, DO_VRSHLU) 595 596 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 597 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 598 599 DO_2OP_S(vrhadds, DO_RHADD_S) 600 DO_2OP_U(vrhaddu, DO_RHADD_U) 601 602 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 603 uint32_t inv, uint32_t carry_in, bool update_flags) 604 { 605 uint16_t mask = mve_element_mask(env); 606 unsigned e; 607 608 /* If any additions trigger, we will update flags. */ 609 if (mask & 0x1111) { 610 update_flags = true; 611 } 612 613 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 614 uint64_t r = carry_in; 615 r += n[H4(e)]; 616 r += m[H4(e)] ^ inv; 617 if (mask & 1) { 618 carry_in = r >> 32; 619 } 620 mergemask(&d[H4(e)], r, mask); 621 } 622 623 if (update_flags) { 624 /* Store C, clear NZV. */ 625 env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK; 626 env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C; 627 } 628 mve_advance_vpt(env); 629 } 630 631 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 632 { 633 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 634 do_vadc(env, vd, vn, vm, 0, carry_in, false); 635 } 636 637 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 638 { 639 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 640 do_vadc(env, vd, vn, vm, -1, carry_in, false); 641 } 642 643 644 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 645 { 646 do_vadc(env, vd, vn, vm, 0, 0, true); 647 } 648 649 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 650 { 651 do_vadc(env, vd, vn, vm, -1, 1, true); 652 } 653 654 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 655 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 656 { \ 657 TYPE *d = vd, *n = vn, *m = vm; \ 658 uint16_t mask = mve_element_mask(env); \ 659 unsigned e; \ 660 TYPE r[16 / ESIZE]; \ 661 /* Calculate all results first to avoid overwriting inputs */ \ 662 for (e = 0; e < 16 / ESIZE; e++) { \ 663 if (!(e & 1)) { \ 664 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 665 } else { \ 666 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 667 } \ 668 } \ 669 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 670 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 671 } \ 672 mve_advance_vpt(env); \ 673 } 674 675 #define DO_VCADD_ALL(OP, FN0, FN1) \ 676 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 677 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 678 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 679 680 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 681 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 682 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 683 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 684 685 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 686 { 687 if (val > max) { 688 *s = true; 689 return max; 690 } else if (val < min) { 691 *s = true; 692 return min; 693 } 694 return val; 695 } 696 697 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 698 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 699 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 700 701 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 702 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 703 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 704 705 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 706 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 707 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 708 709 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 710 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 711 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 712 713 /* 714 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 715 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 716 */ 717 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 718 INT8_MIN, INT8_MAX, s) 719 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 720 INT16_MIN, INT16_MAX, s) 721 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 722 INT32_MIN, INT32_MAX, s) 723 724 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 725 INT8_MIN, INT8_MAX, s) 726 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 727 INT16_MIN, INT16_MAX, s) 728 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 729 INT32_MIN, INT32_MAX, s) 730 731 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 732 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 733 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 734 735 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 736 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 737 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 738 739 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 740 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 741 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 742 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 743 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 744 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 745 746 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 747 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 748 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 749 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 750 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 751 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 752 753 /* 754 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 755 * and friends wanting a uint32_t* sat and our needing a bool*. 756 */ 757 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 758 ({ \ 759 uint32_t su32 = 0; \ 760 typeof(N) r = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 761 if (su32) { \ 762 *satp = true; \ 763 } \ 764 r; \ 765 }) 766 767 #define DO_SQSHL_OP(N, M, satp) \ 768 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 769 #define DO_UQSHL_OP(N, M, satp) \ 770 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 771 #define DO_SQRSHL_OP(N, M, satp) \ 772 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 773 #define DO_UQRSHL_OP(N, M, satp) \ 774 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 775 #define DO_SUQSHL_OP(N, M, satp) \ 776 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 777 778 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 779 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 780 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 781 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 782 783 /* 784 * Multiply add dual returning high half 785 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 786 * whether to add the rounding constant, and the pointer to the 787 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 788 * saturate to twice the input size and return the high half; or 789 * (A * B - C * D) etc for VQDMLSDH. 790 */ 791 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 792 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 793 void *vm) \ 794 { \ 795 TYPE *d = vd, *n = vn, *m = vm; \ 796 uint16_t mask = mve_element_mask(env); \ 797 unsigned e; \ 798 bool qc = false; \ 799 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 800 bool sat = false; \ 801 if ((e & 1) == XCHG) { \ 802 TYPE r = FN(n[H##ESIZE(e)], \ 803 m[H##ESIZE(e - XCHG)], \ 804 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 805 m[H##ESIZE(e + (1 - XCHG))], \ 806 ROUND, &sat); \ 807 mergemask(&d[H##ESIZE(e)], r, mask); \ 808 qc |= sat & mask & 1; \ 809 } \ 810 } \ 811 if (qc) { \ 812 env->vfp.qc[0] = qc; \ 813 } \ 814 mve_advance_vpt(env); \ 815 } 816 817 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 818 int round, bool *sat) 819 { 820 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 821 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 822 } 823 824 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 825 int round, bool *sat) 826 { 827 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 828 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 829 } 830 831 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 832 int round, bool *sat) 833 { 834 int64_t m1 = (int64_t)a * b; 835 int64_t m2 = (int64_t)c * d; 836 int64_t r; 837 /* 838 * Architecturally we should do the entire add, double, round 839 * and then check for saturation. We do three saturating adds, 840 * but we need to be careful about the order. If the first 841 * m1 + m2 saturates then it's impossible for the *2+rc to 842 * bring it back into the non-saturated range. However, if 843 * m1 + m2 is negative then it's possible that doing the doubling 844 * would take the intermediate result below INT64_MAX and the 845 * addition of the rounding constant then brings it back in range. 846 * So we add half the rounding constant before doubling rather 847 * than adding the rounding constant after the doubling. 848 */ 849 if (sadd64_overflow(m1, m2, &r) || 850 sadd64_overflow(r, (round << 30), &r) || 851 sadd64_overflow(r, r, &r)) { 852 *sat = true; 853 return r < 0 ? INT32_MAX : INT32_MIN; 854 } 855 return r >> 32; 856 } 857 858 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 859 int round, bool *sat) 860 { 861 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 862 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 863 } 864 865 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 866 int round, bool *sat) 867 { 868 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 869 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 870 } 871 872 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 873 int round, bool *sat) 874 { 875 int64_t m1 = (int64_t)a * b; 876 int64_t m2 = (int64_t)c * d; 877 int64_t r; 878 /* The same ordering issue as in do_vqdmladh_w applies here too */ 879 if (ssub64_overflow(m1, m2, &r) || 880 sadd64_overflow(r, (round << 30), &r) || 881 sadd64_overflow(r, r, &r)) { 882 *sat = true; 883 return r < 0 ? INT32_MAX : INT32_MIN; 884 } 885 return r >> 32; 886 } 887 888 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 889 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 890 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 891 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 892 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 893 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 894 895 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 896 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 897 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 898 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 899 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 900 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 901 902 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 903 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 904 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 905 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 906 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 907 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 908 909 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 910 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 911 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 912 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 913 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 914 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 915 916 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 917 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 918 uint32_t rm) \ 919 { \ 920 TYPE *d = vd, *n = vn; \ 921 TYPE m = rm; \ 922 uint16_t mask = mve_element_mask(env); \ 923 unsigned e; \ 924 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 925 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 926 } \ 927 mve_advance_vpt(env); \ 928 } 929 930 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 931 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 932 uint32_t rm) \ 933 { \ 934 TYPE *d = vd, *n = vn; \ 935 TYPE m = rm; \ 936 uint16_t mask = mve_element_mask(env); \ 937 unsigned e; \ 938 bool qc = false; \ 939 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 940 bool sat = false; \ 941 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 942 mask); \ 943 qc |= sat & mask & 1; \ 944 } \ 945 if (qc) { \ 946 env->vfp.qc[0] = qc; \ 947 } \ 948 mve_advance_vpt(env); \ 949 } 950 951 /* provide unsigned 2-op scalar helpers for all sizes */ 952 #define DO_2OP_SCALAR_U(OP, FN) \ 953 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 954 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 955 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 956 #define DO_2OP_SCALAR_S(OP, FN) \ 957 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 958 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 959 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 960 961 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 962 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 963 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 964 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 965 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 966 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 967 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 968 969 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 970 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 971 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 972 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 973 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 974 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 975 976 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 977 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 978 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 979 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 980 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 981 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 982 983 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 984 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 985 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 986 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 987 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 988 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 989 990 /* 991 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 992 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 993 * SATMASK specifies which bits of the predicate mask matter for determining 994 * whether to propagate a saturation indication into FPSCR.QC -- for 995 * the 16x16->32 case we must check only the bit corresponding to the T or B 996 * half that we used, but for the 32x32->64 case we propagate if the mask 997 * bit is set for either half. 998 */ 999 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1000 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1001 uint32_t rm) \ 1002 { \ 1003 LTYPE *d = vd; \ 1004 TYPE *n = vn; \ 1005 TYPE m = rm; \ 1006 uint16_t mask = mve_element_mask(env); \ 1007 unsigned le; \ 1008 bool qc = false; \ 1009 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1010 bool sat = false; \ 1011 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 1012 mergemask(&d[H##LESIZE(le)], r, mask); \ 1013 qc |= sat && (mask & SATMASK); \ 1014 } \ 1015 if (qc) { \ 1016 env->vfp.qc[0] = qc; \ 1017 } \ 1018 mve_advance_vpt(env); \ 1019 } 1020 1021 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1022 { 1023 int64_t r = ((int64_t)n * m) * 2; 1024 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1025 } 1026 1027 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1028 { 1029 /* The multiply can't overflow, but the doubling might */ 1030 int64_t r = (int64_t)n * m; 1031 if (r > INT64_MAX / 2) { 1032 *sat = true; 1033 return INT64_MAX; 1034 } else if (r < INT64_MIN / 2) { 1035 *sat = true; 1036 return INT64_MIN; 1037 } else { 1038 return r * 2; 1039 } 1040 } 1041 1042 #define SATMASK16B 1 1043 #define SATMASK16T (1 << 2) 1044 #define SATMASK32 ((1 << 4) | 1) 1045 1046 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1047 do_qdmullh, SATMASK16B) 1048 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1049 do_qdmullw, SATMASK32) 1050 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1051 do_qdmullh, SATMASK16T) 1052 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1053 do_qdmullw, SATMASK32) 1054 1055 /* 1056 * Long saturating ops 1057 */ 1058 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1059 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1060 void *vm) \ 1061 { \ 1062 LTYPE *d = vd; \ 1063 TYPE *n = vn, *m = vm; \ 1064 uint16_t mask = mve_element_mask(env); \ 1065 unsigned le; \ 1066 bool qc = false; \ 1067 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1068 bool sat = false; \ 1069 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1070 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1071 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1072 qc |= sat && (mask & SATMASK); \ 1073 } \ 1074 if (qc) { \ 1075 env->vfp.qc[0] = qc; \ 1076 } \ 1077 mve_advance_vpt(env); \ 1078 } 1079 1080 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1081 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1082 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1083 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1084 1085 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1086 { 1087 m &= 0xff; 1088 if (m == 0) { 1089 return 0; 1090 } 1091 n = revbit8(n); 1092 if (m < 8) { 1093 n >>= 8 - m; 1094 } 1095 return n; 1096 } 1097 1098 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1099 { 1100 m &= 0xff; 1101 if (m == 0) { 1102 return 0; 1103 } 1104 n = revbit16(n); 1105 if (m < 16) { 1106 n >>= 16 - m; 1107 } 1108 return n; 1109 } 1110 1111 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1112 { 1113 m &= 0xff; 1114 if (m == 0) { 1115 return 0; 1116 } 1117 n = revbit32(n); 1118 if (m < 32) { 1119 n >>= 32 - m; 1120 } 1121 return n; 1122 } 1123 1124 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1125 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1126 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1127 1128 /* 1129 * Multiply add long dual accumulate ops. 1130 */ 1131 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1132 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1133 void *vm, uint64_t a) \ 1134 { \ 1135 uint16_t mask = mve_element_mask(env); \ 1136 unsigned e; \ 1137 TYPE *n = vn, *m = vm; \ 1138 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1139 if (mask & 1) { \ 1140 if (e & 1) { \ 1141 a ODDACC \ 1142 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1143 } else { \ 1144 a EVENACC \ 1145 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1146 } \ 1147 } \ 1148 } \ 1149 mve_advance_vpt(env); \ 1150 return a; \ 1151 } 1152 1153 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1154 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1155 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1156 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1157 1158 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1159 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1160 1161 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1162 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1163 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1164 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1165 1166 /* 1167 * Rounding multiply add long dual accumulate high. In the pseudocode 1168 * this is implemented with a 72-bit internal accumulator value of which 1169 * the top 64 bits are returned. We optimize this to avoid having to 1170 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1171 * is squashed back into 64-bits after each beat. 1172 */ 1173 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1174 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1175 void *vm, uint64_t a) \ 1176 { \ 1177 uint16_t mask = mve_element_mask(env); \ 1178 unsigned e; \ 1179 TYPE *n = vn, *m = vm; \ 1180 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1181 if (mask & 1) { \ 1182 LTYPE mul; \ 1183 if (e & 1) { \ 1184 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1185 if (SUB) { \ 1186 mul = -mul; \ 1187 } \ 1188 } else { \ 1189 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1190 } \ 1191 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1192 a += mul; \ 1193 } \ 1194 } \ 1195 mve_advance_vpt(env); \ 1196 return a; \ 1197 } 1198 1199 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1200 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1201 1202 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1203 1204 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1205 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1206 1207 /* Vector add across vector */ 1208 #define DO_VADDV(OP, ESIZE, TYPE) \ 1209 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1210 uint32_t ra) \ 1211 { \ 1212 uint16_t mask = mve_element_mask(env); \ 1213 unsigned e; \ 1214 TYPE *m = vm; \ 1215 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1216 if (mask & 1) { \ 1217 ra += m[H##ESIZE(e)]; \ 1218 } \ 1219 } \ 1220 mve_advance_vpt(env); \ 1221 return ra; \ 1222 } \ 1223 1224 DO_VADDV(vaddvsb, 1, int8_t) 1225 DO_VADDV(vaddvsh, 2, int16_t) 1226 DO_VADDV(vaddvsw, 4, int32_t) 1227 DO_VADDV(vaddvub, 1, uint8_t) 1228 DO_VADDV(vaddvuh, 2, uint16_t) 1229 DO_VADDV(vaddvuw, 4, uint32_t) 1230 1231 #define DO_VADDLV(OP, TYPE, LTYPE) \ 1232 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1233 uint64_t ra) \ 1234 { \ 1235 uint16_t mask = mve_element_mask(env); \ 1236 unsigned e; \ 1237 TYPE *m = vm; \ 1238 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1239 if (mask & 1) { \ 1240 ra += (LTYPE)m[H4(e)]; \ 1241 } \ 1242 } \ 1243 mve_advance_vpt(env); \ 1244 return ra; \ 1245 } \ 1246 1247 DO_VADDLV(vaddlv_s, int32_t, int64_t) 1248 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 1249 1250 /* Shifts by immediate */ 1251 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 1252 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1253 void *vm, uint32_t shift) \ 1254 { \ 1255 TYPE *d = vd, *m = vm; \ 1256 uint16_t mask = mve_element_mask(env); \ 1257 unsigned e; \ 1258 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1259 mergemask(&d[H##ESIZE(e)], \ 1260 FN(m[H##ESIZE(e)], shift), mask); \ 1261 } \ 1262 mve_advance_vpt(env); \ 1263 } 1264 1265 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 1266 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1267 void *vm, uint32_t shift) \ 1268 { \ 1269 TYPE *d = vd, *m = vm; \ 1270 uint16_t mask = mve_element_mask(env); \ 1271 unsigned e; \ 1272 bool qc = false; \ 1273 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1274 bool sat = false; \ 1275 mergemask(&d[H##ESIZE(e)], \ 1276 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 1277 qc |= sat & mask & 1; \ 1278 } \ 1279 if (qc) { \ 1280 env->vfp.qc[0] = qc; \ 1281 } \ 1282 mve_advance_vpt(env); \ 1283 } 1284 1285 /* provide unsigned 2-op shift helpers for all sizes */ 1286 #define DO_2SHIFT_U(OP, FN) \ 1287 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 1288 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 1289 DO_2SHIFT(OP##w, 4, uint32_t, FN) 1290 #define DO_2SHIFT_S(OP, FN) \ 1291 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 1292 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 1293 DO_2SHIFT(OP##w, 4, int32_t, FN) 1294 1295 #define DO_2SHIFT_SAT_U(OP, FN) \ 1296 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 1297 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 1298 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 1299 #define DO_2SHIFT_SAT_S(OP, FN) \ 1300 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 1301 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 1302 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 1303 1304 DO_2SHIFT_U(vshli_u, DO_VSHLU) 1305 DO_2SHIFT_S(vshli_s, DO_VSHLS) 1306 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 1307 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 1308 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 1309 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 1310 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 1311 1312 /* Shift-and-insert; we always work with 64 bits at a time */ 1313 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 1314 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1315 void *vm, uint32_t shift) \ 1316 { \ 1317 uint64_t *d = vd, *m = vm; \ 1318 uint16_t mask; \ 1319 uint64_t shiftmask; \ 1320 unsigned e; \ 1321 if (shift == ESIZE * 8) { \ 1322 /* \ 1323 * Only VSRI can shift by <dt>; it should mean "don't \ 1324 * update the destination". The generic logic can't handle \ 1325 * this because it would try to shift by an out-of-range \ 1326 * amount, so special case it here. \ 1327 */ \ 1328 goto done; \ 1329 } \ 1330 assert(shift < ESIZE * 8); \ 1331 mask = mve_element_mask(env); \ 1332 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 1333 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 1334 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 1335 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 1336 (d[H8(e)] & ~shiftmask); \ 1337 mergemask(&d[H8(e)], r, mask); \ 1338 } \ 1339 done: \ 1340 mve_advance_vpt(env); \ 1341 } 1342 1343 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 1344 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 1345 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 1346 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 1347 1348 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 1349 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 1350 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 1351 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 1352 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 1353 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 1354 1355 /* 1356 * Long shifts taking half-sized inputs from top or bottom of the input 1357 * vector and producing a double-width result. ESIZE, TYPE are for 1358 * the input, and LESIZE, LTYPE for the output. 1359 * Unlike the normal shift helpers, we do not handle negative shift counts, 1360 * because the long shift is strictly left-only. 1361 */ 1362 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 1363 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1364 void *vm, uint32_t shift) \ 1365 { \ 1366 LTYPE *d = vd; \ 1367 TYPE *m = vm; \ 1368 uint16_t mask = mve_element_mask(env); \ 1369 unsigned le; \ 1370 assert(shift <= 16); \ 1371 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1372 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 1373 mergemask(&d[H##LESIZE(le)], r, mask); \ 1374 } \ 1375 mve_advance_vpt(env); \ 1376 } 1377 1378 #define DO_VSHLL_ALL(OP, TOP) \ 1379 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 1380 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 1381 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 1382 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 1383 1384 DO_VSHLL_ALL(vshllb, false) 1385 DO_VSHLL_ALL(vshllt, true) 1386 1387 /* 1388 * Narrowing right shifts, taking a double sized input, shifting it 1389 * and putting the result in either the top or bottom half of the output. 1390 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 1391 */ 1392 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1393 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1394 void *vm, uint32_t shift) \ 1395 { \ 1396 LTYPE *m = vm; \ 1397 TYPE *d = vd; \ 1398 uint16_t mask = mve_element_mask(env); \ 1399 unsigned le; \ 1400 mask >>= ESIZE * TOP; \ 1401 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1402 TYPE r = FN(m[H##LESIZE(le)], shift); \ 1403 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1404 } \ 1405 mve_advance_vpt(env); \ 1406 } 1407 1408 #define DO_VSHRN_ALL(OP, FN) \ 1409 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 1410 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 1411 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 1412 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 1413 1414 static inline uint64_t do_urshr(uint64_t x, unsigned sh) 1415 { 1416 if (likely(sh < 64)) { 1417 return (x >> sh) + ((x >> (sh - 1)) & 1); 1418 } else if (sh == 64) { 1419 return x >> 63; 1420 } else { 1421 return 0; 1422 } 1423 } 1424 1425 static inline int64_t do_srshr(int64_t x, unsigned sh) 1426 { 1427 if (likely(sh < 64)) { 1428 return (x >> sh) + ((x >> (sh - 1)) & 1); 1429 } else { 1430 /* Rounding the sign bit always produces 0. */ 1431 return 0; 1432 } 1433 } 1434 1435 DO_VSHRN_ALL(vshrn, DO_SHR) 1436 DO_VSHRN_ALL(vrshrn, do_urshr) 1437 1438 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 1439 bool *satp) 1440 { 1441 if (val > max) { 1442 *satp = true; 1443 return max; 1444 } else if (val < min) { 1445 *satp = true; 1446 return min; 1447 } else { 1448 return val; 1449 } 1450 } 1451 1452 /* Saturating narrowing right shifts */ 1453 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1454 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1455 void *vm, uint32_t shift) \ 1456 { \ 1457 LTYPE *m = vm; \ 1458 TYPE *d = vd; \ 1459 uint16_t mask = mve_element_mask(env); \ 1460 bool qc = false; \ 1461 unsigned le; \ 1462 mask >>= ESIZE * TOP; \ 1463 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1464 bool sat = false; \ 1465 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 1466 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1467 qc |= sat & mask & 1; \ 1468 } \ 1469 if (qc) { \ 1470 env->vfp.qc[0] = qc; \ 1471 } \ 1472 mve_advance_vpt(env); \ 1473 } 1474 1475 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 1476 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 1477 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 1478 1479 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 1480 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 1481 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 1482 1483 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 1484 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 1485 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 1486 1487 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 1488 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 1489 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 1490 1491 #define DO_SHRN_SB(N, M, SATP) \ 1492 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 1493 #define DO_SHRN_UB(N, M, SATP) \ 1494 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1495 #define DO_SHRUN_B(N, M, SATP) \ 1496 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1497 1498 #define DO_SHRN_SH(N, M, SATP) \ 1499 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 1500 #define DO_SHRN_UH(N, M, SATP) \ 1501 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1502 #define DO_SHRUN_H(N, M, SATP) \ 1503 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1504 1505 #define DO_RSHRN_SB(N, M, SATP) \ 1506 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 1507 #define DO_RSHRN_UB(N, M, SATP) \ 1508 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 1509 #define DO_RSHRUN_B(N, M, SATP) \ 1510 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 1511 1512 #define DO_RSHRN_SH(N, M, SATP) \ 1513 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 1514 #define DO_RSHRN_UH(N, M, SATP) \ 1515 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 1516 #define DO_RSHRUN_H(N, M, SATP) \ 1517 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 1518 1519 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 1520 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 1521 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 1522 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 1523 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 1524 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 1525 1526 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 1527 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 1528 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 1529 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 1530 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 1531 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 1532 1533 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 1534 uint32_t shift) 1535 { 1536 uint32_t *d = vd; 1537 uint16_t mask = mve_element_mask(env); 1538 unsigned e; 1539 uint32_t r; 1540 1541 /* 1542 * For each 32-bit element, we shift it left, bringing in the 1543 * low 'shift' bits of rdm at the bottom. Bits shifted out at 1544 * the top become the new rdm, if the predicate mask permits. 1545 * The final rdm value is returned to update the register. 1546 * shift == 0 here means "shift by 32 bits". 1547 */ 1548 if (shift == 0) { 1549 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1550 r = rdm; 1551 if (mask & 1) { 1552 rdm = d[H4(e)]; 1553 } 1554 mergemask(&d[H4(e)], r, mask); 1555 } 1556 } else { 1557 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 1558 1559 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1560 r = (d[H4(e)] << shift) | (rdm & shiftmask); 1561 if (mask & 1) { 1562 rdm = d[H4(e)] >> (32 - shift); 1563 } 1564 mergemask(&d[H4(e)], r, mask); 1565 } 1566 } 1567 mve_advance_vpt(env); 1568 return rdm; 1569 } 1570 1571 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 1572 { 1573 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 1574 } 1575 1576 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 1577 { 1578 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 1579 } 1580 1581 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 1582 { 1583 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 1584 } 1585 1586 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 1587 { 1588 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 1589 } 1590 1591 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 1592 { 1593 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 1594 } 1595 1596 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 1597 { 1598 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 1599 } 1600 1601 /* Operate on 64-bit values, but saturate at 48 bits */ 1602 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 1603 bool round, uint32_t *sat) 1604 { 1605 int64_t val, extval; 1606 1607 if (shift <= -48) { 1608 /* Rounding the sign bit always produces 0. */ 1609 if (round) { 1610 return 0; 1611 } 1612 return src >> 63; 1613 } else if (shift < 0) { 1614 if (round) { 1615 src >>= -shift - 1; 1616 val = (src >> 1) + (src & 1); 1617 } else { 1618 val = src >> -shift; 1619 } 1620 extval = sextract64(val, 0, 48); 1621 if (!sat || val == extval) { 1622 return extval; 1623 } 1624 } else if (shift < 48) { 1625 int64_t extval = sextract64(src << shift, 0, 48); 1626 if (!sat || src == (extval >> shift)) { 1627 return extval; 1628 } 1629 } else if (!sat || src == 0) { 1630 return 0; 1631 } 1632 1633 *sat = 1; 1634 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 1635 } 1636 1637 /* Operate on 64-bit values, but saturate at 48 bits */ 1638 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 1639 bool round, uint32_t *sat) 1640 { 1641 uint64_t val, extval; 1642 1643 if (shift <= -(48 + round)) { 1644 return 0; 1645 } else if (shift < 0) { 1646 if (round) { 1647 val = src >> (-shift - 1); 1648 val = (val >> 1) + (val & 1); 1649 } else { 1650 val = src >> -shift; 1651 } 1652 extval = extract64(val, 0, 48); 1653 if (!sat || val == extval) { 1654 return extval; 1655 } 1656 } else if (shift < 48) { 1657 uint64_t extval = extract64(src << shift, 0, 48); 1658 if (!sat || src == (extval >> shift)) { 1659 return extval; 1660 } 1661 } else if (!sat || src == 0) { 1662 return 0; 1663 } 1664 1665 *sat = 1; 1666 return MAKE_64BIT_MASK(0, 48); 1667 } 1668 1669 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 1670 { 1671 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 1672 } 1673 1674 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 1675 { 1676 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 1677 } 1678 1679 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 1680 { 1681 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 1682 } 1683 1684 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 1685 { 1686 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 1687 } 1688 1689 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 1690 { 1691 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 1692 } 1693 1694 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 1695 { 1696 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 1697 } 1698 1699 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \ 1700 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 1701 uint32_t offset, uint32_t imm) \ 1702 { \ 1703 TYPE *d = vd; \ 1704 uint16_t mask = mve_element_mask(env); \ 1705 unsigned e; \ 1706 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1707 mergemask(&d[H##ESIZE(e)], offset, mask); \ 1708 offset = FN(offset, imm); \ 1709 } \ 1710 mve_advance_vpt(env); \ 1711 return offset; \ 1712 } 1713 1714 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ 1715 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 1716 uint32_t offset, uint32_t wrap, \ 1717 uint32_t imm) \ 1718 { \ 1719 TYPE *d = vd; \ 1720 uint16_t mask = mve_element_mask(env); \ 1721 unsigned e; \ 1722 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1723 mergemask(&d[H##ESIZE(e)], offset, mask); \ 1724 offset = FN(offset, wrap, imm); \ 1725 } \ 1726 mve_advance_vpt(env); \ 1727 return offset; \ 1728 } 1729 1730 #define DO_VIDUP_ALL(OP, FN) \ 1731 DO_VIDUP(OP##b, 1, int8_t, FN) \ 1732 DO_VIDUP(OP##h, 2, int16_t, FN) \ 1733 DO_VIDUP(OP##w, 4, int32_t, FN) 1734 1735 #define DO_VIWDUP_ALL(OP, FN) \ 1736 DO_VIWDUP(OP##b, 1, int8_t, FN) \ 1737 DO_VIWDUP(OP##h, 2, int16_t, FN) \ 1738 DO_VIWDUP(OP##w, 4, int32_t, FN) 1739 1740 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 1741 { 1742 offset += imm; 1743 if (offset == wrap) { 1744 offset = 0; 1745 } 1746 return offset; 1747 } 1748 1749 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 1750 { 1751 if (offset == 0) { 1752 offset = wrap; 1753 } 1754 offset -= imm; 1755 return offset; 1756 } 1757 1758 DO_VIDUP_ALL(vidup, DO_ADD) 1759 DO_VIWDUP_ALL(viwdup, do_add_wrap) 1760 DO_VIWDUP_ALL(vdwdup, do_sub_wrap) 1761 1762 /* 1763 * Vector comparison. 1764 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. 1765 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. 1766 * P0 bits otherwise are updated with the results of the comparisons. 1767 * We must also keep unchanged the MASK fields at the top of v7m.vpr. 1768 */ 1769 #define DO_VCMP(OP, ESIZE, TYPE, FN) \ 1770 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 1771 { \ 1772 TYPE *n = vn, *m = vm; \ 1773 uint16_t mask = mve_element_mask(env); \ 1774 uint16_t eci_mask = mve_eci_mask(env); \ 1775 uint16_t beatpred = 0; \ 1776 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 1777 unsigned e; \ 1778 for (e = 0; e < 16 / ESIZE; e++) { \ 1779 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ 1780 /* Comparison sets 0/1 bits for each byte in the element */ \ 1781 beatpred |= r * emask; \ 1782 emask <<= ESIZE; \ 1783 } \ 1784 beatpred &= mask; \ 1785 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 1786 (beatpred & eci_mask); \ 1787 mve_advance_vpt(env); \ 1788 } 1789 1790 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ 1791 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1792 uint32_t rm) \ 1793 { \ 1794 TYPE *n = vn; \ 1795 uint16_t mask = mve_element_mask(env); \ 1796 uint16_t eci_mask = mve_eci_mask(env); \ 1797 uint16_t beatpred = 0; \ 1798 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 1799 unsigned e; \ 1800 for (e = 0; e < 16 / ESIZE; e++) { \ 1801 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \ 1802 /* Comparison sets 0/1 bits for each byte in the element */ \ 1803 beatpred |= r * emask; \ 1804 emask <<= ESIZE; \ 1805 } \ 1806 beatpred &= mask; \ 1807 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 1808 (beatpred & eci_mask); \ 1809 mve_advance_vpt(env); \ 1810 } 1811 1812 #define DO_VCMP_S(OP, FN) \ 1813 DO_VCMP(OP##b, 1, int8_t, FN) \ 1814 DO_VCMP(OP##h, 2, int16_t, FN) \ 1815 DO_VCMP(OP##w, 4, int32_t, FN) \ 1816 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ 1817 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ 1818 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) 1819 1820 #define DO_VCMP_U(OP, FN) \ 1821 DO_VCMP(OP##b, 1, uint8_t, FN) \ 1822 DO_VCMP(OP##h, 2, uint16_t, FN) \ 1823 DO_VCMP(OP##w, 4, uint32_t, FN) \ 1824 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ 1825 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ 1826 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) 1827 1828 #define DO_EQ(N, M) ((N) == (M)) 1829 #define DO_NE(N, M) ((N) != (M)) 1830 #define DO_EQ(N, M) ((N) == (M)) 1831 #define DO_EQ(N, M) ((N) == (M)) 1832 #define DO_GE(N, M) ((N) >= (M)) 1833 #define DO_LT(N, M) ((N) < (M)) 1834 #define DO_GT(N, M) ((N) > (M)) 1835 #define DO_LE(N, M) ((N) <= (M)) 1836 1837 DO_VCMP_U(vcmpeq, DO_EQ) 1838 DO_VCMP_U(vcmpne, DO_NE) 1839 DO_VCMP_U(vcmpcs, DO_GE) 1840 DO_VCMP_U(vcmphi, DO_GT) 1841 DO_VCMP_S(vcmpge, DO_GE) 1842 DO_VCMP_S(vcmplt, DO_LT) 1843 DO_VCMP_S(vcmpgt, DO_GT) 1844 DO_VCMP_S(vcmple, DO_LE) 1845 1846 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) 1847 { 1848 /* 1849 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n] 1850 * but note that whether bytes are written to Qd is still subject 1851 * to (all forms of) predication in the usual way. 1852 */ 1853 uint64_t *d = vd, *n = vn, *m = vm; 1854 uint16_t mask = mve_element_mask(env); 1855 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 1856 unsigned e; 1857 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) { 1858 uint64_t r = m[H8(e)]; 1859 mergemask(&r, n[H8(e)], p0); 1860 mergemask(&d[H8(e)], r, mask); 1861 } 1862 mve_advance_vpt(env); 1863 } 1864