1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "accel/tcg/cpu-ldst.h" 26 #include "tcg/tcg.h" 27 #include "fpu/softfloat.h" 28 #include "crypto/clmul.h" 29 30 static uint16_t mve_eci_mask(CPUARMState *env) 31 { 32 /* 33 * Return the mask of which elements in the MVE vector correspond 34 * to beats being executed. The mask has 1 bits for executed lanes 35 * and 0 bits where ECI says this beat was already executed. 36 */ 37 int eci; 38 39 if ((env->condexec_bits & 0xf) != 0) { 40 return 0xffff; 41 } 42 43 eci = env->condexec_bits >> 4; 44 switch (eci) { 45 case ECI_NONE: 46 return 0xffff; 47 case ECI_A0: 48 return 0xfff0; 49 case ECI_A0A1: 50 return 0xff00; 51 case ECI_A0A1A2: 52 case ECI_A0A1A2B0: 53 return 0xf000; 54 default: 55 g_assert_not_reached(); 56 } 57 } 58 59 static uint16_t mve_element_mask(CPUARMState *env) 60 { 61 /* 62 * Return the mask of which elements in the MVE vector should be 63 * updated. This is a combination of multiple things: 64 * (1) by default, we update every lane in the vector 65 * (2) VPT predication stores its state in the VPR register; 66 * (3) low-overhead-branch tail predication will mask out part 67 * the vector on the final iteration of the loop 68 * (4) if EPSR.ECI is set then we must execute only some beats 69 * of the insn 70 * We combine all these into a 16-bit result with the same semantics 71 * as VPR.P0: 0 to mask the lane, 1 if it is active. 72 * 8-bit vector ops will look at all bits of the result; 73 * 16-bit ops will look at bits 0, 2, 4, ...; 74 * 32-bit ops will look at bits 0, 4, 8 and 12. 75 * Compare pseudocode GetCurInstrBeat(), though that only returns 76 * the 4-bit slice of the mask corresponding to a single beat. 77 */ 78 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 79 80 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 81 mask |= 0xff; 82 } 83 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 84 mask |= 0xff00; 85 } 86 87 if (env->v7m.ltpsize < 4 && 88 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 89 /* 90 * Tail predication active, and this is the last loop iteration. 91 * The element size is (1 << ltpsize), and we only want to process 92 * loopcount elements, so we want to retain the least significant 93 * (loopcount * esize) predicate bits and zero out bits above that. 94 */ 95 int masklen = env->regs[14] << env->v7m.ltpsize; 96 assert(masklen <= 16); 97 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 98 mask &= ltpmask; 99 } 100 101 /* 102 * ECI bits indicate which beats are already executed; 103 * we handle this by effectively predicating them out. 104 */ 105 mask &= mve_eci_mask(env); 106 return mask; 107 } 108 109 static void mve_advance_vpt(CPUARMState *env) 110 { 111 /* Advance the VPT and ECI state if necessary */ 112 uint32_t vpr = env->v7m.vpr; 113 unsigned mask01, mask23; 114 uint16_t inv_mask; 115 uint16_t eci_mask = mve_eci_mask(env); 116 117 if ((env->condexec_bits & 0xf) == 0) { 118 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 119 (ECI_A0 << 4) : (ECI_NONE << 4); 120 } 121 122 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 123 /* VPT not enabled, nothing to do */ 124 return; 125 } 126 127 /* Invert P0 bits if needed, but only for beats we actually executed */ 128 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 129 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 130 /* Start by assuming we invert all bits corresponding to executed beats */ 131 inv_mask = eci_mask; 132 if (mask01 <= 8) { 133 /* MASK01 says don't invert low half of P0 */ 134 inv_mask &= ~0xff; 135 } 136 if (mask23 <= 8) { 137 /* MASK23 says don't invert high half of P0 */ 138 inv_mask &= ~0xff00; 139 } 140 vpr ^= inv_mask; 141 /* Only update MASK01 if beat 1 executed */ 142 if (eci_mask & 0xf0) { 143 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 144 } 145 /* Beat 3 always executes, so update MASK23 */ 146 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 147 env->v7m.vpr = vpr; 148 } 149 150 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 151 #define DO_VLDR(OP, MFLAG, MSIZE, MTYPE, LDTYPE, ESIZE, TYPE) \ 152 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 153 { \ 154 TYPE *d = vd; \ 155 uint16_t mask = mve_element_mask(env); \ 156 uint16_t eci_mask = mve_eci_mask(env); \ 157 unsigned b, e; \ 158 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 159 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 160 /* \ 161 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 162 * beats so we don't care if we update part of the dest and \ 163 * then take an exception. \ 164 */ \ 165 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 166 if (eci_mask & (1 << b)) { \ 167 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 168 (MTYPE)cpu_##LDTYPE##_mmu(env, addr, oi, GETPC()) : 0;\ 169 } \ 170 addr += MSIZE; \ 171 } \ 172 mve_advance_vpt(env); \ 173 } 174 175 #define DO_VSTR(OP, MFLAG, MSIZE, STTYPE, ESIZE, TYPE) \ 176 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 177 { \ 178 TYPE *d = vd; \ 179 uint16_t mask = mve_element_mask(env); \ 180 unsigned b, e; \ 181 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 182 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 183 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 184 if (mask & (1 << b)) { \ 185 cpu_##STTYPE##_mmu(env, addr, d[H##ESIZE(e)], oi, GETPC()); \ 186 } \ 187 addr += MSIZE; \ 188 } \ 189 mve_advance_vpt(env); \ 190 } 191 192 DO_VLDR(vldrb, MO_UB, 1, uint8_t, ldb, 1, uint8_t) 193 DO_VLDR(vldrh, MO_TEUW, 2, uint16_t, ldw, 2, uint16_t) 194 DO_VLDR(vldrw, MO_TEUL, 4, uint32_t, ldl, 4, uint32_t) 195 196 DO_VSTR(vstrb, MO_UB, 1, stb, 1, uint8_t) 197 DO_VSTR(vstrh, MO_TEUW, 2, stw, 2, uint16_t) 198 DO_VSTR(vstrw, MO_TEUL, 4, stl, 4, uint32_t) 199 200 DO_VLDR(vldrb_sh, MO_SB, 1, int8_t, ldb, 2, int16_t) 201 DO_VLDR(vldrb_sw, MO_SB, 1, int8_t, ldb, 4, int32_t) 202 DO_VLDR(vldrb_uh, MO_UB, 1, uint8_t, ldb, 2, uint16_t) 203 DO_VLDR(vldrb_uw, MO_UB, 1, uint8_t, ldb, 4, uint32_t) 204 DO_VLDR(vldrh_sw, MO_TESW, 2, int16_t, ldw, 4, int32_t) 205 DO_VLDR(vldrh_uw, MO_TEUW, 2, uint16_t, ldw, 4, uint32_t) 206 207 DO_VSTR(vstrb_h, MO_UB, 1, stb, 2, int16_t) 208 DO_VSTR(vstrb_w, MO_UB, 1, stb, 4, int32_t) 209 DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) 210 211 #undef DO_VLDR 212 #undef DO_VSTR 213 214 /* 215 * Gather loads/scatter stores. Here each element of Qm specifies 216 * an offset to use from the base register Rm. In the _os_ versions 217 * that offset is scaled by the element size. 218 * For loads, predicated lanes are zeroed instead of retaining 219 * their previous values. 220 */ 221 #define DO_VLDR_SG(OP, MFLAG, MTYPE, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN, WB)\ 222 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 223 uint32_t base) \ 224 { \ 225 TYPE *d = vd; \ 226 OFFTYPE *m = vm; \ 227 uint16_t mask = mve_element_mask(env); \ 228 uint16_t eci_mask = mve_eci_mask(env); \ 229 unsigned e; \ 230 uint32_t addr; \ 231 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 232 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 233 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 234 if (!(eci_mask & 1)) { \ 235 continue; \ 236 } \ 237 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 238 d[H##ESIZE(e)] = (mask & 1) ? \ 239 (MTYPE)cpu_##LDTYPE##_mmu(env, addr, oi, GETPC()) : 0; \ 240 if (WB) { \ 241 m[H##ESIZE(e)] = addr; \ 242 } \ 243 } \ 244 mve_advance_vpt(env); \ 245 } 246 247 /* We know here TYPE is unsigned so always the same as the offset type */ 248 #define DO_VSTR_SG(OP, MFLAG, STTYPE, ESIZE, TYPE, ADDRFN, WB) \ 249 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 250 uint32_t base) \ 251 { \ 252 TYPE *d = vd; \ 253 TYPE *m = vm; \ 254 uint16_t mask = mve_element_mask(env); \ 255 uint16_t eci_mask = mve_eci_mask(env); \ 256 unsigned e; \ 257 uint32_t addr; \ 258 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 259 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 260 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 261 if (!(eci_mask & 1)) { \ 262 continue; \ 263 } \ 264 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 265 if (mask & 1) { \ 266 cpu_##STTYPE##_mmu(env, addr, d[H##ESIZE(e)], oi, GETPC()); \ 267 } \ 268 if (WB) { \ 269 m[H##ESIZE(e)] = addr; \ 270 } \ 271 } \ 272 mve_advance_vpt(env); \ 273 } 274 275 /* 276 * 64-bit accesses are slightly different: they are done as two 32-bit 277 * accesses, controlled by the predicate mask for the relevant beat, 278 * and with a single 32-bit offset in the first of the two Qm elements. 279 * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little). 280 * Address writeback happens on the odd beats and updates the address 281 * stored in the even-beat element. 282 */ 283 #define DO_VLDR64_SG(OP, ADDRFN, WB) \ 284 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 285 uint32_t base) \ 286 { \ 287 uint32_t *d = vd; \ 288 uint32_t *m = vm; \ 289 uint16_t mask = mve_element_mask(env); \ 290 uint16_t eci_mask = mve_eci_mask(env); \ 291 unsigned e; \ 292 uint32_t addr; \ 293 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 294 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 295 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 296 if (!(eci_mask & 1)) { \ 297 continue; \ 298 } \ 299 addr = ADDRFN(base, m[H4(e & ~1)]); \ 300 addr += 4 * (e & 1); \ 301 d[H4(e)] = (mask & 1) ? cpu_ldl_mmu(env, addr, oi, GETPC()) : 0; \ 302 if (WB && (e & 1)) { \ 303 m[H4(e & ~1)] = addr - 4; \ 304 } \ 305 } \ 306 mve_advance_vpt(env); \ 307 } 308 309 #define DO_VSTR64_SG(OP, ADDRFN, WB) \ 310 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 311 uint32_t base) \ 312 { \ 313 uint32_t *d = vd; \ 314 uint32_t *m = vm; \ 315 uint16_t mask = mve_element_mask(env); \ 316 uint16_t eci_mask = mve_eci_mask(env); \ 317 unsigned e; \ 318 uint32_t addr; \ 319 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 320 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 321 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 322 if (!(eci_mask & 1)) { \ 323 continue; \ 324 } \ 325 addr = ADDRFN(base, m[H4(e & ~1)]); \ 326 addr += 4 * (e & 1); \ 327 if (mask & 1) { \ 328 cpu_stl_mmu(env, addr, d[H4(e)], oi, GETPC()); \ 329 } \ 330 if (WB && (e & 1)) { \ 331 m[H4(e & ~1)] = addr - 4; \ 332 } \ 333 } \ 334 mve_advance_vpt(env); \ 335 } 336 337 #define ADDR_ADD(BASE, OFFSET) ((BASE) + (OFFSET)) 338 #define ADDR_ADD_OSH(BASE, OFFSET) ((BASE) + ((OFFSET) << 1)) 339 #define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2)) 340 #define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3)) 341 342 DO_VLDR_SG(vldrb_sg_sh, MO_SB, int8_t, ldb, 2, int16_t, uint16_t, ADDR_ADD, false) 343 DO_VLDR_SG(vldrb_sg_sw, MO_SB, int8_t, ldb, 4, int32_t, uint32_t, ADDR_ADD, false) 344 DO_VLDR_SG(vldrh_sg_sw, MO_TESW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_ADD, false) 345 346 DO_VLDR_SG(vldrb_sg_ub, MO_UB, uint8_t, ldb, 1, uint8_t, uint8_t, ADDR_ADD, false) 347 DO_VLDR_SG(vldrb_sg_uh, MO_UB, uint8_t, ldb, 2, uint16_t, uint16_t, ADDR_ADD, false) 348 DO_VLDR_SG(vldrb_sg_uw, MO_UB, uint8_t, ldb, 4, uint32_t, uint32_t, ADDR_ADD, false) 349 DO_VLDR_SG(vldrh_sg_uh, MO_TEUW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_ADD, false) 350 DO_VLDR_SG(vldrh_sg_uw, MO_TEUW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_ADD, false) 351 DO_VLDR_SG(vldrw_sg_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false) 352 DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) 353 354 DO_VLDR_SG(vldrh_sg_os_sw, MO_TESW, int16_t, ldw, 4, 355 int32_t, uint32_t, ADDR_ADD_OSH, false) 356 DO_VLDR_SG(vldrh_sg_os_uh, MO_TEUW, uint16_t, ldw, 2, 357 uint16_t, uint16_t, ADDR_ADD_OSH, false) 358 DO_VLDR_SG(vldrh_sg_os_uw, MO_TEUW, uint16_t, ldw, 4, 359 uint32_t, uint32_t, ADDR_ADD_OSH, false) 360 DO_VLDR_SG(vldrw_sg_os_uw, MO_TEUL, uint32_t, ldl, 4, 361 uint32_t, uint32_t, ADDR_ADD_OSW, false) 362 DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) 363 364 DO_VSTR_SG(vstrb_sg_ub, MO_UB, stb, 1, uint8_t, ADDR_ADD, false) 365 DO_VSTR_SG(vstrb_sg_uh, MO_UB, stb, 2, uint16_t, ADDR_ADD, false) 366 DO_VSTR_SG(vstrb_sg_uw, MO_UB, stb, 4, uint32_t, ADDR_ADD, false) 367 DO_VSTR_SG(vstrh_sg_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD, false) 368 DO_VSTR_SG(vstrh_sg_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD, false) 369 DO_VSTR_SG(vstrw_sg_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, false) 370 DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) 371 372 DO_VSTR_SG(vstrh_sg_os_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD_OSH, false) 373 DO_VSTR_SG(vstrh_sg_os_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD_OSH, false) 374 DO_VSTR_SG(vstrw_sg_os_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD_OSW, false) 375 DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) 376 377 DO_VLDR_SG(vldrw_sg_wb_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true) 378 DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) 379 DO_VSTR_SG(vstrw_sg_wb_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, true) 380 DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) 381 382 /* 383 * Deinterleaving loads/interleaving stores. 384 * 385 * For these helpers we are passed the index of the first Qreg 386 * (VLD2/VST2 will also access Qn+1, VLD4/VST4 access Qn .. Qn+3) 387 * and the value of the base address register Rn. 388 * The helpers are specialized for pattern and element size, so 389 * for instance vld42h is VLD4 with pattern 2, element size MO_16. 390 * 391 * These insns are beatwise but not predicated, so we must honour ECI, 392 * but need not look at mve_element_mask(). 393 * 394 * The pseudocode implements these insns with multiple memory accesses 395 * of the element size, but rules R_VVVG and R_FXDM permit us to make 396 * one 32-bit memory access per beat. 397 */ 398 #define DO_VLD4B(OP, O1, O2, O3, O4) \ 399 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 400 uint32_t base) \ 401 { \ 402 int beat, e; \ 403 uint16_t mask = mve_eci_mask(env); \ 404 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 405 uint32_t addr, data; \ 406 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 407 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 408 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 409 if ((mask & 1) == 0) { \ 410 /* ECI says skip this beat */ \ 411 continue; \ 412 } \ 413 addr = base + off[beat] * 4; \ 414 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 415 for (e = 0; e < 4; e++, data >>= 8) { \ 416 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 417 qd[H1(off[beat])] = data; \ 418 } \ 419 } \ 420 } 421 422 #define DO_VLD4H(OP, O1, O2) \ 423 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 424 uint32_t base) \ 425 { \ 426 int beat; \ 427 uint16_t mask = mve_eci_mask(env); \ 428 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 429 uint32_t addr, data; \ 430 int y; /* y counts 0 2 0 2 */ \ 431 uint16_t *qd; \ 432 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 433 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 434 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 435 if ((mask & 1) == 0) { \ 436 /* ECI says skip this beat */ \ 437 continue; \ 438 } \ 439 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 440 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 441 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 442 qd[H2(off[beat])] = data; \ 443 data >>= 16; \ 444 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 445 qd[H2(off[beat])] = data; \ 446 } \ 447 } 448 449 #define DO_VLD4W(OP, O1, O2, O3, O4) \ 450 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 451 uint32_t base) \ 452 { \ 453 int beat; \ 454 uint16_t mask = mve_eci_mask(env); \ 455 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 456 uint32_t addr, data; \ 457 uint32_t *qd; \ 458 int y; \ 459 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 460 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 461 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 462 if ((mask & 1) == 0) { \ 463 /* ECI says skip this beat */ \ 464 continue; \ 465 } \ 466 addr = base + off[beat] * 4; \ 467 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 468 y = (beat + (O1 & 2)) & 3; \ 469 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 470 qd[H4(off[beat] >> 2)] = data; \ 471 } \ 472 } 473 474 DO_VLD4B(vld40b, 0, 1, 10, 11) 475 DO_VLD4B(vld41b, 2, 3, 12, 13) 476 DO_VLD4B(vld42b, 4, 5, 14, 15) 477 DO_VLD4B(vld43b, 6, 7, 8, 9) 478 479 DO_VLD4H(vld40h, 0, 5) 480 DO_VLD4H(vld41h, 1, 6) 481 DO_VLD4H(vld42h, 2, 7) 482 DO_VLD4H(vld43h, 3, 4) 483 484 DO_VLD4W(vld40w, 0, 1, 10, 11) 485 DO_VLD4W(vld41w, 2, 3, 12, 13) 486 DO_VLD4W(vld42w, 4, 5, 14, 15) 487 DO_VLD4W(vld43w, 6, 7, 8, 9) 488 489 #define DO_VLD2B(OP, O1, O2, O3, O4) \ 490 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 491 uint32_t base) \ 492 { \ 493 int beat, e; \ 494 uint16_t mask = mve_eci_mask(env); \ 495 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 496 uint32_t addr, data; \ 497 uint8_t *qd; \ 498 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 499 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 500 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 501 if ((mask & 1) == 0) { \ 502 /* ECI says skip this beat */ \ 503 continue; \ 504 } \ 505 addr = base + off[beat] * 2; \ 506 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 507 for (e = 0; e < 4; e++, data >>= 8) { \ 508 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 509 qd[H1(off[beat] + (e >> 1))] = data; \ 510 } \ 511 } \ 512 } 513 514 #define DO_VLD2H(OP, O1, O2, O3, O4) \ 515 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 516 uint32_t base) \ 517 { \ 518 int beat; \ 519 uint16_t mask = mve_eci_mask(env); \ 520 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 521 uint32_t addr, data; \ 522 int e; \ 523 uint16_t *qd; \ 524 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 525 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 526 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 527 if ((mask & 1) == 0) { \ 528 /* ECI says skip this beat */ \ 529 continue; \ 530 } \ 531 addr = base + off[beat] * 4; \ 532 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 533 for (e = 0; e < 2; e++, data >>= 16) { \ 534 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 535 qd[H2(off[beat])] = data; \ 536 } \ 537 } \ 538 } 539 540 #define DO_VLD2W(OP, O1, O2, O3, O4) \ 541 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 542 uint32_t base) \ 543 { \ 544 int beat; \ 545 uint16_t mask = mve_eci_mask(env); \ 546 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 547 uint32_t addr, data; \ 548 uint32_t *qd; \ 549 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 550 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 551 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 552 if ((mask & 1) == 0) { \ 553 /* ECI says skip this beat */ \ 554 continue; \ 555 } \ 556 addr = base + off[beat]; \ 557 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 558 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 559 qd[H4(off[beat] >> 3)] = data; \ 560 } \ 561 } 562 563 DO_VLD2B(vld20b, 0, 2, 12, 14) 564 DO_VLD2B(vld21b, 4, 6, 8, 10) 565 566 DO_VLD2H(vld20h, 0, 1, 6, 7) 567 DO_VLD2H(vld21h, 2, 3, 4, 5) 568 569 DO_VLD2W(vld20w, 0, 4, 24, 28) 570 DO_VLD2W(vld21w, 8, 12, 16, 20) 571 572 #define DO_VST4B(OP, O1, O2, O3, O4) \ 573 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 574 uint32_t base) \ 575 { \ 576 int beat, e; \ 577 uint16_t mask = mve_eci_mask(env); \ 578 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 579 uint32_t addr, data; \ 580 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 581 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 582 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 583 if ((mask & 1) == 0) { \ 584 /* ECI says skip this beat */ \ 585 continue; \ 586 } \ 587 addr = base + off[beat] * 4; \ 588 data = 0; \ 589 for (e = 3; e >= 0; e--) { \ 590 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 591 data = (data << 8) | qd[H1(off[beat])]; \ 592 } \ 593 cpu_stl_mmu(env, addr, data, oi, GETPC()); \ 594 } \ 595 } 596 597 #define DO_VST4H(OP, O1, O2) \ 598 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 599 uint32_t base) \ 600 { \ 601 int beat; \ 602 uint16_t mask = mve_eci_mask(env); \ 603 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 604 uint32_t addr, data; \ 605 int y; /* y counts 0 2 0 2 */ \ 606 uint16_t *qd; \ 607 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 608 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 609 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 610 if ((mask & 1) == 0) { \ 611 /* ECI says skip this beat */ \ 612 continue; \ 613 } \ 614 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 615 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 616 data = qd[H2(off[beat])]; \ 617 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 618 data |= qd[H2(off[beat])] << 16; \ 619 cpu_stl_mmu(env, addr, data, oi, GETPC()); \ 620 } \ 621 } 622 623 #define DO_VST4W(OP, O1, O2, O3, O4) \ 624 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 625 uint32_t base) \ 626 { \ 627 int beat; \ 628 uint16_t mask = mve_eci_mask(env); \ 629 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 630 uint32_t addr, data; \ 631 uint32_t *qd; \ 632 int y; \ 633 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 634 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 635 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 636 if ((mask & 1) == 0) { \ 637 /* ECI says skip this beat */ \ 638 continue; \ 639 } \ 640 addr = base + off[beat] * 4; \ 641 y = (beat + (O1 & 2)) & 3; \ 642 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 643 data = qd[H4(off[beat] >> 2)]; \ 644 cpu_stl_mmu(env, addr, data, oi, GETPC()); \ 645 } \ 646 } 647 648 DO_VST4B(vst40b, 0, 1, 10, 11) 649 DO_VST4B(vst41b, 2, 3, 12, 13) 650 DO_VST4B(vst42b, 4, 5, 14, 15) 651 DO_VST4B(vst43b, 6, 7, 8, 9) 652 653 DO_VST4H(vst40h, 0, 5) 654 DO_VST4H(vst41h, 1, 6) 655 DO_VST4H(vst42h, 2, 7) 656 DO_VST4H(vst43h, 3, 4) 657 658 DO_VST4W(vst40w, 0, 1, 10, 11) 659 DO_VST4W(vst41w, 2, 3, 12, 13) 660 DO_VST4W(vst42w, 4, 5, 14, 15) 661 DO_VST4W(vst43w, 6, 7, 8, 9) 662 663 #define DO_VST2B(OP, O1, O2, O3, O4) \ 664 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 665 uint32_t base) \ 666 { \ 667 int beat, e; \ 668 uint16_t mask = mve_eci_mask(env); \ 669 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 670 uint32_t addr, data; \ 671 uint8_t *qd; \ 672 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 673 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 674 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 675 if ((mask & 1) == 0) { \ 676 /* ECI says skip this beat */ \ 677 continue; \ 678 } \ 679 addr = base + off[beat] * 2; \ 680 data = 0; \ 681 for (e = 3; e >= 0; e--) { \ 682 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 683 data = (data << 8) | qd[H1(off[beat] + (e >> 1))]; \ 684 } \ 685 cpu_stl_mmu(env, addr, data, oi, GETPC()); \ 686 } \ 687 } 688 689 #define DO_VST2H(OP, O1, O2, O3, O4) \ 690 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 691 uint32_t base) \ 692 { \ 693 int beat; \ 694 uint16_t mask = mve_eci_mask(env); \ 695 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 696 uint32_t addr, data; \ 697 int e; \ 698 uint16_t *qd; \ 699 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 700 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 701 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 702 if ((mask & 1) == 0) { \ 703 /* ECI says skip this beat */ \ 704 continue; \ 705 } \ 706 addr = base + off[beat] * 4; \ 707 data = 0; \ 708 for (e = 1; e >= 0; e--) { \ 709 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 710 data = (data << 16) | qd[H2(off[beat])]; \ 711 } \ 712 cpu_stl_mmu(env, addr, data, oi, GETPC()); \ 713 } \ 714 } 715 716 #define DO_VST2W(OP, O1, O2, O3, O4) \ 717 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 718 uint32_t base) \ 719 { \ 720 int beat; \ 721 uint16_t mask = mve_eci_mask(env); \ 722 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 723 uint32_t addr, data; \ 724 uint32_t *qd; \ 725 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 726 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 727 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 728 if ((mask & 1) == 0) { \ 729 /* ECI says skip this beat */ \ 730 continue; \ 731 } \ 732 addr = base + off[beat]; \ 733 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 734 data = qd[H4(off[beat] >> 3)]; \ 735 cpu_stl_mmu(env, addr, data, oi, GETPC()); \ 736 } \ 737 } 738 739 DO_VST2B(vst20b, 0, 2, 12, 14) 740 DO_VST2B(vst21b, 4, 6, 8, 10) 741 742 DO_VST2H(vst20h, 0, 1, 6, 7) 743 DO_VST2H(vst21h, 2, 3, 4, 5) 744 745 DO_VST2W(vst20w, 0, 4, 24, 28) 746 DO_VST2W(vst21w, 8, 12, 16, 20) 747 748 /* 749 * The mergemask(D, R, M) macro performs the operation "*D = R" but 750 * storing only the bytes which correspond to 1 bits in M, 751 * leaving other bytes in *D unchanged. We use _Generic 752 * to select the correct implementation based on the type of D. 753 */ 754 755 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 756 { 757 if (mask & 1) { 758 *d = r; 759 } 760 } 761 762 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 763 { 764 mergemask_ub((uint8_t *)d, r, mask); 765 } 766 767 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 768 { 769 uint16_t bmask = expand_pred_b(mask); 770 *d = (*d & ~bmask) | (r & bmask); 771 } 772 773 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 774 { 775 mergemask_uh((uint16_t *)d, r, mask); 776 } 777 778 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 779 { 780 uint32_t bmask = expand_pred_b(mask); 781 *d = (*d & ~bmask) | (r & bmask); 782 } 783 784 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 785 { 786 mergemask_uw((uint32_t *)d, r, mask); 787 } 788 789 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 790 { 791 uint64_t bmask = expand_pred_b(mask); 792 *d = (*d & ~bmask) | (r & bmask); 793 } 794 795 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 796 { 797 mergemask_uq((uint64_t *)d, r, mask); 798 } 799 800 #define mergemask(D, R, M) \ 801 _Generic(D, \ 802 uint8_t *: mergemask_ub, \ 803 int8_t *: mergemask_sb, \ 804 uint16_t *: mergemask_uh, \ 805 int16_t *: mergemask_sh, \ 806 uint32_t *: mergemask_uw, \ 807 int32_t *: mergemask_sw, \ 808 uint64_t *: mergemask_uq, \ 809 int64_t *: mergemask_sq)(D, R, M) 810 811 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 812 { 813 /* 814 * The generated code already replicated an 8 or 16 bit constant 815 * into the 32-bit value, so we only need to write the 32-bit 816 * value to all elements of the Qreg, allowing for predication. 817 */ 818 uint32_t *d = vd; 819 uint16_t mask = mve_element_mask(env); 820 unsigned e; 821 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 822 mergemask(&d[H4(e)], val, mask); 823 } 824 mve_advance_vpt(env); 825 } 826 827 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 828 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 829 { \ 830 TYPE *d = vd, *m = vm; \ 831 uint16_t mask = mve_element_mask(env); \ 832 unsigned e; \ 833 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 834 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 835 } \ 836 mve_advance_vpt(env); \ 837 } 838 839 #define DO_CLS_B(N) (clrsb32(N) - 24) 840 #define DO_CLS_H(N) (clrsb32(N) - 16) 841 842 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 843 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 844 DO_1OP(vclsw, 4, int32_t, clrsb32) 845 846 #define DO_CLZ_B(N) (clz32(N) - 24) 847 #define DO_CLZ_H(N) (clz32(N) - 16) 848 849 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 850 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 851 DO_1OP(vclzw, 4, uint32_t, clz32) 852 853 DO_1OP(vrev16b, 2, uint16_t, bswap16) 854 DO_1OP(vrev32b, 4, uint32_t, bswap32) 855 DO_1OP(vrev32h, 4, uint32_t, hswap32) 856 DO_1OP(vrev64b, 8, uint64_t, bswap64) 857 DO_1OP(vrev64h, 8, uint64_t, hswap64) 858 DO_1OP(vrev64w, 8, uint64_t, wswap64) 859 860 #define DO_NOT(N) (~(N)) 861 862 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 863 864 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 865 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 866 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 867 868 DO_1OP(vabsb, 1, int8_t, DO_ABS) 869 DO_1OP(vabsh, 2, int16_t, DO_ABS) 870 DO_1OP(vabsw, 4, int32_t, DO_ABS) 871 872 /* We can do these 64 bits at a time */ 873 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 874 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 875 876 #define DO_NEG(N) (-(N)) 877 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 878 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 879 880 DO_1OP(vnegb, 1, int8_t, DO_NEG) 881 DO_1OP(vnegh, 2, int16_t, DO_NEG) 882 DO_1OP(vnegw, 4, int32_t, DO_NEG) 883 884 /* We can do these 64 bits at a time */ 885 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 886 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 887 888 /* 889 * 1 operand immediates: Vda is destination and possibly also one source. 890 * All these insns work at 64-bit widths. 891 */ 892 #define DO_1OP_IMM(OP, FN) \ 893 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 894 { \ 895 uint64_t *da = vda; \ 896 uint16_t mask = mve_element_mask(env); \ 897 unsigned e; \ 898 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 899 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 900 } \ 901 mve_advance_vpt(env); \ 902 } 903 904 #define DO_MOVI(N, I) (I) 905 #define DO_ANDI(N, I) ((N) & (I)) 906 #define DO_ORRI(N, I) ((N) | (I)) 907 908 DO_1OP_IMM(vmovi, DO_MOVI) 909 DO_1OP_IMM(vandi, DO_ANDI) 910 DO_1OP_IMM(vorri, DO_ORRI) 911 912 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 913 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 914 void *vd, void *vn, void *vm) \ 915 { \ 916 TYPE *d = vd, *n = vn, *m = vm; \ 917 uint16_t mask = mve_element_mask(env); \ 918 unsigned e; \ 919 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 920 mergemask(&d[H##ESIZE(e)], \ 921 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 922 } \ 923 mve_advance_vpt(env); \ 924 } 925 926 /* provide unsigned 2-op helpers for all sizes */ 927 #define DO_2OP_U(OP, FN) \ 928 DO_2OP(OP##b, 1, uint8_t, FN) \ 929 DO_2OP(OP##h, 2, uint16_t, FN) \ 930 DO_2OP(OP##w, 4, uint32_t, FN) 931 932 /* provide signed 2-op helpers for all sizes */ 933 #define DO_2OP_S(OP, FN) \ 934 DO_2OP(OP##b, 1, int8_t, FN) \ 935 DO_2OP(OP##h, 2, int16_t, FN) \ 936 DO_2OP(OP##w, 4, int32_t, FN) 937 938 /* 939 * "Long" operations where two half-sized inputs (taken from either the 940 * top or the bottom of the input vector) produce a double-width result. 941 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 942 */ 943 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 944 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 945 { \ 946 LTYPE *d = vd; \ 947 TYPE *n = vn, *m = vm; \ 948 uint16_t mask = mve_element_mask(env); \ 949 unsigned le; \ 950 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 951 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 952 m[H##ESIZE(le * 2 + TOP)]); \ 953 mergemask(&d[H##LESIZE(le)], r, mask); \ 954 } \ 955 mve_advance_vpt(env); \ 956 } 957 958 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 959 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 960 { \ 961 TYPE *d = vd, *n = vn, *m = vm; \ 962 uint16_t mask = mve_element_mask(env); \ 963 unsigned e; \ 964 bool qc = false; \ 965 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 966 bool sat = false; \ 967 TYPE r_ = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 968 mergemask(&d[H##ESIZE(e)], r_, mask); \ 969 qc |= sat & mask & 1; \ 970 } \ 971 if (qc) { \ 972 env->vfp.qc[0] = qc; \ 973 } \ 974 mve_advance_vpt(env); \ 975 } 976 977 /* provide unsigned 2-op helpers for all sizes */ 978 #define DO_2OP_SAT_U(OP, FN) \ 979 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 980 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 981 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 982 983 /* provide signed 2-op helpers for all sizes */ 984 #define DO_2OP_SAT_S(OP, FN) \ 985 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 986 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 987 DO_2OP_SAT(OP##w, 4, int32_t, FN) 988 989 #define DO_AND(N, M) ((N) & (M)) 990 #define DO_BIC(N, M) ((N) & ~(M)) 991 #define DO_ORR(N, M) ((N) | (M)) 992 #define DO_ORN(N, M) ((N) | ~(M)) 993 #define DO_EOR(N, M) ((N) ^ (M)) 994 995 DO_2OP(vand, 8, uint64_t, DO_AND) 996 DO_2OP(vbic, 8, uint64_t, DO_BIC) 997 DO_2OP(vorr, 8, uint64_t, DO_ORR) 998 DO_2OP(vorn, 8, uint64_t, DO_ORN) 999 DO_2OP(veor, 8, uint64_t, DO_EOR) 1000 1001 #define DO_ADD(N, M) ((N) + (M)) 1002 #define DO_SUB(N, M) ((N) - (M)) 1003 #define DO_MUL(N, M) ((N) * (M)) 1004 1005 DO_2OP_U(vadd, DO_ADD) 1006 DO_2OP_U(vsub, DO_SUB) 1007 DO_2OP_U(vmul, DO_MUL) 1008 1009 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 1010 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 1011 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 1012 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 1013 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 1014 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 1015 1016 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 1017 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 1018 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 1019 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 1020 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 1021 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 1022 1023 /* 1024 * Polynomial multiply. We can always do this generating 64 bits 1025 * of the result at a time, so we don't need to use DO_2OP_L. 1026 */ 1027 DO_2OP(vmullpbh, 8, uint64_t, clmul_8x4_even) 1028 DO_2OP(vmullpth, 8, uint64_t, clmul_8x4_odd) 1029 DO_2OP(vmullpbw, 8, uint64_t, clmul_16x2_even) 1030 DO_2OP(vmullptw, 8, uint64_t, clmul_16x2_odd) 1031 1032 /* 1033 * Because the computation type is at least twice as large as required, 1034 * these work for both signed and unsigned source types. 1035 */ 1036 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 1037 { 1038 return (n * m) >> 8; 1039 } 1040 1041 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 1042 { 1043 return (n * m) >> 16; 1044 } 1045 1046 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 1047 { 1048 return (n * m) >> 32; 1049 } 1050 1051 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 1052 { 1053 return (n * m + (1U << 7)) >> 8; 1054 } 1055 1056 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 1057 { 1058 return (n * m + (1U << 15)) >> 16; 1059 } 1060 1061 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 1062 { 1063 return (n * m + (1U << 31)) >> 32; 1064 } 1065 1066 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 1067 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 1068 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 1069 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 1070 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 1071 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 1072 1073 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 1074 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 1075 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 1076 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 1077 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 1078 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 1079 1080 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 1081 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 1082 1083 DO_2OP_S(vmaxs, DO_MAX) 1084 DO_2OP_U(vmaxu, DO_MAX) 1085 DO_2OP_S(vmins, DO_MIN) 1086 DO_2OP_U(vminu, DO_MIN) 1087 1088 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 1089 1090 DO_2OP_S(vabds, DO_ABD) 1091 DO_2OP_U(vabdu, DO_ABD) 1092 1093 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 1094 { 1095 return ((uint64_t)n + m) >> 1; 1096 } 1097 1098 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 1099 { 1100 return ((int64_t)n + m) >> 1; 1101 } 1102 1103 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 1104 { 1105 return ((uint64_t)n - m) >> 1; 1106 } 1107 1108 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 1109 { 1110 return ((int64_t)n - m) >> 1; 1111 } 1112 1113 DO_2OP_S(vhadds, do_vhadd_s) 1114 DO_2OP_U(vhaddu, do_vhadd_u) 1115 DO_2OP_S(vhsubs, do_vhsub_s) 1116 DO_2OP_U(vhsubu, do_vhsub_u) 1117 1118 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1119 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1120 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1121 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1122 1123 DO_2OP_S(vshls, DO_VSHLS) 1124 DO_2OP_U(vshlu, DO_VSHLU) 1125 DO_2OP_S(vrshls, DO_VRSHLS) 1126 DO_2OP_U(vrshlu, DO_VRSHLU) 1127 1128 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 1129 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 1130 1131 DO_2OP_S(vrhadds, DO_RHADD_S) 1132 DO_2OP_U(vrhaddu, DO_RHADD_U) 1133 1134 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 1135 uint32_t inv, uint32_t carry_in, bool update_flags) 1136 { 1137 uint16_t mask = mve_element_mask(env); 1138 unsigned e; 1139 1140 /* If any additions trigger, we will update flags. */ 1141 if (mask & 0x1111) { 1142 update_flags = true; 1143 } 1144 1145 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1146 uint64_t r = carry_in; 1147 r += n[H4(e)]; 1148 r += m[H4(e)] ^ inv; 1149 if (mask & 1) { 1150 carry_in = r >> 32; 1151 } 1152 mergemask(&d[H4(e)], r, mask); 1153 } 1154 1155 if (update_flags) { 1156 /* Store C, clear NZV. */ 1157 env->vfp.fpsr &= ~FPSR_NZCV_MASK; 1158 env->vfp.fpsr |= carry_in * FPSR_C; 1159 } 1160 mve_advance_vpt(env); 1161 } 1162 1163 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 1164 { 1165 bool carry_in = env->vfp.fpsr & FPSR_C; 1166 do_vadc(env, vd, vn, vm, 0, carry_in, false); 1167 } 1168 1169 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 1170 { 1171 bool carry_in = env->vfp.fpsr & FPSR_C; 1172 do_vadc(env, vd, vn, vm, -1, carry_in, false); 1173 } 1174 1175 1176 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 1177 { 1178 do_vadc(env, vd, vn, vm, 0, 0, true); 1179 } 1180 1181 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 1182 { 1183 do_vadc(env, vd, vn, vm, -1, 1, true); 1184 } 1185 1186 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 1187 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 1188 { \ 1189 TYPE *d = vd, *n = vn, *m = vm; \ 1190 uint16_t mask = mve_element_mask(env); \ 1191 unsigned e; \ 1192 TYPE r[16 / ESIZE]; \ 1193 /* Calculate all results first to avoid overwriting inputs */ \ 1194 for (e = 0; e < 16 / ESIZE; e++) { \ 1195 if (!(e & 1)) { \ 1196 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 1197 } else { \ 1198 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 1199 } \ 1200 } \ 1201 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1202 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 1203 } \ 1204 mve_advance_vpt(env); \ 1205 } 1206 1207 #define DO_VCADD_ALL(OP, FN0, FN1) \ 1208 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 1209 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 1210 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 1211 1212 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 1213 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 1214 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 1215 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 1216 1217 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 1218 { 1219 if (val > max) { 1220 *s = true; 1221 return max; 1222 } else if (val < min) { 1223 *s = true; 1224 return min; 1225 } 1226 return val; 1227 } 1228 1229 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 1230 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 1231 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 1232 1233 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 1234 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 1235 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 1236 1237 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 1238 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 1239 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 1240 1241 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 1242 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 1243 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 1244 1245 /* 1246 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 1247 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 1248 */ 1249 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 1250 INT8_MIN, INT8_MAX, s) 1251 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 1252 INT16_MIN, INT16_MAX, s) 1253 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 1254 INT32_MIN, INT32_MAX, s) 1255 1256 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 1257 INT8_MIN, INT8_MAX, s) 1258 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 1259 INT16_MIN, INT16_MAX, s) 1260 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 1261 INT32_MIN, INT32_MAX, s) 1262 1263 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 1264 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 1265 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 1266 1267 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 1268 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 1269 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 1270 1271 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 1272 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 1273 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 1274 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 1275 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 1276 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 1277 1278 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 1279 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 1280 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 1281 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 1282 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 1283 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 1284 1285 /* 1286 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 1287 * and friends wanting a uint32_t* sat and our needing a bool*. 1288 */ 1289 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 1290 ({ \ 1291 uint32_t su32 = 0; \ 1292 typeof(N) qrshl_ret = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 1293 if (su32) { \ 1294 *satp = true; \ 1295 } \ 1296 qrshl_ret; \ 1297 }) 1298 1299 #define DO_SQSHL_OP(N, M, satp) \ 1300 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 1301 #define DO_UQSHL_OP(N, M, satp) \ 1302 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 1303 #define DO_SQRSHL_OP(N, M, satp) \ 1304 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 1305 #define DO_UQRSHL_OP(N, M, satp) \ 1306 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 1307 #define DO_SUQSHL_OP(N, M, satp) \ 1308 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 1309 1310 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 1311 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 1312 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 1313 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 1314 1315 /* 1316 * Multiply add dual returning high half 1317 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 1318 * whether to add the rounding constant, and the pointer to the 1319 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 1320 * saturate to twice the input size and return the high half; or 1321 * (A * B - C * D) etc for VQDMLSDH. 1322 */ 1323 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 1324 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1325 void *vm) \ 1326 { \ 1327 TYPE *d = vd, *n = vn, *m = vm; \ 1328 uint16_t mask = mve_element_mask(env); \ 1329 unsigned e; \ 1330 bool qc = false; \ 1331 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1332 bool sat = false; \ 1333 if ((e & 1) == XCHG) { \ 1334 TYPE vqdmladh_ret = FN(n[H##ESIZE(e)], \ 1335 m[H##ESIZE(e - XCHG)], \ 1336 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 1337 m[H##ESIZE(e + (1 - XCHG))], \ 1338 ROUND, &sat); \ 1339 mergemask(&d[H##ESIZE(e)], vqdmladh_ret, mask); \ 1340 qc |= sat & mask & 1; \ 1341 } \ 1342 } \ 1343 if (qc) { \ 1344 env->vfp.qc[0] = qc; \ 1345 } \ 1346 mve_advance_vpt(env); \ 1347 } 1348 1349 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1350 int round, bool *sat) 1351 { 1352 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 1353 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1354 } 1355 1356 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1357 int round, bool *sat) 1358 { 1359 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 1360 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1361 } 1362 1363 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1364 int round, bool *sat) 1365 { 1366 int64_t m1 = (int64_t)a * b; 1367 int64_t m2 = (int64_t)c * d; 1368 int64_t r; 1369 /* 1370 * Architecturally we should do the entire add, double, round 1371 * and then check for saturation. We do three saturating adds, 1372 * but we need to be careful about the order. If the first 1373 * m1 + m2 saturates then it's impossible for the *2+rc to 1374 * bring it back into the non-saturated range. However, if 1375 * m1 + m2 is negative then it's possible that doing the doubling 1376 * would take the intermediate result below INT64_MAX and the 1377 * addition of the rounding constant then brings it back in range. 1378 * So we add half the rounding constant before doubling rather 1379 * than adding the rounding constant after the doubling. 1380 */ 1381 if (sadd64_overflow(m1, m2, &r) || 1382 sadd64_overflow(r, (round << 30), &r) || 1383 sadd64_overflow(r, r, &r)) { 1384 *sat = true; 1385 return r < 0 ? INT32_MAX : INT32_MIN; 1386 } 1387 return r >> 32; 1388 } 1389 1390 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1391 int round, bool *sat) 1392 { 1393 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 1394 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1395 } 1396 1397 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1398 int round, bool *sat) 1399 { 1400 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 1401 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1402 } 1403 1404 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1405 int round, bool *sat) 1406 { 1407 int64_t m1 = (int64_t)a * b; 1408 int64_t m2 = (int64_t)c * d; 1409 int64_t r; 1410 /* The same ordering issue as in do_vqdmladh_w applies here too */ 1411 if (ssub64_overflow(m1, m2, &r) || 1412 sadd64_overflow(r, (round << 30), &r) || 1413 sadd64_overflow(r, r, &r)) { 1414 *sat = true; 1415 return r < 0 ? INT32_MAX : INT32_MIN; 1416 } 1417 return r >> 32; 1418 } 1419 1420 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 1421 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 1422 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 1423 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 1424 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 1425 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 1426 1427 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 1428 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 1429 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 1430 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 1431 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 1432 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 1433 1434 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 1435 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 1436 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 1437 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 1438 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 1439 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 1440 1441 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 1442 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 1443 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 1444 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 1445 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 1446 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 1447 1448 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 1449 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1450 uint32_t rm) \ 1451 { \ 1452 TYPE *d = vd, *n = vn; \ 1453 TYPE m = rm; \ 1454 uint16_t mask = mve_element_mask(env); \ 1455 unsigned e; \ 1456 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1457 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 1458 } \ 1459 mve_advance_vpt(env); \ 1460 } 1461 1462 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 1463 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1464 uint32_t rm) \ 1465 { \ 1466 TYPE *d = vd, *n = vn; \ 1467 TYPE m = rm; \ 1468 uint16_t mask = mve_element_mask(env); \ 1469 unsigned e; \ 1470 bool qc = false; \ 1471 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1472 bool sat = false; \ 1473 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 1474 mask); \ 1475 qc |= sat & mask & 1; \ 1476 } \ 1477 if (qc) { \ 1478 env->vfp.qc[0] = qc; \ 1479 } \ 1480 mve_advance_vpt(env); \ 1481 } 1482 1483 /* "accumulating" version where FN takes d as well as n and m */ 1484 #define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1485 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1486 uint32_t rm) \ 1487 { \ 1488 TYPE *d = vd, *n = vn; \ 1489 TYPE m = rm; \ 1490 uint16_t mask = mve_element_mask(env); \ 1491 unsigned e; \ 1492 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1493 mergemask(&d[H##ESIZE(e)], \ 1494 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \ 1495 } \ 1496 mve_advance_vpt(env); \ 1497 } 1498 1499 #define DO_2OP_SAT_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1500 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1501 uint32_t rm) \ 1502 { \ 1503 TYPE *d = vd, *n = vn; \ 1504 TYPE m = rm; \ 1505 uint16_t mask = mve_element_mask(env); \ 1506 unsigned e; \ 1507 bool qc = false; \ 1508 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1509 bool sat = false; \ 1510 mergemask(&d[H##ESIZE(e)], \ 1511 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m, &sat), \ 1512 mask); \ 1513 qc |= sat & mask & 1; \ 1514 } \ 1515 if (qc) { \ 1516 env->vfp.qc[0] = qc; \ 1517 } \ 1518 mve_advance_vpt(env); \ 1519 } 1520 1521 /* provide unsigned 2-op scalar helpers for all sizes */ 1522 #define DO_2OP_SCALAR_U(OP, FN) \ 1523 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 1524 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 1525 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 1526 #define DO_2OP_SCALAR_S(OP, FN) \ 1527 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 1528 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 1529 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 1530 1531 #define DO_2OP_ACC_SCALAR_U(OP, FN) \ 1532 DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \ 1533 DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \ 1534 DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN) 1535 1536 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 1537 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 1538 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 1539 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 1540 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 1541 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 1542 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 1543 1544 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 1545 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 1546 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 1547 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 1548 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 1549 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 1550 1551 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 1552 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 1553 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 1554 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 1555 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 1556 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 1557 1558 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 1559 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 1560 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 1561 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 1562 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 1563 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 1564 1565 static int8_t do_vqdmlah_b(int8_t a, int8_t b, int8_t c, int round, bool *sat) 1566 { 1567 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 8) + (round << 7); 1568 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1569 } 1570 1571 static int16_t do_vqdmlah_h(int16_t a, int16_t b, int16_t c, 1572 int round, bool *sat) 1573 { 1574 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 16) + (round << 15); 1575 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1576 } 1577 1578 static int32_t do_vqdmlah_w(int32_t a, int32_t b, int32_t c, 1579 int round, bool *sat) 1580 { 1581 /* 1582 * Architecturally we should do the entire add, double, round 1583 * and then check for saturation. We do three saturating adds, 1584 * but we need to be careful about the order. If the first 1585 * m1 + m2 saturates then it's impossible for the *2+rc to 1586 * bring it back into the non-saturated range. However, if 1587 * m1 + m2 is negative then it's possible that doing the doubling 1588 * would take the intermediate result below INT64_MAX and the 1589 * addition of the rounding constant then brings it back in range. 1590 * So we add half the rounding constant and half the "c << esize" 1591 * before doubling rather than adding the rounding constant after 1592 * the doubling. 1593 */ 1594 int64_t m1 = (int64_t)a * b; 1595 int64_t m2 = (int64_t)c << 31; 1596 int64_t r; 1597 if (sadd64_overflow(m1, m2, &r) || 1598 sadd64_overflow(r, (round << 30), &r) || 1599 sadd64_overflow(r, r, &r)) { 1600 *sat = true; 1601 return r < 0 ? INT32_MAX : INT32_MIN; 1602 } 1603 return r >> 32; 1604 } 1605 1606 /* 1607 * The *MLAH insns are vector * scalar + vector; 1608 * the *MLASH insns are vector * vector + scalar 1609 */ 1610 #define DO_VQDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 0, S) 1611 #define DO_VQDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 0, S) 1612 #define DO_VQDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 0, S) 1613 #define DO_VQRDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 1, S) 1614 #define DO_VQRDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 1, S) 1615 #define DO_VQRDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 1, S) 1616 1617 #define DO_VQDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 0, S) 1618 #define DO_VQDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 0, S) 1619 #define DO_VQDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 0, S) 1620 #define DO_VQRDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 1, S) 1621 #define DO_VQRDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 1, S) 1622 #define DO_VQRDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 1, S) 1623 1624 DO_2OP_SAT_ACC_SCALAR(vqdmlahb, 1, int8_t, DO_VQDMLAH_B) 1625 DO_2OP_SAT_ACC_SCALAR(vqdmlahh, 2, int16_t, DO_VQDMLAH_H) 1626 DO_2OP_SAT_ACC_SCALAR(vqdmlahw, 4, int32_t, DO_VQDMLAH_W) 1627 DO_2OP_SAT_ACC_SCALAR(vqrdmlahb, 1, int8_t, DO_VQRDMLAH_B) 1628 DO_2OP_SAT_ACC_SCALAR(vqrdmlahh, 2, int16_t, DO_VQRDMLAH_H) 1629 DO_2OP_SAT_ACC_SCALAR(vqrdmlahw, 4, int32_t, DO_VQRDMLAH_W) 1630 1631 DO_2OP_SAT_ACC_SCALAR(vqdmlashb, 1, int8_t, DO_VQDMLASH_B) 1632 DO_2OP_SAT_ACC_SCALAR(vqdmlashh, 2, int16_t, DO_VQDMLASH_H) 1633 DO_2OP_SAT_ACC_SCALAR(vqdmlashw, 4, int32_t, DO_VQDMLASH_W) 1634 DO_2OP_SAT_ACC_SCALAR(vqrdmlashb, 1, int8_t, DO_VQRDMLASH_B) 1635 DO_2OP_SAT_ACC_SCALAR(vqrdmlashh, 2, int16_t, DO_VQRDMLASH_H) 1636 DO_2OP_SAT_ACC_SCALAR(vqrdmlashw, 4, int32_t, DO_VQRDMLASH_W) 1637 1638 /* Vector by scalar plus vector */ 1639 #define DO_VMLA(D, N, M) ((N) * (M) + (D)) 1640 1641 DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA) 1642 1643 /* Vector by vector plus scalar */ 1644 #define DO_VMLAS(D, N, M) ((N) * (D) + (M)) 1645 1646 DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS) 1647 1648 /* 1649 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 1650 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 1651 * SATMASK specifies which bits of the predicate mask matter for determining 1652 * whether to propagate a saturation indication into FPSCR.QC -- for 1653 * the 16x16->32 case we must check only the bit corresponding to the T or B 1654 * half that we used, but for the 32x32->64 case we propagate if the mask 1655 * bit is set for either half. 1656 */ 1657 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1658 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1659 uint32_t rm) \ 1660 { \ 1661 LTYPE *d = vd; \ 1662 TYPE *n = vn; \ 1663 TYPE m = rm; \ 1664 uint16_t mask = mve_element_mask(env); \ 1665 unsigned le; \ 1666 bool qc = false; \ 1667 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1668 bool sat = false; \ 1669 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 1670 mergemask(&d[H##LESIZE(le)], r, mask); \ 1671 qc |= sat && (mask & SATMASK); \ 1672 } \ 1673 if (qc) { \ 1674 env->vfp.qc[0] = qc; \ 1675 } \ 1676 mve_advance_vpt(env); \ 1677 } 1678 1679 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1680 { 1681 int64_t r = ((int64_t)n * m) * 2; 1682 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1683 } 1684 1685 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1686 { 1687 /* The multiply can't overflow, but the doubling might */ 1688 int64_t r = (int64_t)n * m; 1689 if (r > INT64_MAX / 2) { 1690 *sat = true; 1691 return INT64_MAX; 1692 } else if (r < INT64_MIN / 2) { 1693 *sat = true; 1694 return INT64_MIN; 1695 } else { 1696 return r * 2; 1697 } 1698 } 1699 1700 #define SATMASK16B 1 1701 #define SATMASK16T (1 << 2) 1702 #define SATMASK32 ((1 << 4) | 1) 1703 1704 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1705 do_qdmullh, SATMASK16B) 1706 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1707 do_qdmullw, SATMASK32) 1708 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1709 do_qdmullh, SATMASK16T) 1710 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1711 do_qdmullw, SATMASK32) 1712 1713 /* 1714 * Long saturating ops 1715 */ 1716 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1717 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1718 void *vm) \ 1719 { \ 1720 LTYPE *d = vd; \ 1721 TYPE *n = vn, *m = vm; \ 1722 uint16_t mask = mve_element_mask(env); \ 1723 unsigned le; \ 1724 bool qc = false; \ 1725 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1726 bool sat = false; \ 1727 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1728 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1729 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1730 qc |= sat && (mask & SATMASK); \ 1731 } \ 1732 if (qc) { \ 1733 env->vfp.qc[0] = qc; \ 1734 } \ 1735 mve_advance_vpt(env); \ 1736 } 1737 1738 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1739 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1740 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1741 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1742 1743 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1744 { 1745 m &= 0xff; 1746 if (m == 0) { 1747 return 0; 1748 } 1749 n = revbit8(n); 1750 if (m < 8) { 1751 n >>= 8 - m; 1752 } 1753 return n; 1754 } 1755 1756 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1757 { 1758 m &= 0xff; 1759 if (m == 0) { 1760 return 0; 1761 } 1762 n = revbit16(n); 1763 if (m < 16) { 1764 n >>= 16 - m; 1765 } 1766 return n; 1767 } 1768 1769 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1770 { 1771 m &= 0xff; 1772 if (m == 0) { 1773 return 0; 1774 } 1775 n = revbit32(n); 1776 if (m < 32) { 1777 n >>= 32 - m; 1778 } 1779 return n; 1780 } 1781 1782 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1783 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1784 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1785 1786 /* 1787 * Multiply add long dual accumulate ops. 1788 */ 1789 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1790 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1791 void *vm, uint64_t a) \ 1792 { \ 1793 uint16_t mask = mve_element_mask(env); \ 1794 unsigned e; \ 1795 TYPE *n = vn, *m = vm; \ 1796 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1797 if (mask & 1) { \ 1798 if (e & 1) { \ 1799 a ODDACC \ 1800 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1801 } else { \ 1802 a EVENACC \ 1803 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1804 } \ 1805 } \ 1806 } \ 1807 mve_advance_vpt(env); \ 1808 return a; \ 1809 } 1810 1811 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1812 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1813 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1814 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1815 1816 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1817 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1818 1819 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1820 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1821 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1822 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1823 1824 /* 1825 * Multiply add dual accumulate ops 1826 */ 1827 #define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1828 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1829 void *vm, uint32_t a) \ 1830 { \ 1831 uint16_t mask = mve_element_mask(env); \ 1832 unsigned e; \ 1833 TYPE *n = vn, *m = vm; \ 1834 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1835 if (mask & 1) { \ 1836 if (e & 1) { \ 1837 a ODDACC \ 1838 n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1839 } else { \ 1840 a EVENACC \ 1841 n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1842 } \ 1843 } \ 1844 } \ 1845 mve_advance_vpt(env); \ 1846 return a; \ 1847 } 1848 1849 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ 1850 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \ 1851 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \ 1852 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC) 1853 1854 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ 1855 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \ 1856 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \ 1857 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC) 1858 1859 DO_DAV_S(vmladavs, false, +=, +=) 1860 DO_DAV_U(vmladavu, false, +=, +=) 1861 DO_DAV_S(vmlsdav, false, +=, -=) 1862 DO_DAV_S(vmladavsx, true, +=, +=) 1863 DO_DAV_S(vmlsdavx, true, +=, -=) 1864 1865 /* 1866 * Rounding multiply add long dual accumulate high. In the pseudocode 1867 * this is implemented with a 72-bit internal accumulator value of which 1868 * the top 64 bits are returned. We optimize this to avoid having to 1869 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1870 * is squashed back into 64-bits after each beat. 1871 */ 1872 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1873 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1874 void *vm, uint64_t a) \ 1875 { \ 1876 uint16_t mask = mve_element_mask(env); \ 1877 unsigned e; \ 1878 TYPE *n = vn, *m = vm; \ 1879 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1880 if (mask & 1) { \ 1881 LTYPE mul; \ 1882 if (e & 1) { \ 1883 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1884 if (SUB) { \ 1885 mul = -mul; \ 1886 } \ 1887 } else { \ 1888 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1889 } \ 1890 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1891 a += mul; \ 1892 } \ 1893 } \ 1894 mve_advance_vpt(env); \ 1895 return a; \ 1896 } 1897 1898 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1899 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1900 1901 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1902 1903 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1904 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1905 1906 /* Vector add across vector */ 1907 #define DO_VADDV(OP, ESIZE, TYPE) \ 1908 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1909 uint32_t ra) \ 1910 { \ 1911 uint16_t mask = mve_element_mask(env); \ 1912 unsigned e; \ 1913 TYPE *m = vm; \ 1914 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1915 if (mask & 1) { \ 1916 ra += m[H##ESIZE(e)]; \ 1917 } \ 1918 } \ 1919 mve_advance_vpt(env); \ 1920 return ra; \ 1921 } \ 1922 1923 DO_VADDV(vaddvsb, 1, int8_t) 1924 DO_VADDV(vaddvsh, 2, int16_t) 1925 DO_VADDV(vaddvsw, 4, int32_t) 1926 DO_VADDV(vaddvub, 1, uint8_t) 1927 DO_VADDV(vaddvuh, 2, uint16_t) 1928 DO_VADDV(vaddvuw, 4, uint32_t) 1929 1930 /* 1931 * Vector max/min across vector. Unlike VADDV, we must 1932 * read ra as the element size, not its full width. 1933 * We work with int64_t internally for simplicity. 1934 */ 1935 #define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \ 1936 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1937 uint32_t ra_in) \ 1938 { \ 1939 uint16_t mask = mve_element_mask(env); \ 1940 unsigned e; \ 1941 TYPE *m = vm; \ 1942 int64_t ra = (RATYPE)ra_in; \ 1943 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1944 if (mask & 1) { \ 1945 ra = FN(ra, m[H##ESIZE(e)]); \ 1946 } \ 1947 } \ 1948 mve_advance_vpt(env); \ 1949 return ra; \ 1950 } \ 1951 1952 #define DO_VMAXMINV_U(INSN, FN) \ 1953 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \ 1954 DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \ 1955 DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN) 1956 #define DO_VMAXMINV_S(INSN, FN) \ 1957 DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \ 1958 DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \ 1959 DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN) 1960 1961 /* 1962 * Helpers for max and min of absolute values across vector: 1963 * note that we only take the absolute value of 'm', not 'n' 1964 */ 1965 static int64_t do_maxa(int64_t n, int64_t m) 1966 { 1967 if (m < 0) { 1968 m = -m; 1969 } 1970 return MAX(n, m); 1971 } 1972 1973 static int64_t do_mina(int64_t n, int64_t m) 1974 { 1975 if (m < 0) { 1976 m = -m; 1977 } 1978 return MIN(n, m); 1979 } 1980 1981 DO_VMAXMINV_S(vmaxvs, DO_MAX) 1982 DO_VMAXMINV_U(vmaxvu, DO_MAX) 1983 DO_VMAXMINV_S(vminvs, DO_MIN) 1984 DO_VMAXMINV_U(vminvu, DO_MIN) 1985 /* 1986 * VMAXAV, VMINAV treat the general purpose input as unsigned 1987 * and the vector elements as signed. 1988 */ 1989 DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa) 1990 DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa) 1991 DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa) 1992 DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) 1993 DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) 1994 DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) 1995 1996 #define DO_VABAV(OP, ESIZE, TYPE) \ 1997 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1998 void *vm, uint32_t ra) \ 1999 { \ 2000 uint16_t mask = mve_element_mask(env); \ 2001 unsigned e; \ 2002 TYPE *m = vm, *n = vn; \ 2003 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2004 if (mask & 1) { \ 2005 int64_t n0 = n[H##ESIZE(e)]; \ 2006 int64_t m0 = m[H##ESIZE(e)]; \ 2007 uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \ 2008 ra += r; \ 2009 } \ 2010 } \ 2011 mve_advance_vpt(env); \ 2012 return ra; \ 2013 } 2014 2015 DO_VABAV(vabavsb, 1, int8_t) 2016 DO_VABAV(vabavsh, 2, int16_t) 2017 DO_VABAV(vabavsw, 4, int32_t) 2018 DO_VABAV(vabavub, 1, uint8_t) 2019 DO_VABAV(vabavuh, 2, uint16_t) 2020 DO_VABAV(vabavuw, 4, uint32_t) 2021 2022 #define DO_VADDLV(OP, TYPE, LTYPE) \ 2023 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 2024 uint64_t ra) \ 2025 { \ 2026 uint16_t mask = mve_element_mask(env); \ 2027 unsigned e; \ 2028 TYPE *m = vm; \ 2029 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 2030 if (mask & 1) { \ 2031 ra += (LTYPE)m[H4(e)]; \ 2032 } \ 2033 } \ 2034 mve_advance_vpt(env); \ 2035 return ra; \ 2036 } \ 2037 2038 DO_VADDLV(vaddlv_s, int32_t, int64_t) 2039 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 2040 2041 /* Shifts by immediate */ 2042 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 2043 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2044 void *vm, uint32_t shift) \ 2045 { \ 2046 TYPE *d = vd, *m = vm; \ 2047 uint16_t mask = mve_element_mask(env); \ 2048 unsigned e; \ 2049 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2050 mergemask(&d[H##ESIZE(e)], \ 2051 FN(m[H##ESIZE(e)], shift), mask); \ 2052 } \ 2053 mve_advance_vpt(env); \ 2054 } 2055 2056 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 2057 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2058 void *vm, uint32_t shift) \ 2059 { \ 2060 TYPE *d = vd, *m = vm; \ 2061 uint16_t mask = mve_element_mask(env); \ 2062 unsigned e; \ 2063 bool qc = false; \ 2064 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2065 bool sat = false; \ 2066 mergemask(&d[H##ESIZE(e)], \ 2067 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 2068 qc |= sat & mask & 1; \ 2069 } \ 2070 if (qc) { \ 2071 env->vfp.qc[0] = qc; \ 2072 } \ 2073 mve_advance_vpt(env); \ 2074 } 2075 2076 /* provide unsigned 2-op shift helpers for all sizes */ 2077 #define DO_2SHIFT_U(OP, FN) \ 2078 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 2079 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 2080 DO_2SHIFT(OP##w, 4, uint32_t, FN) 2081 #define DO_2SHIFT_S(OP, FN) \ 2082 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 2083 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 2084 DO_2SHIFT(OP##w, 4, int32_t, FN) 2085 2086 #define DO_2SHIFT_SAT_U(OP, FN) \ 2087 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 2088 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 2089 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 2090 #define DO_2SHIFT_SAT_S(OP, FN) \ 2091 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 2092 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 2093 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 2094 2095 DO_2SHIFT_U(vshli_u, DO_VSHLU) 2096 DO_2SHIFT_S(vshli_s, DO_VSHLS) 2097 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 2098 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 2099 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 2100 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 2101 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 2102 DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP) 2103 DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP) 2104 2105 /* Shift-and-insert; we always work with 64 bits at a time */ 2106 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 2107 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2108 void *vm, uint32_t shift) \ 2109 { \ 2110 uint64_t *d = vd, *m = vm; \ 2111 uint16_t mask; \ 2112 uint64_t shiftmask; \ 2113 unsigned e; \ 2114 if (shift == ESIZE * 8) { \ 2115 /* \ 2116 * Only VSRI can shift by <dt>; it should mean "don't \ 2117 * update the destination". The generic logic can't handle \ 2118 * this because it would try to shift by an out-of-range \ 2119 * amount, so special case it here. \ 2120 */ \ 2121 goto done; \ 2122 } \ 2123 assert(shift < ESIZE * 8); \ 2124 mask = mve_element_mask(env); \ 2125 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 2126 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 2127 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 2128 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 2129 (d[H8(e)] & ~shiftmask); \ 2130 mergemask(&d[H8(e)], r, mask); \ 2131 } \ 2132 done: \ 2133 mve_advance_vpt(env); \ 2134 } 2135 2136 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 2137 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 2138 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 2139 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 2140 2141 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 2142 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 2143 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 2144 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 2145 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 2146 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 2147 2148 /* 2149 * Long shifts taking half-sized inputs from top or bottom of the input 2150 * vector and producing a double-width result. ESIZE, TYPE are for 2151 * the input, and LESIZE, LTYPE for the output. 2152 * Unlike the normal shift helpers, we do not handle negative shift counts, 2153 * because the long shift is strictly left-only. 2154 */ 2155 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2156 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2157 void *vm, uint32_t shift) \ 2158 { \ 2159 LTYPE *d = vd; \ 2160 TYPE *m = vm; \ 2161 uint16_t mask = mve_element_mask(env); \ 2162 unsigned le; \ 2163 assert(shift <= 16); \ 2164 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2165 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 2166 mergemask(&d[H##LESIZE(le)], r, mask); \ 2167 } \ 2168 mve_advance_vpt(env); \ 2169 } 2170 2171 #define DO_VSHLL_ALL(OP, TOP) \ 2172 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 2173 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 2174 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 2175 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 2176 2177 DO_VSHLL_ALL(vshllb, false) 2178 DO_VSHLL_ALL(vshllt, true) 2179 2180 /* 2181 * Narrowing right shifts, taking a double sized input, shifting it 2182 * and putting the result in either the top or bottom half of the output. 2183 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 2184 */ 2185 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2186 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2187 void *vm, uint32_t shift) \ 2188 { \ 2189 LTYPE *m = vm; \ 2190 TYPE *d = vd; \ 2191 uint16_t mask = mve_element_mask(env); \ 2192 unsigned le; \ 2193 mask >>= ESIZE * TOP; \ 2194 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2195 TYPE r = FN(m[H##LESIZE(le)], shift); \ 2196 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2197 } \ 2198 mve_advance_vpt(env); \ 2199 } 2200 2201 #define DO_VSHRN_ALL(OP, FN) \ 2202 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 2203 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 2204 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 2205 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 2206 2207 DO_VSHRN_ALL(vshrn, DO_SHR) 2208 DO_VSHRN_ALL(vrshrn, do_urshr) 2209 2210 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 2211 bool *satp) 2212 { 2213 if (val > max) { 2214 *satp = true; 2215 return max; 2216 } else if (val < min) { 2217 *satp = true; 2218 return min; 2219 } else { 2220 return val; 2221 } 2222 } 2223 2224 /* Saturating narrowing right shifts */ 2225 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2226 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2227 void *vm, uint32_t shift) \ 2228 { \ 2229 LTYPE *m = vm; \ 2230 TYPE *d = vd; \ 2231 uint16_t mask = mve_element_mask(env); \ 2232 bool qc = false; \ 2233 unsigned le; \ 2234 mask >>= ESIZE * TOP; \ 2235 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2236 bool sat = false; \ 2237 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 2238 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2239 qc |= sat & mask & 1; \ 2240 } \ 2241 if (qc) { \ 2242 env->vfp.qc[0] = qc; \ 2243 } \ 2244 mve_advance_vpt(env); \ 2245 } 2246 2247 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 2248 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2249 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2250 2251 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 2252 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2253 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2254 2255 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 2256 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2257 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2258 2259 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 2260 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2261 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2262 2263 #define DO_SHRN_SB(N, M, SATP) \ 2264 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 2265 #define DO_SHRN_UB(N, M, SATP) \ 2266 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2267 #define DO_SHRUN_B(N, M, SATP) \ 2268 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2269 2270 #define DO_SHRN_SH(N, M, SATP) \ 2271 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 2272 #define DO_SHRN_UH(N, M, SATP) \ 2273 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2274 #define DO_SHRUN_H(N, M, SATP) \ 2275 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2276 2277 #define DO_RSHRN_SB(N, M, SATP) \ 2278 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 2279 #define DO_RSHRN_UB(N, M, SATP) \ 2280 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 2281 #define DO_RSHRUN_B(N, M, SATP) \ 2282 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 2283 2284 #define DO_RSHRN_SH(N, M, SATP) \ 2285 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 2286 #define DO_RSHRN_UH(N, M, SATP) \ 2287 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 2288 #define DO_RSHRUN_H(N, M, SATP) \ 2289 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 2290 2291 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 2292 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 2293 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 2294 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 2295 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 2296 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 2297 2298 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 2299 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 2300 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 2301 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 2302 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 2303 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 2304 2305 #define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2306 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2307 { \ 2308 LTYPE *m = vm; \ 2309 TYPE *d = vd; \ 2310 uint16_t mask = mve_element_mask(env); \ 2311 unsigned le; \ 2312 mask >>= ESIZE * TOP; \ 2313 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2314 mergemask(&d[H##ESIZE(le * 2 + TOP)], \ 2315 m[H##LESIZE(le)], mask); \ 2316 } \ 2317 mve_advance_vpt(env); \ 2318 } 2319 2320 DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t) 2321 DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t) 2322 DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t) 2323 DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t) 2324 2325 #define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2326 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2327 { \ 2328 LTYPE *m = vm; \ 2329 TYPE *d = vd; \ 2330 uint16_t mask = mve_element_mask(env); \ 2331 bool qc = false; \ 2332 unsigned le; \ 2333 mask >>= ESIZE * TOP; \ 2334 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2335 bool sat = false; \ 2336 TYPE r = FN(m[H##LESIZE(le)], &sat); \ 2337 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2338 qc |= sat & mask & 1; \ 2339 } \ 2340 if (qc) { \ 2341 env->vfp.qc[0] = qc; \ 2342 } \ 2343 mve_advance_vpt(env); \ 2344 } 2345 2346 #define DO_VMOVN_SAT_UB(BOP, TOP, FN) \ 2347 DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2348 DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2349 2350 #define DO_VMOVN_SAT_UH(BOP, TOP, FN) \ 2351 DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2352 DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2353 2354 #define DO_VMOVN_SAT_SB(BOP, TOP, FN) \ 2355 DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2356 DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2357 2358 #define DO_VMOVN_SAT_SH(BOP, TOP, FN) \ 2359 DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2360 DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2361 2362 #define DO_VQMOVN_SB(N, SATP) \ 2363 do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP) 2364 #define DO_VQMOVN_UB(N, SATP) \ 2365 do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP) 2366 #define DO_VQMOVUN_B(N, SATP) \ 2367 do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP) 2368 2369 #define DO_VQMOVN_SH(N, SATP) \ 2370 do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP) 2371 #define DO_VQMOVN_UH(N, SATP) \ 2372 do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP) 2373 #define DO_VQMOVUN_H(N, SATP) \ 2374 do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP) 2375 2376 DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB) 2377 DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH) 2378 DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB) 2379 DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH) 2380 DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B) 2381 DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H) 2382 2383 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 2384 uint32_t shift) 2385 { 2386 uint32_t *d = vd; 2387 uint16_t mask = mve_element_mask(env); 2388 unsigned e; 2389 uint32_t r; 2390 2391 /* 2392 * For each 32-bit element, we shift it left, bringing in the 2393 * low 'shift' bits of rdm at the bottom. Bits shifted out at 2394 * the top become the new rdm, if the predicate mask permits. 2395 * The final rdm value is returned to update the register. 2396 * shift == 0 here means "shift by 32 bits". 2397 */ 2398 if (shift == 0) { 2399 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2400 r = rdm; 2401 if (mask & 1) { 2402 rdm = d[H4(e)]; 2403 } 2404 mergemask(&d[H4(e)], r, mask); 2405 } 2406 } else { 2407 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 2408 2409 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2410 r = (d[H4(e)] << shift) | (rdm & shiftmask); 2411 if (mask & 1) { 2412 rdm = d[H4(e)] >> (32 - shift); 2413 } 2414 mergemask(&d[H4(e)], r, mask); 2415 } 2416 } 2417 mve_advance_vpt(env); 2418 return rdm; 2419 } 2420 2421 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2422 { 2423 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 2424 } 2425 2426 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 2427 { 2428 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 2429 } 2430 2431 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2432 { 2433 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 2434 } 2435 2436 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2437 { 2438 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 2439 } 2440 2441 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2442 { 2443 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 2444 } 2445 2446 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2447 { 2448 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 2449 } 2450 2451 /* Operate on 64-bit values, but saturate at 48 bits */ 2452 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 2453 bool round, uint32_t *sat) 2454 { 2455 int64_t val, extval; 2456 2457 if (shift <= -48) { 2458 /* Rounding the sign bit always produces 0. */ 2459 if (round) { 2460 return 0; 2461 } 2462 return src >> 63; 2463 } else if (shift < 0) { 2464 if (round) { 2465 src >>= -shift - 1; 2466 val = (src >> 1) + (src & 1); 2467 } else { 2468 val = src >> -shift; 2469 } 2470 extval = sextract64(val, 0, 48); 2471 if (!sat || val == extval) { 2472 return extval; 2473 } 2474 } else if (shift < 48) { 2475 extval = sextract64(src << shift, 0, 48); 2476 if (!sat || src == (extval >> shift)) { 2477 return extval; 2478 } 2479 } else if (!sat || src == 0) { 2480 return 0; 2481 } 2482 2483 *sat = 1; 2484 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 2485 } 2486 2487 /* Operate on 64-bit values, but saturate at 48 bits */ 2488 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 2489 bool round, uint32_t *sat) 2490 { 2491 uint64_t val, extval; 2492 2493 if (shift <= -(48 + round)) { 2494 return 0; 2495 } else if (shift < 0) { 2496 if (round) { 2497 val = src >> (-shift - 1); 2498 val = (val >> 1) + (val & 1); 2499 } else { 2500 val = src >> -shift; 2501 } 2502 extval = extract64(val, 0, 48); 2503 if (!sat || val == extval) { 2504 return extval; 2505 } 2506 } else if (shift < 48) { 2507 extval = extract64(src << shift, 0, 48); 2508 if (!sat || src == (extval >> shift)) { 2509 return extval; 2510 } 2511 } else if (!sat || src == 0) { 2512 return 0; 2513 } 2514 2515 *sat = 1; 2516 return MAKE_64BIT_MASK(0, 48); 2517 } 2518 2519 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 2520 { 2521 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 2522 } 2523 2524 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 2525 { 2526 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 2527 } 2528 2529 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2530 { 2531 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2532 } 2533 2534 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2535 { 2536 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2537 } 2538 2539 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2540 { 2541 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 2542 } 2543 2544 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 2545 { 2546 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 2547 } 2548 2549 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \ 2550 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2551 uint32_t offset, uint32_t imm) \ 2552 { \ 2553 TYPE *d = vd; \ 2554 uint16_t mask = mve_element_mask(env); \ 2555 unsigned e; \ 2556 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2557 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2558 offset = FN(offset, imm); \ 2559 } \ 2560 mve_advance_vpt(env); \ 2561 return offset; \ 2562 } 2563 2564 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ 2565 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2566 uint32_t offset, uint32_t wrap, \ 2567 uint32_t imm) \ 2568 { \ 2569 TYPE *d = vd; \ 2570 uint16_t mask = mve_element_mask(env); \ 2571 unsigned e; \ 2572 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2573 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2574 offset = FN(offset, wrap, imm); \ 2575 } \ 2576 mve_advance_vpt(env); \ 2577 return offset; \ 2578 } 2579 2580 #define DO_VIDUP_ALL(OP, FN) \ 2581 DO_VIDUP(OP##b, 1, int8_t, FN) \ 2582 DO_VIDUP(OP##h, 2, int16_t, FN) \ 2583 DO_VIDUP(OP##w, 4, int32_t, FN) 2584 2585 #define DO_VIWDUP_ALL(OP, FN) \ 2586 DO_VIWDUP(OP##b, 1, int8_t, FN) \ 2587 DO_VIWDUP(OP##h, 2, int16_t, FN) \ 2588 DO_VIWDUP(OP##w, 4, int32_t, FN) 2589 2590 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2591 { 2592 offset += imm; 2593 if (offset == wrap) { 2594 offset = 0; 2595 } 2596 return offset; 2597 } 2598 2599 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2600 { 2601 if (offset == 0) { 2602 offset = wrap; 2603 } 2604 offset -= imm; 2605 return offset; 2606 } 2607 2608 DO_VIDUP_ALL(vidup, DO_ADD) 2609 DO_VIWDUP_ALL(viwdup, do_add_wrap) 2610 DO_VIWDUP_ALL(vdwdup, do_sub_wrap) 2611 2612 /* 2613 * Vector comparison. 2614 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. 2615 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. 2616 * P0 bits otherwise are updated with the results of the comparisons. 2617 * We must also keep unchanged the MASK fields at the top of v7m.vpr. 2618 */ 2619 #define DO_VCMP(OP, ESIZE, TYPE, FN) \ 2620 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 2621 { \ 2622 TYPE *n = vn, *m = vm; \ 2623 uint16_t mask = mve_element_mask(env); \ 2624 uint16_t eci_mask = mve_eci_mask(env); \ 2625 uint16_t beatpred = 0; \ 2626 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2627 unsigned e; \ 2628 for (e = 0; e < 16 / ESIZE; e++) { \ 2629 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ 2630 /* Comparison sets 0/1 bits for each byte in the element */ \ 2631 beatpred |= r * emask; \ 2632 emask <<= ESIZE; \ 2633 } \ 2634 beatpred &= mask; \ 2635 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2636 (beatpred & eci_mask); \ 2637 mve_advance_vpt(env); \ 2638 } 2639 2640 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ 2641 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 2642 uint32_t rm) \ 2643 { \ 2644 TYPE *n = vn; \ 2645 uint16_t mask = mve_element_mask(env); \ 2646 uint16_t eci_mask = mve_eci_mask(env); \ 2647 uint16_t beatpred = 0; \ 2648 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2649 unsigned e; \ 2650 for (e = 0; e < 16 / ESIZE; e++) { \ 2651 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \ 2652 /* Comparison sets 0/1 bits for each byte in the element */ \ 2653 beatpred |= r * emask; \ 2654 emask <<= ESIZE; \ 2655 } \ 2656 beatpred &= mask; \ 2657 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2658 (beatpred & eci_mask); \ 2659 mve_advance_vpt(env); \ 2660 } 2661 2662 #define DO_VCMP_S(OP, FN) \ 2663 DO_VCMP(OP##b, 1, int8_t, FN) \ 2664 DO_VCMP(OP##h, 2, int16_t, FN) \ 2665 DO_VCMP(OP##w, 4, int32_t, FN) \ 2666 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ 2667 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ 2668 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) 2669 2670 #define DO_VCMP_U(OP, FN) \ 2671 DO_VCMP(OP##b, 1, uint8_t, FN) \ 2672 DO_VCMP(OP##h, 2, uint16_t, FN) \ 2673 DO_VCMP(OP##w, 4, uint32_t, FN) \ 2674 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ 2675 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ 2676 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) 2677 2678 #define DO_EQ(N, M) ((N) == (M)) 2679 #define DO_NE(N, M) ((N) != (M)) 2680 #define DO_EQ(N, M) ((N) == (M)) 2681 #define DO_EQ(N, M) ((N) == (M)) 2682 #define DO_GE(N, M) ((N) >= (M)) 2683 #define DO_LT(N, M) ((N) < (M)) 2684 #define DO_GT(N, M) ((N) > (M)) 2685 #define DO_LE(N, M) ((N) <= (M)) 2686 2687 DO_VCMP_U(vcmpeq, DO_EQ) 2688 DO_VCMP_U(vcmpne, DO_NE) 2689 DO_VCMP_U(vcmpcs, DO_GE) 2690 DO_VCMP_U(vcmphi, DO_GT) 2691 DO_VCMP_S(vcmpge, DO_GE) 2692 DO_VCMP_S(vcmplt, DO_LT) 2693 DO_VCMP_S(vcmpgt, DO_GT) 2694 DO_VCMP_S(vcmple, DO_LE) 2695 2696 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) 2697 { 2698 /* 2699 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n] 2700 * but note that whether bytes are written to Qd is still subject 2701 * to (all forms of) predication in the usual way. 2702 */ 2703 uint64_t *d = vd, *n = vn, *m = vm; 2704 uint16_t mask = mve_element_mask(env); 2705 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 2706 unsigned e; 2707 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) { 2708 uint64_t r = m[H8(e)]; 2709 mergemask(&r, n[H8(e)], p0); 2710 mergemask(&d[H8(e)], r, mask); 2711 } 2712 mve_advance_vpt(env); 2713 } 2714 2715 void HELPER(mve_vpnot)(CPUARMState *env) 2716 { 2717 /* 2718 * P0 bits for unexecuted beats (where eci_mask is 0) are unchanged. 2719 * P0 bits for predicated lanes in executed bits (where mask is 0) are 0. 2720 * P0 bits otherwise are inverted. 2721 * (This is the same logic as VCMP.) 2722 * This insn is itself subject to predication and to beat-wise execution, 2723 * and after it executes VPT state advances in the usual way. 2724 */ 2725 uint16_t mask = mve_element_mask(env); 2726 uint16_t eci_mask = mve_eci_mask(env); 2727 uint16_t beatpred = ~env->v7m.vpr & mask; 2728 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask); 2729 mve_advance_vpt(env); 2730 } 2731 2732 /* 2733 * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed, 2734 * otherwise set according to value of Rn. The calculation of 2735 * newmask here works in the same way as the calculation of the 2736 * ltpmask in mve_element_mask(), but we have pre-calculated 2737 * the masklen in the generated code. 2738 */ 2739 void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen) 2740 { 2741 uint16_t mask = mve_element_mask(env); 2742 uint16_t eci_mask = mve_eci_mask(env); 2743 uint16_t newmask; 2744 2745 assert(masklen <= 16); 2746 newmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 2747 newmask &= mask; 2748 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask); 2749 mve_advance_vpt(env); 2750 } 2751 2752 #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ 2753 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2754 { \ 2755 TYPE *d = vd, *m = vm; \ 2756 uint16_t mask = mve_element_mask(env); \ 2757 unsigned e; \ 2758 bool qc = false; \ 2759 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2760 bool sat = false; \ 2761 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)], &sat), mask); \ 2762 qc |= sat & mask & 1; \ 2763 } \ 2764 if (qc) { \ 2765 env->vfp.qc[0] = qc; \ 2766 } \ 2767 mve_advance_vpt(env); \ 2768 } 2769 2770 #define DO_VQABS_B(N, SATP) \ 2771 do_sat_bhs(DO_ABS((int64_t)N), INT8_MIN, INT8_MAX, SATP) 2772 #define DO_VQABS_H(N, SATP) \ 2773 do_sat_bhs(DO_ABS((int64_t)N), INT16_MIN, INT16_MAX, SATP) 2774 #define DO_VQABS_W(N, SATP) \ 2775 do_sat_bhs(DO_ABS((int64_t)N), INT32_MIN, INT32_MAX, SATP) 2776 2777 #define DO_VQNEG_B(N, SATP) do_sat_bhs(-(int64_t)N, INT8_MIN, INT8_MAX, SATP) 2778 #define DO_VQNEG_H(N, SATP) do_sat_bhs(-(int64_t)N, INT16_MIN, INT16_MAX, SATP) 2779 #define DO_VQNEG_W(N, SATP) do_sat_bhs(-(int64_t)N, INT32_MIN, INT32_MAX, SATP) 2780 2781 DO_1OP_SAT(vqabsb, 1, int8_t, DO_VQABS_B) 2782 DO_1OP_SAT(vqabsh, 2, int16_t, DO_VQABS_H) 2783 DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W) 2784 2785 DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B) 2786 DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H) 2787 DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W) 2788 2789 /* 2790 * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its 2791 * absolute value; we then do an unsigned comparison. 2792 */ 2793 #define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \ 2794 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2795 { \ 2796 UTYPE *d = vd; \ 2797 STYPE *m = vm; \ 2798 uint16_t mask = mve_element_mask(env); \ 2799 unsigned e; \ 2800 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2801 UTYPE r = DO_ABS(m[H##ESIZE(e)]); \ 2802 r = FN(d[H##ESIZE(e)], r); \ 2803 mergemask(&d[H##ESIZE(e)], r, mask); \ 2804 } \ 2805 mve_advance_vpt(env); \ 2806 } 2807 2808 DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX) 2809 DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX) 2810 DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) 2811 DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) 2812 DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) 2813 DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) 2814 2815 /* 2816 * 2-operand floating point. Note that if an element is partially 2817 * predicated we must do the FP operation to update the non-predicated 2818 * bytes, but we must be careful to avoid updating the FP exception 2819 * state unless byte 0 of the element was unpredicated. 2820 */ 2821 #define DO_2OP_FP(OP, ESIZE, TYPE, FN) \ 2822 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2823 void *vd, void *vn, void *vm) \ 2824 { \ 2825 TYPE *d = vd, *n = vn, *m = vm; \ 2826 TYPE r; \ 2827 uint16_t mask = mve_element_mask(env); \ 2828 unsigned e; \ 2829 float_status *fpst; \ 2830 float_status scratch_fpst; \ 2831 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2832 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2833 continue; \ 2834 } \ 2835 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2836 if (!(mask & 1)) { \ 2837 /* We need the result but without updating flags */ \ 2838 scratch_fpst = *fpst; \ 2839 fpst = &scratch_fpst; \ 2840 } \ 2841 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 2842 mergemask(&d[H##ESIZE(e)], r, mask); \ 2843 } \ 2844 mve_advance_vpt(env); \ 2845 } 2846 2847 #define DO_2OP_FP_ALL(OP, FN) \ 2848 DO_2OP_FP(OP##h, 2, float16, float16_##FN) \ 2849 DO_2OP_FP(OP##s, 4, float32, float32_##FN) 2850 2851 DO_2OP_FP_ALL(vfadd, add) 2852 DO_2OP_FP_ALL(vfsub, sub) 2853 DO_2OP_FP_ALL(vfmul, mul) 2854 2855 static inline float16 float16_abd(float16 a, float16 b, float_status *s) 2856 { 2857 return float16_abs(float16_sub(a, b, s)); 2858 } 2859 2860 static inline float32 float32_abd(float32 a, float32 b, float_status *s) 2861 { 2862 return float32_abs(float32_sub(a, b, s)); 2863 } 2864 2865 DO_2OP_FP_ALL(vfabd, abd) 2866 DO_2OP_FP_ALL(vmaxnm, maxnum) 2867 DO_2OP_FP_ALL(vminnm, minnum) 2868 2869 static inline float16 float16_maxnuma(float16 a, float16 b, float_status *s) 2870 { 2871 return float16_maxnum(float16_abs(a), float16_abs(b), s); 2872 } 2873 2874 static inline float32 float32_maxnuma(float32 a, float32 b, float_status *s) 2875 { 2876 return float32_maxnum(float32_abs(a), float32_abs(b), s); 2877 } 2878 2879 static inline float16 float16_minnuma(float16 a, float16 b, float_status *s) 2880 { 2881 return float16_minnum(float16_abs(a), float16_abs(b), s); 2882 } 2883 2884 static inline float32 float32_minnuma(float32 a, float32 b, float_status *s) 2885 { 2886 return float32_minnum(float32_abs(a), float32_abs(b), s); 2887 } 2888 2889 DO_2OP_FP_ALL(vmaxnma, maxnuma) 2890 DO_2OP_FP_ALL(vminnma, minnuma) 2891 2892 #define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \ 2893 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2894 void *vd, void *vn, void *vm) \ 2895 { \ 2896 TYPE *d = vd, *n = vn, *m = vm; \ 2897 TYPE r[16 / ESIZE]; \ 2898 uint16_t tm, mask = mve_element_mask(env); \ 2899 unsigned e; \ 2900 float_status *fpst; \ 2901 float_status scratch_fpst; \ 2902 /* Calculate all results first to avoid overwriting inputs */ \ 2903 for (e = 0, tm = mask; e < 16 / ESIZE; e++, tm >>= ESIZE) { \ 2904 if ((tm & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2905 r[e] = 0; \ 2906 continue; \ 2907 } \ 2908 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2909 if (!(tm & 1)) { \ 2910 /* We need the result but without updating flags */ \ 2911 scratch_fpst = *fpst; \ 2912 fpst = &scratch_fpst; \ 2913 } \ 2914 if (!(e & 1)) { \ 2915 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)], fpst); \ 2916 } else { \ 2917 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)], fpst); \ 2918 } \ 2919 } \ 2920 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2921 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 2922 } \ 2923 mve_advance_vpt(env); \ 2924 } 2925 2926 DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, float16_add) 2927 DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add) 2928 DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub) 2929 DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) 2930 2931 #define DO_VFMA(OP, ESIZE, TYPE, CHS) \ 2932 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2933 void *vd, void *vn, void *vm) \ 2934 { \ 2935 TYPE *d = vd, *n = vn, *m = vm; \ 2936 TYPE r; \ 2937 uint16_t mask = mve_element_mask(env); \ 2938 unsigned e; \ 2939 float_status *fpst; \ 2940 float_status scratch_fpst; \ 2941 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2942 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2943 continue; \ 2944 } \ 2945 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2946 if (!(mask & 1)) { \ 2947 /* We need the result but without updating flags */ \ 2948 scratch_fpst = *fpst; \ 2949 fpst = &scratch_fpst; \ 2950 } \ 2951 r = n[H##ESIZE(e)]; \ 2952 if (CHS) { \ 2953 r = TYPE##_chs(r); \ 2954 } \ 2955 r = TYPE##_muladd(r, m[H##ESIZE(e)], d[H##ESIZE(e)], \ 2956 0, fpst); \ 2957 mergemask(&d[H##ESIZE(e)], r, mask); \ 2958 } \ 2959 mve_advance_vpt(env); \ 2960 } 2961 2962 DO_VFMA(vfmah, 2, float16, false) 2963 DO_VFMA(vfmas, 4, float32, false) 2964 DO_VFMA(vfmsh, 2, float16, true) 2965 DO_VFMA(vfmss, 4, float32, true) 2966 2967 #define DO_VCMLA(OP, ESIZE, TYPE, ROT, FN) \ 2968 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2969 void *vd, void *vn, void *vm) \ 2970 { \ 2971 TYPE *d = vd, *n = vn, *m = vm; \ 2972 TYPE r0, r1, e1, e2, e3, e4; \ 2973 uint16_t mask = mve_element_mask(env); \ 2974 unsigned e; \ 2975 float_status *fpst0, *fpst1; \ 2976 float_status scratch_fpst; \ 2977 /* We loop through pairs of elements at a time */ \ 2978 for (e = 0; e < 16 / ESIZE; e += 2, mask >>= ESIZE * 2) { \ 2979 if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) == 0) { \ 2980 continue; \ 2981 } \ 2982 fpst0 = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2983 fpst1 = fpst0; \ 2984 if (!(mask & 1)) { \ 2985 scratch_fpst = *fpst0; \ 2986 fpst0 = &scratch_fpst; \ 2987 } \ 2988 if (!(mask & (1 << ESIZE))) { \ 2989 scratch_fpst = *fpst1; \ 2990 fpst1 = &scratch_fpst; \ 2991 } \ 2992 switch (ROT) { \ 2993 case 0: \ 2994 e1 = m[H##ESIZE(e)]; \ 2995 e2 = n[H##ESIZE(e)]; \ 2996 e3 = m[H##ESIZE(e + 1)]; \ 2997 e4 = n[H##ESIZE(e)]; \ 2998 break; \ 2999 case 1: \ 3000 e1 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 3001 e2 = n[H##ESIZE(e + 1)]; \ 3002 e3 = m[H##ESIZE(e)]; \ 3003 e4 = n[H##ESIZE(e + 1)]; \ 3004 break; \ 3005 case 2: \ 3006 e1 = TYPE##_chs(m[H##ESIZE(e)]); \ 3007 e2 = n[H##ESIZE(e)]; \ 3008 e3 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 3009 e4 = n[H##ESIZE(e)]; \ 3010 break; \ 3011 case 3: \ 3012 e1 = m[H##ESIZE(e + 1)]; \ 3013 e2 = n[H##ESIZE(e + 1)]; \ 3014 e3 = TYPE##_chs(m[H##ESIZE(e)]); \ 3015 e4 = n[H##ESIZE(e + 1)]; \ 3016 break; \ 3017 default: \ 3018 g_assert_not_reached(); \ 3019 } \ 3020 r0 = FN(e2, e1, d[H##ESIZE(e)], fpst0); \ 3021 r1 = FN(e4, e3, d[H##ESIZE(e + 1)], fpst1); \ 3022 mergemask(&d[H##ESIZE(e)], r0, mask); \ 3023 mergemask(&d[H##ESIZE(e + 1)], r1, mask >> ESIZE); \ 3024 } \ 3025 mve_advance_vpt(env); \ 3026 } 3027 3028 #define DO_VCMULH(N, M, D, S) float16_mul(N, M, S) 3029 #define DO_VCMULS(N, M, D, S) float32_mul(N, M, S) 3030 3031 #define DO_VCMLAH(N, M, D, S) float16_muladd(N, M, D, 0, S) 3032 #define DO_VCMLAS(N, M, D, S) float32_muladd(N, M, D, 0, S) 3033 3034 DO_VCMLA(vcmul0h, 2, float16, 0, DO_VCMULH) 3035 DO_VCMLA(vcmul0s, 4, float32, 0, DO_VCMULS) 3036 DO_VCMLA(vcmul90h, 2, float16, 1, DO_VCMULH) 3037 DO_VCMLA(vcmul90s, 4, float32, 1, DO_VCMULS) 3038 DO_VCMLA(vcmul180h, 2, float16, 2, DO_VCMULH) 3039 DO_VCMLA(vcmul180s, 4, float32, 2, DO_VCMULS) 3040 DO_VCMLA(vcmul270h, 2, float16, 3, DO_VCMULH) 3041 DO_VCMLA(vcmul270s, 4, float32, 3, DO_VCMULS) 3042 3043 DO_VCMLA(vcmla0h, 2, float16, 0, DO_VCMLAH) 3044 DO_VCMLA(vcmla0s, 4, float32, 0, DO_VCMLAS) 3045 DO_VCMLA(vcmla90h, 2, float16, 1, DO_VCMLAH) 3046 DO_VCMLA(vcmla90s, 4, float32, 1, DO_VCMLAS) 3047 DO_VCMLA(vcmla180h, 2, float16, 2, DO_VCMLAH) 3048 DO_VCMLA(vcmla180s, 4, float32, 2, DO_VCMLAS) 3049 DO_VCMLA(vcmla270h, 2, float16, 3, DO_VCMLAH) 3050 DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) 3051 3052 #define DO_2OP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3053 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3054 void *vd, void *vn, uint32_t rm) \ 3055 { \ 3056 TYPE *d = vd, *n = vn; \ 3057 TYPE r, m = rm; \ 3058 uint16_t mask = mve_element_mask(env); \ 3059 unsigned e; \ 3060 float_status *fpst; \ 3061 float_status scratch_fpst; \ 3062 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3063 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3064 continue; \ 3065 } \ 3066 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3067 if (!(mask & 1)) { \ 3068 /* We need the result but without updating flags */ \ 3069 scratch_fpst = *fpst; \ 3070 fpst = &scratch_fpst; \ 3071 } \ 3072 r = FN(n[H##ESIZE(e)], m, fpst); \ 3073 mergemask(&d[H##ESIZE(e)], r, mask); \ 3074 } \ 3075 mve_advance_vpt(env); \ 3076 } 3077 3078 #define DO_2OP_FP_SCALAR_ALL(OP, FN) \ 3079 DO_2OP_FP_SCALAR(OP##h, 2, float16, float16_##FN) \ 3080 DO_2OP_FP_SCALAR(OP##s, 4, float32, float32_##FN) 3081 3082 DO_2OP_FP_SCALAR_ALL(vfadd_scalar, add) 3083 DO_2OP_FP_SCALAR_ALL(vfsub_scalar, sub) 3084 DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) 3085 3086 #define DO_2OP_FP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 3087 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3088 void *vd, void *vn, uint32_t rm) \ 3089 { \ 3090 TYPE *d = vd, *n = vn; \ 3091 TYPE r, m = rm; \ 3092 uint16_t mask = mve_element_mask(env); \ 3093 unsigned e; \ 3094 float_status *fpst; \ 3095 float_status scratch_fpst; \ 3096 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3097 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3098 continue; \ 3099 } \ 3100 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3101 if (!(mask & 1)) { \ 3102 /* We need the result but without updating flags */ \ 3103 scratch_fpst = *fpst; \ 3104 fpst = &scratch_fpst; \ 3105 } \ 3106 r = FN(n[H##ESIZE(e)], m, d[H##ESIZE(e)], 0, fpst); \ 3107 mergemask(&d[H##ESIZE(e)], r, mask); \ 3108 } \ 3109 mve_advance_vpt(env); \ 3110 } 3111 3112 /* VFMAS is vector * vector + scalar, so swap op2 and op3 */ 3113 #define DO_VFMAS_SCALARH(N, M, D, F, S) float16_muladd(N, D, M, F, S) 3114 #define DO_VFMAS_SCALARS(N, M, D, F, S) float32_muladd(N, D, M, F, S) 3115 3116 /* VFMA is vector * scalar + vector */ 3117 DO_2OP_FP_ACC_SCALAR(vfma_scalarh, 2, float16, float16_muladd) 3118 DO_2OP_FP_ACC_SCALAR(vfma_scalars, 4, float32, float32_muladd) 3119 DO_2OP_FP_ACC_SCALAR(vfmas_scalarh, 2, float16, DO_VFMAS_SCALARH) 3120 DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) 3121 3122 /* Floating point max/min across vector. */ 3123 #define DO_FP_VMAXMINV(OP, ESIZE, TYPE, ABS, FN) \ 3124 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 3125 uint32_t ra_in) \ 3126 { \ 3127 uint16_t mask = mve_element_mask(env); \ 3128 unsigned e; \ 3129 TYPE *m = vm; \ 3130 TYPE ra = (TYPE)ra_in; \ 3131 float_status *fpst = \ 3132 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3133 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3134 if (mask & 1) { \ 3135 TYPE v = m[H##ESIZE(e)]; \ 3136 if (TYPE##_is_signaling_nan(ra, fpst)) { \ 3137 ra = TYPE##_silence_nan(ra, fpst); \ 3138 float_raise(float_flag_invalid, fpst); \ 3139 } \ 3140 if (TYPE##_is_signaling_nan(v, fpst)) { \ 3141 v = TYPE##_silence_nan(v, fpst); \ 3142 float_raise(float_flag_invalid, fpst); \ 3143 } \ 3144 if (ABS) { \ 3145 v = TYPE##_abs(v); \ 3146 } \ 3147 ra = FN(ra, v, fpst); \ 3148 } \ 3149 } \ 3150 mve_advance_vpt(env); \ 3151 return ra; \ 3152 } \ 3153 3154 #define NOP(X) (X) 3155 3156 DO_FP_VMAXMINV(vmaxnmvh, 2, float16, false, float16_maxnum) 3157 DO_FP_VMAXMINV(vmaxnmvs, 4, float32, false, float32_maxnum) 3158 DO_FP_VMAXMINV(vminnmvh, 2, float16, false, float16_minnum) 3159 DO_FP_VMAXMINV(vminnmvs, 4, float32, false, float32_minnum) 3160 DO_FP_VMAXMINV(vmaxnmavh, 2, float16, true, float16_maxnum) 3161 DO_FP_VMAXMINV(vmaxnmavs, 4, float32, true, float32_maxnum) 3162 DO_FP_VMAXMINV(vminnmavh, 2, float16, true, float16_minnum) 3163 DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) 3164 3165 /* FP compares; note that all comparisons signal InvalidOp for QNaNs */ 3166 #define DO_VCMP_FP(OP, ESIZE, TYPE, FN) \ 3167 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 3168 { \ 3169 TYPE *n = vn, *m = vm; \ 3170 uint16_t mask = mve_element_mask(env); \ 3171 uint16_t eci_mask = mve_eci_mask(env); \ 3172 uint16_t beatpred = 0; \ 3173 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3174 unsigned e; \ 3175 float_status *fpst; \ 3176 float_status scratch_fpst; \ 3177 bool r; \ 3178 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3179 if ((mask & emask) == 0) { \ 3180 continue; \ 3181 } \ 3182 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3183 if (!(mask & (1 << (e * ESIZE)))) { \ 3184 /* We need the result but without updating flags */ \ 3185 scratch_fpst = *fpst; \ 3186 fpst = &scratch_fpst; \ 3187 } \ 3188 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 3189 /* Comparison sets 0/1 bits for each byte in the element */ \ 3190 beatpred |= r * emask; \ 3191 } \ 3192 beatpred &= mask; \ 3193 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3194 (beatpred & eci_mask); \ 3195 mve_advance_vpt(env); \ 3196 } 3197 3198 #define DO_VCMP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3199 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 3200 uint32_t rm) \ 3201 { \ 3202 TYPE *n = vn; \ 3203 uint16_t mask = mve_element_mask(env); \ 3204 uint16_t eci_mask = mve_eci_mask(env); \ 3205 uint16_t beatpred = 0; \ 3206 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3207 unsigned e; \ 3208 float_status *fpst; \ 3209 float_status scratch_fpst; \ 3210 bool r; \ 3211 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3212 if ((mask & emask) == 0) { \ 3213 continue; \ 3214 } \ 3215 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3216 if (!(mask & (1 << (e * ESIZE)))) { \ 3217 /* We need the result but without updating flags */ \ 3218 scratch_fpst = *fpst; \ 3219 fpst = &scratch_fpst; \ 3220 } \ 3221 r = FN(n[H##ESIZE(e)], (TYPE)rm, fpst); \ 3222 /* Comparison sets 0/1 bits for each byte in the element */ \ 3223 beatpred |= r * emask; \ 3224 } \ 3225 beatpred &= mask; \ 3226 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3227 (beatpred & eci_mask); \ 3228 mve_advance_vpt(env); \ 3229 } 3230 3231 #define DO_VCMP_FP_BOTH(VOP, SOP, ESIZE, TYPE, FN) \ 3232 DO_VCMP_FP(VOP, ESIZE, TYPE, FN) \ 3233 DO_VCMP_FP_SCALAR(SOP, ESIZE, TYPE, FN) 3234 3235 /* 3236 * Some care is needed here to get the correct result for the unordered case. 3237 * Architecturally EQ, GE and GT are defined to be false for unordered, but 3238 * the NE, LT and LE comparisons are defined as simple logical inverses of 3239 * EQ, GE and GT and so they must return true for unordered. The softfloat 3240 * comparison functions float*_{eq,le,lt} all return false for unordered. 3241 */ 3242 #define DO_GE16(X, Y, S) float16_le(Y, X, S) 3243 #define DO_GE32(X, Y, S) float32_le(Y, X, S) 3244 #define DO_GT16(X, Y, S) float16_lt(Y, X, S) 3245 #define DO_GT32(X, Y, S) float32_lt(Y, X, S) 3246 3247 DO_VCMP_FP_BOTH(vfcmpeqh, vfcmpeq_scalarh, 2, float16, float16_eq) 3248 DO_VCMP_FP_BOTH(vfcmpeqs, vfcmpeq_scalars, 4, float32, float32_eq) 3249 3250 DO_VCMP_FP_BOTH(vfcmpneh, vfcmpne_scalarh, 2, float16, !float16_eq) 3251 DO_VCMP_FP_BOTH(vfcmpnes, vfcmpne_scalars, 4, float32, !float32_eq) 3252 3253 DO_VCMP_FP_BOTH(vfcmpgeh, vfcmpge_scalarh, 2, float16, DO_GE16) 3254 DO_VCMP_FP_BOTH(vfcmpges, vfcmpge_scalars, 4, float32, DO_GE32) 3255 3256 DO_VCMP_FP_BOTH(vfcmplth, vfcmplt_scalarh, 2, float16, !DO_GE16) 3257 DO_VCMP_FP_BOTH(vfcmplts, vfcmplt_scalars, 4, float32, !DO_GE32) 3258 3259 DO_VCMP_FP_BOTH(vfcmpgth, vfcmpgt_scalarh, 2, float16, DO_GT16) 3260 DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float32, DO_GT32) 3261 3262 DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) 3263 DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) 3264 3265 #define DO_VCVT_FIXED(OP, ESIZE, TYPE, FN) \ 3266 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm, \ 3267 uint32_t shift) \ 3268 { \ 3269 TYPE *d = vd, *m = vm; \ 3270 TYPE r; \ 3271 uint16_t mask = mve_element_mask(env); \ 3272 unsigned e; \ 3273 float_status *fpst; \ 3274 float_status scratch_fpst; \ 3275 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3276 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3277 continue; \ 3278 } \ 3279 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3280 if (!(mask & 1)) { \ 3281 /* We need the result but without updating flags */ \ 3282 scratch_fpst = *fpst; \ 3283 fpst = &scratch_fpst; \ 3284 } \ 3285 r = FN(m[H##ESIZE(e)], shift, fpst); \ 3286 mergemask(&d[H##ESIZE(e)], r, mask); \ 3287 } \ 3288 mve_advance_vpt(env); \ 3289 } 3290 3291 DO_VCVT_FIXED(vcvt_sh, 2, int16_t, helper_vfp_shtoh) 3292 DO_VCVT_FIXED(vcvt_uh, 2, uint16_t, helper_vfp_uhtoh) 3293 DO_VCVT_FIXED(vcvt_hs, 2, int16_t, helper_vfp_toshh_round_to_zero) 3294 DO_VCVT_FIXED(vcvt_hu, 2, uint16_t, helper_vfp_touhh_round_to_zero) 3295 DO_VCVT_FIXED(vcvt_sf, 4, int32_t, helper_vfp_sltos) 3296 DO_VCVT_FIXED(vcvt_uf, 4, uint32_t, helper_vfp_ultos) 3297 DO_VCVT_FIXED(vcvt_fs, 4, int32_t, helper_vfp_tosls_round_to_zero) 3298 DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) 3299 3300 /* VCVT with specified rmode */ 3301 #define DO_VCVT_RMODE(OP, ESIZE, TYPE, FN) \ 3302 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3303 void *vd, void *vm, uint32_t rmode) \ 3304 { \ 3305 TYPE *d = vd, *m = vm; \ 3306 TYPE r; \ 3307 uint16_t mask = mve_element_mask(env); \ 3308 unsigned e; \ 3309 float_status *fpst; \ 3310 float_status scratch_fpst; \ 3311 float_status *base_fpst = \ 3312 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3313 uint32_t prev_rmode = get_float_rounding_mode(base_fpst); \ 3314 set_float_rounding_mode(rmode, base_fpst); \ 3315 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3316 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3317 continue; \ 3318 } \ 3319 fpst = base_fpst; \ 3320 if (!(mask & 1)) { \ 3321 /* We need the result but without updating flags */ \ 3322 scratch_fpst = *fpst; \ 3323 fpst = &scratch_fpst; \ 3324 } \ 3325 r = FN(m[H##ESIZE(e)], 0, fpst); \ 3326 mergemask(&d[H##ESIZE(e)], r, mask); \ 3327 } \ 3328 set_float_rounding_mode(prev_rmode, base_fpst); \ 3329 mve_advance_vpt(env); \ 3330 } 3331 3332 DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_toshh) 3333 DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) 3334 DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) 3335 DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) 3336 3337 #define DO_VRINT_RM_H(M, F, S) helper_rinth(M, S) 3338 #define DO_VRINT_RM_S(M, F, S) helper_rints(M, S) 3339 3340 DO_VCVT_RMODE(vrint_rm_h, 2, uint16_t, DO_VRINT_RM_H) 3341 DO_VCVT_RMODE(vrint_rm_s, 4, uint32_t, DO_VRINT_RM_S) 3342 3343 /* 3344 * VCVT between halfprec and singleprec. As usual for halfprec 3345 * conversions, FZ16 is ignored and AHP is observed. 3346 */ 3347 static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) 3348 { 3349 uint16_t *d = vd; 3350 uint32_t *m = vm; 3351 uint16_t r; 3352 uint16_t mask = mve_element_mask(env); 3353 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3354 unsigned e; 3355 float_status *fpst; 3356 float_status scratch_fpst; 3357 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3358 bool old_fz = get_flush_to_zero(base_fpst); 3359 set_flush_to_zero(false, base_fpst); 3360 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3361 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3362 continue; 3363 } 3364 fpst = base_fpst; 3365 if (!(mask & 1)) { 3366 /* We need the result but without updating flags */ 3367 scratch_fpst = *fpst; 3368 fpst = &scratch_fpst; 3369 } 3370 r = float32_to_float16(m[H4(e)], ieee, fpst); 3371 mergemask(&d[H2(e * 2 + top)], r, mask >> (top * 2)); 3372 } 3373 set_flush_to_zero(old_fz, base_fpst); 3374 mve_advance_vpt(env); 3375 } 3376 3377 static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) 3378 { 3379 uint32_t *d = vd; 3380 uint16_t *m = vm; 3381 uint32_t r; 3382 uint16_t mask = mve_element_mask(env); 3383 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3384 unsigned e; 3385 float_status *fpst; 3386 float_status scratch_fpst; 3387 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3388 bool old_fiz = get_flush_inputs_to_zero(base_fpst); 3389 set_flush_inputs_to_zero(false, base_fpst); 3390 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3391 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3392 continue; 3393 } 3394 fpst = base_fpst; 3395 if (!(mask & (1 << (top * 2)))) { 3396 /* We need the result but without updating flags */ 3397 scratch_fpst = *fpst; 3398 fpst = &scratch_fpst; 3399 } 3400 r = float16_to_float32(m[H2(e * 2 + top)], ieee, fpst); 3401 mergemask(&d[H4(e)], r, mask); 3402 } 3403 set_flush_inputs_to_zero(old_fiz, base_fpst); 3404 mve_advance_vpt(env); 3405 } 3406 3407 void HELPER(mve_vcvtb_sh)(CPUARMState *env, void *vd, void *vm) 3408 { 3409 do_vcvt_sh(env, vd, vm, 0); 3410 } 3411 void HELPER(mve_vcvtt_sh)(CPUARMState *env, void *vd, void *vm) 3412 { 3413 do_vcvt_sh(env, vd, vm, 1); 3414 } 3415 void HELPER(mve_vcvtb_hs)(CPUARMState *env, void *vd, void *vm) 3416 { 3417 do_vcvt_hs(env, vd, vm, 0); 3418 } 3419 void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) 3420 { 3421 do_vcvt_hs(env, vd, vm, 1); 3422 } 3423 3424 #define DO_1OP_FP(OP, ESIZE, TYPE, FN) \ 3425 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm) \ 3426 { \ 3427 TYPE *d = vd, *m = vm; \ 3428 TYPE r; \ 3429 uint16_t mask = mve_element_mask(env); \ 3430 unsigned e; \ 3431 float_status *fpst; \ 3432 float_status scratch_fpst; \ 3433 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3434 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3435 continue; \ 3436 } \ 3437 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3438 if (!(mask & 1)) { \ 3439 /* We need the result but without updating flags */ \ 3440 scratch_fpst = *fpst; \ 3441 fpst = &scratch_fpst; \ 3442 } \ 3443 r = FN(m[H##ESIZE(e)], fpst); \ 3444 mergemask(&d[H##ESIZE(e)], r, mask); \ 3445 } \ 3446 mve_advance_vpt(env); \ 3447 } 3448 3449 DO_1OP_FP(vrintx_h, 2, float16, float16_round_to_int) 3450 DO_1OP_FP(vrintx_s, 4, float32, float32_round_to_int) 3451