1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "accel/tcg/cpu-ldst.h" 26 #include "tcg/tcg.h" 27 #include "fpu/softfloat.h" 28 #include "crypto/clmul.h" 29 30 static uint16_t mve_eci_mask(CPUARMState *env) 31 { 32 /* 33 * Return the mask of which elements in the MVE vector correspond 34 * to beats being executed. The mask has 1 bits for executed lanes 35 * and 0 bits where ECI says this beat was already executed. 36 */ 37 int eci; 38 39 if ((env->condexec_bits & 0xf) != 0) { 40 return 0xffff; 41 } 42 43 eci = env->condexec_bits >> 4; 44 switch (eci) { 45 case ECI_NONE: 46 return 0xffff; 47 case ECI_A0: 48 return 0xfff0; 49 case ECI_A0A1: 50 return 0xff00; 51 case ECI_A0A1A2: 52 case ECI_A0A1A2B0: 53 return 0xf000; 54 default: 55 g_assert_not_reached(); 56 } 57 } 58 59 static uint16_t mve_element_mask(CPUARMState *env) 60 { 61 /* 62 * Return the mask of which elements in the MVE vector should be 63 * updated. This is a combination of multiple things: 64 * (1) by default, we update every lane in the vector 65 * (2) VPT predication stores its state in the VPR register; 66 * (3) low-overhead-branch tail predication will mask out part 67 * the vector on the final iteration of the loop 68 * (4) if EPSR.ECI is set then we must execute only some beats 69 * of the insn 70 * We combine all these into a 16-bit result with the same semantics 71 * as VPR.P0: 0 to mask the lane, 1 if it is active. 72 * 8-bit vector ops will look at all bits of the result; 73 * 16-bit ops will look at bits 0, 2, 4, ...; 74 * 32-bit ops will look at bits 0, 4, 8 and 12. 75 * Compare pseudocode GetCurInstrBeat(), though that only returns 76 * the 4-bit slice of the mask corresponding to a single beat. 77 */ 78 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 79 80 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 81 mask |= 0xff; 82 } 83 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 84 mask |= 0xff00; 85 } 86 87 if (env->v7m.ltpsize < 4 && 88 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 89 /* 90 * Tail predication active, and this is the last loop iteration. 91 * The element size is (1 << ltpsize), and we only want to process 92 * loopcount elements, so we want to retain the least significant 93 * (loopcount * esize) predicate bits and zero out bits above that. 94 */ 95 int masklen = env->regs[14] << env->v7m.ltpsize; 96 assert(masklen <= 16); 97 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 98 mask &= ltpmask; 99 } 100 101 /* 102 * ECI bits indicate which beats are already executed; 103 * we handle this by effectively predicating them out. 104 */ 105 mask &= mve_eci_mask(env); 106 return mask; 107 } 108 109 static void mve_advance_vpt(CPUARMState *env) 110 { 111 /* Advance the VPT and ECI state if necessary */ 112 uint32_t vpr = env->v7m.vpr; 113 unsigned mask01, mask23; 114 uint16_t inv_mask; 115 uint16_t eci_mask = mve_eci_mask(env); 116 117 if ((env->condexec_bits & 0xf) == 0) { 118 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 119 (ECI_A0 << 4) : (ECI_NONE << 4); 120 } 121 122 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 123 /* VPT not enabled, nothing to do */ 124 return; 125 } 126 127 /* Invert P0 bits if needed, but only for beats we actually executed */ 128 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 129 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 130 /* Start by assuming we invert all bits corresponding to executed beats */ 131 inv_mask = eci_mask; 132 if (mask01 <= 8) { 133 /* MASK01 says don't invert low half of P0 */ 134 inv_mask &= ~0xff; 135 } 136 if (mask23 <= 8) { 137 /* MASK23 says don't invert high half of P0 */ 138 inv_mask &= ~0xff00; 139 } 140 vpr ^= inv_mask; 141 /* Only update MASK01 if beat 1 executed */ 142 if (eci_mask & 0xf0) { 143 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 144 } 145 /* Beat 3 always executes, so update MASK23 */ 146 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 147 env->v7m.vpr = vpr; 148 } 149 150 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 151 #define DO_VLDR(OP, MFLAG, MSIZE, MTYPE, LDTYPE, ESIZE, TYPE) \ 152 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 153 { \ 154 TYPE *d = vd; \ 155 uint16_t mask = mve_element_mask(env); \ 156 uint16_t eci_mask = mve_eci_mask(env); \ 157 unsigned b, e; \ 158 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 159 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 160 /* \ 161 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 162 * beats so we don't care if we update part of the dest and \ 163 * then take an exception. \ 164 */ \ 165 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 166 if (eci_mask & (1 << b)) { \ 167 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 168 (MTYPE)cpu_##LDTYPE##_mmu(env, addr, oi, GETPC()) : 0;\ 169 } \ 170 addr += MSIZE; \ 171 } \ 172 mve_advance_vpt(env); \ 173 } 174 175 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ 176 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 177 { \ 178 TYPE *d = vd; \ 179 uint16_t mask = mve_element_mask(env); \ 180 unsigned b, e; \ 181 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 182 if (mask & (1 << b)) { \ 183 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 184 } \ 185 addr += MSIZE; \ 186 } \ 187 mve_advance_vpt(env); \ 188 } 189 190 DO_VLDR(vldrb, MO_UB, 1, uint8_t, ldb, 1, uint8_t) 191 DO_VLDR(vldrh, MO_TEUW, 2, uint16_t, ldw, 2, uint16_t) 192 DO_VLDR(vldrw, MO_TEUL, 4, uint32_t, ldl, 4, uint32_t) 193 194 DO_VSTR(vstrb, 1, stb, 1, uint8_t) 195 DO_VSTR(vstrh, 2, stw, 2, uint16_t) 196 DO_VSTR(vstrw, 4, stl, 4, uint32_t) 197 198 DO_VLDR(vldrb_sh, MO_SB, 1, int8_t, ldb, 2, int16_t) 199 DO_VLDR(vldrb_sw, MO_SB, 1, int8_t, ldb, 4, int32_t) 200 DO_VLDR(vldrb_uh, MO_UB, 1, uint8_t, ldb, 2, uint16_t) 201 DO_VLDR(vldrb_uw, MO_UB, 1, uint8_t, ldb, 4, uint32_t) 202 DO_VLDR(vldrh_sw, MO_TESW, 2, int16_t, ldw, 4, int32_t) 203 DO_VLDR(vldrh_uw, MO_TEUW, 2, uint16_t, ldw, 4, uint32_t) 204 205 DO_VSTR(vstrb_h, 1, stb, 2, int16_t) 206 DO_VSTR(vstrb_w, 1, stb, 4, int32_t) 207 DO_VSTR(vstrh_w, 2, stw, 4, int32_t) 208 209 #undef DO_VLDR 210 #undef DO_VSTR 211 212 /* 213 * Gather loads/scatter stores. Here each element of Qm specifies 214 * an offset to use from the base register Rm. In the _os_ versions 215 * that offset is scaled by the element size. 216 * For loads, predicated lanes are zeroed instead of retaining 217 * their previous values. 218 */ 219 #define DO_VLDR_SG(OP, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN, WB) \ 220 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 221 uint32_t base) \ 222 { \ 223 TYPE *d = vd; \ 224 OFFTYPE *m = vm; \ 225 uint16_t mask = mve_element_mask(env); \ 226 uint16_t eci_mask = mve_eci_mask(env); \ 227 unsigned e; \ 228 uint32_t addr; \ 229 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 230 if (!(eci_mask & 1)) { \ 231 continue; \ 232 } \ 233 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 234 d[H##ESIZE(e)] = (mask & 1) ? \ 235 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 236 if (WB) { \ 237 m[H##ESIZE(e)] = addr; \ 238 } \ 239 } \ 240 mve_advance_vpt(env); \ 241 } 242 243 /* We know here TYPE is unsigned so always the same as the offset type */ 244 #define DO_VSTR_SG(OP, STTYPE, ESIZE, TYPE, ADDRFN, WB) \ 245 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 246 uint32_t base) \ 247 { \ 248 TYPE *d = vd; \ 249 TYPE *m = vm; \ 250 uint16_t mask = mve_element_mask(env); \ 251 uint16_t eci_mask = mve_eci_mask(env); \ 252 unsigned e; \ 253 uint32_t addr; \ 254 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 255 if (!(eci_mask & 1)) { \ 256 continue; \ 257 } \ 258 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 259 if (mask & 1) { \ 260 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 261 } \ 262 if (WB) { \ 263 m[H##ESIZE(e)] = addr; \ 264 } \ 265 } \ 266 mve_advance_vpt(env); \ 267 } 268 269 /* 270 * 64-bit accesses are slightly different: they are done as two 32-bit 271 * accesses, controlled by the predicate mask for the relevant beat, 272 * and with a single 32-bit offset in the first of the two Qm elements. 273 * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little). 274 * Address writeback happens on the odd beats and updates the address 275 * stored in the even-beat element. 276 */ 277 #define DO_VLDR64_SG(OP, ADDRFN, WB) \ 278 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 279 uint32_t base) \ 280 { \ 281 uint32_t *d = vd; \ 282 uint32_t *m = vm; \ 283 uint16_t mask = mve_element_mask(env); \ 284 uint16_t eci_mask = mve_eci_mask(env); \ 285 unsigned e; \ 286 uint32_t addr; \ 287 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 288 if (!(eci_mask & 1)) { \ 289 continue; \ 290 } \ 291 addr = ADDRFN(base, m[H4(e & ~1)]); \ 292 addr += 4 * (e & 1); \ 293 d[H4(e)] = (mask & 1) ? cpu_ldl_data_ra(env, addr, GETPC()) : 0; \ 294 if (WB && (e & 1)) { \ 295 m[H4(e & ~1)] = addr - 4; \ 296 } \ 297 } \ 298 mve_advance_vpt(env); \ 299 } 300 301 #define DO_VSTR64_SG(OP, ADDRFN, WB) \ 302 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 303 uint32_t base) \ 304 { \ 305 uint32_t *d = vd; \ 306 uint32_t *m = vm; \ 307 uint16_t mask = mve_element_mask(env); \ 308 uint16_t eci_mask = mve_eci_mask(env); \ 309 unsigned e; \ 310 uint32_t addr; \ 311 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 312 if (!(eci_mask & 1)) { \ 313 continue; \ 314 } \ 315 addr = ADDRFN(base, m[H4(e & ~1)]); \ 316 addr += 4 * (e & 1); \ 317 if (mask & 1) { \ 318 cpu_stl_data_ra(env, addr, d[H4(e)], GETPC()); \ 319 } \ 320 if (WB && (e & 1)) { \ 321 m[H4(e & ~1)] = addr - 4; \ 322 } \ 323 } \ 324 mve_advance_vpt(env); \ 325 } 326 327 #define ADDR_ADD(BASE, OFFSET) ((BASE) + (OFFSET)) 328 #define ADDR_ADD_OSH(BASE, OFFSET) ((BASE) + ((OFFSET) << 1)) 329 #define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2)) 330 #define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3)) 331 332 DO_VLDR_SG(vldrb_sg_sh, ldsb, 2, int16_t, uint16_t, ADDR_ADD, false) 333 DO_VLDR_SG(vldrb_sg_sw, ldsb, 4, int32_t, uint32_t, ADDR_ADD, false) 334 DO_VLDR_SG(vldrh_sg_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD, false) 335 336 DO_VLDR_SG(vldrb_sg_ub, ldub, 1, uint8_t, uint8_t, ADDR_ADD, false) 337 DO_VLDR_SG(vldrb_sg_uh, ldub, 2, uint16_t, uint16_t, ADDR_ADD, false) 338 DO_VLDR_SG(vldrb_sg_uw, ldub, 4, uint32_t, uint32_t, ADDR_ADD, false) 339 DO_VLDR_SG(vldrh_sg_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD, false) 340 DO_VLDR_SG(vldrh_sg_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD, false) 341 DO_VLDR_SG(vldrw_sg_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false) 342 DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) 343 344 DO_VLDR_SG(vldrh_sg_os_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD_OSH, false) 345 DO_VLDR_SG(vldrh_sg_os_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD_OSH, false) 346 DO_VLDR_SG(vldrh_sg_os_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD_OSH, false) 347 DO_VLDR_SG(vldrw_sg_os_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW, false) 348 DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) 349 350 DO_VSTR_SG(vstrb_sg_ub, stb, 1, uint8_t, ADDR_ADD, false) 351 DO_VSTR_SG(vstrb_sg_uh, stb, 2, uint16_t, ADDR_ADD, false) 352 DO_VSTR_SG(vstrb_sg_uw, stb, 4, uint32_t, ADDR_ADD, false) 353 DO_VSTR_SG(vstrh_sg_uh, stw, 2, uint16_t, ADDR_ADD, false) 354 DO_VSTR_SG(vstrh_sg_uw, stw, 4, uint32_t, ADDR_ADD, false) 355 DO_VSTR_SG(vstrw_sg_uw, stl, 4, uint32_t, ADDR_ADD, false) 356 DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) 357 358 DO_VSTR_SG(vstrh_sg_os_uh, stw, 2, uint16_t, ADDR_ADD_OSH, false) 359 DO_VSTR_SG(vstrh_sg_os_uw, stw, 4, uint32_t, ADDR_ADD_OSH, false) 360 DO_VSTR_SG(vstrw_sg_os_uw, stl, 4, uint32_t, ADDR_ADD_OSW, false) 361 DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) 362 363 DO_VLDR_SG(vldrw_sg_wb_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true) 364 DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) 365 DO_VSTR_SG(vstrw_sg_wb_uw, stl, 4, uint32_t, ADDR_ADD, true) 366 DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) 367 368 /* 369 * Deinterleaving loads/interleaving stores. 370 * 371 * For these helpers we are passed the index of the first Qreg 372 * (VLD2/VST2 will also access Qn+1, VLD4/VST4 access Qn .. Qn+3) 373 * and the value of the base address register Rn. 374 * The helpers are specialized for pattern and element size, so 375 * for instance vld42h is VLD4 with pattern 2, element size MO_16. 376 * 377 * These insns are beatwise but not predicated, so we must honour ECI, 378 * but need not look at mve_element_mask(). 379 * 380 * The pseudocode implements these insns with multiple memory accesses 381 * of the element size, but rules R_VVVG and R_FXDM permit us to make 382 * one 32-bit memory access per beat. 383 */ 384 #define DO_VLD4B(OP, O1, O2, O3, O4) \ 385 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 386 uint32_t base) \ 387 { \ 388 int beat, e; \ 389 uint16_t mask = mve_eci_mask(env); \ 390 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 391 uint32_t addr, data; \ 392 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 393 if ((mask & 1) == 0) { \ 394 /* ECI says skip this beat */ \ 395 continue; \ 396 } \ 397 addr = base + off[beat] * 4; \ 398 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 399 for (e = 0; e < 4; e++, data >>= 8) { \ 400 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 401 qd[H1(off[beat])] = data; \ 402 } \ 403 } \ 404 } 405 406 #define DO_VLD4H(OP, O1, O2) \ 407 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 408 uint32_t base) \ 409 { \ 410 int beat; \ 411 uint16_t mask = mve_eci_mask(env); \ 412 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 413 uint32_t addr, data; \ 414 int y; /* y counts 0 2 0 2 */ \ 415 uint16_t *qd; \ 416 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 417 if ((mask & 1) == 0) { \ 418 /* ECI says skip this beat */ \ 419 continue; \ 420 } \ 421 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 422 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 423 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 424 qd[H2(off[beat])] = data; \ 425 data >>= 16; \ 426 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 427 qd[H2(off[beat])] = data; \ 428 } \ 429 } 430 431 #define DO_VLD4W(OP, O1, O2, O3, O4) \ 432 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 433 uint32_t base) \ 434 { \ 435 int beat; \ 436 uint16_t mask = mve_eci_mask(env); \ 437 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 438 uint32_t addr, data; \ 439 uint32_t *qd; \ 440 int y; \ 441 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 442 if ((mask & 1) == 0) { \ 443 /* ECI says skip this beat */ \ 444 continue; \ 445 } \ 446 addr = base + off[beat] * 4; \ 447 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 448 y = (beat + (O1 & 2)) & 3; \ 449 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 450 qd[H4(off[beat] >> 2)] = data; \ 451 } \ 452 } 453 454 DO_VLD4B(vld40b, 0, 1, 10, 11) 455 DO_VLD4B(vld41b, 2, 3, 12, 13) 456 DO_VLD4B(vld42b, 4, 5, 14, 15) 457 DO_VLD4B(vld43b, 6, 7, 8, 9) 458 459 DO_VLD4H(vld40h, 0, 5) 460 DO_VLD4H(vld41h, 1, 6) 461 DO_VLD4H(vld42h, 2, 7) 462 DO_VLD4H(vld43h, 3, 4) 463 464 DO_VLD4W(vld40w, 0, 1, 10, 11) 465 DO_VLD4W(vld41w, 2, 3, 12, 13) 466 DO_VLD4W(vld42w, 4, 5, 14, 15) 467 DO_VLD4W(vld43w, 6, 7, 8, 9) 468 469 #define DO_VLD2B(OP, O1, O2, O3, O4) \ 470 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 471 uint32_t base) \ 472 { \ 473 int beat, e; \ 474 uint16_t mask = mve_eci_mask(env); \ 475 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 476 uint32_t addr, data; \ 477 uint8_t *qd; \ 478 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 479 if ((mask & 1) == 0) { \ 480 /* ECI says skip this beat */ \ 481 continue; \ 482 } \ 483 addr = base + off[beat] * 2; \ 484 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 485 for (e = 0; e < 4; e++, data >>= 8) { \ 486 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 487 qd[H1(off[beat] + (e >> 1))] = data; \ 488 } \ 489 } \ 490 } 491 492 #define DO_VLD2H(OP, O1, O2, O3, O4) \ 493 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 494 uint32_t base) \ 495 { \ 496 int beat; \ 497 uint16_t mask = mve_eci_mask(env); \ 498 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 499 uint32_t addr, data; \ 500 int e; \ 501 uint16_t *qd; \ 502 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 503 if ((mask & 1) == 0) { \ 504 /* ECI says skip this beat */ \ 505 continue; \ 506 } \ 507 addr = base + off[beat] * 4; \ 508 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 509 for (e = 0; e < 2; e++, data >>= 16) { \ 510 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 511 qd[H2(off[beat])] = data; \ 512 } \ 513 } \ 514 } 515 516 #define DO_VLD2W(OP, O1, O2, O3, O4) \ 517 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 518 uint32_t base) \ 519 { \ 520 int beat; \ 521 uint16_t mask = mve_eci_mask(env); \ 522 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 523 uint32_t addr, data; \ 524 uint32_t *qd; \ 525 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 526 if ((mask & 1) == 0) { \ 527 /* ECI says skip this beat */ \ 528 continue; \ 529 } \ 530 addr = base + off[beat]; \ 531 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \ 532 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 533 qd[H4(off[beat] >> 3)] = data; \ 534 } \ 535 } 536 537 DO_VLD2B(vld20b, 0, 2, 12, 14) 538 DO_VLD2B(vld21b, 4, 6, 8, 10) 539 540 DO_VLD2H(vld20h, 0, 1, 6, 7) 541 DO_VLD2H(vld21h, 2, 3, 4, 5) 542 543 DO_VLD2W(vld20w, 0, 4, 24, 28) 544 DO_VLD2W(vld21w, 8, 12, 16, 20) 545 546 #define DO_VST4B(OP, O1, O2, O3, O4) \ 547 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 548 uint32_t base) \ 549 { \ 550 int beat, e; \ 551 uint16_t mask = mve_eci_mask(env); \ 552 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 553 uint32_t addr, data; \ 554 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 555 if ((mask & 1) == 0) { \ 556 /* ECI says skip this beat */ \ 557 continue; \ 558 } \ 559 addr = base + off[beat] * 4; \ 560 data = 0; \ 561 for (e = 3; e >= 0; e--) { \ 562 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 563 data = (data << 8) | qd[H1(off[beat])]; \ 564 } \ 565 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 566 } \ 567 } 568 569 #define DO_VST4H(OP, O1, O2) \ 570 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 571 uint32_t base) \ 572 { \ 573 int beat; \ 574 uint16_t mask = mve_eci_mask(env); \ 575 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 576 uint32_t addr, data; \ 577 int y; /* y counts 0 2 0 2 */ \ 578 uint16_t *qd; \ 579 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 580 if ((mask & 1) == 0) { \ 581 /* ECI says skip this beat */ \ 582 continue; \ 583 } \ 584 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 585 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 586 data = qd[H2(off[beat])]; \ 587 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 588 data |= qd[H2(off[beat])] << 16; \ 589 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 590 } \ 591 } 592 593 #define DO_VST4W(OP, O1, O2, O3, O4) \ 594 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 595 uint32_t base) \ 596 { \ 597 int beat; \ 598 uint16_t mask = mve_eci_mask(env); \ 599 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 600 uint32_t addr, data; \ 601 uint32_t *qd; \ 602 int y; \ 603 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 604 if ((mask & 1) == 0) { \ 605 /* ECI says skip this beat */ \ 606 continue; \ 607 } \ 608 addr = base + off[beat] * 4; \ 609 y = (beat + (O1 & 2)) & 3; \ 610 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 611 data = qd[H4(off[beat] >> 2)]; \ 612 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 613 } \ 614 } 615 616 DO_VST4B(vst40b, 0, 1, 10, 11) 617 DO_VST4B(vst41b, 2, 3, 12, 13) 618 DO_VST4B(vst42b, 4, 5, 14, 15) 619 DO_VST4B(vst43b, 6, 7, 8, 9) 620 621 DO_VST4H(vst40h, 0, 5) 622 DO_VST4H(vst41h, 1, 6) 623 DO_VST4H(vst42h, 2, 7) 624 DO_VST4H(vst43h, 3, 4) 625 626 DO_VST4W(vst40w, 0, 1, 10, 11) 627 DO_VST4W(vst41w, 2, 3, 12, 13) 628 DO_VST4W(vst42w, 4, 5, 14, 15) 629 DO_VST4W(vst43w, 6, 7, 8, 9) 630 631 #define DO_VST2B(OP, O1, O2, O3, O4) \ 632 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 633 uint32_t base) \ 634 { \ 635 int beat, e; \ 636 uint16_t mask = mve_eci_mask(env); \ 637 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 638 uint32_t addr, data; \ 639 uint8_t *qd; \ 640 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 641 if ((mask & 1) == 0) { \ 642 /* ECI says skip this beat */ \ 643 continue; \ 644 } \ 645 addr = base + off[beat] * 2; \ 646 data = 0; \ 647 for (e = 3; e >= 0; e--) { \ 648 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 649 data = (data << 8) | qd[H1(off[beat] + (e >> 1))]; \ 650 } \ 651 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 652 } \ 653 } 654 655 #define DO_VST2H(OP, O1, O2, O3, O4) \ 656 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 657 uint32_t base) \ 658 { \ 659 int beat; \ 660 uint16_t mask = mve_eci_mask(env); \ 661 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 662 uint32_t addr, data; \ 663 int e; \ 664 uint16_t *qd; \ 665 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 666 if ((mask & 1) == 0) { \ 667 /* ECI says skip this beat */ \ 668 continue; \ 669 } \ 670 addr = base + off[beat] * 4; \ 671 data = 0; \ 672 for (e = 1; e >= 0; e--) { \ 673 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 674 data = (data << 16) | qd[H2(off[beat])]; \ 675 } \ 676 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 677 } \ 678 } 679 680 #define DO_VST2W(OP, O1, O2, O3, O4) \ 681 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 682 uint32_t base) \ 683 { \ 684 int beat; \ 685 uint16_t mask = mve_eci_mask(env); \ 686 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 687 uint32_t addr, data; \ 688 uint32_t *qd; \ 689 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 690 if ((mask & 1) == 0) { \ 691 /* ECI says skip this beat */ \ 692 continue; \ 693 } \ 694 addr = base + off[beat]; \ 695 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 696 data = qd[H4(off[beat] >> 3)]; \ 697 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 698 } \ 699 } 700 701 DO_VST2B(vst20b, 0, 2, 12, 14) 702 DO_VST2B(vst21b, 4, 6, 8, 10) 703 704 DO_VST2H(vst20h, 0, 1, 6, 7) 705 DO_VST2H(vst21h, 2, 3, 4, 5) 706 707 DO_VST2W(vst20w, 0, 4, 24, 28) 708 DO_VST2W(vst21w, 8, 12, 16, 20) 709 710 /* 711 * The mergemask(D, R, M) macro performs the operation "*D = R" but 712 * storing only the bytes which correspond to 1 bits in M, 713 * leaving other bytes in *D unchanged. We use _Generic 714 * to select the correct implementation based on the type of D. 715 */ 716 717 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 718 { 719 if (mask & 1) { 720 *d = r; 721 } 722 } 723 724 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 725 { 726 mergemask_ub((uint8_t *)d, r, mask); 727 } 728 729 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 730 { 731 uint16_t bmask = expand_pred_b(mask); 732 *d = (*d & ~bmask) | (r & bmask); 733 } 734 735 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 736 { 737 mergemask_uh((uint16_t *)d, r, mask); 738 } 739 740 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 741 { 742 uint32_t bmask = expand_pred_b(mask); 743 *d = (*d & ~bmask) | (r & bmask); 744 } 745 746 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 747 { 748 mergemask_uw((uint32_t *)d, r, mask); 749 } 750 751 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 752 { 753 uint64_t bmask = expand_pred_b(mask); 754 *d = (*d & ~bmask) | (r & bmask); 755 } 756 757 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 758 { 759 mergemask_uq((uint64_t *)d, r, mask); 760 } 761 762 #define mergemask(D, R, M) \ 763 _Generic(D, \ 764 uint8_t *: mergemask_ub, \ 765 int8_t *: mergemask_sb, \ 766 uint16_t *: mergemask_uh, \ 767 int16_t *: mergemask_sh, \ 768 uint32_t *: mergemask_uw, \ 769 int32_t *: mergemask_sw, \ 770 uint64_t *: mergemask_uq, \ 771 int64_t *: mergemask_sq)(D, R, M) 772 773 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 774 { 775 /* 776 * The generated code already replicated an 8 or 16 bit constant 777 * into the 32-bit value, so we only need to write the 32-bit 778 * value to all elements of the Qreg, allowing for predication. 779 */ 780 uint32_t *d = vd; 781 uint16_t mask = mve_element_mask(env); 782 unsigned e; 783 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 784 mergemask(&d[H4(e)], val, mask); 785 } 786 mve_advance_vpt(env); 787 } 788 789 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 790 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 791 { \ 792 TYPE *d = vd, *m = vm; \ 793 uint16_t mask = mve_element_mask(env); \ 794 unsigned e; \ 795 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 796 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 797 } \ 798 mve_advance_vpt(env); \ 799 } 800 801 #define DO_CLS_B(N) (clrsb32(N) - 24) 802 #define DO_CLS_H(N) (clrsb32(N) - 16) 803 804 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 805 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 806 DO_1OP(vclsw, 4, int32_t, clrsb32) 807 808 #define DO_CLZ_B(N) (clz32(N) - 24) 809 #define DO_CLZ_H(N) (clz32(N) - 16) 810 811 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 812 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 813 DO_1OP(vclzw, 4, uint32_t, clz32) 814 815 DO_1OP(vrev16b, 2, uint16_t, bswap16) 816 DO_1OP(vrev32b, 4, uint32_t, bswap32) 817 DO_1OP(vrev32h, 4, uint32_t, hswap32) 818 DO_1OP(vrev64b, 8, uint64_t, bswap64) 819 DO_1OP(vrev64h, 8, uint64_t, hswap64) 820 DO_1OP(vrev64w, 8, uint64_t, wswap64) 821 822 #define DO_NOT(N) (~(N)) 823 824 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 825 826 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 827 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 828 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 829 830 DO_1OP(vabsb, 1, int8_t, DO_ABS) 831 DO_1OP(vabsh, 2, int16_t, DO_ABS) 832 DO_1OP(vabsw, 4, int32_t, DO_ABS) 833 834 /* We can do these 64 bits at a time */ 835 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 836 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 837 838 #define DO_NEG(N) (-(N)) 839 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 840 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 841 842 DO_1OP(vnegb, 1, int8_t, DO_NEG) 843 DO_1OP(vnegh, 2, int16_t, DO_NEG) 844 DO_1OP(vnegw, 4, int32_t, DO_NEG) 845 846 /* We can do these 64 bits at a time */ 847 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 848 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 849 850 /* 851 * 1 operand immediates: Vda is destination and possibly also one source. 852 * All these insns work at 64-bit widths. 853 */ 854 #define DO_1OP_IMM(OP, FN) \ 855 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 856 { \ 857 uint64_t *da = vda; \ 858 uint16_t mask = mve_element_mask(env); \ 859 unsigned e; \ 860 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 861 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 862 } \ 863 mve_advance_vpt(env); \ 864 } 865 866 #define DO_MOVI(N, I) (I) 867 #define DO_ANDI(N, I) ((N) & (I)) 868 #define DO_ORRI(N, I) ((N) | (I)) 869 870 DO_1OP_IMM(vmovi, DO_MOVI) 871 DO_1OP_IMM(vandi, DO_ANDI) 872 DO_1OP_IMM(vorri, DO_ORRI) 873 874 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 875 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 876 void *vd, void *vn, void *vm) \ 877 { \ 878 TYPE *d = vd, *n = vn, *m = vm; \ 879 uint16_t mask = mve_element_mask(env); \ 880 unsigned e; \ 881 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 882 mergemask(&d[H##ESIZE(e)], \ 883 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 884 } \ 885 mve_advance_vpt(env); \ 886 } 887 888 /* provide unsigned 2-op helpers for all sizes */ 889 #define DO_2OP_U(OP, FN) \ 890 DO_2OP(OP##b, 1, uint8_t, FN) \ 891 DO_2OP(OP##h, 2, uint16_t, FN) \ 892 DO_2OP(OP##w, 4, uint32_t, FN) 893 894 /* provide signed 2-op helpers for all sizes */ 895 #define DO_2OP_S(OP, FN) \ 896 DO_2OP(OP##b, 1, int8_t, FN) \ 897 DO_2OP(OP##h, 2, int16_t, FN) \ 898 DO_2OP(OP##w, 4, int32_t, FN) 899 900 /* 901 * "Long" operations where two half-sized inputs (taken from either the 902 * top or the bottom of the input vector) produce a double-width result. 903 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 904 */ 905 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 906 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 907 { \ 908 LTYPE *d = vd; \ 909 TYPE *n = vn, *m = vm; \ 910 uint16_t mask = mve_element_mask(env); \ 911 unsigned le; \ 912 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 913 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 914 m[H##ESIZE(le * 2 + TOP)]); \ 915 mergemask(&d[H##LESIZE(le)], r, mask); \ 916 } \ 917 mve_advance_vpt(env); \ 918 } 919 920 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 921 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 922 { \ 923 TYPE *d = vd, *n = vn, *m = vm; \ 924 uint16_t mask = mve_element_mask(env); \ 925 unsigned e; \ 926 bool qc = false; \ 927 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 928 bool sat = false; \ 929 TYPE r_ = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 930 mergemask(&d[H##ESIZE(e)], r_, mask); \ 931 qc |= sat & mask & 1; \ 932 } \ 933 if (qc) { \ 934 env->vfp.qc[0] = qc; \ 935 } \ 936 mve_advance_vpt(env); \ 937 } 938 939 /* provide unsigned 2-op helpers for all sizes */ 940 #define DO_2OP_SAT_U(OP, FN) \ 941 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 942 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 943 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 944 945 /* provide signed 2-op helpers for all sizes */ 946 #define DO_2OP_SAT_S(OP, FN) \ 947 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 948 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 949 DO_2OP_SAT(OP##w, 4, int32_t, FN) 950 951 #define DO_AND(N, M) ((N) & (M)) 952 #define DO_BIC(N, M) ((N) & ~(M)) 953 #define DO_ORR(N, M) ((N) | (M)) 954 #define DO_ORN(N, M) ((N) | ~(M)) 955 #define DO_EOR(N, M) ((N) ^ (M)) 956 957 DO_2OP(vand, 8, uint64_t, DO_AND) 958 DO_2OP(vbic, 8, uint64_t, DO_BIC) 959 DO_2OP(vorr, 8, uint64_t, DO_ORR) 960 DO_2OP(vorn, 8, uint64_t, DO_ORN) 961 DO_2OP(veor, 8, uint64_t, DO_EOR) 962 963 #define DO_ADD(N, M) ((N) + (M)) 964 #define DO_SUB(N, M) ((N) - (M)) 965 #define DO_MUL(N, M) ((N) * (M)) 966 967 DO_2OP_U(vadd, DO_ADD) 968 DO_2OP_U(vsub, DO_SUB) 969 DO_2OP_U(vmul, DO_MUL) 970 971 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 972 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 973 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 974 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 975 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 976 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 977 978 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 979 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 980 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 981 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 982 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 983 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 984 985 /* 986 * Polynomial multiply. We can always do this generating 64 bits 987 * of the result at a time, so we don't need to use DO_2OP_L. 988 */ 989 DO_2OP(vmullpbh, 8, uint64_t, clmul_8x4_even) 990 DO_2OP(vmullpth, 8, uint64_t, clmul_8x4_odd) 991 DO_2OP(vmullpbw, 8, uint64_t, clmul_16x2_even) 992 DO_2OP(vmullptw, 8, uint64_t, clmul_16x2_odd) 993 994 /* 995 * Because the computation type is at least twice as large as required, 996 * these work for both signed and unsigned source types. 997 */ 998 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 999 { 1000 return (n * m) >> 8; 1001 } 1002 1003 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 1004 { 1005 return (n * m) >> 16; 1006 } 1007 1008 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 1009 { 1010 return (n * m) >> 32; 1011 } 1012 1013 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 1014 { 1015 return (n * m + (1U << 7)) >> 8; 1016 } 1017 1018 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 1019 { 1020 return (n * m + (1U << 15)) >> 16; 1021 } 1022 1023 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 1024 { 1025 return (n * m + (1U << 31)) >> 32; 1026 } 1027 1028 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 1029 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 1030 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 1031 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 1032 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 1033 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 1034 1035 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 1036 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 1037 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 1038 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 1039 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 1040 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 1041 1042 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 1043 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 1044 1045 DO_2OP_S(vmaxs, DO_MAX) 1046 DO_2OP_U(vmaxu, DO_MAX) 1047 DO_2OP_S(vmins, DO_MIN) 1048 DO_2OP_U(vminu, DO_MIN) 1049 1050 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 1051 1052 DO_2OP_S(vabds, DO_ABD) 1053 DO_2OP_U(vabdu, DO_ABD) 1054 1055 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 1056 { 1057 return ((uint64_t)n + m) >> 1; 1058 } 1059 1060 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 1061 { 1062 return ((int64_t)n + m) >> 1; 1063 } 1064 1065 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 1066 { 1067 return ((uint64_t)n - m) >> 1; 1068 } 1069 1070 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 1071 { 1072 return ((int64_t)n - m) >> 1; 1073 } 1074 1075 DO_2OP_S(vhadds, do_vhadd_s) 1076 DO_2OP_U(vhaddu, do_vhadd_u) 1077 DO_2OP_S(vhsubs, do_vhsub_s) 1078 DO_2OP_U(vhsubu, do_vhsub_u) 1079 1080 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1081 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1082 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1083 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1084 1085 DO_2OP_S(vshls, DO_VSHLS) 1086 DO_2OP_U(vshlu, DO_VSHLU) 1087 DO_2OP_S(vrshls, DO_VRSHLS) 1088 DO_2OP_U(vrshlu, DO_VRSHLU) 1089 1090 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 1091 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 1092 1093 DO_2OP_S(vrhadds, DO_RHADD_S) 1094 DO_2OP_U(vrhaddu, DO_RHADD_U) 1095 1096 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 1097 uint32_t inv, uint32_t carry_in, bool update_flags) 1098 { 1099 uint16_t mask = mve_element_mask(env); 1100 unsigned e; 1101 1102 /* If any additions trigger, we will update flags. */ 1103 if (mask & 0x1111) { 1104 update_flags = true; 1105 } 1106 1107 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1108 uint64_t r = carry_in; 1109 r += n[H4(e)]; 1110 r += m[H4(e)] ^ inv; 1111 if (mask & 1) { 1112 carry_in = r >> 32; 1113 } 1114 mergemask(&d[H4(e)], r, mask); 1115 } 1116 1117 if (update_flags) { 1118 /* Store C, clear NZV. */ 1119 env->vfp.fpsr &= ~FPSR_NZCV_MASK; 1120 env->vfp.fpsr |= carry_in * FPSR_C; 1121 } 1122 mve_advance_vpt(env); 1123 } 1124 1125 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 1126 { 1127 bool carry_in = env->vfp.fpsr & FPSR_C; 1128 do_vadc(env, vd, vn, vm, 0, carry_in, false); 1129 } 1130 1131 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 1132 { 1133 bool carry_in = env->vfp.fpsr & FPSR_C; 1134 do_vadc(env, vd, vn, vm, -1, carry_in, false); 1135 } 1136 1137 1138 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 1139 { 1140 do_vadc(env, vd, vn, vm, 0, 0, true); 1141 } 1142 1143 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 1144 { 1145 do_vadc(env, vd, vn, vm, -1, 1, true); 1146 } 1147 1148 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 1149 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 1150 { \ 1151 TYPE *d = vd, *n = vn, *m = vm; \ 1152 uint16_t mask = mve_element_mask(env); \ 1153 unsigned e; \ 1154 TYPE r[16 / ESIZE]; \ 1155 /* Calculate all results first to avoid overwriting inputs */ \ 1156 for (e = 0; e < 16 / ESIZE; e++) { \ 1157 if (!(e & 1)) { \ 1158 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 1159 } else { \ 1160 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 1161 } \ 1162 } \ 1163 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1164 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 1165 } \ 1166 mve_advance_vpt(env); \ 1167 } 1168 1169 #define DO_VCADD_ALL(OP, FN0, FN1) \ 1170 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 1171 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 1172 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 1173 1174 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 1175 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 1176 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 1177 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 1178 1179 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 1180 { 1181 if (val > max) { 1182 *s = true; 1183 return max; 1184 } else if (val < min) { 1185 *s = true; 1186 return min; 1187 } 1188 return val; 1189 } 1190 1191 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 1192 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 1193 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 1194 1195 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 1196 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 1197 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 1198 1199 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 1200 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 1201 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 1202 1203 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 1204 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 1205 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 1206 1207 /* 1208 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 1209 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 1210 */ 1211 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 1212 INT8_MIN, INT8_MAX, s) 1213 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 1214 INT16_MIN, INT16_MAX, s) 1215 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 1216 INT32_MIN, INT32_MAX, s) 1217 1218 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 1219 INT8_MIN, INT8_MAX, s) 1220 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 1221 INT16_MIN, INT16_MAX, s) 1222 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 1223 INT32_MIN, INT32_MAX, s) 1224 1225 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 1226 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 1227 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 1228 1229 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 1230 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 1231 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 1232 1233 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 1234 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 1235 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 1236 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 1237 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 1238 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 1239 1240 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 1241 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 1242 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 1243 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 1244 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 1245 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 1246 1247 /* 1248 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 1249 * and friends wanting a uint32_t* sat and our needing a bool*. 1250 */ 1251 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 1252 ({ \ 1253 uint32_t su32 = 0; \ 1254 typeof(N) qrshl_ret = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 1255 if (su32) { \ 1256 *satp = true; \ 1257 } \ 1258 qrshl_ret; \ 1259 }) 1260 1261 #define DO_SQSHL_OP(N, M, satp) \ 1262 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 1263 #define DO_UQSHL_OP(N, M, satp) \ 1264 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 1265 #define DO_SQRSHL_OP(N, M, satp) \ 1266 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 1267 #define DO_UQRSHL_OP(N, M, satp) \ 1268 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 1269 #define DO_SUQSHL_OP(N, M, satp) \ 1270 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 1271 1272 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 1273 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 1274 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 1275 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 1276 1277 /* 1278 * Multiply add dual returning high half 1279 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 1280 * whether to add the rounding constant, and the pointer to the 1281 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 1282 * saturate to twice the input size and return the high half; or 1283 * (A * B - C * D) etc for VQDMLSDH. 1284 */ 1285 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 1286 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1287 void *vm) \ 1288 { \ 1289 TYPE *d = vd, *n = vn, *m = vm; \ 1290 uint16_t mask = mve_element_mask(env); \ 1291 unsigned e; \ 1292 bool qc = false; \ 1293 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1294 bool sat = false; \ 1295 if ((e & 1) == XCHG) { \ 1296 TYPE vqdmladh_ret = FN(n[H##ESIZE(e)], \ 1297 m[H##ESIZE(e - XCHG)], \ 1298 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 1299 m[H##ESIZE(e + (1 - XCHG))], \ 1300 ROUND, &sat); \ 1301 mergemask(&d[H##ESIZE(e)], vqdmladh_ret, mask); \ 1302 qc |= sat & mask & 1; \ 1303 } \ 1304 } \ 1305 if (qc) { \ 1306 env->vfp.qc[0] = qc; \ 1307 } \ 1308 mve_advance_vpt(env); \ 1309 } 1310 1311 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1312 int round, bool *sat) 1313 { 1314 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 1315 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1316 } 1317 1318 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1319 int round, bool *sat) 1320 { 1321 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 1322 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1323 } 1324 1325 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1326 int round, bool *sat) 1327 { 1328 int64_t m1 = (int64_t)a * b; 1329 int64_t m2 = (int64_t)c * d; 1330 int64_t r; 1331 /* 1332 * Architecturally we should do the entire add, double, round 1333 * and then check for saturation. We do three saturating adds, 1334 * but we need to be careful about the order. If the first 1335 * m1 + m2 saturates then it's impossible for the *2+rc to 1336 * bring it back into the non-saturated range. However, if 1337 * m1 + m2 is negative then it's possible that doing the doubling 1338 * would take the intermediate result below INT64_MAX and the 1339 * addition of the rounding constant then brings it back in range. 1340 * So we add half the rounding constant before doubling rather 1341 * than adding the rounding constant after the doubling. 1342 */ 1343 if (sadd64_overflow(m1, m2, &r) || 1344 sadd64_overflow(r, (round << 30), &r) || 1345 sadd64_overflow(r, r, &r)) { 1346 *sat = true; 1347 return r < 0 ? INT32_MAX : INT32_MIN; 1348 } 1349 return r >> 32; 1350 } 1351 1352 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1353 int round, bool *sat) 1354 { 1355 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 1356 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1357 } 1358 1359 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1360 int round, bool *sat) 1361 { 1362 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 1363 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1364 } 1365 1366 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1367 int round, bool *sat) 1368 { 1369 int64_t m1 = (int64_t)a * b; 1370 int64_t m2 = (int64_t)c * d; 1371 int64_t r; 1372 /* The same ordering issue as in do_vqdmladh_w applies here too */ 1373 if (ssub64_overflow(m1, m2, &r) || 1374 sadd64_overflow(r, (round << 30), &r) || 1375 sadd64_overflow(r, r, &r)) { 1376 *sat = true; 1377 return r < 0 ? INT32_MAX : INT32_MIN; 1378 } 1379 return r >> 32; 1380 } 1381 1382 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 1383 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 1384 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 1385 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 1386 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 1387 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 1388 1389 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 1390 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 1391 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 1392 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 1393 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 1394 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 1395 1396 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 1397 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 1398 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 1399 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 1400 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 1401 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 1402 1403 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 1404 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 1405 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 1406 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 1407 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 1408 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 1409 1410 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 1411 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1412 uint32_t rm) \ 1413 { \ 1414 TYPE *d = vd, *n = vn; \ 1415 TYPE m = rm; \ 1416 uint16_t mask = mve_element_mask(env); \ 1417 unsigned e; \ 1418 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1419 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 1420 } \ 1421 mve_advance_vpt(env); \ 1422 } 1423 1424 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 1425 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1426 uint32_t rm) \ 1427 { \ 1428 TYPE *d = vd, *n = vn; \ 1429 TYPE m = rm; \ 1430 uint16_t mask = mve_element_mask(env); \ 1431 unsigned e; \ 1432 bool qc = false; \ 1433 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1434 bool sat = false; \ 1435 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 1436 mask); \ 1437 qc |= sat & mask & 1; \ 1438 } \ 1439 if (qc) { \ 1440 env->vfp.qc[0] = qc; \ 1441 } \ 1442 mve_advance_vpt(env); \ 1443 } 1444 1445 /* "accumulating" version where FN takes d as well as n and m */ 1446 #define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1447 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1448 uint32_t rm) \ 1449 { \ 1450 TYPE *d = vd, *n = vn; \ 1451 TYPE m = rm; \ 1452 uint16_t mask = mve_element_mask(env); \ 1453 unsigned e; \ 1454 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1455 mergemask(&d[H##ESIZE(e)], \ 1456 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \ 1457 } \ 1458 mve_advance_vpt(env); \ 1459 } 1460 1461 #define DO_2OP_SAT_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1462 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1463 uint32_t rm) \ 1464 { \ 1465 TYPE *d = vd, *n = vn; \ 1466 TYPE m = rm; \ 1467 uint16_t mask = mve_element_mask(env); \ 1468 unsigned e; \ 1469 bool qc = false; \ 1470 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1471 bool sat = false; \ 1472 mergemask(&d[H##ESIZE(e)], \ 1473 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m, &sat), \ 1474 mask); \ 1475 qc |= sat & mask & 1; \ 1476 } \ 1477 if (qc) { \ 1478 env->vfp.qc[0] = qc; \ 1479 } \ 1480 mve_advance_vpt(env); \ 1481 } 1482 1483 /* provide unsigned 2-op scalar helpers for all sizes */ 1484 #define DO_2OP_SCALAR_U(OP, FN) \ 1485 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 1486 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 1487 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 1488 #define DO_2OP_SCALAR_S(OP, FN) \ 1489 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 1490 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 1491 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 1492 1493 #define DO_2OP_ACC_SCALAR_U(OP, FN) \ 1494 DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \ 1495 DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \ 1496 DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN) 1497 1498 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 1499 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 1500 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 1501 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 1502 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 1503 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 1504 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 1505 1506 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 1507 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 1508 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 1509 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 1510 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 1511 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 1512 1513 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 1514 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 1515 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 1516 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 1517 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 1518 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 1519 1520 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 1521 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 1522 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 1523 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 1524 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 1525 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 1526 1527 static int8_t do_vqdmlah_b(int8_t a, int8_t b, int8_t c, int round, bool *sat) 1528 { 1529 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 8) + (round << 7); 1530 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1531 } 1532 1533 static int16_t do_vqdmlah_h(int16_t a, int16_t b, int16_t c, 1534 int round, bool *sat) 1535 { 1536 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 16) + (round << 15); 1537 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1538 } 1539 1540 static int32_t do_vqdmlah_w(int32_t a, int32_t b, int32_t c, 1541 int round, bool *sat) 1542 { 1543 /* 1544 * Architecturally we should do the entire add, double, round 1545 * and then check for saturation. We do three saturating adds, 1546 * but we need to be careful about the order. If the first 1547 * m1 + m2 saturates then it's impossible for the *2+rc to 1548 * bring it back into the non-saturated range. However, if 1549 * m1 + m2 is negative then it's possible that doing the doubling 1550 * would take the intermediate result below INT64_MAX and the 1551 * addition of the rounding constant then brings it back in range. 1552 * So we add half the rounding constant and half the "c << esize" 1553 * before doubling rather than adding the rounding constant after 1554 * the doubling. 1555 */ 1556 int64_t m1 = (int64_t)a * b; 1557 int64_t m2 = (int64_t)c << 31; 1558 int64_t r; 1559 if (sadd64_overflow(m1, m2, &r) || 1560 sadd64_overflow(r, (round << 30), &r) || 1561 sadd64_overflow(r, r, &r)) { 1562 *sat = true; 1563 return r < 0 ? INT32_MAX : INT32_MIN; 1564 } 1565 return r >> 32; 1566 } 1567 1568 /* 1569 * The *MLAH insns are vector * scalar + vector; 1570 * the *MLASH insns are vector * vector + scalar 1571 */ 1572 #define DO_VQDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 0, S) 1573 #define DO_VQDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 0, S) 1574 #define DO_VQDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 0, S) 1575 #define DO_VQRDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 1, S) 1576 #define DO_VQRDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 1, S) 1577 #define DO_VQRDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 1, S) 1578 1579 #define DO_VQDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 0, S) 1580 #define DO_VQDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 0, S) 1581 #define DO_VQDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 0, S) 1582 #define DO_VQRDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 1, S) 1583 #define DO_VQRDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 1, S) 1584 #define DO_VQRDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 1, S) 1585 1586 DO_2OP_SAT_ACC_SCALAR(vqdmlahb, 1, int8_t, DO_VQDMLAH_B) 1587 DO_2OP_SAT_ACC_SCALAR(vqdmlahh, 2, int16_t, DO_VQDMLAH_H) 1588 DO_2OP_SAT_ACC_SCALAR(vqdmlahw, 4, int32_t, DO_VQDMLAH_W) 1589 DO_2OP_SAT_ACC_SCALAR(vqrdmlahb, 1, int8_t, DO_VQRDMLAH_B) 1590 DO_2OP_SAT_ACC_SCALAR(vqrdmlahh, 2, int16_t, DO_VQRDMLAH_H) 1591 DO_2OP_SAT_ACC_SCALAR(vqrdmlahw, 4, int32_t, DO_VQRDMLAH_W) 1592 1593 DO_2OP_SAT_ACC_SCALAR(vqdmlashb, 1, int8_t, DO_VQDMLASH_B) 1594 DO_2OP_SAT_ACC_SCALAR(vqdmlashh, 2, int16_t, DO_VQDMLASH_H) 1595 DO_2OP_SAT_ACC_SCALAR(vqdmlashw, 4, int32_t, DO_VQDMLASH_W) 1596 DO_2OP_SAT_ACC_SCALAR(vqrdmlashb, 1, int8_t, DO_VQRDMLASH_B) 1597 DO_2OP_SAT_ACC_SCALAR(vqrdmlashh, 2, int16_t, DO_VQRDMLASH_H) 1598 DO_2OP_SAT_ACC_SCALAR(vqrdmlashw, 4, int32_t, DO_VQRDMLASH_W) 1599 1600 /* Vector by scalar plus vector */ 1601 #define DO_VMLA(D, N, M) ((N) * (M) + (D)) 1602 1603 DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA) 1604 1605 /* Vector by vector plus scalar */ 1606 #define DO_VMLAS(D, N, M) ((N) * (D) + (M)) 1607 1608 DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS) 1609 1610 /* 1611 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 1612 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 1613 * SATMASK specifies which bits of the predicate mask matter for determining 1614 * whether to propagate a saturation indication into FPSCR.QC -- for 1615 * the 16x16->32 case we must check only the bit corresponding to the T or B 1616 * half that we used, but for the 32x32->64 case we propagate if the mask 1617 * bit is set for either half. 1618 */ 1619 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1620 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1621 uint32_t rm) \ 1622 { \ 1623 LTYPE *d = vd; \ 1624 TYPE *n = vn; \ 1625 TYPE m = rm; \ 1626 uint16_t mask = mve_element_mask(env); \ 1627 unsigned le; \ 1628 bool qc = false; \ 1629 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1630 bool sat = false; \ 1631 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 1632 mergemask(&d[H##LESIZE(le)], r, mask); \ 1633 qc |= sat && (mask & SATMASK); \ 1634 } \ 1635 if (qc) { \ 1636 env->vfp.qc[0] = qc; \ 1637 } \ 1638 mve_advance_vpt(env); \ 1639 } 1640 1641 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1642 { 1643 int64_t r = ((int64_t)n * m) * 2; 1644 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1645 } 1646 1647 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1648 { 1649 /* The multiply can't overflow, but the doubling might */ 1650 int64_t r = (int64_t)n * m; 1651 if (r > INT64_MAX / 2) { 1652 *sat = true; 1653 return INT64_MAX; 1654 } else if (r < INT64_MIN / 2) { 1655 *sat = true; 1656 return INT64_MIN; 1657 } else { 1658 return r * 2; 1659 } 1660 } 1661 1662 #define SATMASK16B 1 1663 #define SATMASK16T (1 << 2) 1664 #define SATMASK32 ((1 << 4) | 1) 1665 1666 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1667 do_qdmullh, SATMASK16B) 1668 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1669 do_qdmullw, SATMASK32) 1670 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1671 do_qdmullh, SATMASK16T) 1672 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1673 do_qdmullw, SATMASK32) 1674 1675 /* 1676 * Long saturating ops 1677 */ 1678 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1679 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1680 void *vm) \ 1681 { \ 1682 LTYPE *d = vd; \ 1683 TYPE *n = vn, *m = vm; \ 1684 uint16_t mask = mve_element_mask(env); \ 1685 unsigned le; \ 1686 bool qc = false; \ 1687 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1688 bool sat = false; \ 1689 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1690 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1691 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1692 qc |= sat && (mask & SATMASK); \ 1693 } \ 1694 if (qc) { \ 1695 env->vfp.qc[0] = qc; \ 1696 } \ 1697 mve_advance_vpt(env); \ 1698 } 1699 1700 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1701 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1702 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1703 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1704 1705 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1706 { 1707 m &= 0xff; 1708 if (m == 0) { 1709 return 0; 1710 } 1711 n = revbit8(n); 1712 if (m < 8) { 1713 n >>= 8 - m; 1714 } 1715 return n; 1716 } 1717 1718 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1719 { 1720 m &= 0xff; 1721 if (m == 0) { 1722 return 0; 1723 } 1724 n = revbit16(n); 1725 if (m < 16) { 1726 n >>= 16 - m; 1727 } 1728 return n; 1729 } 1730 1731 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1732 { 1733 m &= 0xff; 1734 if (m == 0) { 1735 return 0; 1736 } 1737 n = revbit32(n); 1738 if (m < 32) { 1739 n >>= 32 - m; 1740 } 1741 return n; 1742 } 1743 1744 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1745 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1746 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1747 1748 /* 1749 * Multiply add long dual accumulate ops. 1750 */ 1751 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1752 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1753 void *vm, uint64_t a) \ 1754 { \ 1755 uint16_t mask = mve_element_mask(env); \ 1756 unsigned e; \ 1757 TYPE *n = vn, *m = vm; \ 1758 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1759 if (mask & 1) { \ 1760 if (e & 1) { \ 1761 a ODDACC \ 1762 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1763 } else { \ 1764 a EVENACC \ 1765 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1766 } \ 1767 } \ 1768 } \ 1769 mve_advance_vpt(env); \ 1770 return a; \ 1771 } 1772 1773 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1774 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1775 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1776 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1777 1778 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1779 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1780 1781 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1782 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1783 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1784 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1785 1786 /* 1787 * Multiply add dual accumulate ops 1788 */ 1789 #define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1790 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1791 void *vm, uint32_t a) \ 1792 { \ 1793 uint16_t mask = mve_element_mask(env); \ 1794 unsigned e; \ 1795 TYPE *n = vn, *m = vm; \ 1796 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1797 if (mask & 1) { \ 1798 if (e & 1) { \ 1799 a ODDACC \ 1800 n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1801 } else { \ 1802 a EVENACC \ 1803 n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1804 } \ 1805 } \ 1806 } \ 1807 mve_advance_vpt(env); \ 1808 return a; \ 1809 } 1810 1811 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ 1812 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \ 1813 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \ 1814 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC) 1815 1816 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ 1817 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \ 1818 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \ 1819 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC) 1820 1821 DO_DAV_S(vmladavs, false, +=, +=) 1822 DO_DAV_U(vmladavu, false, +=, +=) 1823 DO_DAV_S(vmlsdav, false, +=, -=) 1824 DO_DAV_S(vmladavsx, true, +=, +=) 1825 DO_DAV_S(vmlsdavx, true, +=, -=) 1826 1827 /* 1828 * Rounding multiply add long dual accumulate high. In the pseudocode 1829 * this is implemented with a 72-bit internal accumulator value of which 1830 * the top 64 bits are returned. We optimize this to avoid having to 1831 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1832 * is squashed back into 64-bits after each beat. 1833 */ 1834 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1835 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1836 void *vm, uint64_t a) \ 1837 { \ 1838 uint16_t mask = mve_element_mask(env); \ 1839 unsigned e; \ 1840 TYPE *n = vn, *m = vm; \ 1841 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1842 if (mask & 1) { \ 1843 LTYPE mul; \ 1844 if (e & 1) { \ 1845 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1846 if (SUB) { \ 1847 mul = -mul; \ 1848 } \ 1849 } else { \ 1850 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1851 } \ 1852 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1853 a += mul; \ 1854 } \ 1855 } \ 1856 mve_advance_vpt(env); \ 1857 return a; \ 1858 } 1859 1860 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1861 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1862 1863 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1864 1865 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1866 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1867 1868 /* Vector add across vector */ 1869 #define DO_VADDV(OP, ESIZE, TYPE) \ 1870 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1871 uint32_t ra) \ 1872 { \ 1873 uint16_t mask = mve_element_mask(env); \ 1874 unsigned e; \ 1875 TYPE *m = vm; \ 1876 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1877 if (mask & 1) { \ 1878 ra += m[H##ESIZE(e)]; \ 1879 } \ 1880 } \ 1881 mve_advance_vpt(env); \ 1882 return ra; \ 1883 } \ 1884 1885 DO_VADDV(vaddvsb, 1, int8_t) 1886 DO_VADDV(vaddvsh, 2, int16_t) 1887 DO_VADDV(vaddvsw, 4, int32_t) 1888 DO_VADDV(vaddvub, 1, uint8_t) 1889 DO_VADDV(vaddvuh, 2, uint16_t) 1890 DO_VADDV(vaddvuw, 4, uint32_t) 1891 1892 /* 1893 * Vector max/min across vector. Unlike VADDV, we must 1894 * read ra as the element size, not its full width. 1895 * We work with int64_t internally for simplicity. 1896 */ 1897 #define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \ 1898 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1899 uint32_t ra_in) \ 1900 { \ 1901 uint16_t mask = mve_element_mask(env); \ 1902 unsigned e; \ 1903 TYPE *m = vm; \ 1904 int64_t ra = (RATYPE)ra_in; \ 1905 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1906 if (mask & 1) { \ 1907 ra = FN(ra, m[H##ESIZE(e)]); \ 1908 } \ 1909 } \ 1910 mve_advance_vpt(env); \ 1911 return ra; \ 1912 } \ 1913 1914 #define DO_VMAXMINV_U(INSN, FN) \ 1915 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \ 1916 DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \ 1917 DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN) 1918 #define DO_VMAXMINV_S(INSN, FN) \ 1919 DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \ 1920 DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \ 1921 DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN) 1922 1923 /* 1924 * Helpers for max and min of absolute values across vector: 1925 * note that we only take the absolute value of 'm', not 'n' 1926 */ 1927 static int64_t do_maxa(int64_t n, int64_t m) 1928 { 1929 if (m < 0) { 1930 m = -m; 1931 } 1932 return MAX(n, m); 1933 } 1934 1935 static int64_t do_mina(int64_t n, int64_t m) 1936 { 1937 if (m < 0) { 1938 m = -m; 1939 } 1940 return MIN(n, m); 1941 } 1942 1943 DO_VMAXMINV_S(vmaxvs, DO_MAX) 1944 DO_VMAXMINV_U(vmaxvu, DO_MAX) 1945 DO_VMAXMINV_S(vminvs, DO_MIN) 1946 DO_VMAXMINV_U(vminvu, DO_MIN) 1947 /* 1948 * VMAXAV, VMINAV treat the general purpose input as unsigned 1949 * and the vector elements as signed. 1950 */ 1951 DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa) 1952 DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa) 1953 DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa) 1954 DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) 1955 DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) 1956 DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) 1957 1958 #define DO_VABAV(OP, ESIZE, TYPE) \ 1959 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1960 void *vm, uint32_t ra) \ 1961 { \ 1962 uint16_t mask = mve_element_mask(env); \ 1963 unsigned e; \ 1964 TYPE *m = vm, *n = vn; \ 1965 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1966 if (mask & 1) { \ 1967 int64_t n0 = n[H##ESIZE(e)]; \ 1968 int64_t m0 = m[H##ESIZE(e)]; \ 1969 uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \ 1970 ra += r; \ 1971 } \ 1972 } \ 1973 mve_advance_vpt(env); \ 1974 return ra; \ 1975 } 1976 1977 DO_VABAV(vabavsb, 1, int8_t) 1978 DO_VABAV(vabavsh, 2, int16_t) 1979 DO_VABAV(vabavsw, 4, int32_t) 1980 DO_VABAV(vabavub, 1, uint8_t) 1981 DO_VABAV(vabavuh, 2, uint16_t) 1982 DO_VABAV(vabavuw, 4, uint32_t) 1983 1984 #define DO_VADDLV(OP, TYPE, LTYPE) \ 1985 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1986 uint64_t ra) \ 1987 { \ 1988 uint16_t mask = mve_element_mask(env); \ 1989 unsigned e; \ 1990 TYPE *m = vm; \ 1991 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1992 if (mask & 1) { \ 1993 ra += (LTYPE)m[H4(e)]; \ 1994 } \ 1995 } \ 1996 mve_advance_vpt(env); \ 1997 return ra; \ 1998 } \ 1999 2000 DO_VADDLV(vaddlv_s, int32_t, int64_t) 2001 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 2002 2003 /* Shifts by immediate */ 2004 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 2005 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2006 void *vm, uint32_t shift) \ 2007 { \ 2008 TYPE *d = vd, *m = vm; \ 2009 uint16_t mask = mve_element_mask(env); \ 2010 unsigned e; \ 2011 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2012 mergemask(&d[H##ESIZE(e)], \ 2013 FN(m[H##ESIZE(e)], shift), mask); \ 2014 } \ 2015 mve_advance_vpt(env); \ 2016 } 2017 2018 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 2019 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2020 void *vm, uint32_t shift) \ 2021 { \ 2022 TYPE *d = vd, *m = vm; \ 2023 uint16_t mask = mve_element_mask(env); \ 2024 unsigned e; \ 2025 bool qc = false; \ 2026 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2027 bool sat = false; \ 2028 mergemask(&d[H##ESIZE(e)], \ 2029 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 2030 qc |= sat & mask & 1; \ 2031 } \ 2032 if (qc) { \ 2033 env->vfp.qc[0] = qc; \ 2034 } \ 2035 mve_advance_vpt(env); \ 2036 } 2037 2038 /* provide unsigned 2-op shift helpers for all sizes */ 2039 #define DO_2SHIFT_U(OP, FN) \ 2040 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 2041 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 2042 DO_2SHIFT(OP##w, 4, uint32_t, FN) 2043 #define DO_2SHIFT_S(OP, FN) \ 2044 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 2045 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 2046 DO_2SHIFT(OP##w, 4, int32_t, FN) 2047 2048 #define DO_2SHIFT_SAT_U(OP, FN) \ 2049 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 2050 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 2051 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 2052 #define DO_2SHIFT_SAT_S(OP, FN) \ 2053 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 2054 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 2055 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 2056 2057 DO_2SHIFT_U(vshli_u, DO_VSHLU) 2058 DO_2SHIFT_S(vshli_s, DO_VSHLS) 2059 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 2060 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 2061 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 2062 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 2063 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 2064 DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP) 2065 DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP) 2066 2067 /* Shift-and-insert; we always work with 64 bits at a time */ 2068 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 2069 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2070 void *vm, uint32_t shift) \ 2071 { \ 2072 uint64_t *d = vd, *m = vm; \ 2073 uint16_t mask; \ 2074 uint64_t shiftmask; \ 2075 unsigned e; \ 2076 if (shift == ESIZE * 8) { \ 2077 /* \ 2078 * Only VSRI can shift by <dt>; it should mean "don't \ 2079 * update the destination". The generic logic can't handle \ 2080 * this because it would try to shift by an out-of-range \ 2081 * amount, so special case it here. \ 2082 */ \ 2083 goto done; \ 2084 } \ 2085 assert(shift < ESIZE * 8); \ 2086 mask = mve_element_mask(env); \ 2087 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 2088 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 2089 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 2090 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 2091 (d[H8(e)] & ~shiftmask); \ 2092 mergemask(&d[H8(e)], r, mask); \ 2093 } \ 2094 done: \ 2095 mve_advance_vpt(env); \ 2096 } 2097 2098 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 2099 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 2100 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 2101 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 2102 2103 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 2104 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 2105 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 2106 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 2107 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 2108 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 2109 2110 /* 2111 * Long shifts taking half-sized inputs from top or bottom of the input 2112 * vector and producing a double-width result. ESIZE, TYPE are for 2113 * the input, and LESIZE, LTYPE for the output. 2114 * Unlike the normal shift helpers, we do not handle negative shift counts, 2115 * because the long shift is strictly left-only. 2116 */ 2117 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2118 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2119 void *vm, uint32_t shift) \ 2120 { \ 2121 LTYPE *d = vd; \ 2122 TYPE *m = vm; \ 2123 uint16_t mask = mve_element_mask(env); \ 2124 unsigned le; \ 2125 assert(shift <= 16); \ 2126 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2127 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 2128 mergemask(&d[H##LESIZE(le)], r, mask); \ 2129 } \ 2130 mve_advance_vpt(env); \ 2131 } 2132 2133 #define DO_VSHLL_ALL(OP, TOP) \ 2134 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 2135 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 2136 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 2137 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 2138 2139 DO_VSHLL_ALL(vshllb, false) 2140 DO_VSHLL_ALL(vshllt, true) 2141 2142 /* 2143 * Narrowing right shifts, taking a double sized input, shifting it 2144 * and putting the result in either the top or bottom half of the output. 2145 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 2146 */ 2147 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2148 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2149 void *vm, uint32_t shift) \ 2150 { \ 2151 LTYPE *m = vm; \ 2152 TYPE *d = vd; \ 2153 uint16_t mask = mve_element_mask(env); \ 2154 unsigned le; \ 2155 mask >>= ESIZE * TOP; \ 2156 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2157 TYPE r = FN(m[H##LESIZE(le)], shift); \ 2158 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2159 } \ 2160 mve_advance_vpt(env); \ 2161 } 2162 2163 #define DO_VSHRN_ALL(OP, FN) \ 2164 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 2165 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 2166 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 2167 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 2168 2169 static inline uint64_t do_urshr(uint64_t x, unsigned sh) 2170 { 2171 if (likely(sh < 64)) { 2172 return (x >> sh) + ((x >> (sh - 1)) & 1); 2173 } else if (sh == 64) { 2174 return x >> 63; 2175 } else { 2176 return 0; 2177 } 2178 } 2179 2180 static inline int64_t do_srshr(int64_t x, unsigned sh) 2181 { 2182 if (likely(sh < 64)) { 2183 return (x >> sh) + ((x >> (sh - 1)) & 1); 2184 } else { 2185 /* Rounding the sign bit always produces 0. */ 2186 return 0; 2187 } 2188 } 2189 2190 DO_VSHRN_ALL(vshrn, DO_SHR) 2191 DO_VSHRN_ALL(vrshrn, do_urshr) 2192 2193 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 2194 bool *satp) 2195 { 2196 if (val > max) { 2197 *satp = true; 2198 return max; 2199 } else if (val < min) { 2200 *satp = true; 2201 return min; 2202 } else { 2203 return val; 2204 } 2205 } 2206 2207 /* Saturating narrowing right shifts */ 2208 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2209 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2210 void *vm, uint32_t shift) \ 2211 { \ 2212 LTYPE *m = vm; \ 2213 TYPE *d = vd; \ 2214 uint16_t mask = mve_element_mask(env); \ 2215 bool qc = false; \ 2216 unsigned le; \ 2217 mask >>= ESIZE * TOP; \ 2218 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2219 bool sat = false; \ 2220 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 2221 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2222 qc |= sat & mask & 1; \ 2223 } \ 2224 if (qc) { \ 2225 env->vfp.qc[0] = qc; \ 2226 } \ 2227 mve_advance_vpt(env); \ 2228 } 2229 2230 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 2231 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2232 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2233 2234 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 2235 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2236 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2237 2238 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 2239 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2240 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2241 2242 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 2243 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2244 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2245 2246 #define DO_SHRN_SB(N, M, SATP) \ 2247 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 2248 #define DO_SHRN_UB(N, M, SATP) \ 2249 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2250 #define DO_SHRUN_B(N, M, SATP) \ 2251 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2252 2253 #define DO_SHRN_SH(N, M, SATP) \ 2254 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 2255 #define DO_SHRN_UH(N, M, SATP) \ 2256 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2257 #define DO_SHRUN_H(N, M, SATP) \ 2258 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2259 2260 #define DO_RSHRN_SB(N, M, SATP) \ 2261 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 2262 #define DO_RSHRN_UB(N, M, SATP) \ 2263 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 2264 #define DO_RSHRUN_B(N, M, SATP) \ 2265 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 2266 2267 #define DO_RSHRN_SH(N, M, SATP) \ 2268 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 2269 #define DO_RSHRN_UH(N, M, SATP) \ 2270 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 2271 #define DO_RSHRUN_H(N, M, SATP) \ 2272 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 2273 2274 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 2275 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 2276 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 2277 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 2278 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 2279 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 2280 2281 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 2282 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 2283 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 2284 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 2285 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 2286 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 2287 2288 #define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2289 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2290 { \ 2291 LTYPE *m = vm; \ 2292 TYPE *d = vd; \ 2293 uint16_t mask = mve_element_mask(env); \ 2294 unsigned le; \ 2295 mask >>= ESIZE * TOP; \ 2296 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2297 mergemask(&d[H##ESIZE(le * 2 + TOP)], \ 2298 m[H##LESIZE(le)], mask); \ 2299 } \ 2300 mve_advance_vpt(env); \ 2301 } 2302 2303 DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t) 2304 DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t) 2305 DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t) 2306 DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t) 2307 2308 #define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2309 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2310 { \ 2311 LTYPE *m = vm; \ 2312 TYPE *d = vd; \ 2313 uint16_t mask = mve_element_mask(env); \ 2314 bool qc = false; \ 2315 unsigned le; \ 2316 mask >>= ESIZE * TOP; \ 2317 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2318 bool sat = false; \ 2319 TYPE r = FN(m[H##LESIZE(le)], &sat); \ 2320 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2321 qc |= sat & mask & 1; \ 2322 } \ 2323 if (qc) { \ 2324 env->vfp.qc[0] = qc; \ 2325 } \ 2326 mve_advance_vpt(env); \ 2327 } 2328 2329 #define DO_VMOVN_SAT_UB(BOP, TOP, FN) \ 2330 DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2331 DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2332 2333 #define DO_VMOVN_SAT_UH(BOP, TOP, FN) \ 2334 DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2335 DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2336 2337 #define DO_VMOVN_SAT_SB(BOP, TOP, FN) \ 2338 DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2339 DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2340 2341 #define DO_VMOVN_SAT_SH(BOP, TOP, FN) \ 2342 DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2343 DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2344 2345 #define DO_VQMOVN_SB(N, SATP) \ 2346 do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP) 2347 #define DO_VQMOVN_UB(N, SATP) \ 2348 do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP) 2349 #define DO_VQMOVUN_B(N, SATP) \ 2350 do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP) 2351 2352 #define DO_VQMOVN_SH(N, SATP) \ 2353 do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP) 2354 #define DO_VQMOVN_UH(N, SATP) \ 2355 do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP) 2356 #define DO_VQMOVUN_H(N, SATP) \ 2357 do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP) 2358 2359 DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB) 2360 DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH) 2361 DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB) 2362 DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH) 2363 DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B) 2364 DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H) 2365 2366 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 2367 uint32_t shift) 2368 { 2369 uint32_t *d = vd; 2370 uint16_t mask = mve_element_mask(env); 2371 unsigned e; 2372 uint32_t r; 2373 2374 /* 2375 * For each 32-bit element, we shift it left, bringing in the 2376 * low 'shift' bits of rdm at the bottom. Bits shifted out at 2377 * the top become the new rdm, if the predicate mask permits. 2378 * The final rdm value is returned to update the register. 2379 * shift == 0 here means "shift by 32 bits". 2380 */ 2381 if (shift == 0) { 2382 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2383 r = rdm; 2384 if (mask & 1) { 2385 rdm = d[H4(e)]; 2386 } 2387 mergemask(&d[H4(e)], r, mask); 2388 } 2389 } else { 2390 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 2391 2392 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2393 r = (d[H4(e)] << shift) | (rdm & shiftmask); 2394 if (mask & 1) { 2395 rdm = d[H4(e)] >> (32 - shift); 2396 } 2397 mergemask(&d[H4(e)], r, mask); 2398 } 2399 } 2400 mve_advance_vpt(env); 2401 return rdm; 2402 } 2403 2404 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2405 { 2406 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 2407 } 2408 2409 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 2410 { 2411 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 2412 } 2413 2414 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2415 { 2416 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 2417 } 2418 2419 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2420 { 2421 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 2422 } 2423 2424 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2425 { 2426 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 2427 } 2428 2429 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2430 { 2431 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 2432 } 2433 2434 /* Operate on 64-bit values, but saturate at 48 bits */ 2435 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 2436 bool round, uint32_t *sat) 2437 { 2438 int64_t val, extval; 2439 2440 if (shift <= -48) { 2441 /* Rounding the sign bit always produces 0. */ 2442 if (round) { 2443 return 0; 2444 } 2445 return src >> 63; 2446 } else if (shift < 0) { 2447 if (round) { 2448 src >>= -shift - 1; 2449 val = (src >> 1) + (src & 1); 2450 } else { 2451 val = src >> -shift; 2452 } 2453 extval = sextract64(val, 0, 48); 2454 if (!sat || val == extval) { 2455 return extval; 2456 } 2457 } else if (shift < 48) { 2458 extval = sextract64(src << shift, 0, 48); 2459 if (!sat || src == (extval >> shift)) { 2460 return extval; 2461 } 2462 } else if (!sat || src == 0) { 2463 return 0; 2464 } 2465 2466 *sat = 1; 2467 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 2468 } 2469 2470 /* Operate on 64-bit values, but saturate at 48 bits */ 2471 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 2472 bool round, uint32_t *sat) 2473 { 2474 uint64_t val, extval; 2475 2476 if (shift <= -(48 + round)) { 2477 return 0; 2478 } else if (shift < 0) { 2479 if (round) { 2480 val = src >> (-shift - 1); 2481 val = (val >> 1) + (val & 1); 2482 } else { 2483 val = src >> -shift; 2484 } 2485 extval = extract64(val, 0, 48); 2486 if (!sat || val == extval) { 2487 return extval; 2488 } 2489 } else if (shift < 48) { 2490 extval = extract64(src << shift, 0, 48); 2491 if (!sat || src == (extval >> shift)) { 2492 return extval; 2493 } 2494 } else if (!sat || src == 0) { 2495 return 0; 2496 } 2497 2498 *sat = 1; 2499 return MAKE_64BIT_MASK(0, 48); 2500 } 2501 2502 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 2503 { 2504 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 2505 } 2506 2507 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 2508 { 2509 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 2510 } 2511 2512 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2513 { 2514 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2515 } 2516 2517 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2518 { 2519 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2520 } 2521 2522 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2523 { 2524 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 2525 } 2526 2527 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 2528 { 2529 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 2530 } 2531 2532 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \ 2533 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2534 uint32_t offset, uint32_t imm) \ 2535 { \ 2536 TYPE *d = vd; \ 2537 uint16_t mask = mve_element_mask(env); \ 2538 unsigned e; \ 2539 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2540 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2541 offset = FN(offset, imm); \ 2542 } \ 2543 mve_advance_vpt(env); \ 2544 return offset; \ 2545 } 2546 2547 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ 2548 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2549 uint32_t offset, uint32_t wrap, \ 2550 uint32_t imm) \ 2551 { \ 2552 TYPE *d = vd; \ 2553 uint16_t mask = mve_element_mask(env); \ 2554 unsigned e; \ 2555 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2556 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2557 offset = FN(offset, wrap, imm); \ 2558 } \ 2559 mve_advance_vpt(env); \ 2560 return offset; \ 2561 } 2562 2563 #define DO_VIDUP_ALL(OP, FN) \ 2564 DO_VIDUP(OP##b, 1, int8_t, FN) \ 2565 DO_VIDUP(OP##h, 2, int16_t, FN) \ 2566 DO_VIDUP(OP##w, 4, int32_t, FN) 2567 2568 #define DO_VIWDUP_ALL(OP, FN) \ 2569 DO_VIWDUP(OP##b, 1, int8_t, FN) \ 2570 DO_VIWDUP(OP##h, 2, int16_t, FN) \ 2571 DO_VIWDUP(OP##w, 4, int32_t, FN) 2572 2573 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2574 { 2575 offset += imm; 2576 if (offset == wrap) { 2577 offset = 0; 2578 } 2579 return offset; 2580 } 2581 2582 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2583 { 2584 if (offset == 0) { 2585 offset = wrap; 2586 } 2587 offset -= imm; 2588 return offset; 2589 } 2590 2591 DO_VIDUP_ALL(vidup, DO_ADD) 2592 DO_VIWDUP_ALL(viwdup, do_add_wrap) 2593 DO_VIWDUP_ALL(vdwdup, do_sub_wrap) 2594 2595 /* 2596 * Vector comparison. 2597 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. 2598 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. 2599 * P0 bits otherwise are updated with the results of the comparisons. 2600 * We must also keep unchanged the MASK fields at the top of v7m.vpr. 2601 */ 2602 #define DO_VCMP(OP, ESIZE, TYPE, FN) \ 2603 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 2604 { \ 2605 TYPE *n = vn, *m = vm; \ 2606 uint16_t mask = mve_element_mask(env); \ 2607 uint16_t eci_mask = mve_eci_mask(env); \ 2608 uint16_t beatpred = 0; \ 2609 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2610 unsigned e; \ 2611 for (e = 0; e < 16 / ESIZE; e++) { \ 2612 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ 2613 /* Comparison sets 0/1 bits for each byte in the element */ \ 2614 beatpred |= r * emask; \ 2615 emask <<= ESIZE; \ 2616 } \ 2617 beatpred &= mask; \ 2618 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2619 (beatpred & eci_mask); \ 2620 mve_advance_vpt(env); \ 2621 } 2622 2623 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ 2624 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 2625 uint32_t rm) \ 2626 { \ 2627 TYPE *n = vn; \ 2628 uint16_t mask = mve_element_mask(env); \ 2629 uint16_t eci_mask = mve_eci_mask(env); \ 2630 uint16_t beatpred = 0; \ 2631 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2632 unsigned e; \ 2633 for (e = 0; e < 16 / ESIZE; e++) { \ 2634 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \ 2635 /* Comparison sets 0/1 bits for each byte in the element */ \ 2636 beatpred |= r * emask; \ 2637 emask <<= ESIZE; \ 2638 } \ 2639 beatpred &= mask; \ 2640 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2641 (beatpred & eci_mask); \ 2642 mve_advance_vpt(env); \ 2643 } 2644 2645 #define DO_VCMP_S(OP, FN) \ 2646 DO_VCMP(OP##b, 1, int8_t, FN) \ 2647 DO_VCMP(OP##h, 2, int16_t, FN) \ 2648 DO_VCMP(OP##w, 4, int32_t, FN) \ 2649 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ 2650 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ 2651 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) 2652 2653 #define DO_VCMP_U(OP, FN) \ 2654 DO_VCMP(OP##b, 1, uint8_t, FN) \ 2655 DO_VCMP(OP##h, 2, uint16_t, FN) \ 2656 DO_VCMP(OP##w, 4, uint32_t, FN) \ 2657 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ 2658 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ 2659 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) 2660 2661 #define DO_EQ(N, M) ((N) == (M)) 2662 #define DO_NE(N, M) ((N) != (M)) 2663 #define DO_EQ(N, M) ((N) == (M)) 2664 #define DO_EQ(N, M) ((N) == (M)) 2665 #define DO_GE(N, M) ((N) >= (M)) 2666 #define DO_LT(N, M) ((N) < (M)) 2667 #define DO_GT(N, M) ((N) > (M)) 2668 #define DO_LE(N, M) ((N) <= (M)) 2669 2670 DO_VCMP_U(vcmpeq, DO_EQ) 2671 DO_VCMP_U(vcmpne, DO_NE) 2672 DO_VCMP_U(vcmpcs, DO_GE) 2673 DO_VCMP_U(vcmphi, DO_GT) 2674 DO_VCMP_S(vcmpge, DO_GE) 2675 DO_VCMP_S(vcmplt, DO_LT) 2676 DO_VCMP_S(vcmpgt, DO_GT) 2677 DO_VCMP_S(vcmple, DO_LE) 2678 2679 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) 2680 { 2681 /* 2682 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n] 2683 * but note that whether bytes are written to Qd is still subject 2684 * to (all forms of) predication in the usual way. 2685 */ 2686 uint64_t *d = vd, *n = vn, *m = vm; 2687 uint16_t mask = mve_element_mask(env); 2688 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 2689 unsigned e; 2690 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) { 2691 uint64_t r = m[H8(e)]; 2692 mergemask(&r, n[H8(e)], p0); 2693 mergemask(&d[H8(e)], r, mask); 2694 } 2695 mve_advance_vpt(env); 2696 } 2697 2698 void HELPER(mve_vpnot)(CPUARMState *env) 2699 { 2700 /* 2701 * P0 bits for unexecuted beats (where eci_mask is 0) are unchanged. 2702 * P0 bits for predicated lanes in executed bits (where mask is 0) are 0. 2703 * P0 bits otherwise are inverted. 2704 * (This is the same logic as VCMP.) 2705 * This insn is itself subject to predication and to beat-wise execution, 2706 * and after it executes VPT state advances in the usual way. 2707 */ 2708 uint16_t mask = mve_element_mask(env); 2709 uint16_t eci_mask = mve_eci_mask(env); 2710 uint16_t beatpred = ~env->v7m.vpr & mask; 2711 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask); 2712 mve_advance_vpt(env); 2713 } 2714 2715 /* 2716 * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed, 2717 * otherwise set according to value of Rn. The calculation of 2718 * newmask here works in the same way as the calculation of the 2719 * ltpmask in mve_element_mask(), but we have pre-calculated 2720 * the masklen in the generated code. 2721 */ 2722 void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen) 2723 { 2724 uint16_t mask = mve_element_mask(env); 2725 uint16_t eci_mask = mve_eci_mask(env); 2726 uint16_t newmask; 2727 2728 assert(masklen <= 16); 2729 newmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 2730 newmask &= mask; 2731 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask); 2732 mve_advance_vpt(env); 2733 } 2734 2735 #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ 2736 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2737 { \ 2738 TYPE *d = vd, *m = vm; \ 2739 uint16_t mask = mve_element_mask(env); \ 2740 unsigned e; \ 2741 bool qc = false; \ 2742 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2743 bool sat = false; \ 2744 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)], &sat), mask); \ 2745 qc |= sat & mask & 1; \ 2746 } \ 2747 if (qc) { \ 2748 env->vfp.qc[0] = qc; \ 2749 } \ 2750 mve_advance_vpt(env); \ 2751 } 2752 2753 #define DO_VQABS_B(N, SATP) \ 2754 do_sat_bhs(DO_ABS((int64_t)N), INT8_MIN, INT8_MAX, SATP) 2755 #define DO_VQABS_H(N, SATP) \ 2756 do_sat_bhs(DO_ABS((int64_t)N), INT16_MIN, INT16_MAX, SATP) 2757 #define DO_VQABS_W(N, SATP) \ 2758 do_sat_bhs(DO_ABS((int64_t)N), INT32_MIN, INT32_MAX, SATP) 2759 2760 #define DO_VQNEG_B(N, SATP) do_sat_bhs(-(int64_t)N, INT8_MIN, INT8_MAX, SATP) 2761 #define DO_VQNEG_H(N, SATP) do_sat_bhs(-(int64_t)N, INT16_MIN, INT16_MAX, SATP) 2762 #define DO_VQNEG_W(N, SATP) do_sat_bhs(-(int64_t)N, INT32_MIN, INT32_MAX, SATP) 2763 2764 DO_1OP_SAT(vqabsb, 1, int8_t, DO_VQABS_B) 2765 DO_1OP_SAT(vqabsh, 2, int16_t, DO_VQABS_H) 2766 DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W) 2767 2768 DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B) 2769 DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H) 2770 DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W) 2771 2772 /* 2773 * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its 2774 * absolute value; we then do an unsigned comparison. 2775 */ 2776 #define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \ 2777 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2778 { \ 2779 UTYPE *d = vd; \ 2780 STYPE *m = vm; \ 2781 uint16_t mask = mve_element_mask(env); \ 2782 unsigned e; \ 2783 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2784 UTYPE r = DO_ABS(m[H##ESIZE(e)]); \ 2785 r = FN(d[H##ESIZE(e)], r); \ 2786 mergemask(&d[H##ESIZE(e)], r, mask); \ 2787 } \ 2788 mve_advance_vpt(env); \ 2789 } 2790 2791 DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX) 2792 DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX) 2793 DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) 2794 DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) 2795 DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) 2796 DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) 2797 2798 /* 2799 * 2-operand floating point. Note that if an element is partially 2800 * predicated we must do the FP operation to update the non-predicated 2801 * bytes, but we must be careful to avoid updating the FP exception 2802 * state unless byte 0 of the element was unpredicated. 2803 */ 2804 #define DO_2OP_FP(OP, ESIZE, TYPE, FN) \ 2805 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2806 void *vd, void *vn, void *vm) \ 2807 { \ 2808 TYPE *d = vd, *n = vn, *m = vm; \ 2809 TYPE r; \ 2810 uint16_t mask = mve_element_mask(env); \ 2811 unsigned e; \ 2812 float_status *fpst; \ 2813 float_status scratch_fpst; \ 2814 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2815 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2816 continue; \ 2817 } \ 2818 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2819 if (!(mask & 1)) { \ 2820 /* We need the result but without updating flags */ \ 2821 scratch_fpst = *fpst; \ 2822 fpst = &scratch_fpst; \ 2823 } \ 2824 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 2825 mergemask(&d[H##ESIZE(e)], r, mask); \ 2826 } \ 2827 mve_advance_vpt(env); \ 2828 } 2829 2830 #define DO_2OP_FP_ALL(OP, FN) \ 2831 DO_2OP_FP(OP##h, 2, float16, float16_##FN) \ 2832 DO_2OP_FP(OP##s, 4, float32, float32_##FN) 2833 2834 DO_2OP_FP_ALL(vfadd, add) 2835 DO_2OP_FP_ALL(vfsub, sub) 2836 DO_2OP_FP_ALL(vfmul, mul) 2837 2838 static inline float16 float16_abd(float16 a, float16 b, float_status *s) 2839 { 2840 return float16_abs(float16_sub(a, b, s)); 2841 } 2842 2843 static inline float32 float32_abd(float32 a, float32 b, float_status *s) 2844 { 2845 return float32_abs(float32_sub(a, b, s)); 2846 } 2847 2848 DO_2OP_FP_ALL(vfabd, abd) 2849 DO_2OP_FP_ALL(vmaxnm, maxnum) 2850 DO_2OP_FP_ALL(vminnm, minnum) 2851 2852 static inline float16 float16_maxnuma(float16 a, float16 b, float_status *s) 2853 { 2854 return float16_maxnum(float16_abs(a), float16_abs(b), s); 2855 } 2856 2857 static inline float32 float32_maxnuma(float32 a, float32 b, float_status *s) 2858 { 2859 return float32_maxnum(float32_abs(a), float32_abs(b), s); 2860 } 2861 2862 static inline float16 float16_minnuma(float16 a, float16 b, float_status *s) 2863 { 2864 return float16_minnum(float16_abs(a), float16_abs(b), s); 2865 } 2866 2867 static inline float32 float32_minnuma(float32 a, float32 b, float_status *s) 2868 { 2869 return float32_minnum(float32_abs(a), float32_abs(b), s); 2870 } 2871 2872 DO_2OP_FP_ALL(vmaxnma, maxnuma) 2873 DO_2OP_FP_ALL(vminnma, minnuma) 2874 2875 #define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \ 2876 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2877 void *vd, void *vn, void *vm) \ 2878 { \ 2879 TYPE *d = vd, *n = vn, *m = vm; \ 2880 TYPE r[16 / ESIZE]; \ 2881 uint16_t tm, mask = mve_element_mask(env); \ 2882 unsigned e; \ 2883 float_status *fpst; \ 2884 float_status scratch_fpst; \ 2885 /* Calculate all results first to avoid overwriting inputs */ \ 2886 for (e = 0, tm = mask; e < 16 / ESIZE; e++, tm >>= ESIZE) { \ 2887 if ((tm & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2888 r[e] = 0; \ 2889 continue; \ 2890 } \ 2891 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2892 if (!(tm & 1)) { \ 2893 /* We need the result but without updating flags */ \ 2894 scratch_fpst = *fpst; \ 2895 fpst = &scratch_fpst; \ 2896 } \ 2897 if (!(e & 1)) { \ 2898 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)], fpst); \ 2899 } else { \ 2900 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)], fpst); \ 2901 } \ 2902 } \ 2903 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2904 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 2905 } \ 2906 mve_advance_vpt(env); \ 2907 } 2908 2909 DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, float16_add) 2910 DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add) 2911 DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub) 2912 DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) 2913 2914 #define DO_VFMA(OP, ESIZE, TYPE, CHS) \ 2915 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2916 void *vd, void *vn, void *vm) \ 2917 { \ 2918 TYPE *d = vd, *n = vn, *m = vm; \ 2919 TYPE r; \ 2920 uint16_t mask = mve_element_mask(env); \ 2921 unsigned e; \ 2922 float_status *fpst; \ 2923 float_status scratch_fpst; \ 2924 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2925 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2926 continue; \ 2927 } \ 2928 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2929 if (!(mask & 1)) { \ 2930 /* We need the result but without updating flags */ \ 2931 scratch_fpst = *fpst; \ 2932 fpst = &scratch_fpst; \ 2933 } \ 2934 r = n[H##ESIZE(e)]; \ 2935 if (CHS) { \ 2936 r = TYPE##_chs(r); \ 2937 } \ 2938 r = TYPE##_muladd(r, m[H##ESIZE(e)], d[H##ESIZE(e)], \ 2939 0, fpst); \ 2940 mergemask(&d[H##ESIZE(e)], r, mask); \ 2941 } \ 2942 mve_advance_vpt(env); \ 2943 } 2944 2945 DO_VFMA(vfmah, 2, float16, false) 2946 DO_VFMA(vfmas, 4, float32, false) 2947 DO_VFMA(vfmsh, 2, float16, true) 2948 DO_VFMA(vfmss, 4, float32, true) 2949 2950 #define DO_VCMLA(OP, ESIZE, TYPE, ROT, FN) \ 2951 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2952 void *vd, void *vn, void *vm) \ 2953 { \ 2954 TYPE *d = vd, *n = vn, *m = vm; \ 2955 TYPE r0, r1, e1, e2, e3, e4; \ 2956 uint16_t mask = mve_element_mask(env); \ 2957 unsigned e; \ 2958 float_status *fpst0, *fpst1; \ 2959 float_status scratch_fpst; \ 2960 /* We loop through pairs of elements at a time */ \ 2961 for (e = 0; e < 16 / ESIZE; e += 2, mask >>= ESIZE * 2) { \ 2962 if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) == 0) { \ 2963 continue; \ 2964 } \ 2965 fpst0 = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2966 fpst1 = fpst0; \ 2967 if (!(mask & 1)) { \ 2968 scratch_fpst = *fpst0; \ 2969 fpst0 = &scratch_fpst; \ 2970 } \ 2971 if (!(mask & (1 << ESIZE))) { \ 2972 scratch_fpst = *fpst1; \ 2973 fpst1 = &scratch_fpst; \ 2974 } \ 2975 switch (ROT) { \ 2976 case 0: \ 2977 e1 = m[H##ESIZE(e)]; \ 2978 e2 = n[H##ESIZE(e)]; \ 2979 e3 = m[H##ESIZE(e + 1)]; \ 2980 e4 = n[H##ESIZE(e)]; \ 2981 break; \ 2982 case 1: \ 2983 e1 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 2984 e2 = n[H##ESIZE(e + 1)]; \ 2985 e3 = m[H##ESIZE(e)]; \ 2986 e4 = n[H##ESIZE(e + 1)]; \ 2987 break; \ 2988 case 2: \ 2989 e1 = TYPE##_chs(m[H##ESIZE(e)]); \ 2990 e2 = n[H##ESIZE(e)]; \ 2991 e3 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 2992 e4 = n[H##ESIZE(e)]; \ 2993 break; \ 2994 case 3: \ 2995 e1 = m[H##ESIZE(e + 1)]; \ 2996 e2 = n[H##ESIZE(e + 1)]; \ 2997 e3 = TYPE##_chs(m[H##ESIZE(e)]); \ 2998 e4 = n[H##ESIZE(e + 1)]; \ 2999 break; \ 3000 default: \ 3001 g_assert_not_reached(); \ 3002 } \ 3003 r0 = FN(e2, e1, d[H##ESIZE(e)], fpst0); \ 3004 r1 = FN(e4, e3, d[H##ESIZE(e + 1)], fpst1); \ 3005 mergemask(&d[H##ESIZE(e)], r0, mask); \ 3006 mergemask(&d[H##ESIZE(e + 1)], r1, mask >> ESIZE); \ 3007 } \ 3008 mve_advance_vpt(env); \ 3009 } 3010 3011 #define DO_VCMULH(N, M, D, S) float16_mul(N, M, S) 3012 #define DO_VCMULS(N, M, D, S) float32_mul(N, M, S) 3013 3014 #define DO_VCMLAH(N, M, D, S) float16_muladd(N, M, D, 0, S) 3015 #define DO_VCMLAS(N, M, D, S) float32_muladd(N, M, D, 0, S) 3016 3017 DO_VCMLA(vcmul0h, 2, float16, 0, DO_VCMULH) 3018 DO_VCMLA(vcmul0s, 4, float32, 0, DO_VCMULS) 3019 DO_VCMLA(vcmul90h, 2, float16, 1, DO_VCMULH) 3020 DO_VCMLA(vcmul90s, 4, float32, 1, DO_VCMULS) 3021 DO_VCMLA(vcmul180h, 2, float16, 2, DO_VCMULH) 3022 DO_VCMLA(vcmul180s, 4, float32, 2, DO_VCMULS) 3023 DO_VCMLA(vcmul270h, 2, float16, 3, DO_VCMULH) 3024 DO_VCMLA(vcmul270s, 4, float32, 3, DO_VCMULS) 3025 3026 DO_VCMLA(vcmla0h, 2, float16, 0, DO_VCMLAH) 3027 DO_VCMLA(vcmla0s, 4, float32, 0, DO_VCMLAS) 3028 DO_VCMLA(vcmla90h, 2, float16, 1, DO_VCMLAH) 3029 DO_VCMLA(vcmla90s, 4, float32, 1, DO_VCMLAS) 3030 DO_VCMLA(vcmla180h, 2, float16, 2, DO_VCMLAH) 3031 DO_VCMLA(vcmla180s, 4, float32, 2, DO_VCMLAS) 3032 DO_VCMLA(vcmla270h, 2, float16, 3, DO_VCMLAH) 3033 DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) 3034 3035 #define DO_2OP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3036 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3037 void *vd, void *vn, uint32_t rm) \ 3038 { \ 3039 TYPE *d = vd, *n = vn; \ 3040 TYPE r, m = rm; \ 3041 uint16_t mask = mve_element_mask(env); \ 3042 unsigned e; \ 3043 float_status *fpst; \ 3044 float_status scratch_fpst; \ 3045 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3046 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3047 continue; \ 3048 } \ 3049 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3050 if (!(mask & 1)) { \ 3051 /* We need the result but without updating flags */ \ 3052 scratch_fpst = *fpst; \ 3053 fpst = &scratch_fpst; \ 3054 } \ 3055 r = FN(n[H##ESIZE(e)], m, fpst); \ 3056 mergemask(&d[H##ESIZE(e)], r, mask); \ 3057 } \ 3058 mve_advance_vpt(env); \ 3059 } 3060 3061 #define DO_2OP_FP_SCALAR_ALL(OP, FN) \ 3062 DO_2OP_FP_SCALAR(OP##h, 2, float16, float16_##FN) \ 3063 DO_2OP_FP_SCALAR(OP##s, 4, float32, float32_##FN) 3064 3065 DO_2OP_FP_SCALAR_ALL(vfadd_scalar, add) 3066 DO_2OP_FP_SCALAR_ALL(vfsub_scalar, sub) 3067 DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) 3068 3069 #define DO_2OP_FP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 3070 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3071 void *vd, void *vn, uint32_t rm) \ 3072 { \ 3073 TYPE *d = vd, *n = vn; \ 3074 TYPE r, m = rm; \ 3075 uint16_t mask = mve_element_mask(env); \ 3076 unsigned e; \ 3077 float_status *fpst; \ 3078 float_status scratch_fpst; \ 3079 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3080 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3081 continue; \ 3082 } \ 3083 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3084 if (!(mask & 1)) { \ 3085 /* We need the result but without updating flags */ \ 3086 scratch_fpst = *fpst; \ 3087 fpst = &scratch_fpst; \ 3088 } \ 3089 r = FN(n[H##ESIZE(e)], m, d[H##ESIZE(e)], 0, fpst); \ 3090 mergemask(&d[H##ESIZE(e)], r, mask); \ 3091 } \ 3092 mve_advance_vpt(env); \ 3093 } 3094 3095 /* VFMAS is vector * vector + scalar, so swap op2 and op3 */ 3096 #define DO_VFMAS_SCALARH(N, M, D, F, S) float16_muladd(N, D, M, F, S) 3097 #define DO_VFMAS_SCALARS(N, M, D, F, S) float32_muladd(N, D, M, F, S) 3098 3099 /* VFMA is vector * scalar + vector */ 3100 DO_2OP_FP_ACC_SCALAR(vfma_scalarh, 2, float16, float16_muladd) 3101 DO_2OP_FP_ACC_SCALAR(vfma_scalars, 4, float32, float32_muladd) 3102 DO_2OP_FP_ACC_SCALAR(vfmas_scalarh, 2, float16, DO_VFMAS_SCALARH) 3103 DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) 3104 3105 /* Floating point max/min across vector. */ 3106 #define DO_FP_VMAXMINV(OP, ESIZE, TYPE, ABS, FN) \ 3107 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 3108 uint32_t ra_in) \ 3109 { \ 3110 uint16_t mask = mve_element_mask(env); \ 3111 unsigned e; \ 3112 TYPE *m = vm; \ 3113 TYPE ra = (TYPE)ra_in; \ 3114 float_status *fpst = \ 3115 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3116 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3117 if (mask & 1) { \ 3118 TYPE v = m[H##ESIZE(e)]; \ 3119 if (TYPE##_is_signaling_nan(ra, fpst)) { \ 3120 ra = TYPE##_silence_nan(ra, fpst); \ 3121 float_raise(float_flag_invalid, fpst); \ 3122 } \ 3123 if (TYPE##_is_signaling_nan(v, fpst)) { \ 3124 v = TYPE##_silence_nan(v, fpst); \ 3125 float_raise(float_flag_invalid, fpst); \ 3126 } \ 3127 if (ABS) { \ 3128 v = TYPE##_abs(v); \ 3129 } \ 3130 ra = FN(ra, v, fpst); \ 3131 } \ 3132 } \ 3133 mve_advance_vpt(env); \ 3134 return ra; \ 3135 } \ 3136 3137 #define NOP(X) (X) 3138 3139 DO_FP_VMAXMINV(vmaxnmvh, 2, float16, false, float16_maxnum) 3140 DO_FP_VMAXMINV(vmaxnmvs, 4, float32, false, float32_maxnum) 3141 DO_FP_VMAXMINV(vminnmvh, 2, float16, false, float16_minnum) 3142 DO_FP_VMAXMINV(vminnmvs, 4, float32, false, float32_minnum) 3143 DO_FP_VMAXMINV(vmaxnmavh, 2, float16, true, float16_maxnum) 3144 DO_FP_VMAXMINV(vmaxnmavs, 4, float32, true, float32_maxnum) 3145 DO_FP_VMAXMINV(vminnmavh, 2, float16, true, float16_minnum) 3146 DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) 3147 3148 /* FP compares; note that all comparisons signal InvalidOp for QNaNs */ 3149 #define DO_VCMP_FP(OP, ESIZE, TYPE, FN) \ 3150 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 3151 { \ 3152 TYPE *n = vn, *m = vm; \ 3153 uint16_t mask = mve_element_mask(env); \ 3154 uint16_t eci_mask = mve_eci_mask(env); \ 3155 uint16_t beatpred = 0; \ 3156 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3157 unsigned e; \ 3158 float_status *fpst; \ 3159 float_status scratch_fpst; \ 3160 bool r; \ 3161 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3162 if ((mask & emask) == 0) { \ 3163 continue; \ 3164 } \ 3165 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3166 if (!(mask & (1 << (e * ESIZE)))) { \ 3167 /* We need the result but without updating flags */ \ 3168 scratch_fpst = *fpst; \ 3169 fpst = &scratch_fpst; \ 3170 } \ 3171 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 3172 /* Comparison sets 0/1 bits for each byte in the element */ \ 3173 beatpred |= r * emask; \ 3174 } \ 3175 beatpred &= mask; \ 3176 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3177 (beatpred & eci_mask); \ 3178 mve_advance_vpt(env); \ 3179 } 3180 3181 #define DO_VCMP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3182 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 3183 uint32_t rm) \ 3184 { \ 3185 TYPE *n = vn; \ 3186 uint16_t mask = mve_element_mask(env); \ 3187 uint16_t eci_mask = mve_eci_mask(env); \ 3188 uint16_t beatpred = 0; \ 3189 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3190 unsigned e; \ 3191 float_status *fpst; \ 3192 float_status scratch_fpst; \ 3193 bool r; \ 3194 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3195 if ((mask & emask) == 0) { \ 3196 continue; \ 3197 } \ 3198 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3199 if (!(mask & (1 << (e * ESIZE)))) { \ 3200 /* We need the result but without updating flags */ \ 3201 scratch_fpst = *fpst; \ 3202 fpst = &scratch_fpst; \ 3203 } \ 3204 r = FN(n[H##ESIZE(e)], (TYPE)rm, fpst); \ 3205 /* Comparison sets 0/1 bits for each byte in the element */ \ 3206 beatpred |= r * emask; \ 3207 } \ 3208 beatpred &= mask; \ 3209 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3210 (beatpred & eci_mask); \ 3211 mve_advance_vpt(env); \ 3212 } 3213 3214 #define DO_VCMP_FP_BOTH(VOP, SOP, ESIZE, TYPE, FN) \ 3215 DO_VCMP_FP(VOP, ESIZE, TYPE, FN) \ 3216 DO_VCMP_FP_SCALAR(SOP, ESIZE, TYPE, FN) 3217 3218 /* 3219 * Some care is needed here to get the correct result for the unordered case. 3220 * Architecturally EQ, GE and GT are defined to be false for unordered, but 3221 * the NE, LT and LE comparisons are defined as simple logical inverses of 3222 * EQ, GE and GT and so they must return true for unordered. The softfloat 3223 * comparison functions float*_{eq,le,lt} all return false for unordered. 3224 */ 3225 #define DO_GE16(X, Y, S) float16_le(Y, X, S) 3226 #define DO_GE32(X, Y, S) float32_le(Y, X, S) 3227 #define DO_GT16(X, Y, S) float16_lt(Y, X, S) 3228 #define DO_GT32(X, Y, S) float32_lt(Y, X, S) 3229 3230 DO_VCMP_FP_BOTH(vfcmpeqh, vfcmpeq_scalarh, 2, float16, float16_eq) 3231 DO_VCMP_FP_BOTH(vfcmpeqs, vfcmpeq_scalars, 4, float32, float32_eq) 3232 3233 DO_VCMP_FP_BOTH(vfcmpneh, vfcmpne_scalarh, 2, float16, !float16_eq) 3234 DO_VCMP_FP_BOTH(vfcmpnes, vfcmpne_scalars, 4, float32, !float32_eq) 3235 3236 DO_VCMP_FP_BOTH(vfcmpgeh, vfcmpge_scalarh, 2, float16, DO_GE16) 3237 DO_VCMP_FP_BOTH(vfcmpges, vfcmpge_scalars, 4, float32, DO_GE32) 3238 3239 DO_VCMP_FP_BOTH(vfcmplth, vfcmplt_scalarh, 2, float16, !DO_GE16) 3240 DO_VCMP_FP_BOTH(vfcmplts, vfcmplt_scalars, 4, float32, !DO_GE32) 3241 3242 DO_VCMP_FP_BOTH(vfcmpgth, vfcmpgt_scalarh, 2, float16, DO_GT16) 3243 DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float32, DO_GT32) 3244 3245 DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) 3246 DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) 3247 3248 #define DO_VCVT_FIXED(OP, ESIZE, TYPE, FN) \ 3249 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm, \ 3250 uint32_t shift) \ 3251 { \ 3252 TYPE *d = vd, *m = vm; \ 3253 TYPE r; \ 3254 uint16_t mask = mve_element_mask(env); \ 3255 unsigned e; \ 3256 float_status *fpst; \ 3257 float_status scratch_fpst; \ 3258 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3259 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3260 continue; \ 3261 } \ 3262 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3263 if (!(mask & 1)) { \ 3264 /* We need the result but without updating flags */ \ 3265 scratch_fpst = *fpst; \ 3266 fpst = &scratch_fpst; \ 3267 } \ 3268 r = FN(m[H##ESIZE(e)], shift, fpst); \ 3269 mergemask(&d[H##ESIZE(e)], r, mask); \ 3270 } \ 3271 mve_advance_vpt(env); \ 3272 } 3273 3274 DO_VCVT_FIXED(vcvt_sh, 2, int16_t, helper_vfp_shtoh) 3275 DO_VCVT_FIXED(vcvt_uh, 2, uint16_t, helper_vfp_uhtoh) 3276 DO_VCVT_FIXED(vcvt_hs, 2, int16_t, helper_vfp_toshh_round_to_zero) 3277 DO_VCVT_FIXED(vcvt_hu, 2, uint16_t, helper_vfp_touhh_round_to_zero) 3278 DO_VCVT_FIXED(vcvt_sf, 4, int32_t, helper_vfp_sltos) 3279 DO_VCVT_FIXED(vcvt_uf, 4, uint32_t, helper_vfp_ultos) 3280 DO_VCVT_FIXED(vcvt_fs, 4, int32_t, helper_vfp_tosls_round_to_zero) 3281 DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) 3282 3283 /* VCVT with specified rmode */ 3284 #define DO_VCVT_RMODE(OP, ESIZE, TYPE, FN) \ 3285 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3286 void *vd, void *vm, uint32_t rmode) \ 3287 { \ 3288 TYPE *d = vd, *m = vm; \ 3289 TYPE r; \ 3290 uint16_t mask = mve_element_mask(env); \ 3291 unsigned e; \ 3292 float_status *fpst; \ 3293 float_status scratch_fpst; \ 3294 float_status *base_fpst = \ 3295 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3296 uint32_t prev_rmode = get_float_rounding_mode(base_fpst); \ 3297 set_float_rounding_mode(rmode, base_fpst); \ 3298 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3299 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3300 continue; \ 3301 } \ 3302 fpst = base_fpst; \ 3303 if (!(mask & 1)) { \ 3304 /* We need the result but without updating flags */ \ 3305 scratch_fpst = *fpst; \ 3306 fpst = &scratch_fpst; \ 3307 } \ 3308 r = FN(m[H##ESIZE(e)], 0, fpst); \ 3309 mergemask(&d[H##ESIZE(e)], r, mask); \ 3310 } \ 3311 set_float_rounding_mode(prev_rmode, base_fpst); \ 3312 mve_advance_vpt(env); \ 3313 } 3314 3315 DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_toshh) 3316 DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) 3317 DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) 3318 DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) 3319 3320 #define DO_VRINT_RM_H(M, F, S) helper_rinth(M, S) 3321 #define DO_VRINT_RM_S(M, F, S) helper_rints(M, S) 3322 3323 DO_VCVT_RMODE(vrint_rm_h, 2, uint16_t, DO_VRINT_RM_H) 3324 DO_VCVT_RMODE(vrint_rm_s, 4, uint32_t, DO_VRINT_RM_S) 3325 3326 /* 3327 * VCVT between halfprec and singleprec. As usual for halfprec 3328 * conversions, FZ16 is ignored and AHP is observed. 3329 */ 3330 static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) 3331 { 3332 uint16_t *d = vd; 3333 uint32_t *m = vm; 3334 uint16_t r; 3335 uint16_t mask = mve_element_mask(env); 3336 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3337 unsigned e; 3338 float_status *fpst; 3339 float_status scratch_fpst; 3340 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3341 bool old_fz = get_flush_to_zero(base_fpst); 3342 set_flush_to_zero(false, base_fpst); 3343 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3344 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3345 continue; 3346 } 3347 fpst = base_fpst; 3348 if (!(mask & 1)) { 3349 /* We need the result but without updating flags */ 3350 scratch_fpst = *fpst; 3351 fpst = &scratch_fpst; 3352 } 3353 r = float32_to_float16(m[H4(e)], ieee, fpst); 3354 mergemask(&d[H2(e * 2 + top)], r, mask >> (top * 2)); 3355 } 3356 set_flush_to_zero(old_fz, base_fpst); 3357 mve_advance_vpt(env); 3358 } 3359 3360 static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) 3361 { 3362 uint32_t *d = vd; 3363 uint16_t *m = vm; 3364 uint32_t r; 3365 uint16_t mask = mve_element_mask(env); 3366 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3367 unsigned e; 3368 float_status *fpst; 3369 float_status scratch_fpst; 3370 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3371 bool old_fiz = get_flush_inputs_to_zero(base_fpst); 3372 set_flush_inputs_to_zero(false, base_fpst); 3373 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3374 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3375 continue; 3376 } 3377 fpst = base_fpst; 3378 if (!(mask & (1 << (top * 2)))) { 3379 /* We need the result but without updating flags */ 3380 scratch_fpst = *fpst; 3381 fpst = &scratch_fpst; 3382 } 3383 r = float16_to_float32(m[H2(e * 2 + top)], ieee, fpst); 3384 mergemask(&d[H4(e)], r, mask); 3385 } 3386 set_flush_inputs_to_zero(old_fiz, base_fpst); 3387 mve_advance_vpt(env); 3388 } 3389 3390 void HELPER(mve_vcvtb_sh)(CPUARMState *env, void *vd, void *vm) 3391 { 3392 do_vcvt_sh(env, vd, vm, 0); 3393 } 3394 void HELPER(mve_vcvtt_sh)(CPUARMState *env, void *vd, void *vm) 3395 { 3396 do_vcvt_sh(env, vd, vm, 1); 3397 } 3398 void HELPER(mve_vcvtb_hs)(CPUARMState *env, void *vd, void *vm) 3399 { 3400 do_vcvt_hs(env, vd, vm, 0); 3401 } 3402 void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) 3403 { 3404 do_vcvt_hs(env, vd, vm, 1); 3405 } 3406 3407 #define DO_1OP_FP(OP, ESIZE, TYPE, FN) \ 3408 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm) \ 3409 { \ 3410 TYPE *d = vd, *m = vm; \ 3411 TYPE r; \ 3412 uint16_t mask = mve_element_mask(env); \ 3413 unsigned e; \ 3414 float_status *fpst; \ 3415 float_status scratch_fpst; \ 3416 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3417 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3418 continue; \ 3419 } \ 3420 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3421 if (!(mask & 1)) { \ 3422 /* We need the result but without updating flags */ \ 3423 scratch_fpst = *fpst; \ 3424 fpst = &scratch_fpst; \ 3425 } \ 3426 r = FN(m[H##ESIZE(e)], fpst); \ 3427 mergemask(&d[H##ESIZE(e)], r, mask); \ 3428 } \ 3429 mve_advance_vpt(env); \ 3430 } 3431 3432 DO_1OP_FP(vrintx_h, 2, float16, float16_round_to_int) 3433 DO_1OP_FP(vrintx_s, 4, float32, float32_round_to_int) 3434