1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/exec-all.h" 27 #include "tcg/tcg.h" 28 29 static uint16_t mve_eci_mask(CPUARMState *env) 30 { 31 /* 32 * Return the mask of which elements in the MVE vector correspond 33 * to beats being executed. The mask has 1 bits for executed lanes 34 * and 0 bits where ECI says this beat was already executed. 35 */ 36 int eci; 37 38 if ((env->condexec_bits & 0xf) != 0) { 39 return 0xffff; 40 } 41 42 eci = env->condexec_bits >> 4; 43 switch (eci) { 44 case ECI_NONE: 45 return 0xffff; 46 case ECI_A0: 47 return 0xfff0; 48 case ECI_A0A1: 49 return 0xff00; 50 case ECI_A0A1A2: 51 case ECI_A0A1A2B0: 52 return 0xf000; 53 default: 54 g_assert_not_reached(); 55 } 56 } 57 58 static uint16_t mve_element_mask(CPUARMState *env) 59 { 60 /* 61 * Return the mask of which elements in the MVE vector should be 62 * updated. This is a combination of multiple things: 63 * (1) by default, we update every lane in the vector 64 * (2) VPT predication stores its state in the VPR register; 65 * (3) low-overhead-branch tail predication will mask out part 66 * the vector on the final iteration of the loop 67 * (4) if EPSR.ECI is set then we must execute only some beats 68 * of the insn 69 * We combine all these into a 16-bit result with the same semantics 70 * as VPR.P0: 0 to mask the lane, 1 if it is active. 71 * 8-bit vector ops will look at all bits of the result; 72 * 16-bit ops will look at bits 0, 2, 4, ...; 73 * 32-bit ops will look at bits 0, 4, 8 and 12. 74 * Compare pseudocode GetCurInstrBeat(), though that only returns 75 * the 4-bit slice of the mask corresponding to a single beat. 76 */ 77 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 78 79 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 80 mask |= 0xff; 81 } 82 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 83 mask |= 0xff00; 84 } 85 86 if (env->v7m.ltpsize < 4 && 87 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 88 /* 89 * Tail predication active, and this is the last loop iteration. 90 * The element size is (1 << ltpsize), and we only want to process 91 * loopcount elements, so we want to retain the least significant 92 * (loopcount * esize) predicate bits and zero out bits above that. 93 */ 94 int masklen = env->regs[14] << env->v7m.ltpsize; 95 assert(masklen <= 16); 96 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 97 mask &= ltpmask; 98 } 99 100 /* 101 * ECI bits indicate which beats are already executed; 102 * we handle this by effectively predicating them out. 103 */ 104 mask &= mve_eci_mask(env); 105 return mask; 106 } 107 108 static void mve_advance_vpt(CPUARMState *env) 109 { 110 /* Advance the VPT and ECI state if necessary */ 111 uint32_t vpr = env->v7m.vpr; 112 unsigned mask01, mask23; 113 uint16_t inv_mask; 114 uint16_t eci_mask = mve_eci_mask(env); 115 116 if ((env->condexec_bits & 0xf) == 0) { 117 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 118 (ECI_A0 << 4) : (ECI_NONE << 4); 119 } 120 121 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 122 /* VPT not enabled, nothing to do */ 123 return; 124 } 125 126 /* Invert P0 bits if needed, but only for beats we actually executed */ 127 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 128 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 129 /* Start by assuming we invert all bits corresponding to executed beats */ 130 inv_mask = eci_mask; 131 if (mask01 <= 8) { 132 /* MASK01 says don't invert low half of P0 */ 133 inv_mask &= ~0xff; 134 } 135 if (mask23 <= 8) { 136 /* MASK23 says don't invert high half of P0 */ 137 inv_mask &= ~0xff00; 138 } 139 vpr ^= inv_mask; 140 /* Only update MASK01 if beat 1 executed */ 141 if (eci_mask & 0xf0) { 142 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 143 } 144 /* Beat 3 always executes, so update MASK23 */ 145 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 146 env->v7m.vpr = vpr; 147 } 148 149 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 150 #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ 151 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 152 { \ 153 TYPE *d = vd; \ 154 uint16_t mask = mve_element_mask(env); \ 155 uint16_t eci_mask = mve_eci_mask(env); \ 156 unsigned b, e; \ 157 /* \ 158 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 159 * beats so we don't care if we update part of the dest and \ 160 * then take an exception. \ 161 */ \ 162 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 163 if (eci_mask & (1 << b)) { \ 164 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 165 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \ 166 } \ 167 addr += MSIZE; \ 168 } \ 169 mve_advance_vpt(env); \ 170 } 171 172 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ 173 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 174 { \ 175 TYPE *d = vd; \ 176 uint16_t mask = mve_element_mask(env); \ 177 unsigned b, e; \ 178 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 179 if (mask & (1 << b)) { \ 180 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 181 } \ 182 addr += MSIZE; \ 183 } \ 184 mve_advance_vpt(env); \ 185 } 186 187 DO_VLDR(vldrb, 1, ldub, 1, uint8_t) 188 DO_VLDR(vldrh, 2, lduw, 2, uint16_t) 189 DO_VLDR(vldrw, 4, ldl, 4, uint32_t) 190 191 DO_VSTR(vstrb, 1, stb, 1, uint8_t) 192 DO_VSTR(vstrh, 2, stw, 2, uint16_t) 193 DO_VSTR(vstrw, 4, stl, 4, uint32_t) 194 195 DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t) 196 DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t) 197 DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t) 198 DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t) 199 DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t) 200 DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t) 201 202 DO_VSTR(vstrb_h, 1, stb, 2, int16_t) 203 DO_VSTR(vstrb_w, 1, stb, 4, int32_t) 204 DO_VSTR(vstrh_w, 2, stw, 4, int32_t) 205 206 #undef DO_VLDR 207 #undef DO_VSTR 208 209 /* 210 * The mergemask(D, R, M) macro performs the operation "*D = R" but 211 * storing only the bytes which correspond to 1 bits in M, 212 * leaving other bytes in *D unchanged. We use _Generic 213 * to select the correct implementation based on the type of D. 214 */ 215 216 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 217 { 218 if (mask & 1) { 219 *d = r; 220 } 221 } 222 223 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 224 { 225 mergemask_ub((uint8_t *)d, r, mask); 226 } 227 228 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 229 { 230 uint16_t bmask = expand_pred_b_data[mask & 3]; 231 *d = (*d & ~bmask) | (r & bmask); 232 } 233 234 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 235 { 236 mergemask_uh((uint16_t *)d, r, mask); 237 } 238 239 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 240 { 241 uint32_t bmask = expand_pred_b_data[mask & 0xf]; 242 *d = (*d & ~bmask) | (r & bmask); 243 } 244 245 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 246 { 247 mergemask_uw((uint32_t *)d, r, mask); 248 } 249 250 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 251 { 252 uint64_t bmask = expand_pred_b_data[mask & 0xff]; 253 *d = (*d & ~bmask) | (r & bmask); 254 } 255 256 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 257 { 258 mergemask_uq((uint64_t *)d, r, mask); 259 } 260 261 #define mergemask(D, R, M) \ 262 _Generic(D, \ 263 uint8_t *: mergemask_ub, \ 264 int8_t *: mergemask_sb, \ 265 uint16_t *: mergemask_uh, \ 266 int16_t *: mergemask_sh, \ 267 uint32_t *: mergemask_uw, \ 268 int32_t *: mergemask_sw, \ 269 uint64_t *: mergemask_uq, \ 270 int64_t *: mergemask_sq)(D, R, M) 271 272 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 273 { 274 /* 275 * The generated code already replicated an 8 or 16 bit constant 276 * into the 32-bit value, so we only need to write the 32-bit 277 * value to all elements of the Qreg, allowing for predication. 278 */ 279 uint32_t *d = vd; 280 uint16_t mask = mve_element_mask(env); 281 unsigned e; 282 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 283 mergemask(&d[H4(e)], val, mask); 284 } 285 mve_advance_vpt(env); 286 } 287 288 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 289 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 290 { \ 291 TYPE *d = vd, *m = vm; \ 292 uint16_t mask = mve_element_mask(env); \ 293 unsigned e; \ 294 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 295 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 296 } \ 297 mve_advance_vpt(env); \ 298 } 299 300 #define DO_CLS_B(N) (clrsb32(N) - 24) 301 #define DO_CLS_H(N) (clrsb32(N) - 16) 302 303 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 304 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 305 DO_1OP(vclsw, 4, int32_t, clrsb32) 306 307 #define DO_CLZ_B(N) (clz32(N) - 24) 308 #define DO_CLZ_H(N) (clz32(N) - 16) 309 310 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 311 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 312 DO_1OP(vclzw, 4, uint32_t, clz32) 313 314 DO_1OP(vrev16b, 2, uint16_t, bswap16) 315 DO_1OP(vrev32b, 4, uint32_t, bswap32) 316 DO_1OP(vrev32h, 4, uint32_t, hswap32) 317 DO_1OP(vrev64b, 8, uint64_t, bswap64) 318 DO_1OP(vrev64h, 8, uint64_t, hswap64) 319 DO_1OP(vrev64w, 8, uint64_t, wswap64) 320 321 #define DO_NOT(N) (~(N)) 322 323 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 324 325 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 326 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 327 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 328 329 DO_1OP(vabsb, 1, int8_t, DO_ABS) 330 DO_1OP(vabsh, 2, int16_t, DO_ABS) 331 DO_1OP(vabsw, 4, int32_t, DO_ABS) 332 333 /* We can do these 64 bits at a time */ 334 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 335 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 336 337 #define DO_NEG(N) (-(N)) 338 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 339 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 340 341 DO_1OP(vnegb, 1, int8_t, DO_NEG) 342 DO_1OP(vnegh, 2, int16_t, DO_NEG) 343 DO_1OP(vnegw, 4, int32_t, DO_NEG) 344 345 /* We can do these 64 bits at a time */ 346 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 347 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 348 349 /* 350 * 1 operand immediates: Vda is destination and possibly also one source. 351 * All these insns work at 64-bit widths. 352 */ 353 #define DO_1OP_IMM(OP, FN) \ 354 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 355 { \ 356 uint64_t *da = vda; \ 357 uint16_t mask = mve_element_mask(env); \ 358 unsigned e; \ 359 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 360 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 361 } \ 362 mve_advance_vpt(env); \ 363 } 364 365 #define DO_MOVI(N, I) (I) 366 #define DO_ANDI(N, I) ((N) & (I)) 367 #define DO_ORRI(N, I) ((N) | (I)) 368 369 DO_1OP_IMM(vmovi, DO_MOVI) 370 DO_1OP_IMM(vandi, DO_ANDI) 371 DO_1OP_IMM(vorri, DO_ORRI) 372 373 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 374 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 375 void *vd, void *vn, void *vm) \ 376 { \ 377 TYPE *d = vd, *n = vn, *m = vm; \ 378 uint16_t mask = mve_element_mask(env); \ 379 unsigned e; \ 380 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 381 mergemask(&d[H##ESIZE(e)], \ 382 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 383 } \ 384 mve_advance_vpt(env); \ 385 } 386 387 /* provide unsigned 2-op helpers for all sizes */ 388 #define DO_2OP_U(OP, FN) \ 389 DO_2OP(OP##b, 1, uint8_t, FN) \ 390 DO_2OP(OP##h, 2, uint16_t, FN) \ 391 DO_2OP(OP##w, 4, uint32_t, FN) 392 393 /* provide signed 2-op helpers for all sizes */ 394 #define DO_2OP_S(OP, FN) \ 395 DO_2OP(OP##b, 1, int8_t, FN) \ 396 DO_2OP(OP##h, 2, int16_t, FN) \ 397 DO_2OP(OP##w, 4, int32_t, FN) 398 399 /* 400 * "Long" operations where two half-sized inputs (taken from either the 401 * top or the bottom of the input vector) produce a double-width result. 402 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 403 */ 404 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 405 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 406 { \ 407 LTYPE *d = vd; \ 408 TYPE *n = vn, *m = vm; \ 409 uint16_t mask = mve_element_mask(env); \ 410 unsigned le; \ 411 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 412 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 413 m[H##ESIZE(le * 2 + TOP)]); \ 414 mergemask(&d[H##LESIZE(le)], r, mask); \ 415 } \ 416 mve_advance_vpt(env); \ 417 } 418 419 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 420 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 421 { \ 422 TYPE *d = vd, *n = vn, *m = vm; \ 423 uint16_t mask = mve_element_mask(env); \ 424 unsigned e; \ 425 bool qc = false; \ 426 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 427 bool sat = false; \ 428 TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 429 mergemask(&d[H##ESIZE(e)], r, mask); \ 430 qc |= sat & mask & 1; \ 431 } \ 432 if (qc) { \ 433 env->vfp.qc[0] = qc; \ 434 } \ 435 mve_advance_vpt(env); \ 436 } 437 438 /* provide unsigned 2-op helpers for all sizes */ 439 #define DO_2OP_SAT_U(OP, FN) \ 440 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 441 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 442 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 443 444 /* provide signed 2-op helpers for all sizes */ 445 #define DO_2OP_SAT_S(OP, FN) \ 446 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 447 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 448 DO_2OP_SAT(OP##w, 4, int32_t, FN) 449 450 #define DO_AND(N, M) ((N) & (M)) 451 #define DO_BIC(N, M) ((N) & ~(M)) 452 #define DO_ORR(N, M) ((N) | (M)) 453 #define DO_ORN(N, M) ((N) | ~(M)) 454 #define DO_EOR(N, M) ((N) ^ (M)) 455 456 DO_2OP(vand, 8, uint64_t, DO_AND) 457 DO_2OP(vbic, 8, uint64_t, DO_BIC) 458 DO_2OP(vorr, 8, uint64_t, DO_ORR) 459 DO_2OP(vorn, 8, uint64_t, DO_ORN) 460 DO_2OP(veor, 8, uint64_t, DO_EOR) 461 462 #define DO_ADD(N, M) ((N) + (M)) 463 #define DO_SUB(N, M) ((N) - (M)) 464 #define DO_MUL(N, M) ((N) * (M)) 465 466 DO_2OP_U(vadd, DO_ADD) 467 DO_2OP_U(vsub, DO_SUB) 468 DO_2OP_U(vmul, DO_MUL) 469 470 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 471 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 472 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 473 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 474 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 475 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 476 477 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 478 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 479 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 480 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 481 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 482 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 483 484 /* 485 * Because the computation type is at least twice as large as required, 486 * these work for both signed and unsigned source types. 487 */ 488 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 489 { 490 return (n * m) >> 8; 491 } 492 493 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 494 { 495 return (n * m) >> 16; 496 } 497 498 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 499 { 500 return (n * m) >> 32; 501 } 502 503 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 504 { 505 return (n * m + (1U << 7)) >> 8; 506 } 507 508 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 509 { 510 return (n * m + (1U << 15)) >> 16; 511 } 512 513 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 514 { 515 return (n * m + (1U << 31)) >> 32; 516 } 517 518 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 519 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 520 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 521 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 522 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 523 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 524 525 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 526 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 527 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 528 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 529 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 530 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 531 532 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 533 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 534 535 DO_2OP_S(vmaxs, DO_MAX) 536 DO_2OP_U(vmaxu, DO_MAX) 537 DO_2OP_S(vmins, DO_MIN) 538 DO_2OP_U(vminu, DO_MIN) 539 540 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 541 542 DO_2OP_S(vabds, DO_ABD) 543 DO_2OP_U(vabdu, DO_ABD) 544 545 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 546 { 547 return ((uint64_t)n + m) >> 1; 548 } 549 550 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 551 { 552 return ((int64_t)n + m) >> 1; 553 } 554 555 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 556 { 557 return ((uint64_t)n - m) >> 1; 558 } 559 560 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 561 { 562 return ((int64_t)n - m) >> 1; 563 } 564 565 DO_2OP_S(vhadds, do_vhadd_s) 566 DO_2OP_U(vhaddu, do_vhadd_u) 567 DO_2OP_S(vhsubs, do_vhsub_s) 568 DO_2OP_U(vhsubu, do_vhsub_u) 569 570 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 571 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 572 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 573 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 574 575 DO_2OP_S(vshls, DO_VSHLS) 576 DO_2OP_U(vshlu, DO_VSHLU) 577 DO_2OP_S(vrshls, DO_VRSHLS) 578 DO_2OP_U(vrshlu, DO_VRSHLU) 579 580 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 581 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 582 583 DO_2OP_S(vrhadds, DO_RHADD_S) 584 DO_2OP_U(vrhaddu, DO_RHADD_U) 585 586 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 587 uint32_t inv, uint32_t carry_in, bool update_flags) 588 { 589 uint16_t mask = mve_element_mask(env); 590 unsigned e; 591 592 /* If any additions trigger, we will update flags. */ 593 if (mask & 0x1111) { 594 update_flags = true; 595 } 596 597 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 598 uint64_t r = carry_in; 599 r += n[H4(e)]; 600 r += m[H4(e)] ^ inv; 601 if (mask & 1) { 602 carry_in = r >> 32; 603 } 604 mergemask(&d[H4(e)], r, mask); 605 } 606 607 if (update_flags) { 608 /* Store C, clear NZV. */ 609 env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK; 610 env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C; 611 } 612 mve_advance_vpt(env); 613 } 614 615 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 616 { 617 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 618 do_vadc(env, vd, vn, vm, 0, carry_in, false); 619 } 620 621 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 622 { 623 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 624 do_vadc(env, vd, vn, vm, -1, carry_in, false); 625 } 626 627 628 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 629 { 630 do_vadc(env, vd, vn, vm, 0, 0, true); 631 } 632 633 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 634 { 635 do_vadc(env, vd, vn, vm, -1, 1, true); 636 } 637 638 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 639 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 640 { \ 641 TYPE *d = vd, *n = vn, *m = vm; \ 642 uint16_t mask = mve_element_mask(env); \ 643 unsigned e; \ 644 TYPE r[16 / ESIZE]; \ 645 /* Calculate all results first to avoid overwriting inputs */ \ 646 for (e = 0; e < 16 / ESIZE; e++) { \ 647 if (!(e & 1)) { \ 648 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 649 } else { \ 650 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 651 } \ 652 } \ 653 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 654 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 655 } \ 656 mve_advance_vpt(env); \ 657 } 658 659 #define DO_VCADD_ALL(OP, FN0, FN1) \ 660 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 661 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 662 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 663 664 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 665 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 666 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 667 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 668 669 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 670 { 671 if (val > max) { 672 *s = true; 673 return max; 674 } else if (val < min) { 675 *s = true; 676 return min; 677 } 678 return val; 679 } 680 681 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 682 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 683 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 684 685 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 686 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 687 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 688 689 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 690 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 691 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 692 693 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 694 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 695 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 696 697 /* 698 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 699 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 700 */ 701 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 702 INT8_MIN, INT8_MAX, s) 703 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 704 INT16_MIN, INT16_MAX, s) 705 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 706 INT32_MIN, INT32_MAX, s) 707 708 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 709 INT8_MIN, INT8_MAX, s) 710 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 711 INT16_MIN, INT16_MAX, s) 712 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 713 INT32_MIN, INT32_MAX, s) 714 715 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 716 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 717 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 718 719 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 720 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 721 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 722 723 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 724 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 725 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 726 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 727 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 728 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 729 730 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 731 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 732 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 733 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 734 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 735 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 736 737 /* 738 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 739 * and friends wanting a uint32_t* sat and our needing a bool*. 740 */ 741 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 742 ({ \ 743 uint32_t su32 = 0; \ 744 typeof(N) r = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 745 if (su32) { \ 746 *satp = true; \ 747 } \ 748 r; \ 749 }) 750 751 #define DO_SQSHL_OP(N, M, satp) \ 752 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 753 #define DO_UQSHL_OP(N, M, satp) \ 754 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 755 #define DO_SQRSHL_OP(N, M, satp) \ 756 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 757 #define DO_UQRSHL_OP(N, M, satp) \ 758 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 759 #define DO_SUQSHL_OP(N, M, satp) \ 760 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 761 762 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 763 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 764 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 765 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 766 767 /* 768 * Multiply add dual returning high half 769 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 770 * whether to add the rounding constant, and the pointer to the 771 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 772 * saturate to twice the input size and return the high half; or 773 * (A * B - C * D) etc for VQDMLSDH. 774 */ 775 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 776 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 777 void *vm) \ 778 { \ 779 TYPE *d = vd, *n = vn, *m = vm; \ 780 uint16_t mask = mve_element_mask(env); \ 781 unsigned e; \ 782 bool qc = false; \ 783 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 784 bool sat = false; \ 785 if ((e & 1) == XCHG) { \ 786 TYPE r = FN(n[H##ESIZE(e)], \ 787 m[H##ESIZE(e - XCHG)], \ 788 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 789 m[H##ESIZE(e + (1 - XCHG))], \ 790 ROUND, &sat); \ 791 mergemask(&d[H##ESIZE(e)], r, mask); \ 792 qc |= sat & mask & 1; \ 793 } \ 794 } \ 795 if (qc) { \ 796 env->vfp.qc[0] = qc; \ 797 } \ 798 mve_advance_vpt(env); \ 799 } 800 801 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 802 int round, bool *sat) 803 { 804 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 805 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 806 } 807 808 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 809 int round, bool *sat) 810 { 811 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 812 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 813 } 814 815 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 816 int round, bool *sat) 817 { 818 int64_t m1 = (int64_t)a * b; 819 int64_t m2 = (int64_t)c * d; 820 int64_t r; 821 /* 822 * Architecturally we should do the entire add, double, round 823 * and then check for saturation. We do three saturating adds, 824 * but we need to be careful about the order. If the first 825 * m1 + m2 saturates then it's impossible for the *2+rc to 826 * bring it back into the non-saturated range. However, if 827 * m1 + m2 is negative then it's possible that doing the doubling 828 * would take the intermediate result below INT64_MAX and the 829 * addition of the rounding constant then brings it back in range. 830 * So we add half the rounding constant before doubling rather 831 * than adding the rounding constant after the doubling. 832 */ 833 if (sadd64_overflow(m1, m2, &r) || 834 sadd64_overflow(r, (round << 30), &r) || 835 sadd64_overflow(r, r, &r)) { 836 *sat = true; 837 return r < 0 ? INT32_MAX : INT32_MIN; 838 } 839 return r >> 32; 840 } 841 842 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 843 int round, bool *sat) 844 { 845 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 846 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 847 } 848 849 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 850 int round, bool *sat) 851 { 852 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 853 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 854 } 855 856 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 857 int round, bool *sat) 858 { 859 int64_t m1 = (int64_t)a * b; 860 int64_t m2 = (int64_t)c * d; 861 int64_t r; 862 /* The same ordering issue as in do_vqdmladh_w applies here too */ 863 if (ssub64_overflow(m1, m2, &r) || 864 sadd64_overflow(r, (round << 30), &r) || 865 sadd64_overflow(r, r, &r)) { 866 *sat = true; 867 return r < 0 ? INT32_MAX : INT32_MIN; 868 } 869 return r >> 32; 870 } 871 872 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 873 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 874 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 875 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 876 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 877 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 878 879 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 880 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 881 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 882 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 883 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 884 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 885 886 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 887 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 888 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 889 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 890 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 891 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 892 893 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 894 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 895 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 896 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 897 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 898 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 899 900 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 901 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 902 uint32_t rm) \ 903 { \ 904 TYPE *d = vd, *n = vn; \ 905 TYPE m = rm; \ 906 uint16_t mask = mve_element_mask(env); \ 907 unsigned e; \ 908 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 909 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 910 } \ 911 mve_advance_vpt(env); \ 912 } 913 914 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 915 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 916 uint32_t rm) \ 917 { \ 918 TYPE *d = vd, *n = vn; \ 919 TYPE m = rm; \ 920 uint16_t mask = mve_element_mask(env); \ 921 unsigned e; \ 922 bool qc = false; \ 923 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 924 bool sat = false; \ 925 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 926 mask); \ 927 qc |= sat & mask & 1; \ 928 } \ 929 if (qc) { \ 930 env->vfp.qc[0] = qc; \ 931 } \ 932 mve_advance_vpt(env); \ 933 } 934 935 /* provide unsigned 2-op scalar helpers for all sizes */ 936 #define DO_2OP_SCALAR_U(OP, FN) \ 937 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 938 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 939 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 940 #define DO_2OP_SCALAR_S(OP, FN) \ 941 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 942 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 943 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 944 945 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 946 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 947 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 948 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 949 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 950 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 951 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 952 953 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 954 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 955 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 956 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 957 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 958 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 959 960 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 961 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 962 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 963 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 964 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 965 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 966 967 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 968 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 969 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 970 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 971 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 972 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 973 974 /* 975 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 976 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 977 * SATMASK specifies which bits of the predicate mask matter for determining 978 * whether to propagate a saturation indication into FPSCR.QC -- for 979 * the 16x16->32 case we must check only the bit corresponding to the T or B 980 * half that we used, but for the 32x32->64 case we propagate if the mask 981 * bit is set for either half. 982 */ 983 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 984 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 985 uint32_t rm) \ 986 { \ 987 LTYPE *d = vd; \ 988 TYPE *n = vn; \ 989 TYPE m = rm; \ 990 uint16_t mask = mve_element_mask(env); \ 991 unsigned le; \ 992 bool qc = false; \ 993 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 994 bool sat = false; \ 995 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 996 mergemask(&d[H##LESIZE(le)], r, mask); \ 997 qc |= sat && (mask & SATMASK); \ 998 } \ 999 if (qc) { \ 1000 env->vfp.qc[0] = qc; \ 1001 } \ 1002 mve_advance_vpt(env); \ 1003 } 1004 1005 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1006 { 1007 int64_t r = ((int64_t)n * m) * 2; 1008 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1009 } 1010 1011 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1012 { 1013 /* The multiply can't overflow, but the doubling might */ 1014 int64_t r = (int64_t)n * m; 1015 if (r > INT64_MAX / 2) { 1016 *sat = true; 1017 return INT64_MAX; 1018 } else if (r < INT64_MIN / 2) { 1019 *sat = true; 1020 return INT64_MIN; 1021 } else { 1022 return r * 2; 1023 } 1024 } 1025 1026 #define SATMASK16B 1 1027 #define SATMASK16T (1 << 2) 1028 #define SATMASK32 ((1 << 4) | 1) 1029 1030 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1031 do_qdmullh, SATMASK16B) 1032 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1033 do_qdmullw, SATMASK32) 1034 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1035 do_qdmullh, SATMASK16T) 1036 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1037 do_qdmullw, SATMASK32) 1038 1039 /* 1040 * Long saturating ops 1041 */ 1042 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1043 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1044 void *vm) \ 1045 { \ 1046 LTYPE *d = vd; \ 1047 TYPE *n = vn, *m = vm; \ 1048 uint16_t mask = mve_element_mask(env); \ 1049 unsigned le; \ 1050 bool qc = false; \ 1051 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1052 bool sat = false; \ 1053 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1054 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1055 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1056 qc |= sat && (mask & SATMASK); \ 1057 } \ 1058 if (qc) { \ 1059 env->vfp.qc[0] = qc; \ 1060 } \ 1061 mve_advance_vpt(env); \ 1062 } 1063 1064 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1065 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1066 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1067 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1068 1069 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1070 { 1071 m &= 0xff; 1072 if (m == 0) { 1073 return 0; 1074 } 1075 n = revbit8(n); 1076 if (m < 8) { 1077 n >>= 8 - m; 1078 } 1079 return n; 1080 } 1081 1082 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1083 { 1084 m &= 0xff; 1085 if (m == 0) { 1086 return 0; 1087 } 1088 n = revbit16(n); 1089 if (m < 16) { 1090 n >>= 16 - m; 1091 } 1092 return n; 1093 } 1094 1095 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1096 { 1097 m &= 0xff; 1098 if (m == 0) { 1099 return 0; 1100 } 1101 n = revbit32(n); 1102 if (m < 32) { 1103 n >>= 32 - m; 1104 } 1105 return n; 1106 } 1107 1108 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1109 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1110 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1111 1112 /* 1113 * Multiply add long dual accumulate ops. 1114 */ 1115 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1116 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1117 void *vm, uint64_t a) \ 1118 { \ 1119 uint16_t mask = mve_element_mask(env); \ 1120 unsigned e; \ 1121 TYPE *n = vn, *m = vm; \ 1122 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1123 if (mask & 1) { \ 1124 if (e & 1) { \ 1125 a ODDACC \ 1126 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1127 } else { \ 1128 a EVENACC \ 1129 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1130 } \ 1131 } \ 1132 } \ 1133 mve_advance_vpt(env); \ 1134 return a; \ 1135 } 1136 1137 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1138 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1139 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1140 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1141 1142 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1143 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1144 1145 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1146 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1147 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1148 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1149 1150 /* 1151 * Rounding multiply add long dual accumulate high. In the pseudocode 1152 * this is implemented with a 72-bit internal accumulator value of which 1153 * the top 64 bits are returned. We optimize this to avoid having to 1154 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1155 * is squashed back into 64-bits after each beat. 1156 */ 1157 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1158 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1159 void *vm, uint64_t a) \ 1160 { \ 1161 uint16_t mask = mve_element_mask(env); \ 1162 unsigned e; \ 1163 TYPE *n = vn, *m = vm; \ 1164 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1165 if (mask & 1) { \ 1166 LTYPE mul; \ 1167 if (e & 1) { \ 1168 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1169 if (SUB) { \ 1170 mul = -mul; \ 1171 } \ 1172 } else { \ 1173 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1174 } \ 1175 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1176 a += mul; \ 1177 } \ 1178 } \ 1179 mve_advance_vpt(env); \ 1180 return a; \ 1181 } 1182 1183 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1184 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1185 1186 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1187 1188 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1189 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1190 1191 /* Vector add across vector */ 1192 #define DO_VADDV(OP, ESIZE, TYPE) \ 1193 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1194 uint32_t ra) \ 1195 { \ 1196 uint16_t mask = mve_element_mask(env); \ 1197 unsigned e; \ 1198 TYPE *m = vm; \ 1199 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1200 if (mask & 1) { \ 1201 ra += m[H##ESIZE(e)]; \ 1202 } \ 1203 } \ 1204 mve_advance_vpt(env); \ 1205 return ra; \ 1206 } \ 1207 1208 DO_VADDV(vaddvsb, 1, int8_t) 1209 DO_VADDV(vaddvsh, 2, int16_t) 1210 DO_VADDV(vaddvsw, 4, int32_t) 1211 DO_VADDV(vaddvub, 1, uint8_t) 1212 DO_VADDV(vaddvuh, 2, uint16_t) 1213 DO_VADDV(vaddvuw, 4, uint32_t) 1214 1215 #define DO_VADDLV(OP, TYPE, LTYPE) \ 1216 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1217 uint64_t ra) \ 1218 { \ 1219 uint16_t mask = mve_element_mask(env); \ 1220 unsigned e; \ 1221 TYPE *m = vm; \ 1222 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1223 if (mask & 1) { \ 1224 ra += (LTYPE)m[H4(e)]; \ 1225 } \ 1226 } \ 1227 mve_advance_vpt(env); \ 1228 return ra; \ 1229 } \ 1230 1231 DO_VADDLV(vaddlv_s, int32_t, int64_t) 1232 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 1233 1234 /* Shifts by immediate */ 1235 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 1236 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1237 void *vm, uint32_t shift) \ 1238 { \ 1239 TYPE *d = vd, *m = vm; \ 1240 uint16_t mask = mve_element_mask(env); \ 1241 unsigned e; \ 1242 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1243 mergemask(&d[H##ESIZE(e)], \ 1244 FN(m[H##ESIZE(e)], shift), mask); \ 1245 } \ 1246 mve_advance_vpt(env); \ 1247 } 1248 1249 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 1250 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1251 void *vm, uint32_t shift) \ 1252 { \ 1253 TYPE *d = vd, *m = vm; \ 1254 uint16_t mask = mve_element_mask(env); \ 1255 unsigned e; \ 1256 bool qc = false; \ 1257 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1258 bool sat = false; \ 1259 mergemask(&d[H##ESIZE(e)], \ 1260 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 1261 qc |= sat & mask & 1; \ 1262 } \ 1263 if (qc) { \ 1264 env->vfp.qc[0] = qc; \ 1265 } \ 1266 mve_advance_vpt(env); \ 1267 } 1268 1269 /* provide unsigned 2-op shift helpers for all sizes */ 1270 #define DO_2SHIFT_U(OP, FN) \ 1271 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 1272 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 1273 DO_2SHIFT(OP##w, 4, uint32_t, FN) 1274 #define DO_2SHIFT_S(OP, FN) \ 1275 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 1276 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 1277 DO_2SHIFT(OP##w, 4, int32_t, FN) 1278 1279 #define DO_2SHIFT_SAT_U(OP, FN) \ 1280 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 1281 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 1282 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 1283 #define DO_2SHIFT_SAT_S(OP, FN) \ 1284 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 1285 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 1286 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 1287 1288 DO_2SHIFT_U(vshli_u, DO_VSHLU) 1289 DO_2SHIFT_S(vshli_s, DO_VSHLS) 1290 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 1291 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 1292 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 1293 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 1294 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 1295 1296 /* Shift-and-insert; we always work with 64 bits at a time */ 1297 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 1298 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1299 void *vm, uint32_t shift) \ 1300 { \ 1301 uint64_t *d = vd, *m = vm; \ 1302 uint16_t mask; \ 1303 uint64_t shiftmask; \ 1304 unsigned e; \ 1305 if (shift == ESIZE * 8) { \ 1306 /* \ 1307 * Only VSRI can shift by <dt>; it should mean "don't \ 1308 * update the destination". The generic logic can't handle \ 1309 * this because it would try to shift by an out-of-range \ 1310 * amount, so special case it here. \ 1311 */ \ 1312 goto done; \ 1313 } \ 1314 assert(shift < ESIZE * 8); \ 1315 mask = mve_element_mask(env); \ 1316 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 1317 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 1318 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 1319 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 1320 (d[H8(e)] & ~shiftmask); \ 1321 mergemask(&d[H8(e)], r, mask); \ 1322 } \ 1323 done: \ 1324 mve_advance_vpt(env); \ 1325 } 1326 1327 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 1328 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 1329 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 1330 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 1331 1332 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 1333 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 1334 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 1335 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 1336 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 1337 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 1338 1339 /* 1340 * Long shifts taking half-sized inputs from top or bottom of the input 1341 * vector and producing a double-width result. ESIZE, TYPE are for 1342 * the input, and LESIZE, LTYPE for the output. 1343 * Unlike the normal shift helpers, we do not handle negative shift counts, 1344 * because the long shift is strictly left-only. 1345 */ 1346 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 1347 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1348 void *vm, uint32_t shift) \ 1349 { \ 1350 LTYPE *d = vd; \ 1351 TYPE *m = vm; \ 1352 uint16_t mask = mve_element_mask(env); \ 1353 unsigned le; \ 1354 assert(shift <= 16); \ 1355 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1356 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 1357 mergemask(&d[H##LESIZE(le)], r, mask); \ 1358 } \ 1359 mve_advance_vpt(env); \ 1360 } 1361 1362 #define DO_VSHLL_ALL(OP, TOP) \ 1363 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 1364 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 1365 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 1366 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 1367 1368 DO_VSHLL_ALL(vshllb, false) 1369 DO_VSHLL_ALL(vshllt, true) 1370 1371 /* 1372 * Narrowing right shifts, taking a double sized input, shifting it 1373 * and putting the result in either the top or bottom half of the output. 1374 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 1375 */ 1376 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1377 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1378 void *vm, uint32_t shift) \ 1379 { \ 1380 LTYPE *m = vm; \ 1381 TYPE *d = vd; \ 1382 uint16_t mask = mve_element_mask(env); \ 1383 unsigned le; \ 1384 mask >>= ESIZE * TOP; \ 1385 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1386 TYPE r = FN(m[H##LESIZE(le)], shift); \ 1387 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1388 } \ 1389 mve_advance_vpt(env); \ 1390 } 1391 1392 #define DO_VSHRN_ALL(OP, FN) \ 1393 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 1394 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 1395 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 1396 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 1397 1398 static inline uint64_t do_urshr(uint64_t x, unsigned sh) 1399 { 1400 if (likely(sh < 64)) { 1401 return (x >> sh) + ((x >> (sh - 1)) & 1); 1402 } else if (sh == 64) { 1403 return x >> 63; 1404 } else { 1405 return 0; 1406 } 1407 } 1408 1409 static inline int64_t do_srshr(int64_t x, unsigned sh) 1410 { 1411 if (likely(sh < 64)) { 1412 return (x >> sh) + ((x >> (sh - 1)) & 1); 1413 } else { 1414 /* Rounding the sign bit always produces 0. */ 1415 return 0; 1416 } 1417 } 1418 1419 DO_VSHRN_ALL(vshrn, DO_SHR) 1420 DO_VSHRN_ALL(vrshrn, do_urshr) 1421 1422 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 1423 bool *satp) 1424 { 1425 if (val > max) { 1426 *satp = true; 1427 return max; 1428 } else if (val < min) { 1429 *satp = true; 1430 return min; 1431 } else { 1432 return val; 1433 } 1434 } 1435 1436 /* Saturating narrowing right shifts */ 1437 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 1438 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 1439 void *vm, uint32_t shift) \ 1440 { \ 1441 LTYPE *m = vm; \ 1442 TYPE *d = vd; \ 1443 uint16_t mask = mve_element_mask(env); \ 1444 bool qc = false; \ 1445 unsigned le; \ 1446 mask >>= ESIZE * TOP; \ 1447 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1448 bool sat = false; \ 1449 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 1450 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 1451 qc |= sat & mask & 1; \ 1452 } \ 1453 if (qc) { \ 1454 env->vfp.qc[0] = qc; \ 1455 } \ 1456 mve_advance_vpt(env); \ 1457 } 1458 1459 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 1460 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 1461 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 1462 1463 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 1464 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 1465 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 1466 1467 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 1468 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 1469 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 1470 1471 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 1472 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 1473 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 1474 1475 #define DO_SHRN_SB(N, M, SATP) \ 1476 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 1477 #define DO_SHRN_UB(N, M, SATP) \ 1478 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1479 #define DO_SHRUN_B(N, M, SATP) \ 1480 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 1481 1482 #define DO_SHRN_SH(N, M, SATP) \ 1483 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 1484 #define DO_SHRN_UH(N, M, SATP) \ 1485 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1486 #define DO_SHRUN_H(N, M, SATP) \ 1487 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 1488 1489 #define DO_RSHRN_SB(N, M, SATP) \ 1490 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 1491 #define DO_RSHRN_UB(N, M, SATP) \ 1492 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 1493 #define DO_RSHRUN_B(N, M, SATP) \ 1494 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 1495 1496 #define DO_RSHRN_SH(N, M, SATP) \ 1497 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 1498 #define DO_RSHRN_UH(N, M, SATP) \ 1499 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 1500 #define DO_RSHRUN_H(N, M, SATP) \ 1501 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 1502 1503 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 1504 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 1505 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 1506 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 1507 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 1508 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 1509 1510 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 1511 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 1512 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 1513 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 1514 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 1515 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 1516 1517 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 1518 uint32_t shift) 1519 { 1520 uint32_t *d = vd; 1521 uint16_t mask = mve_element_mask(env); 1522 unsigned e; 1523 uint32_t r; 1524 1525 /* 1526 * For each 32-bit element, we shift it left, bringing in the 1527 * low 'shift' bits of rdm at the bottom. Bits shifted out at 1528 * the top become the new rdm, if the predicate mask permits. 1529 * The final rdm value is returned to update the register. 1530 * shift == 0 here means "shift by 32 bits". 1531 */ 1532 if (shift == 0) { 1533 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1534 r = rdm; 1535 if (mask & 1) { 1536 rdm = d[H4(e)]; 1537 } 1538 mergemask(&d[H4(e)], r, mask); 1539 } 1540 } else { 1541 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 1542 1543 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1544 r = (d[H4(e)] << shift) | (rdm & shiftmask); 1545 if (mask & 1) { 1546 rdm = d[H4(e)] >> (32 - shift); 1547 } 1548 mergemask(&d[H4(e)], r, mask); 1549 } 1550 } 1551 mve_advance_vpt(env); 1552 return rdm; 1553 } 1554 1555 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 1556 { 1557 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 1558 } 1559 1560 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 1561 { 1562 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 1563 } 1564 1565 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 1566 { 1567 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 1568 } 1569 1570 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 1571 { 1572 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 1573 } 1574 1575 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 1576 { 1577 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 1578 } 1579 1580 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 1581 { 1582 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 1583 } 1584 1585 /* Operate on 64-bit values, but saturate at 48 bits */ 1586 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 1587 bool round, uint32_t *sat) 1588 { 1589 int64_t val, extval; 1590 1591 if (shift <= -48) { 1592 /* Rounding the sign bit always produces 0. */ 1593 if (round) { 1594 return 0; 1595 } 1596 return src >> 63; 1597 } else if (shift < 0) { 1598 if (round) { 1599 src >>= -shift - 1; 1600 val = (src >> 1) + (src & 1); 1601 } else { 1602 val = src >> -shift; 1603 } 1604 extval = sextract64(val, 0, 48); 1605 if (!sat || val == extval) { 1606 return extval; 1607 } 1608 } else if (shift < 48) { 1609 int64_t extval = sextract64(src << shift, 0, 48); 1610 if (!sat || src == (extval >> shift)) { 1611 return extval; 1612 } 1613 } else if (!sat || src == 0) { 1614 return 0; 1615 } 1616 1617 *sat = 1; 1618 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 1619 } 1620 1621 /* Operate on 64-bit values, but saturate at 48 bits */ 1622 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 1623 bool round, uint32_t *sat) 1624 { 1625 uint64_t val, extval; 1626 1627 if (shift <= -(48 + round)) { 1628 return 0; 1629 } else if (shift < 0) { 1630 if (round) { 1631 val = src >> (-shift - 1); 1632 val = (val >> 1) + (val & 1); 1633 } else { 1634 val = src >> -shift; 1635 } 1636 extval = extract64(val, 0, 48); 1637 if (!sat || val == extval) { 1638 return extval; 1639 } 1640 } else if (shift < 48) { 1641 uint64_t extval = extract64(src << shift, 0, 48); 1642 if (!sat || src == (extval >> shift)) { 1643 return extval; 1644 } 1645 } else if (!sat || src == 0) { 1646 return 0; 1647 } 1648 1649 *sat = 1; 1650 return MAKE_64BIT_MASK(0, 48); 1651 } 1652 1653 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 1654 { 1655 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 1656 } 1657 1658 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 1659 { 1660 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 1661 } 1662 1663 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 1664 { 1665 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 1666 } 1667 1668 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 1669 { 1670 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 1671 } 1672 1673 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 1674 { 1675 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 1676 } 1677 1678 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 1679 { 1680 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 1681 } 1682