1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/exec-all.h" 27 #include "tcg/tcg.h" 28 29 static uint16_t mve_element_mask(CPUARMState *env) 30 { 31 /* 32 * Return the mask of which elements in the MVE vector should be 33 * updated. This is a combination of multiple things: 34 * (1) by default, we update every lane in the vector 35 * (2) VPT predication stores its state in the VPR register; 36 * (3) low-overhead-branch tail predication will mask out part 37 * the vector on the final iteration of the loop 38 * (4) if EPSR.ECI is set then we must execute only some beats 39 * of the insn 40 * We combine all these into a 16-bit result with the same semantics 41 * as VPR.P0: 0 to mask the lane, 1 if it is active. 42 * 8-bit vector ops will look at all bits of the result; 43 * 16-bit ops will look at bits 0, 2, 4, ...; 44 * 32-bit ops will look at bits 0, 4, 8 and 12. 45 * Compare pseudocode GetCurInstrBeat(), though that only returns 46 * the 4-bit slice of the mask corresponding to a single beat. 47 */ 48 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 49 50 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 51 mask |= 0xff; 52 } 53 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 54 mask |= 0xff00; 55 } 56 57 if (env->v7m.ltpsize < 4 && 58 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 59 /* 60 * Tail predication active, and this is the last loop iteration. 61 * The element size is (1 << ltpsize), and we only want to process 62 * loopcount elements, so we want to retain the least significant 63 * (loopcount * esize) predicate bits and zero out bits above that. 64 */ 65 int masklen = env->regs[14] << env->v7m.ltpsize; 66 assert(masklen <= 16); 67 mask &= MAKE_64BIT_MASK(0, masklen); 68 } 69 70 if ((env->condexec_bits & 0xf) == 0) { 71 /* 72 * ECI bits indicate which beats are already executed; 73 * we handle this by effectively predicating them out. 74 */ 75 int eci = env->condexec_bits >> 4; 76 switch (eci) { 77 case ECI_NONE: 78 break; 79 case ECI_A0: 80 mask &= 0xfff0; 81 break; 82 case ECI_A0A1: 83 mask &= 0xff00; 84 break; 85 case ECI_A0A1A2: 86 case ECI_A0A1A2B0: 87 mask &= 0xf000; 88 break; 89 default: 90 g_assert_not_reached(); 91 } 92 } 93 94 return mask; 95 } 96 97 static void mve_advance_vpt(CPUARMState *env) 98 { 99 /* Advance the VPT and ECI state if necessary */ 100 uint32_t vpr = env->v7m.vpr; 101 unsigned mask01, mask23; 102 103 if ((env->condexec_bits & 0xf) == 0) { 104 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 105 (ECI_A0 << 4) : (ECI_NONE << 4); 106 } 107 108 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 109 /* VPT not enabled, nothing to do */ 110 return; 111 } 112 113 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 114 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 115 if (mask01 > 8) { 116 /* high bit set, but not 0b1000: invert the relevant half of P0 */ 117 vpr ^= 0xff; 118 } 119 if (mask23 > 8) { 120 /* high bit set, but not 0b1000: invert the relevant half of P0 */ 121 vpr ^= 0xff00; 122 } 123 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 124 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 125 env->v7m.vpr = vpr; 126 } 127 128 129 #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ 130 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 131 { \ 132 TYPE *d = vd; \ 133 uint16_t mask = mve_element_mask(env); \ 134 unsigned b, e; \ 135 /* \ 136 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 137 * beats so we don't care if we update part of the dest and \ 138 * then take an exception. \ 139 */ \ 140 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 141 if (mask & (1 << b)) { \ 142 d[H##ESIZE(e)] = cpu_##LDTYPE##_data_ra(env, addr, GETPC()); \ 143 } \ 144 addr += MSIZE; \ 145 } \ 146 mve_advance_vpt(env); \ 147 } 148 149 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ 150 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 151 { \ 152 TYPE *d = vd; \ 153 uint16_t mask = mve_element_mask(env); \ 154 unsigned b, e; \ 155 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 156 if (mask & (1 << b)) { \ 157 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ 158 } \ 159 addr += MSIZE; \ 160 } \ 161 mve_advance_vpt(env); \ 162 } 163 164 DO_VLDR(vldrb, 1, ldub, 1, uint8_t) 165 DO_VLDR(vldrh, 2, lduw, 2, uint16_t) 166 DO_VLDR(vldrw, 4, ldl, 4, uint32_t) 167 168 DO_VSTR(vstrb, 1, stb, 1, uint8_t) 169 DO_VSTR(vstrh, 2, stw, 2, uint16_t) 170 DO_VSTR(vstrw, 4, stl, 4, uint32_t) 171 172 DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t) 173 DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t) 174 DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t) 175 DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t) 176 DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t) 177 DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t) 178 179 DO_VSTR(vstrb_h, 1, stb, 2, int16_t) 180 DO_VSTR(vstrb_w, 1, stb, 4, int32_t) 181 DO_VSTR(vstrh_w, 2, stw, 4, int32_t) 182 183 #undef DO_VLDR 184 #undef DO_VSTR 185 186 /* 187 * The mergemask(D, R, M) macro performs the operation "*D = R" but 188 * storing only the bytes which correspond to 1 bits in M, 189 * leaving other bytes in *D unchanged. We use _Generic 190 * to select the correct implementation based on the type of D. 191 */ 192 193 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 194 { 195 if (mask & 1) { 196 *d = r; 197 } 198 } 199 200 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 201 { 202 mergemask_ub((uint8_t *)d, r, mask); 203 } 204 205 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 206 { 207 uint16_t bmask = expand_pred_b_data[mask & 3]; 208 *d = (*d & ~bmask) | (r & bmask); 209 } 210 211 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 212 { 213 mergemask_uh((uint16_t *)d, r, mask); 214 } 215 216 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 217 { 218 uint32_t bmask = expand_pred_b_data[mask & 0xf]; 219 *d = (*d & ~bmask) | (r & bmask); 220 } 221 222 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 223 { 224 mergemask_uw((uint32_t *)d, r, mask); 225 } 226 227 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 228 { 229 uint64_t bmask = expand_pred_b_data[mask & 0xff]; 230 *d = (*d & ~bmask) | (r & bmask); 231 } 232 233 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 234 { 235 mergemask_uq((uint64_t *)d, r, mask); 236 } 237 238 #define mergemask(D, R, M) \ 239 _Generic(D, \ 240 uint8_t *: mergemask_ub, \ 241 int8_t *: mergemask_sb, \ 242 uint16_t *: mergemask_uh, \ 243 int16_t *: mergemask_sh, \ 244 uint32_t *: mergemask_uw, \ 245 int32_t *: mergemask_sw, \ 246 uint64_t *: mergemask_uq, \ 247 int64_t *: mergemask_sq)(D, R, M) 248 249 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 250 { 251 /* 252 * The generated code already replicated an 8 or 16 bit constant 253 * into the 32-bit value, so we only need to write the 32-bit 254 * value to all elements of the Qreg, allowing for predication. 255 */ 256 uint32_t *d = vd; 257 uint16_t mask = mve_element_mask(env); 258 unsigned e; 259 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 260 mergemask(&d[H4(e)], val, mask); 261 } 262 mve_advance_vpt(env); 263 } 264 265 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 266 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 267 { \ 268 TYPE *d = vd, *m = vm; \ 269 uint16_t mask = mve_element_mask(env); \ 270 unsigned e; \ 271 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 272 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 273 } \ 274 mve_advance_vpt(env); \ 275 } 276 277 #define DO_CLS_B(N) (clrsb32(N) - 24) 278 #define DO_CLS_H(N) (clrsb32(N) - 16) 279 280 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 281 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 282 DO_1OP(vclsw, 4, int32_t, clrsb32) 283 284 #define DO_CLZ_B(N) (clz32(N) - 24) 285 #define DO_CLZ_H(N) (clz32(N) - 16) 286 287 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 288 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 289 DO_1OP(vclzw, 4, uint32_t, clz32) 290 291 DO_1OP(vrev16b, 2, uint16_t, bswap16) 292 DO_1OP(vrev32b, 4, uint32_t, bswap32) 293 DO_1OP(vrev32h, 4, uint32_t, hswap32) 294 DO_1OP(vrev64b, 8, uint64_t, bswap64) 295 DO_1OP(vrev64h, 8, uint64_t, hswap64) 296 DO_1OP(vrev64w, 8, uint64_t, wswap64) 297 298 #define DO_NOT(N) (~(N)) 299 300 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 301 302 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 303 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 304 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 305 306 DO_1OP(vabsb, 1, int8_t, DO_ABS) 307 DO_1OP(vabsh, 2, int16_t, DO_ABS) 308 DO_1OP(vabsw, 4, int32_t, DO_ABS) 309 310 /* We can do these 64 bits at a time */ 311 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 312 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 313 314 #define DO_NEG(N) (-(N)) 315 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 316 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 317 318 DO_1OP(vnegb, 1, int8_t, DO_NEG) 319 DO_1OP(vnegh, 2, int16_t, DO_NEG) 320 DO_1OP(vnegw, 4, int32_t, DO_NEG) 321 322 /* We can do these 64 bits at a time */ 323 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 324 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 325 326 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 327 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 328 void *vd, void *vn, void *vm) \ 329 { \ 330 TYPE *d = vd, *n = vn, *m = vm; \ 331 uint16_t mask = mve_element_mask(env); \ 332 unsigned e; \ 333 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 334 mergemask(&d[H##ESIZE(e)], \ 335 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 336 } \ 337 mve_advance_vpt(env); \ 338 } 339 340 /* provide unsigned 2-op helpers for all sizes */ 341 #define DO_2OP_U(OP, FN) \ 342 DO_2OP(OP##b, 1, uint8_t, FN) \ 343 DO_2OP(OP##h, 2, uint16_t, FN) \ 344 DO_2OP(OP##w, 4, uint32_t, FN) 345 346 /* provide signed 2-op helpers for all sizes */ 347 #define DO_2OP_S(OP, FN) \ 348 DO_2OP(OP##b, 1, int8_t, FN) \ 349 DO_2OP(OP##h, 2, int16_t, FN) \ 350 DO_2OP(OP##w, 4, int32_t, FN) 351 352 /* 353 * "Long" operations where two half-sized inputs (taken from either the 354 * top or the bottom of the input vector) produce a double-width result. 355 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 356 */ 357 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 358 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 359 { \ 360 LTYPE *d = vd; \ 361 TYPE *n = vn, *m = vm; \ 362 uint16_t mask = mve_element_mask(env); \ 363 unsigned le; \ 364 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 365 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 366 m[H##ESIZE(le * 2 + TOP)]); \ 367 mergemask(&d[H##LESIZE(le)], r, mask); \ 368 } \ 369 mve_advance_vpt(env); \ 370 } 371 372 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 373 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 374 { \ 375 TYPE *d = vd, *n = vn, *m = vm; \ 376 uint16_t mask = mve_element_mask(env); \ 377 unsigned e; \ 378 bool qc = false; \ 379 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 380 bool sat = false; \ 381 TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 382 mergemask(&d[H##ESIZE(e)], r, mask); \ 383 qc |= sat & mask & 1; \ 384 } \ 385 if (qc) { \ 386 env->vfp.qc[0] = qc; \ 387 } \ 388 mve_advance_vpt(env); \ 389 } 390 391 /* provide unsigned 2-op helpers for all sizes */ 392 #define DO_2OP_SAT_U(OP, FN) \ 393 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 394 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 395 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 396 397 /* provide signed 2-op helpers for all sizes */ 398 #define DO_2OP_SAT_S(OP, FN) \ 399 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 400 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 401 DO_2OP_SAT(OP##w, 4, int32_t, FN) 402 403 #define DO_AND(N, M) ((N) & (M)) 404 #define DO_BIC(N, M) ((N) & ~(M)) 405 #define DO_ORR(N, M) ((N) | (M)) 406 #define DO_ORN(N, M) ((N) | ~(M)) 407 #define DO_EOR(N, M) ((N) ^ (M)) 408 409 DO_2OP(vand, 8, uint64_t, DO_AND) 410 DO_2OP(vbic, 8, uint64_t, DO_BIC) 411 DO_2OP(vorr, 8, uint64_t, DO_ORR) 412 DO_2OP(vorn, 8, uint64_t, DO_ORN) 413 DO_2OP(veor, 8, uint64_t, DO_EOR) 414 415 #define DO_ADD(N, M) ((N) + (M)) 416 #define DO_SUB(N, M) ((N) - (M)) 417 #define DO_MUL(N, M) ((N) * (M)) 418 419 DO_2OP_U(vadd, DO_ADD) 420 DO_2OP_U(vsub, DO_SUB) 421 DO_2OP_U(vmul, DO_MUL) 422 423 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 424 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 425 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 426 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 427 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 428 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 429 430 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 431 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 432 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 433 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 434 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 435 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 436 437 /* 438 * Because the computation type is at least twice as large as required, 439 * these work for both signed and unsigned source types. 440 */ 441 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 442 { 443 return (n * m) >> 8; 444 } 445 446 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 447 { 448 return (n * m) >> 16; 449 } 450 451 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 452 { 453 return (n * m) >> 32; 454 } 455 456 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 457 { 458 return (n * m + (1U << 7)) >> 8; 459 } 460 461 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 462 { 463 return (n * m + (1U << 15)) >> 16; 464 } 465 466 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 467 { 468 return (n * m + (1U << 31)) >> 32; 469 } 470 471 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 472 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 473 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 474 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 475 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 476 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 477 478 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 479 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 480 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 481 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 482 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 483 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 484 485 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 486 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 487 488 DO_2OP_S(vmaxs, DO_MAX) 489 DO_2OP_U(vmaxu, DO_MAX) 490 DO_2OP_S(vmins, DO_MIN) 491 DO_2OP_U(vminu, DO_MIN) 492 493 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 494 495 DO_2OP_S(vabds, DO_ABD) 496 DO_2OP_U(vabdu, DO_ABD) 497 498 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 499 { 500 return ((uint64_t)n + m) >> 1; 501 } 502 503 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 504 { 505 return ((int64_t)n + m) >> 1; 506 } 507 508 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 509 { 510 return ((uint64_t)n - m) >> 1; 511 } 512 513 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 514 { 515 return ((int64_t)n - m) >> 1; 516 } 517 518 DO_2OP_S(vhadds, do_vhadd_s) 519 DO_2OP_U(vhaddu, do_vhadd_u) 520 DO_2OP_S(vhsubs, do_vhsub_s) 521 DO_2OP_U(vhsubu, do_vhsub_u) 522 523 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 524 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 525 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 526 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 527 528 DO_2OP_S(vshls, DO_VSHLS) 529 DO_2OP_U(vshlu, DO_VSHLU) 530 DO_2OP_S(vrshls, DO_VRSHLS) 531 DO_2OP_U(vrshlu, DO_VRSHLU) 532 533 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 534 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 535 536 DO_2OP_S(vrhadds, DO_RHADD_S) 537 DO_2OP_U(vrhaddu, DO_RHADD_U) 538 539 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 540 uint32_t inv, uint32_t carry_in, bool update_flags) 541 { 542 uint16_t mask = mve_element_mask(env); 543 unsigned e; 544 545 /* If any additions trigger, we will update flags. */ 546 if (mask & 0x1111) { 547 update_flags = true; 548 } 549 550 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 551 uint64_t r = carry_in; 552 r += n[H4(e)]; 553 r += m[H4(e)] ^ inv; 554 if (mask & 1) { 555 carry_in = r >> 32; 556 } 557 mergemask(&d[H4(e)], r, mask); 558 } 559 560 if (update_flags) { 561 /* Store C, clear NZV. */ 562 env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK; 563 env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C; 564 } 565 mve_advance_vpt(env); 566 } 567 568 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 569 { 570 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 571 do_vadc(env, vd, vn, vm, 0, carry_in, false); 572 } 573 574 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 575 { 576 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; 577 do_vadc(env, vd, vn, vm, -1, carry_in, false); 578 } 579 580 581 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 582 { 583 do_vadc(env, vd, vn, vm, 0, 0, true); 584 } 585 586 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 587 { 588 do_vadc(env, vd, vn, vm, -1, 1, true); 589 } 590 591 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 592 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 593 { \ 594 TYPE *d = vd, *n = vn, *m = vm; \ 595 uint16_t mask = mve_element_mask(env); \ 596 unsigned e; \ 597 TYPE r[16 / ESIZE]; \ 598 /* Calculate all results first to avoid overwriting inputs */ \ 599 for (e = 0; e < 16 / ESIZE; e++) { \ 600 if (!(e & 1)) { \ 601 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 602 } else { \ 603 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 604 } \ 605 } \ 606 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 607 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 608 } \ 609 mve_advance_vpt(env); \ 610 } 611 612 #define DO_VCADD_ALL(OP, FN0, FN1) \ 613 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 614 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 615 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 616 617 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 618 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 619 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 620 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 621 622 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 623 { 624 if (val > max) { 625 *s = true; 626 return max; 627 } else if (val < min) { 628 *s = true; 629 return min; 630 } 631 return val; 632 } 633 634 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 635 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 636 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 637 638 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 639 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 640 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 641 642 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 643 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 644 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 645 646 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 647 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 648 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 649 650 /* 651 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 652 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 653 */ 654 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 655 INT8_MIN, INT8_MAX, s) 656 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 657 INT16_MIN, INT16_MAX, s) 658 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 659 INT32_MIN, INT32_MAX, s) 660 661 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 662 INT8_MIN, INT8_MAX, s) 663 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 664 INT16_MIN, INT16_MAX, s) 665 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 666 INT32_MIN, INT32_MAX, s) 667 668 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 669 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 670 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 671 672 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 673 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 674 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 675 676 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 677 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 678 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 679 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 680 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 681 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 682 683 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 684 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 685 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 686 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 687 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 688 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 689 690 /* 691 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 692 * and friends wanting a uint32_t* sat and our needing a bool*. 693 */ 694 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 695 ({ \ 696 uint32_t su32 = 0; \ 697 typeof(N) r = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 698 if (su32) { \ 699 *satp = true; \ 700 } \ 701 r; \ 702 }) 703 704 #define DO_SQSHL_OP(N, M, satp) \ 705 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 706 #define DO_UQSHL_OP(N, M, satp) \ 707 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 708 #define DO_SQRSHL_OP(N, M, satp) \ 709 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 710 #define DO_UQRSHL_OP(N, M, satp) \ 711 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 712 713 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 714 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 715 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 716 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 717 718 /* 719 * Multiply add dual returning high half 720 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 721 * whether to add the rounding constant, and the pointer to the 722 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 723 * saturate to twice the input size and return the high half; or 724 * (A * B - C * D) etc for VQDMLSDH. 725 */ 726 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 727 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 728 void *vm) \ 729 { \ 730 TYPE *d = vd, *n = vn, *m = vm; \ 731 uint16_t mask = mve_element_mask(env); \ 732 unsigned e; \ 733 bool qc = false; \ 734 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 735 bool sat = false; \ 736 if ((e & 1) == XCHG) { \ 737 TYPE r = FN(n[H##ESIZE(e)], \ 738 m[H##ESIZE(e - XCHG)], \ 739 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 740 m[H##ESIZE(e + (1 - XCHG))], \ 741 ROUND, &sat); \ 742 mergemask(&d[H##ESIZE(e)], r, mask); \ 743 qc |= sat & mask & 1; \ 744 } \ 745 } \ 746 if (qc) { \ 747 env->vfp.qc[0] = qc; \ 748 } \ 749 mve_advance_vpt(env); \ 750 } 751 752 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 753 int round, bool *sat) 754 { 755 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 756 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 757 } 758 759 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 760 int round, bool *sat) 761 { 762 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 763 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 764 } 765 766 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 767 int round, bool *sat) 768 { 769 int64_t m1 = (int64_t)a * b; 770 int64_t m2 = (int64_t)c * d; 771 int64_t r; 772 /* 773 * Architecturally we should do the entire add, double, round 774 * and then check for saturation. We do three saturating adds, 775 * but we need to be careful about the order. If the first 776 * m1 + m2 saturates then it's impossible for the *2+rc to 777 * bring it back into the non-saturated range. However, if 778 * m1 + m2 is negative then it's possible that doing the doubling 779 * would take the intermediate result below INT64_MAX and the 780 * addition of the rounding constant then brings it back in range. 781 * So we add half the rounding constant before doubling rather 782 * than adding the rounding constant after the doubling. 783 */ 784 if (sadd64_overflow(m1, m2, &r) || 785 sadd64_overflow(r, (round << 30), &r) || 786 sadd64_overflow(r, r, &r)) { 787 *sat = true; 788 return r < 0 ? INT32_MAX : INT32_MIN; 789 } 790 return r >> 32; 791 } 792 793 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 794 int round, bool *sat) 795 { 796 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 797 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 798 } 799 800 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 801 int round, bool *sat) 802 { 803 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 804 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 805 } 806 807 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 808 int round, bool *sat) 809 { 810 int64_t m1 = (int64_t)a * b; 811 int64_t m2 = (int64_t)c * d; 812 int64_t r; 813 /* The same ordering issue as in do_vqdmladh_w applies here too */ 814 if (ssub64_overflow(m1, m2, &r) || 815 sadd64_overflow(r, (round << 30), &r) || 816 sadd64_overflow(r, r, &r)) { 817 *sat = true; 818 return r < 0 ? INT32_MAX : INT32_MIN; 819 } 820 return r >> 32; 821 } 822 823 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 824 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 825 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 826 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 827 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 828 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 829 830 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 831 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 832 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 833 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 834 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 835 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 836 837 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 838 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 839 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 840 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 841 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 842 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 843 844 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 845 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 846 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 847 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 848 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 849 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 850 851 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 852 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 853 uint32_t rm) \ 854 { \ 855 TYPE *d = vd, *n = vn; \ 856 TYPE m = rm; \ 857 uint16_t mask = mve_element_mask(env); \ 858 unsigned e; \ 859 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 860 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 861 } \ 862 mve_advance_vpt(env); \ 863 } 864 865 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 866 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 867 uint32_t rm) \ 868 { \ 869 TYPE *d = vd, *n = vn; \ 870 TYPE m = rm; \ 871 uint16_t mask = mve_element_mask(env); \ 872 unsigned e; \ 873 bool qc = false; \ 874 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 875 bool sat = false; \ 876 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 877 mask); \ 878 qc |= sat & mask & 1; \ 879 } \ 880 if (qc) { \ 881 env->vfp.qc[0] = qc; \ 882 } \ 883 mve_advance_vpt(env); \ 884 } 885 886 /* provide unsigned 2-op scalar helpers for all sizes */ 887 #define DO_2OP_SCALAR_U(OP, FN) \ 888 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 889 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 890 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 891 #define DO_2OP_SCALAR_S(OP, FN) \ 892 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 893 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 894 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 895 896 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 897 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 898 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 899 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 900 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 901 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 902 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 903 904 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 905 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 906 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 907 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 908 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 909 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 910 911 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 912 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 913 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 914 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 915 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 916 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 917 918 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 919 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 920 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 921 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 922 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 923 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 924 925 /* 926 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 927 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 928 * SATMASK specifies which bits of the predicate mask matter for determining 929 * whether to propagate a saturation indication into FPSCR.QC -- for 930 * the 16x16->32 case we must check only the bit corresponding to the T or B 931 * half that we used, but for the 32x32->64 case we propagate if the mask 932 * bit is set for either half. 933 */ 934 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 935 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 936 uint32_t rm) \ 937 { \ 938 LTYPE *d = vd; \ 939 TYPE *n = vn; \ 940 TYPE m = rm; \ 941 uint16_t mask = mve_element_mask(env); \ 942 unsigned le; \ 943 bool qc = false; \ 944 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 945 bool sat = false; \ 946 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 947 mergemask(&d[H##LESIZE(le)], r, mask); \ 948 qc |= sat && (mask & SATMASK); \ 949 } \ 950 if (qc) { \ 951 env->vfp.qc[0] = qc; \ 952 } \ 953 mve_advance_vpt(env); \ 954 } 955 956 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 957 { 958 int64_t r = ((int64_t)n * m) * 2; 959 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 960 } 961 962 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 963 { 964 /* The multiply can't overflow, but the doubling might */ 965 int64_t r = (int64_t)n * m; 966 if (r > INT64_MAX / 2) { 967 *sat = true; 968 return INT64_MAX; 969 } else if (r < INT64_MIN / 2) { 970 *sat = true; 971 return INT64_MIN; 972 } else { 973 return r * 2; 974 } 975 } 976 977 #define SATMASK16B 1 978 #define SATMASK16T (1 << 2) 979 #define SATMASK32 ((1 << 4) | 1) 980 981 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 982 do_qdmullh, SATMASK16B) 983 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 984 do_qdmullw, SATMASK32) 985 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 986 do_qdmullh, SATMASK16T) 987 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 988 do_qdmullw, SATMASK32) 989 990 /* 991 * Long saturating ops 992 */ 993 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 994 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 995 void *vm) \ 996 { \ 997 LTYPE *d = vd; \ 998 TYPE *n = vn, *m = vm; \ 999 uint16_t mask = mve_element_mask(env); \ 1000 unsigned le; \ 1001 bool qc = false; \ 1002 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1003 bool sat = false; \ 1004 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1005 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1006 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1007 qc |= sat && (mask & SATMASK); \ 1008 } \ 1009 if (qc) { \ 1010 env->vfp.qc[0] = qc; \ 1011 } \ 1012 mve_advance_vpt(env); \ 1013 } 1014 1015 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1016 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1017 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1018 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1019 1020 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1021 { 1022 m &= 0xff; 1023 if (m == 0) { 1024 return 0; 1025 } 1026 n = revbit8(n); 1027 if (m < 8) { 1028 n >>= 8 - m; 1029 } 1030 return n; 1031 } 1032 1033 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1034 { 1035 m &= 0xff; 1036 if (m == 0) { 1037 return 0; 1038 } 1039 n = revbit16(n); 1040 if (m < 16) { 1041 n >>= 16 - m; 1042 } 1043 return n; 1044 } 1045 1046 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1047 { 1048 m &= 0xff; 1049 if (m == 0) { 1050 return 0; 1051 } 1052 n = revbit32(n); 1053 if (m < 32) { 1054 n >>= 32 - m; 1055 } 1056 return n; 1057 } 1058 1059 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1060 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1061 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1062 1063 /* 1064 * Multiply add long dual accumulate ops. 1065 */ 1066 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1067 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1068 void *vm, uint64_t a) \ 1069 { \ 1070 uint16_t mask = mve_element_mask(env); \ 1071 unsigned e; \ 1072 TYPE *n = vn, *m = vm; \ 1073 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1074 if (mask & 1) { \ 1075 if (e & 1) { \ 1076 a ODDACC \ 1077 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1078 } else { \ 1079 a EVENACC \ 1080 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1081 } \ 1082 } \ 1083 } \ 1084 mve_advance_vpt(env); \ 1085 return a; \ 1086 } 1087 1088 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1089 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1090 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1091 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1092 1093 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1094 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1095 1096 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1097 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1098 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1099 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1100 1101 /* 1102 * Rounding multiply add long dual accumulate high. In the pseudocode 1103 * this is implemented with a 72-bit internal accumulator value of which 1104 * the top 64 bits are returned. We optimize this to avoid having to 1105 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1106 * is squashed back into 64-bits after each beat. 1107 */ 1108 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1109 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1110 void *vm, uint64_t a) \ 1111 { \ 1112 uint16_t mask = mve_element_mask(env); \ 1113 unsigned e; \ 1114 TYPE *n = vn, *m = vm; \ 1115 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1116 if (mask & 1) { \ 1117 LTYPE mul; \ 1118 if (e & 1) { \ 1119 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1120 if (SUB) { \ 1121 mul = -mul; \ 1122 } \ 1123 } else { \ 1124 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1125 } \ 1126 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1127 a += mul; \ 1128 } \ 1129 } \ 1130 mve_advance_vpt(env); \ 1131 return a; \ 1132 } 1133 1134 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1135 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1136 1137 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1138 1139 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1140 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1141 1142 /* Vector add across vector */ 1143 #define DO_VADDV(OP, ESIZE, TYPE) \ 1144 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1145 uint32_t ra) \ 1146 { \ 1147 uint16_t mask = mve_element_mask(env); \ 1148 unsigned e; \ 1149 TYPE *m = vm; \ 1150 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1151 if (mask & 1) { \ 1152 ra += m[H##ESIZE(e)]; \ 1153 } \ 1154 } \ 1155 mve_advance_vpt(env); \ 1156 return ra; \ 1157 } \ 1158 1159 DO_VADDV(vaddvsb, 1, uint8_t) 1160 DO_VADDV(vaddvsh, 2, uint16_t) 1161 DO_VADDV(vaddvsw, 4, uint32_t) 1162 DO_VADDV(vaddvub, 1, uint8_t) 1163 DO_VADDV(vaddvuh, 2, uint16_t) 1164 DO_VADDV(vaddvuw, 4, uint32_t) 1165