1 /* 2 * M-profile MVE Operations 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "vec_internal.h" 24 #include "exec/helper-proto.h" 25 #include "accel/tcg/cpu-ldst.h" 26 #include "tcg/tcg.h" 27 #include "fpu/softfloat.h" 28 #include "crypto/clmul.h" 29 30 static uint16_t mve_eci_mask(CPUARMState *env) 31 { 32 /* 33 * Return the mask of which elements in the MVE vector correspond 34 * to beats being executed. The mask has 1 bits for executed lanes 35 * and 0 bits where ECI says this beat was already executed. 36 */ 37 int eci; 38 39 if ((env->condexec_bits & 0xf) != 0) { 40 return 0xffff; 41 } 42 43 eci = env->condexec_bits >> 4; 44 switch (eci) { 45 case ECI_NONE: 46 return 0xffff; 47 case ECI_A0: 48 return 0xfff0; 49 case ECI_A0A1: 50 return 0xff00; 51 case ECI_A0A1A2: 52 case ECI_A0A1A2B0: 53 return 0xf000; 54 default: 55 g_assert_not_reached(); 56 } 57 } 58 59 static uint16_t mve_element_mask(CPUARMState *env) 60 { 61 /* 62 * Return the mask of which elements in the MVE vector should be 63 * updated. This is a combination of multiple things: 64 * (1) by default, we update every lane in the vector 65 * (2) VPT predication stores its state in the VPR register; 66 * (3) low-overhead-branch tail predication will mask out part 67 * the vector on the final iteration of the loop 68 * (4) if EPSR.ECI is set then we must execute only some beats 69 * of the insn 70 * We combine all these into a 16-bit result with the same semantics 71 * as VPR.P0: 0 to mask the lane, 1 if it is active. 72 * 8-bit vector ops will look at all bits of the result; 73 * 16-bit ops will look at bits 0, 2, 4, ...; 74 * 32-bit ops will look at bits 0, 4, 8 and 12. 75 * Compare pseudocode GetCurInstrBeat(), though that only returns 76 * the 4-bit slice of the mask corresponding to a single beat. 77 */ 78 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 79 80 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { 81 mask |= 0xff; 82 } 83 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { 84 mask |= 0xff00; 85 } 86 87 if (env->v7m.ltpsize < 4 && 88 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { 89 /* 90 * Tail predication active, and this is the last loop iteration. 91 * The element size is (1 << ltpsize), and we only want to process 92 * loopcount elements, so we want to retain the least significant 93 * (loopcount * esize) predicate bits and zero out bits above that. 94 */ 95 int masklen = env->regs[14] << env->v7m.ltpsize; 96 assert(masklen <= 16); 97 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 98 mask &= ltpmask; 99 } 100 101 /* 102 * ECI bits indicate which beats are already executed; 103 * we handle this by effectively predicating them out. 104 */ 105 mask &= mve_eci_mask(env); 106 return mask; 107 } 108 109 static void mve_advance_vpt(CPUARMState *env) 110 { 111 /* Advance the VPT and ECI state if necessary */ 112 uint32_t vpr = env->v7m.vpr; 113 unsigned mask01, mask23; 114 uint16_t inv_mask; 115 uint16_t eci_mask = mve_eci_mask(env); 116 117 if ((env->condexec_bits & 0xf) == 0) { 118 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? 119 (ECI_A0 << 4) : (ECI_NONE << 4); 120 } 121 122 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { 123 /* VPT not enabled, nothing to do */ 124 return; 125 } 126 127 /* Invert P0 bits if needed, but only for beats we actually executed */ 128 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); 129 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); 130 /* Start by assuming we invert all bits corresponding to executed beats */ 131 inv_mask = eci_mask; 132 if (mask01 <= 8) { 133 /* MASK01 says don't invert low half of P0 */ 134 inv_mask &= ~0xff; 135 } 136 if (mask23 <= 8) { 137 /* MASK23 says don't invert high half of P0 */ 138 inv_mask &= ~0xff00; 139 } 140 vpr ^= inv_mask; 141 /* Only update MASK01 if beat 1 executed */ 142 if (eci_mask & 0xf0) { 143 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); 144 } 145 /* Beat 3 always executes, so update MASK23 */ 146 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); 147 env->v7m.vpr = vpr; 148 } 149 150 /* For loads, predicated lanes are zeroed instead of keeping their old values */ 151 #define DO_VLDR(OP, MFLAG, MSIZE, MTYPE, LDTYPE, ESIZE, TYPE) \ 152 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 153 { \ 154 TYPE *d = vd; \ 155 uint16_t mask = mve_element_mask(env); \ 156 uint16_t eci_mask = mve_eci_mask(env); \ 157 unsigned b, e; \ 158 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 159 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 160 /* \ 161 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ 162 * beats so we don't care if we update part of the dest and \ 163 * then take an exception. \ 164 */ \ 165 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 166 if (eci_mask & (1 << b)) { \ 167 d[H##ESIZE(e)] = (mask & (1 << b)) ? \ 168 (MTYPE)cpu_##LDTYPE##_mmu(env, addr, oi, GETPC()) : 0;\ 169 } \ 170 addr += MSIZE; \ 171 } \ 172 mve_advance_vpt(env); \ 173 } 174 175 #define DO_VSTR(OP, MFLAG, MSIZE, STTYPE, ESIZE, TYPE) \ 176 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ 177 { \ 178 TYPE *d = vd; \ 179 uint16_t mask = mve_element_mask(env); \ 180 unsigned b, e; \ 181 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 182 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 183 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ 184 if (mask & (1 << b)) { \ 185 cpu_##STTYPE##_mmu(env, addr, d[H##ESIZE(e)], oi, GETPC()); \ 186 } \ 187 addr += MSIZE; \ 188 } \ 189 mve_advance_vpt(env); \ 190 } 191 192 DO_VLDR(vldrb, MO_UB, 1, uint8_t, ldb, 1, uint8_t) 193 DO_VLDR(vldrh, MO_TEUW, 2, uint16_t, ldw, 2, uint16_t) 194 DO_VLDR(vldrw, MO_TEUL, 4, uint32_t, ldl, 4, uint32_t) 195 196 DO_VSTR(vstrb, MO_UB, 1, stb, 1, uint8_t) 197 DO_VSTR(vstrh, MO_TEUW, 2, stw, 2, uint16_t) 198 DO_VSTR(vstrw, MO_TEUL, 4, stl, 4, uint32_t) 199 200 DO_VLDR(vldrb_sh, MO_SB, 1, int8_t, ldb, 2, int16_t) 201 DO_VLDR(vldrb_sw, MO_SB, 1, int8_t, ldb, 4, int32_t) 202 DO_VLDR(vldrb_uh, MO_UB, 1, uint8_t, ldb, 2, uint16_t) 203 DO_VLDR(vldrb_uw, MO_UB, 1, uint8_t, ldb, 4, uint32_t) 204 DO_VLDR(vldrh_sw, MO_TESW, 2, int16_t, ldw, 4, int32_t) 205 DO_VLDR(vldrh_uw, MO_TEUW, 2, uint16_t, ldw, 4, uint32_t) 206 207 DO_VSTR(vstrb_h, MO_UB, 1, stb, 2, int16_t) 208 DO_VSTR(vstrb_w, MO_UB, 1, stb, 4, int32_t) 209 DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) 210 211 #undef DO_VLDR 212 #undef DO_VSTR 213 214 /* 215 * Gather loads/scatter stores. Here each element of Qm specifies 216 * an offset to use from the base register Rm. In the _os_ versions 217 * that offset is scaled by the element size. 218 * For loads, predicated lanes are zeroed instead of retaining 219 * their previous values. 220 */ 221 #define DO_VLDR_SG(OP, MFLAG, MTYPE, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN, WB)\ 222 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 223 uint32_t base) \ 224 { \ 225 TYPE *d = vd; \ 226 OFFTYPE *m = vm; \ 227 uint16_t mask = mve_element_mask(env); \ 228 uint16_t eci_mask = mve_eci_mask(env); \ 229 unsigned e; \ 230 uint32_t addr; \ 231 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 232 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 233 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 234 if (!(eci_mask & 1)) { \ 235 continue; \ 236 } \ 237 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 238 d[H##ESIZE(e)] = (mask & 1) ? \ 239 (MTYPE)cpu_##LDTYPE##_mmu(env, addr, oi, GETPC()) : 0; \ 240 if (WB) { \ 241 m[H##ESIZE(e)] = addr; \ 242 } \ 243 } \ 244 mve_advance_vpt(env); \ 245 } 246 247 /* We know here TYPE is unsigned so always the same as the offset type */ 248 #define DO_VSTR_SG(OP, MFLAG, STTYPE, ESIZE, TYPE, ADDRFN, WB) \ 249 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 250 uint32_t base) \ 251 { \ 252 TYPE *d = vd; \ 253 TYPE *m = vm; \ 254 uint16_t mask = mve_element_mask(env); \ 255 uint16_t eci_mask = mve_eci_mask(env); \ 256 unsigned e; \ 257 uint32_t addr; \ 258 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 259 MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ 260 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \ 261 if (!(eci_mask & 1)) { \ 262 continue; \ 263 } \ 264 addr = ADDRFN(base, m[H##ESIZE(e)]); \ 265 if (mask & 1) { \ 266 cpu_##STTYPE##_mmu(env, addr, d[H##ESIZE(e)], oi, GETPC()); \ 267 } \ 268 if (WB) { \ 269 m[H##ESIZE(e)] = addr; \ 270 } \ 271 } \ 272 mve_advance_vpt(env); \ 273 } 274 275 /* 276 * 64-bit accesses are slightly different: they are done as two 32-bit 277 * accesses, controlled by the predicate mask for the relevant beat, 278 * and with a single 32-bit offset in the first of the two Qm elements. 279 * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little). 280 * Address writeback happens on the odd beats and updates the address 281 * stored in the even-beat element. 282 */ 283 #define DO_VLDR64_SG(OP, ADDRFN, WB) \ 284 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 285 uint32_t base) \ 286 { \ 287 uint32_t *d = vd; \ 288 uint32_t *m = vm; \ 289 uint16_t mask = mve_element_mask(env); \ 290 uint16_t eci_mask = mve_eci_mask(env); \ 291 unsigned e; \ 292 uint32_t addr; \ 293 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 294 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 295 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 296 if (!(eci_mask & 1)) { \ 297 continue; \ 298 } \ 299 addr = ADDRFN(base, m[H4(e & ~1)]); \ 300 addr += 4 * (e & 1); \ 301 d[H4(e)] = (mask & 1) ? cpu_ldl_mmu(env, addr, oi, GETPC()) : 0; \ 302 if (WB && (e & 1)) { \ 303 m[H4(e & ~1)] = addr - 4; \ 304 } \ 305 } \ 306 mve_advance_vpt(env); \ 307 } 308 309 #define DO_VSTR64_SG(OP, ADDRFN, WB) \ 310 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \ 311 uint32_t base) \ 312 { \ 313 uint32_t *d = vd; \ 314 uint32_t *m = vm; \ 315 uint16_t mask = mve_element_mask(env); \ 316 uint16_t eci_mask = mve_eci_mask(env); \ 317 unsigned e; \ 318 uint32_t addr; \ 319 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 320 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 321 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \ 322 if (!(eci_mask & 1)) { \ 323 continue; \ 324 } \ 325 addr = ADDRFN(base, m[H4(e & ~1)]); \ 326 addr += 4 * (e & 1); \ 327 if (mask & 1) { \ 328 cpu_stl_mmu(env, addr, d[H4(e)], oi, GETPC()); \ 329 } \ 330 if (WB && (e & 1)) { \ 331 m[H4(e & ~1)] = addr - 4; \ 332 } \ 333 } \ 334 mve_advance_vpt(env); \ 335 } 336 337 #define ADDR_ADD(BASE, OFFSET) ((BASE) + (OFFSET)) 338 #define ADDR_ADD_OSH(BASE, OFFSET) ((BASE) + ((OFFSET) << 1)) 339 #define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2)) 340 #define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3)) 341 342 DO_VLDR_SG(vldrb_sg_sh, MO_SB, int8_t, ldb, 2, int16_t, uint16_t, ADDR_ADD, false) 343 DO_VLDR_SG(vldrb_sg_sw, MO_SB, int8_t, ldb, 4, int32_t, uint32_t, ADDR_ADD, false) 344 DO_VLDR_SG(vldrh_sg_sw, MO_TESW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_ADD, false) 345 346 DO_VLDR_SG(vldrb_sg_ub, MO_UB, uint8_t, ldb, 1, uint8_t, uint8_t, ADDR_ADD, false) 347 DO_VLDR_SG(vldrb_sg_uh, MO_UB, uint8_t, ldb, 2, uint16_t, uint16_t, ADDR_ADD, false) 348 DO_VLDR_SG(vldrb_sg_uw, MO_UB, uint8_t, ldb, 4, uint32_t, uint32_t, ADDR_ADD, false) 349 DO_VLDR_SG(vldrh_sg_uh, MO_TEUW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_ADD, false) 350 DO_VLDR_SG(vldrh_sg_uw, MO_TEUW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_ADD, false) 351 DO_VLDR_SG(vldrw_sg_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false) 352 DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) 353 354 DO_VLDR_SG(vldrh_sg_os_sw, MO_TESW, int16_t, ldw, 4, 355 int32_t, uint32_t, ADDR_ADD_OSH, false) 356 DO_VLDR_SG(vldrh_sg_os_uh, MO_TEUW, uint16_t, ldw, 2, 357 uint16_t, uint16_t, ADDR_ADD_OSH, false) 358 DO_VLDR_SG(vldrh_sg_os_uw, MO_TEUW, uint16_t, ldw, 4, 359 uint32_t, uint32_t, ADDR_ADD_OSH, false) 360 DO_VLDR_SG(vldrw_sg_os_uw, MO_TEUL, uint32_t, ldl, 4, 361 uint32_t, uint32_t, ADDR_ADD_OSW, false) 362 DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) 363 364 DO_VSTR_SG(vstrb_sg_ub, MO_UB, stb, 1, uint8_t, ADDR_ADD, false) 365 DO_VSTR_SG(vstrb_sg_uh, MO_UB, stb, 2, uint16_t, ADDR_ADD, false) 366 DO_VSTR_SG(vstrb_sg_uw, MO_UB, stb, 4, uint32_t, ADDR_ADD, false) 367 DO_VSTR_SG(vstrh_sg_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD, false) 368 DO_VSTR_SG(vstrh_sg_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD, false) 369 DO_VSTR_SG(vstrw_sg_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, false) 370 DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) 371 372 DO_VSTR_SG(vstrh_sg_os_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD_OSH, false) 373 DO_VSTR_SG(vstrh_sg_os_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD_OSH, false) 374 DO_VSTR_SG(vstrw_sg_os_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD_OSW, false) 375 DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) 376 377 DO_VLDR_SG(vldrw_sg_wb_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true) 378 DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) 379 DO_VSTR_SG(vstrw_sg_wb_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, true) 380 DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) 381 382 /* 383 * Deinterleaving loads/interleaving stores. 384 * 385 * For these helpers we are passed the index of the first Qreg 386 * (VLD2/VST2 will also access Qn+1, VLD4/VST4 access Qn .. Qn+3) 387 * and the value of the base address register Rn. 388 * The helpers are specialized for pattern and element size, so 389 * for instance vld42h is VLD4 with pattern 2, element size MO_16. 390 * 391 * These insns are beatwise but not predicated, so we must honour ECI, 392 * but need not look at mve_element_mask(). 393 * 394 * The pseudocode implements these insns with multiple memory accesses 395 * of the element size, but rules R_VVVG and R_FXDM permit us to make 396 * one 32-bit memory access per beat. 397 */ 398 #define DO_VLD4B(OP, O1, O2, O3, O4) \ 399 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 400 uint32_t base) \ 401 { \ 402 int beat, e; \ 403 uint16_t mask = mve_eci_mask(env); \ 404 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 405 uint32_t addr, data; \ 406 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 407 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 408 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 409 if ((mask & 1) == 0) { \ 410 /* ECI says skip this beat */ \ 411 continue; \ 412 } \ 413 addr = base + off[beat] * 4; \ 414 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 415 for (e = 0; e < 4; e++, data >>= 8) { \ 416 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 417 qd[H1(off[beat])] = data; \ 418 } \ 419 } \ 420 } 421 422 #define DO_VLD4H(OP, O1, O2) \ 423 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 424 uint32_t base) \ 425 { \ 426 int beat; \ 427 uint16_t mask = mve_eci_mask(env); \ 428 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 429 uint32_t addr, data; \ 430 int y; /* y counts 0 2 0 2 */ \ 431 uint16_t *qd; \ 432 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 433 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 434 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 435 if ((mask & 1) == 0) { \ 436 /* ECI says skip this beat */ \ 437 continue; \ 438 } \ 439 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 440 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 441 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 442 qd[H2(off[beat])] = data; \ 443 data >>= 16; \ 444 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 445 qd[H2(off[beat])] = data; \ 446 } \ 447 } 448 449 #define DO_VLD4W(OP, O1, O2, O3, O4) \ 450 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 451 uint32_t base) \ 452 { \ 453 int beat; \ 454 uint16_t mask = mve_eci_mask(env); \ 455 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 456 uint32_t addr, data; \ 457 uint32_t *qd; \ 458 int y; \ 459 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 460 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 461 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 462 if ((mask & 1) == 0) { \ 463 /* ECI says skip this beat */ \ 464 continue; \ 465 } \ 466 addr = base + off[beat] * 4; \ 467 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 468 y = (beat + (O1 & 2)) & 3; \ 469 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 470 qd[H4(off[beat] >> 2)] = data; \ 471 } \ 472 } 473 474 DO_VLD4B(vld40b, 0, 1, 10, 11) 475 DO_VLD4B(vld41b, 2, 3, 12, 13) 476 DO_VLD4B(vld42b, 4, 5, 14, 15) 477 DO_VLD4B(vld43b, 6, 7, 8, 9) 478 479 DO_VLD4H(vld40h, 0, 5) 480 DO_VLD4H(vld41h, 1, 6) 481 DO_VLD4H(vld42h, 2, 7) 482 DO_VLD4H(vld43h, 3, 4) 483 484 DO_VLD4W(vld40w, 0, 1, 10, 11) 485 DO_VLD4W(vld41w, 2, 3, 12, 13) 486 DO_VLD4W(vld42w, 4, 5, 14, 15) 487 DO_VLD4W(vld43w, 6, 7, 8, 9) 488 489 #define DO_VLD2B(OP, O1, O2, O3, O4) \ 490 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 491 uint32_t base) \ 492 { \ 493 int beat, e; \ 494 uint16_t mask = mve_eci_mask(env); \ 495 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 496 uint32_t addr, data; \ 497 uint8_t *qd; \ 498 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 499 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 500 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 501 if ((mask & 1) == 0) { \ 502 /* ECI says skip this beat */ \ 503 continue; \ 504 } \ 505 addr = base + off[beat] * 2; \ 506 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 507 for (e = 0; e < 4; e++, data >>= 8) { \ 508 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 509 qd[H1(off[beat] + (e >> 1))] = data; \ 510 } \ 511 } \ 512 } 513 514 #define DO_VLD2H(OP, O1, O2, O3, O4) \ 515 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 516 uint32_t base) \ 517 { \ 518 int beat; \ 519 uint16_t mask = mve_eci_mask(env); \ 520 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 521 uint32_t addr, data; \ 522 int e; \ 523 uint16_t *qd; \ 524 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 525 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 526 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 527 if ((mask & 1) == 0) { \ 528 /* ECI says skip this beat */ \ 529 continue; \ 530 } \ 531 addr = base + off[beat] * 4; \ 532 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 533 for (e = 0; e < 2; e++, data >>= 16) { \ 534 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 535 qd[H2(off[beat])] = data; \ 536 } \ 537 } \ 538 } 539 540 #define DO_VLD2W(OP, O1, O2, O3, O4) \ 541 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 542 uint32_t base) \ 543 { \ 544 int beat; \ 545 uint16_t mask = mve_eci_mask(env); \ 546 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 547 uint32_t addr, data; \ 548 uint32_t *qd; \ 549 int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \ 550 MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ 551 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 552 if ((mask & 1) == 0) { \ 553 /* ECI says skip this beat */ \ 554 continue; \ 555 } \ 556 addr = base + off[beat]; \ 557 data = cpu_ldl_mmu(env, addr, oi, GETPC()); \ 558 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 559 qd[H4(off[beat] >> 3)] = data; \ 560 } \ 561 } 562 563 DO_VLD2B(vld20b, 0, 2, 12, 14) 564 DO_VLD2B(vld21b, 4, 6, 8, 10) 565 566 DO_VLD2H(vld20h, 0, 1, 6, 7) 567 DO_VLD2H(vld21h, 2, 3, 4, 5) 568 569 DO_VLD2W(vld20w, 0, 4, 24, 28) 570 DO_VLD2W(vld21w, 8, 12, 16, 20) 571 572 #define DO_VST4B(OP, O1, O2, O3, O4) \ 573 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 574 uint32_t base) \ 575 { \ 576 int beat, e; \ 577 uint16_t mask = mve_eci_mask(env); \ 578 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 579 uint32_t addr, data; \ 580 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 581 if ((mask & 1) == 0) { \ 582 /* ECI says skip this beat */ \ 583 continue; \ 584 } \ 585 addr = base + off[beat] * 4; \ 586 data = 0; \ 587 for (e = 3; e >= 0; e--) { \ 588 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \ 589 data = (data << 8) | qd[H1(off[beat])]; \ 590 } \ 591 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 592 } \ 593 } 594 595 #define DO_VST4H(OP, O1, O2) \ 596 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 597 uint32_t base) \ 598 { \ 599 int beat; \ 600 uint16_t mask = mve_eci_mask(env); \ 601 static const uint8_t off[4] = { O1, O1, O2, O2 }; \ 602 uint32_t addr, data; \ 603 int y; /* y counts 0 2 0 2 */ \ 604 uint16_t *qd; \ 605 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \ 606 if ((mask & 1) == 0) { \ 607 /* ECI says skip this beat */ \ 608 continue; \ 609 } \ 610 addr = base + off[beat] * 8 + (beat & 1) * 4; \ 611 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \ 612 data = qd[H2(off[beat])]; \ 613 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \ 614 data |= qd[H2(off[beat])] << 16; \ 615 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 616 } \ 617 } 618 619 #define DO_VST4W(OP, O1, O2, O3, O4) \ 620 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 621 uint32_t base) \ 622 { \ 623 int beat; \ 624 uint16_t mask = mve_eci_mask(env); \ 625 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 626 uint32_t addr, data; \ 627 uint32_t *qd; \ 628 int y; \ 629 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 630 if ((mask & 1) == 0) { \ 631 /* ECI says skip this beat */ \ 632 continue; \ 633 } \ 634 addr = base + off[beat] * 4; \ 635 y = (beat + (O1 & 2)) & 3; \ 636 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \ 637 data = qd[H4(off[beat] >> 2)]; \ 638 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 639 } \ 640 } 641 642 DO_VST4B(vst40b, 0, 1, 10, 11) 643 DO_VST4B(vst41b, 2, 3, 12, 13) 644 DO_VST4B(vst42b, 4, 5, 14, 15) 645 DO_VST4B(vst43b, 6, 7, 8, 9) 646 647 DO_VST4H(vst40h, 0, 5) 648 DO_VST4H(vst41h, 1, 6) 649 DO_VST4H(vst42h, 2, 7) 650 DO_VST4H(vst43h, 3, 4) 651 652 DO_VST4W(vst40w, 0, 1, 10, 11) 653 DO_VST4W(vst41w, 2, 3, 12, 13) 654 DO_VST4W(vst42w, 4, 5, 14, 15) 655 DO_VST4W(vst43w, 6, 7, 8, 9) 656 657 #define DO_VST2B(OP, O1, O2, O3, O4) \ 658 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 659 uint32_t base) \ 660 { \ 661 int beat, e; \ 662 uint16_t mask = mve_eci_mask(env); \ 663 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 664 uint32_t addr, data; \ 665 uint8_t *qd; \ 666 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 667 if ((mask & 1) == 0) { \ 668 /* ECI says skip this beat */ \ 669 continue; \ 670 } \ 671 addr = base + off[beat] * 2; \ 672 data = 0; \ 673 for (e = 3; e >= 0; e--) { \ 674 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \ 675 data = (data << 8) | qd[H1(off[beat] + (e >> 1))]; \ 676 } \ 677 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 678 } \ 679 } 680 681 #define DO_VST2H(OP, O1, O2, O3, O4) \ 682 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 683 uint32_t base) \ 684 { \ 685 int beat; \ 686 uint16_t mask = mve_eci_mask(env); \ 687 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 688 uint32_t addr, data; \ 689 int e; \ 690 uint16_t *qd; \ 691 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 692 if ((mask & 1) == 0) { \ 693 /* ECI says skip this beat */ \ 694 continue; \ 695 } \ 696 addr = base + off[beat] * 4; \ 697 data = 0; \ 698 for (e = 1; e >= 0; e--) { \ 699 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \ 700 data = (data << 16) | qd[H2(off[beat])]; \ 701 } \ 702 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 703 } \ 704 } 705 706 #define DO_VST2W(OP, O1, O2, O3, O4) \ 707 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \ 708 uint32_t base) \ 709 { \ 710 int beat; \ 711 uint16_t mask = mve_eci_mask(env); \ 712 static const uint8_t off[4] = { O1, O2, O3, O4 }; \ 713 uint32_t addr, data; \ 714 uint32_t *qd; \ 715 for (beat = 0; beat < 4; beat++, mask >>= 4) { \ 716 if ((mask & 1) == 0) { \ 717 /* ECI says skip this beat */ \ 718 continue; \ 719 } \ 720 addr = base + off[beat]; \ 721 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \ 722 data = qd[H4(off[beat] >> 3)]; \ 723 cpu_stl_le_data_ra(env, addr, data, GETPC()); \ 724 } \ 725 } 726 727 DO_VST2B(vst20b, 0, 2, 12, 14) 728 DO_VST2B(vst21b, 4, 6, 8, 10) 729 730 DO_VST2H(vst20h, 0, 1, 6, 7) 731 DO_VST2H(vst21h, 2, 3, 4, 5) 732 733 DO_VST2W(vst20w, 0, 4, 24, 28) 734 DO_VST2W(vst21w, 8, 12, 16, 20) 735 736 /* 737 * The mergemask(D, R, M) macro performs the operation "*D = R" but 738 * storing only the bytes which correspond to 1 bits in M, 739 * leaving other bytes in *D unchanged. We use _Generic 740 * to select the correct implementation based on the type of D. 741 */ 742 743 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) 744 { 745 if (mask & 1) { 746 *d = r; 747 } 748 } 749 750 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) 751 { 752 mergemask_ub((uint8_t *)d, r, mask); 753 } 754 755 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) 756 { 757 uint16_t bmask = expand_pred_b(mask); 758 *d = (*d & ~bmask) | (r & bmask); 759 } 760 761 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) 762 { 763 mergemask_uh((uint16_t *)d, r, mask); 764 } 765 766 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) 767 { 768 uint32_t bmask = expand_pred_b(mask); 769 *d = (*d & ~bmask) | (r & bmask); 770 } 771 772 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) 773 { 774 mergemask_uw((uint32_t *)d, r, mask); 775 } 776 777 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) 778 { 779 uint64_t bmask = expand_pred_b(mask); 780 *d = (*d & ~bmask) | (r & bmask); 781 } 782 783 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) 784 { 785 mergemask_uq((uint64_t *)d, r, mask); 786 } 787 788 #define mergemask(D, R, M) \ 789 _Generic(D, \ 790 uint8_t *: mergemask_ub, \ 791 int8_t *: mergemask_sb, \ 792 uint16_t *: mergemask_uh, \ 793 int16_t *: mergemask_sh, \ 794 uint32_t *: mergemask_uw, \ 795 int32_t *: mergemask_sw, \ 796 uint64_t *: mergemask_uq, \ 797 int64_t *: mergemask_sq)(D, R, M) 798 799 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) 800 { 801 /* 802 * The generated code already replicated an 8 or 16 bit constant 803 * into the 32-bit value, so we only need to write the 32-bit 804 * value to all elements of the Qreg, allowing for predication. 805 */ 806 uint32_t *d = vd; 807 uint16_t mask = mve_element_mask(env); 808 unsigned e; 809 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 810 mergemask(&d[H4(e)], val, mask); 811 } 812 mve_advance_vpt(env); 813 } 814 815 #define DO_1OP(OP, ESIZE, TYPE, FN) \ 816 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 817 { \ 818 TYPE *d = vd, *m = vm; \ 819 uint16_t mask = mve_element_mask(env); \ 820 unsigned e; \ 821 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 822 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ 823 } \ 824 mve_advance_vpt(env); \ 825 } 826 827 #define DO_CLS_B(N) (clrsb32(N) - 24) 828 #define DO_CLS_H(N) (clrsb32(N) - 16) 829 830 DO_1OP(vclsb, 1, int8_t, DO_CLS_B) 831 DO_1OP(vclsh, 2, int16_t, DO_CLS_H) 832 DO_1OP(vclsw, 4, int32_t, clrsb32) 833 834 #define DO_CLZ_B(N) (clz32(N) - 24) 835 #define DO_CLZ_H(N) (clz32(N) - 16) 836 837 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) 838 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) 839 DO_1OP(vclzw, 4, uint32_t, clz32) 840 841 DO_1OP(vrev16b, 2, uint16_t, bswap16) 842 DO_1OP(vrev32b, 4, uint32_t, bswap32) 843 DO_1OP(vrev32h, 4, uint32_t, hswap32) 844 DO_1OP(vrev64b, 8, uint64_t, bswap64) 845 DO_1OP(vrev64h, 8, uint64_t, hswap64) 846 DO_1OP(vrev64w, 8, uint64_t, wswap64) 847 848 #define DO_NOT(N) (~(N)) 849 850 DO_1OP(vmvn, 8, uint64_t, DO_NOT) 851 852 #define DO_ABS(N) ((N) < 0 ? -(N) : (N)) 853 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) 854 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) 855 856 DO_1OP(vabsb, 1, int8_t, DO_ABS) 857 DO_1OP(vabsh, 2, int16_t, DO_ABS) 858 DO_1OP(vabsw, 4, int32_t, DO_ABS) 859 860 /* We can do these 64 bits at a time */ 861 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) 862 DO_1OP(vfabss, 8, uint64_t, DO_FABSS) 863 864 #define DO_NEG(N) (-(N)) 865 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) 866 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) 867 868 DO_1OP(vnegb, 1, int8_t, DO_NEG) 869 DO_1OP(vnegh, 2, int16_t, DO_NEG) 870 DO_1OP(vnegw, 4, int32_t, DO_NEG) 871 872 /* We can do these 64 bits at a time */ 873 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) 874 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) 875 876 /* 877 * 1 operand immediates: Vda is destination and possibly also one source. 878 * All these insns work at 64-bit widths. 879 */ 880 #define DO_1OP_IMM(OP, FN) \ 881 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ 882 { \ 883 uint64_t *da = vda; \ 884 uint16_t mask = mve_element_mask(env); \ 885 unsigned e; \ 886 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 887 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ 888 } \ 889 mve_advance_vpt(env); \ 890 } 891 892 #define DO_MOVI(N, I) (I) 893 #define DO_ANDI(N, I) ((N) & (I)) 894 #define DO_ORRI(N, I) ((N) | (I)) 895 896 DO_1OP_IMM(vmovi, DO_MOVI) 897 DO_1OP_IMM(vandi, DO_ANDI) 898 DO_1OP_IMM(vorri, DO_ORRI) 899 900 #define DO_2OP(OP, ESIZE, TYPE, FN) \ 901 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 902 void *vd, void *vn, void *vm) \ 903 { \ 904 TYPE *d = vd, *n = vn, *m = vm; \ 905 uint16_t mask = mve_element_mask(env); \ 906 unsigned e; \ 907 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 908 mergemask(&d[H##ESIZE(e)], \ 909 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ 910 } \ 911 mve_advance_vpt(env); \ 912 } 913 914 /* provide unsigned 2-op helpers for all sizes */ 915 #define DO_2OP_U(OP, FN) \ 916 DO_2OP(OP##b, 1, uint8_t, FN) \ 917 DO_2OP(OP##h, 2, uint16_t, FN) \ 918 DO_2OP(OP##w, 4, uint32_t, FN) 919 920 /* provide signed 2-op helpers for all sizes */ 921 #define DO_2OP_S(OP, FN) \ 922 DO_2OP(OP##b, 1, int8_t, FN) \ 923 DO_2OP(OP##h, 2, int16_t, FN) \ 924 DO_2OP(OP##w, 4, int32_t, FN) 925 926 /* 927 * "Long" operations where two half-sized inputs (taken from either the 928 * top or the bottom of the input vector) produce a double-width result. 929 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. 930 */ 931 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 932 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 933 { \ 934 LTYPE *d = vd; \ 935 TYPE *n = vn, *m = vm; \ 936 uint16_t mask = mve_element_mask(env); \ 937 unsigned le; \ 938 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 939 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ 940 m[H##ESIZE(le * 2 + TOP)]); \ 941 mergemask(&d[H##LESIZE(le)], r, mask); \ 942 } \ 943 mve_advance_vpt(env); \ 944 } 945 946 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ 947 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 948 { \ 949 TYPE *d = vd, *n = vn, *m = vm; \ 950 uint16_t mask = mve_element_mask(env); \ 951 unsigned e; \ 952 bool qc = false; \ 953 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 954 bool sat = false; \ 955 TYPE r_ = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ 956 mergemask(&d[H##ESIZE(e)], r_, mask); \ 957 qc |= sat & mask & 1; \ 958 } \ 959 if (qc) { \ 960 env->vfp.qc[0] = qc; \ 961 } \ 962 mve_advance_vpt(env); \ 963 } 964 965 /* provide unsigned 2-op helpers for all sizes */ 966 #define DO_2OP_SAT_U(OP, FN) \ 967 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ 968 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ 969 DO_2OP_SAT(OP##w, 4, uint32_t, FN) 970 971 /* provide signed 2-op helpers for all sizes */ 972 #define DO_2OP_SAT_S(OP, FN) \ 973 DO_2OP_SAT(OP##b, 1, int8_t, FN) \ 974 DO_2OP_SAT(OP##h, 2, int16_t, FN) \ 975 DO_2OP_SAT(OP##w, 4, int32_t, FN) 976 977 #define DO_AND(N, M) ((N) & (M)) 978 #define DO_BIC(N, M) ((N) & ~(M)) 979 #define DO_ORR(N, M) ((N) | (M)) 980 #define DO_ORN(N, M) ((N) | ~(M)) 981 #define DO_EOR(N, M) ((N) ^ (M)) 982 983 DO_2OP(vand, 8, uint64_t, DO_AND) 984 DO_2OP(vbic, 8, uint64_t, DO_BIC) 985 DO_2OP(vorr, 8, uint64_t, DO_ORR) 986 DO_2OP(vorn, 8, uint64_t, DO_ORN) 987 DO_2OP(veor, 8, uint64_t, DO_EOR) 988 989 #define DO_ADD(N, M) ((N) + (M)) 990 #define DO_SUB(N, M) ((N) - (M)) 991 #define DO_MUL(N, M) ((N) * (M)) 992 993 DO_2OP_U(vadd, DO_ADD) 994 DO_2OP_U(vsub, DO_SUB) 995 DO_2OP_U(vmul, DO_MUL) 996 997 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) 998 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) 999 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) 1000 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) 1001 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) 1002 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) 1003 1004 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) 1005 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) 1006 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) 1007 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) 1008 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) 1009 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) 1010 1011 /* 1012 * Polynomial multiply. We can always do this generating 64 bits 1013 * of the result at a time, so we don't need to use DO_2OP_L. 1014 */ 1015 DO_2OP(vmullpbh, 8, uint64_t, clmul_8x4_even) 1016 DO_2OP(vmullpth, 8, uint64_t, clmul_8x4_odd) 1017 DO_2OP(vmullpbw, 8, uint64_t, clmul_16x2_even) 1018 DO_2OP(vmullptw, 8, uint64_t, clmul_16x2_odd) 1019 1020 /* 1021 * Because the computation type is at least twice as large as required, 1022 * these work for both signed and unsigned source types. 1023 */ 1024 static inline uint8_t do_mulh_b(int32_t n, int32_t m) 1025 { 1026 return (n * m) >> 8; 1027 } 1028 1029 static inline uint16_t do_mulh_h(int32_t n, int32_t m) 1030 { 1031 return (n * m) >> 16; 1032 } 1033 1034 static inline uint32_t do_mulh_w(int64_t n, int64_t m) 1035 { 1036 return (n * m) >> 32; 1037 } 1038 1039 static inline uint8_t do_rmulh_b(int32_t n, int32_t m) 1040 { 1041 return (n * m + (1U << 7)) >> 8; 1042 } 1043 1044 static inline uint16_t do_rmulh_h(int32_t n, int32_t m) 1045 { 1046 return (n * m + (1U << 15)) >> 16; 1047 } 1048 1049 static inline uint32_t do_rmulh_w(int64_t n, int64_t m) 1050 { 1051 return (n * m + (1U << 31)) >> 32; 1052 } 1053 1054 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) 1055 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) 1056 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) 1057 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) 1058 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) 1059 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) 1060 1061 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) 1062 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) 1063 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) 1064 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) 1065 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) 1066 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) 1067 1068 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 1069 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 1070 1071 DO_2OP_S(vmaxs, DO_MAX) 1072 DO_2OP_U(vmaxu, DO_MAX) 1073 DO_2OP_S(vmins, DO_MIN) 1074 DO_2OP_U(vminu, DO_MIN) 1075 1076 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) 1077 1078 DO_2OP_S(vabds, DO_ABD) 1079 DO_2OP_U(vabdu, DO_ABD) 1080 1081 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) 1082 { 1083 return ((uint64_t)n + m) >> 1; 1084 } 1085 1086 static inline int32_t do_vhadd_s(int32_t n, int32_t m) 1087 { 1088 return ((int64_t)n + m) >> 1; 1089 } 1090 1091 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) 1092 { 1093 return ((uint64_t)n - m) >> 1; 1094 } 1095 1096 static inline int32_t do_vhsub_s(int32_t n, int32_t m) 1097 { 1098 return ((int64_t)n - m) >> 1; 1099 } 1100 1101 DO_2OP_S(vhadds, do_vhadd_s) 1102 DO_2OP_U(vhaddu, do_vhadd_u) 1103 DO_2OP_S(vhsubs, do_vhsub_s) 1104 DO_2OP_U(vhsubu, do_vhsub_u) 1105 1106 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1107 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) 1108 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1109 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) 1110 1111 DO_2OP_S(vshls, DO_VSHLS) 1112 DO_2OP_U(vshlu, DO_VSHLU) 1113 DO_2OP_S(vrshls, DO_VRSHLS) 1114 DO_2OP_U(vrshlu, DO_VRSHLU) 1115 1116 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) 1117 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) 1118 1119 DO_2OP_S(vrhadds, DO_RHADD_S) 1120 DO_2OP_U(vrhaddu, DO_RHADD_U) 1121 1122 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, 1123 uint32_t inv, uint32_t carry_in, bool update_flags) 1124 { 1125 uint16_t mask = mve_element_mask(env); 1126 unsigned e; 1127 1128 /* If any additions trigger, we will update flags. */ 1129 if (mask & 0x1111) { 1130 update_flags = true; 1131 } 1132 1133 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 1134 uint64_t r = carry_in; 1135 r += n[H4(e)]; 1136 r += m[H4(e)] ^ inv; 1137 if (mask & 1) { 1138 carry_in = r >> 32; 1139 } 1140 mergemask(&d[H4(e)], r, mask); 1141 } 1142 1143 if (update_flags) { 1144 /* Store C, clear NZV. */ 1145 env->vfp.fpsr &= ~FPSR_NZCV_MASK; 1146 env->vfp.fpsr |= carry_in * FPSR_C; 1147 } 1148 mve_advance_vpt(env); 1149 } 1150 1151 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) 1152 { 1153 bool carry_in = env->vfp.fpsr & FPSR_C; 1154 do_vadc(env, vd, vn, vm, 0, carry_in, false); 1155 } 1156 1157 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) 1158 { 1159 bool carry_in = env->vfp.fpsr & FPSR_C; 1160 do_vadc(env, vd, vn, vm, -1, carry_in, false); 1161 } 1162 1163 1164 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) 1165 { 1166 do_vadc(env, vd, vn, vm, 0, 0, true); 1167 } 1168 1169 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) 1170 { 1171 do_vadc(env, vd, vn, vm, -1, 1, true); 1172 } 1173 1174 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ 1175 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ 1176 { \ 1177 TYPE *d = vd, *n = vn, *m = vm; \ 1178 uint16_t mask = mve_element_mask(env); \ 1179 unsigned e; \ 1180 TYPE r[16 / ESIZE]; \ 1181 /* Calculate all results first to avoid overwriting inputs */ \ 1182 for (e = 0; e < 16 / ESIZE; e++) { \ 1183 if (!(e & 1)) { \ 1184 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ 1185 } else { \ 1186 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ 1187 } \ 1188 } \ 1189 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1190 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 1191 } \ 1192 mve_advance_vpt(env); \ 1193 } 1194 1195 #define DO_VCADD_ALL(OP, FN0, FN1) \ 1196 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ 1197 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ 1198 DO_VCADD(OP##w, 4, int32_t, FN0, FN1) 1199 1200 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) 1201 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) 1202 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) 1203 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) 1204 1205 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) 1206 { 1207 if (val > max) { 1208 *s = true; 1209 return max; 1210 } else if (val < min) { 1211 *s = true; 1212 return min; 1213 } 1214 return val; 1215 } 1216 1217 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) 1218 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) 1219 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) 1220 1221 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) 1222 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) 1223 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) 1224 1225 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) 1226 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) 1227 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) 1228 1229 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) 1230 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) 1231 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) 1232 1233 /* 1234 * For QDMULH and QRDMULH we simplify "double and shift by esize" into 1235 * "shift by esize-1", adjusting the QRDMULH rounding constant to match. 1236 */ 1237 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ 1238 INT8_MIN, INT8_MAX, s) 1239 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ 1240 INT16_MIN, INT16_MAX, s) 1241 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ 1242 INT32_MIN, INT32_MAX, s) 1243 1244 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ 1245 INT8_MIN, INT8_MAX, s) 1246 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ 1247 INT16_MIN, INT16_MAX, s) 1248 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ 1249 INT32_MIN, INT32_MAX, s) 1250 1251 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) 1252 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) 1253 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) 1254 1255 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) 1256 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) 1257 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) 1258 1259 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) 1260 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) 1261 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) 1262 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) 1263 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) 1264 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) 1265 1266 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) 1267 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) 1268 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) 1269 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) 1270 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) 1271 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) 1272 1273 /* 1274 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() 1275 * and friends wanting a uint32_t* sat and our needing a bool*. 1276 */ 1277 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ 1278 ({ \ 1279 uint32_t su32 = 0; \ 1280 typeof(N) qrshl_ret = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ 1281 if (su32) { \ 1282 *satp = true; \ 1283 } \ 1284 qrshl_ret; \ 1285 }) 1286 1287 #define DO_SQSHL_OP(N, M, satp) \ 1288 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) 1289 #define DO_UQSHL_OP(N, M, satp) \ 1290 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) 1291 #define DO_SQRSHL_OP(N, M, satp) \ 1292 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) 1293 #define DO_UQRSHL_OP(N, M, satp) \ 1294 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) 1295 #define DO_SUQSHL_OP(N, M, satp) \ 1296 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) 1297 1298 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) 1299 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) 1300 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) 1301 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) 1302 1303 /* 1304 * Multiply add dual returning high half 1305 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of 1306 * whether to add the rounding constant, and the pointer to the 1307 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", 1308 * saturate to twice the input size and return the high half; or 1309 * (A * B - C * D) etc for VQDMLSDH. 1310 */ 1311 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ 1312 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1313 void *vm) \ 1314 { \ 1315 TYPE *d = vd, *n = vn, *m = vm; \ 1316 uint16_t mask = mve_element_mask(env); \ 1317 unsigned e; \ 1318 bool qc = false; \ 1319 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1320 bool sat = false; \ 1321 if ((e & 1) == XCHG) { \ 1322 TYPE vqdmladh_ret = FN(n[H##ESIZE(e)], \ 1323 m[H##ESIZE(e - XCHG)], \ 1324 n[H##ESIZE(e + (1 - 2 * XCHG))], \ 1325 m[H##ESIZE(e + (1 - XCHG))], \ 1326 ROUND, &sat); \ 1327 mergemask(&d[H##ESIZE(e)], vqdmladh_ret, mask); \ 1328 qc |= sat & mask & 1; \ 1329 } \ 1330 } \ 1331 if (qc) { \ 1332 env->vfp.qc[0] = qc; \ 1333 } \ 1334 mve_advance_vpt(env); \ 1335 } 1336 1337 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1338 int round, bool *sat) 1339 { 1340 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); 1341 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1342 } 1343 1344 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1345 int round, bool *sat) 1346 { 1347 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); 1348 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1349 } 1350 1351 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1352 int round, bool *sat) 1353 { 1354 int64_t m1 = (int64_t)a * b; 1355 int64_t m2 = (int64_t)c * d; 1356 int64_t r; 1357 /* 1358 * Architecturally we should do the entire add, double, round 1359 * and then check for saturation. We do three saturating adds, 1360 * but we need to be careful about the order. If the first 1361 * m1 + m2 saturates then it's impossible for the *2+rc to 1362 * bring it back into the non-saturated range. However, if 1363 * m1 + m2 is negative then it's possible that doing the doubling 1364 * would take the intermediate result below INT64_MAX and the 1365 * addition of the rounding constant then brings it back in range. 1366 * So we add half the rounding constant before doubling rather 1367 * than adding the rounding constant after the doubling. 1368 */ 1369 if (sadd64_overflow(m1, m2, &r) || 1370 sadd64_overflow(r, (round << 30), &r) || 1371 sadd64_overflow(r, r, &r)) { 1372 *sat = true; 1373 return r < 0 ? INT32_MAX : INT32_MIN; 1374 } 1375 return r >> 32; 1376 } 1377 1378 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, 1379 int round, bool *sat) 1380 { 1381 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); 1382 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1383 } 1384 1385 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, 1386 int round, bool *sat) 1387 { 1388 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); 1389 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1390 } 1391 1392 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, 1393 int round, bool *sat) 1394 { 1395 int64_t m1 = (int64_t)a * b; 1396 int64_t m2 = (int64_t)c * d; 1397 int64_t r; 1398 /* The same ordering issue as in do_vqdmladh_w applies here too */ 1399 if (ssub64_overflow(m1, m2, &r) || 1400 sadd64_overflow(r, (round << 30), &r) || 1401 sadd64_overflow(r, r, &r)) { 1402 *sat = true; 1403 return r < 0 ? INT32_MAX : INT32_MIN; 1404 } 1405 return r >> 32; 1406 } 1407 1408 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) 1409 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) 1410 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) 1411 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) 1412 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) 1413 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) 1414 1415 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) 1416 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) 1417 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) 1418 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) 1419 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) 1420 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) 1421 1422 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) 1423 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) 1424 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) 1425 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) 1426 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) 1427 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) 1428 1429 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) 1430 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) 1431 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) 1432 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) 1433 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) 1434 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) 1435 1436 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ 1437 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1438 uint32_t rm) \ 1439 { \ 1440 TYPE *d = vd, *n = vn; \ 1441 TYPE m = rm; \ 1442 uint16_t mask = mve_element_mask(env); \ 1443 unsigned e; \ 1444 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1445 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ 1446 } \ 1447 mve_advance_vpt(env); \ 1448 } 1449 1450 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ 1451 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1452 uint32_t rm) \ 1453 { \ 1454 TYPE *d = vd, *n = vn; \ 1455 TYPE m = rm; \ 1456 uint16_t mask = mve_element_mask(env); \ 1457 unsigned e; \ 1458 bool qc = false; \ 1459 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1460 bool sat = false; \ 1461 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ 1462 mask); \ 1463 qc |= sat & mask & 1; \ 1464 } \ 1465 if (qc) { \ 1466 env->vfp.qc[0] = qc; \ 1467 } \ 1468 mve_advance_vpt(env); \ 1469 } 1470 1471 /* "accumulating" version where FN takes d as well as n and m */ 1472 #define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1473 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1474 uint32_t rm) \ 1475 { \ 1476 TYPE *d = vd, *n = vn; \ 1477 TYPE m = rm; \ 1478 uint16_t mask = mve_element_mask(env); \ 1479 unsigned e; \ 1480 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1481 mergemask(&d[H##ESIZE(e)], \ 1482 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \ 1483 } \ 1484 mve_advance_vpt(env); \ 1485 } 1486 1487 #define DO_2OP_SAT_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 1488 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1489 uint32_t rm) \ 1490 { \ 1491 TYPE *d = vd, *n = vn; \ 1492 TYPE m = rm; \ 1493 uint16_t mask = mve_element_mask(env); \ 1494 unsigned e; \ 1495 bool qc = false; \ 1496 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1497 bool sat = false; \ 1498 mergemask(&d[H##ESIZE(e)], \ 1499 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m, &sat), \ 1500 mask); \ 1501 qc |= sat & mask & 1; \ 1502 } \ 1503 if (qc) { \ 1504 env->vfp.qc[0] = qc; \ 1505 } \ 1506 mve_advance_vpt(env); \ 1507 } 1508 1509 /* provide unsigned 2-op scalar helpers for all sizes */ 1510 #define DO_2OP_SCALAR_U(OP, FN) \ 1511 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ 1512 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ 1513 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) 1514 #define DO_2OP_SCALAR_S(OP, FN) \ 1515 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ 1516 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ 1517 DO_2OP_SCALAR(OP##w, 4, int32_t, FN) 1518 1519 #define DO_2OP_ACC_SCALAR_U(OP, FN) \ 1520 DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \ 1521 DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \ 1522 DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN) 1523 1524 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) 1525 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) 1526 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) 1527 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) 1528 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) 1529 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) 1530 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) 1531 1532 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) 1533 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) 1534 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) 1535 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) 1536 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) 1537 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) 1538 1539 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) 1540 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) 1541 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) 1542 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) 1543 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) 1544 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) 1545 1546 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) 1547 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) 1548 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) 1549 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) 1550 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) 1551 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) 1552 1553 static int8_t do_vqdmlah_b(int8_t a, int8_t b, int8_t c, int round, bool *sat) 1554 { 1555 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 8) + (round << 7); 1556 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; 1557 } 1558 1559 static int16_t do_vqdmlah_h(int16_t a, int16_t b, int16_t c, 1560 int round, bool *sat) 1561 { 1562 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 16) + (round << 15); 1563 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; 1564 } 1565 1566 static int32_t do_vqdmlah_w(int32_t a, int32_t b, int32_t c, 1567 int round, bool *sat) 1568 { 1569 /* 1570 * Architecturally we should do the entire add, double, round 1571 * and then check for saturation. We do three saturating adds, 1572 * but we need to be careful about the order. If the first 1573 * m1 + m2 saturates then it's impossible for the *2+rc to 1574 * bring it back into the non-saturated range. However, if 1575 * m1 + m2 is negative then it's possible that doing the doubling 1576 * would take the intermediate result below INT64_MAX and the 1577 * addition of the rounding constant then brings it back in range. 1578 * So we add half the rounding constant and half the "c << esize" 1579 * before doubling rather than adding the rounding constant after 1580 * the doubling. 1581 */ 1582 int64_t m1 = (int64_t)a * b; 1583 int64_t m2 = (int64_t)c << 31; 1584 int64_t r; 1585 if (sadd64_overflow(m1, m2, &r) || 1586 sadd64_overflow(r, (round << 30), &r) || 1587 sadd64_overflow(r, r, &r)) { 1588 *sat = true; 1589 return r < 0 ? INT32_MAX : INT32_MIN; 1590 } 1591 return r >> 32; 1592 } 1593 1594 /* 1595 * The *MLAH insns are vector * scalar + vector; 1596 * the *MLASH insns are vector * vector + scalar 1597 */ 1598 #define DO_VQDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 0, S) 1599 #define DO_VQDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 0, S) 1600 #define DO_VQDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 0, S) 1601 #define DO_VQRDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 1, S) 1602 #define DO_VQRDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 1, S) 1603 #define DO_VQRDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 1, S) 1604 1605 #define DO_VQDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 0, S) 1606 #define DO_VQDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 0, S) 1607 #define DO_VQDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 0, S) 1608 #define DO_VQRDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 1, S) 1609 #define DO_VQRDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 1, S) 1610 #define DO_VQRDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 1, S) 1611 1612 DO_2OP_SAT_ACC_SCALAR(vqdmlahb, 1, int8_t, DO_VQDMLAH_B) 1613 DO_2OP_SAT_ACC_SCALAR(vqdmlahh, 2, int16_t, DO_VQDMLAH_H) 1614 DO_2OP_SAT_ACC_SCALAR(vqdmlahw, 4, int32_t, DO_VQDMLAH_W) 1615 DO_2OP_SAT_ACC_SCALAR(vqrdmlahb, 1, int8_t, DO_VQRDMLAH_B) 1616 DO_2OP_SAT_ACC_SCALAR(vqrdmlahh, 2, int16_t, DO_VQRDMLAH_H) 1617 DO_2OP_SAT_ACC_SCALAR(vqrdmlahw, 4, int32_t, DO_VQRDMLAH_W) 1618 1619 DO_2OP_SAT_ACC_SCALAR(vqdmlashb, 1, int8_t, DO_VQDMLASH_B) 1620 DO_2OP_SAT_ACC_SCALAR(vqdmlashh, 2, int16_t, DO_VQDMLASH_H) 1621 DO_2OP_SAT_ACC_SCALAR(vqdmlashw, 4, int32_t, DO_VQDMLASH_W) 1622 DO_2OP_SAT_ACC_SCALAR(vqrdmlashb, 1, int8_t, DO_VQRDMLASH_B) 1623 DO_2OP_SAT_ACC_SCALAR(vqrdmlashh, 2, int16_t, DO_VQRDMLASH_H) 1624 DO_2OP_SAT_ACC_SCALAR(vqrdmlashw, 4, int32_t, DO_VQRDMLASH_W) 1625 1626 /* Vector by scalar plus vector */ 1627 #define DO_VMLA(D, N, M) ((N) * (M) + (D)) 1628 1629 DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA) 1630 1631 /* Vector by vector plus scalar */ 1632 #define DO_VMLAS(D, N, M) ((N) * (D) + (M)) 1633 1634 DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS) 1635 1636 /* 1637 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the 1638 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. 1639 * SATMASK specifies which bits of the predicate mask matter for determining 1640 * whether to propagate a saturation indication into FPSCR.QC -- for 1641 * the 16x16->32 case we must check only the bit corresponding to the T or B 1642 * half that we used, but for the 32x32->64 case we propagate if the mask 1643 * bit is set for either half. 1644 */ 1645 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1646 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1647 uint32_t rm) \ 1648 { \ 1649 LTYPE *d = vd; \ 1650 TYPE *n = vn; \ 1651 TYPE m = rm; \ 1652 uint16_t mask = mve_element_mask(env); \ 1653 unsigned le; \ 1654 bool qc = false; \ 1655 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1656 bool sat = false; \ 1657 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ 1658 mergemask(&d[H##LESIZE(le)], r, mask); \ 1659 qc |= sat && (mask & SATMASK); \ 1660 } \ 1661 if (qc) { \ 1662 env->vfp.qc[0] = qc; \ 1663 } \ 1664 mve_advance_vpt(env); \ 1665 } 1666 1667 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) 1668 { 1669 int64_t r = ((int64_t)n * m) * 2; 1670 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); 1671 } 1672 1673 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) 1674 { 1675 /* The multiply can't overflow, but the doubling might */ 1676 int64_t r = (int64_t)n * m; 1677 if (r > INT64_MAX / 2) { 1678 *sat = true; 1679 return INT64_MAX; 1680 } else if (r < INT64_MIN / 2) { 1681 *sat = true; 1682 return INT64_MIN; 1683 } else { 1684 return r * 2; 1685 } 1686 } 1687 1688 #define SATMASK16B 1 1689 #define SATMASK16T (1 << 2) 1690 #define SATMASK32 ((1 << 4) | 1) 1691 1692 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ 1693 do_qdmullh, SATMASK16B) 1694 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ 1695 do_qdmullw, SATMASK32) 1696 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ 1697 do_qdmullh, SATMASK16T) 1698 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ 1699 do_qdmullw, SATMASK32) 1700 1701 /* 1702 * Long saturating ops 1703 */ 1704 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ 1705 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ 1706 void *vm) \ 1707 { \ 1708 LTYPE *d = vd; \ 1709 TYPE *n = vn, *m = vm; \ 1710 uint16_t mask = mve_element_mask(env); \ 1711 unsigned le; \ 1712 bool qc = false; \ 1713 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 1714 bool sat = false; \ 1715 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ 1716 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ 1717 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ 1718 qc |= sat && (mask & SATMASK); \ 1719 } \ 1720 if (qc) { \ 1721 env->vfp.qc[0] = qc; \ 1722 } \ 1723 mve_advance_vpt(env); \ 1724 } 1725 1726 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) 1727 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1728 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) 1729 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) 1730 1731 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) 1732 { 1733 m &= 0xff; 1734 if (m == 0) { 1735 return 0; 1736 } 1737 n = revbit8(n); 1738 if (m < 8) { 1739 n >>= 8 - m; 1740 } 1741 return n; 1742 } 1743 1744 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) 1745 { 1746 m &= 0xff; 1747 if (m == 0) { 1748 return 0; 1749 } 1750 n = revbit16(n); 1751 if (m < 16) { 1752 n >>= 16 - m; 1753 } 1754 return n; 1755 } 1756 1757 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) 1758 { 1759 m &= 0xff; 1760 if (m == 0) { 1761 return 0; 1762 } 1763 n = revbit32(n); 1764 if (m < 32) { 1765 n >>= 32 - m; 1766 } 1767 return n; 1768 } 1769 1770 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) 1771 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) 1772 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) 1773 1774 /* 1775 * Multiply add long dual accumulate ops. 1776 */ 1777 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1778 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1779 void *vm, uint64_t a) \ 1780 { \ 1781 uint16_t mask = mve_element_mask(env); \ 1782 unsigned e; \ 1783 TYPE *n = vn, *m = vm; \ 1784 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1785 if (mask & 1) { \ 1786 if (e & 1) { \ 1787 a ODDACC \ 1788 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1789 } else { \ 1790 a EVENACC \ 1791 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1792 } \ 1793 } \ 1794 } \ 1795 mve_advance_vpt(env); \ 1796 return a; \ 1797 } 1798 1799 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) 1800 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) 1801 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) 1802 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) 1803 1804 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) 1805 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) 1806 1807 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) 1808 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) 1809 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) 1810 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) 1811 1812 /* 1813 * Multiply add dual accumulate ops 1814 */ 1815 #define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ 1816 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1817 void *vm, uint32_t a) \ 1818 { \ 1819 uint16_t mask = mve_element_mask(env); \ 1820 unsigned e; \ 1821 TYPE *n = vn, *m = vm; \ 1822 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1823 if (mask & 1) { \ 1824 if (e & 1) { \ 1825 a ODDACC \ 1826 n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ 1827 } else { \ 1828 a EVENACC \ 1829 n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ 1830 } \ 1831 } \ 1832 } \ 1833 mve_advance_vpt(env); \ 1834 return a; \ 1835 } 1836 1837 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ 1838 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \ 1839 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \ 1840 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC) 1841 1842 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ 1843 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \ 1844 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \ 1845 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC) 1846 1847 DO_DAV_S(vmladavs, false, +=, +=) 1848 DO_DAV_U(vmladavu, false, +=, +=) 1849 DO_DAV_S(vmlsdav, false, +=, -=) 1850 DO_DAV_S(vmladavsx, true, +=, +=) 1851 DO_DAV_S(vmlsdavx, true, +=, -=) 1852 1853 /* 1854 * Rounding multiply add long dual accumulate high. In the pseudocode 1855 * this is implemented with a 72-bit internal accumulator value of which 1856 * the top 64 bits are returned. We optimize this to avoid having to 1857 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator 1858 * is squashed back into 64-bits after each beat. 1859 */ 1860 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ 1861 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1862 void *vm, uint64_t a) \ 1863 { \ 1864 uint16_t mask = mve_element_mask(env); \ 1865 unsigned e; \ 1866 TYPE *n = vn, *m = vm; \ 1867 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 1868 if (mask & 1) { \ 1869 LTYPE mul; \ 1870 if (e & 1) { \ 1871 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ 1872 if (SUB) { \ 1873 mul = -mul; \ 1874 } \ 1875 } else { \ 1876 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ 1877 } \ 1878 mul = (mul >> 8) + ((mul >> 7) & 1); \ 1879 a += mul; \ 1880 } \ 1881 } \ 1882 mve_advance_vpt(env); \ 1883 return a; \ 1884 } 1885 1886 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) 1887 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) 1888 1889 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) 1890 1891 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) 1892 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) 1893 1894 /* Vector add across vector */ 1895 #define DO_VADDV(OP, ESIZE, TYPE) \ 1896 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1897 uint32_t ra) \ 1898 { \ 1899 uint16_t mask = mve_element_mask(env); \ 1900 unsigned e; \ 1901 TYPE *m = vm; \ 1902 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1903 if (mask & 1) { \ 1904 ra += m[H##ESIZE(e)]; \ 1905 } \ 1906 } \ 1907 mve_advance_vpt(env); \ 1908 return ra; \ 1909 } \ 1910 1911 DO_VADDV(vaddvsb, 1, int8_t) 1912 DO_VADDV(vaddvsh, 2, int16_t) 1913 DO_VADDV(vaddvsw, 4, int32_t) 1914 DO_VADDV(vaddvub, 1, uint8_t) 1915 DO_VADDV(vaddvuh, 2, uint16_t) 1916 DO_VADDV(vaddvuw, 4, uint32_t) 1917 1918 /* 1919 * Vector max/min across vector. Unlike VADDV, we must 1920 * read ra as the element size, not its full width. 1921 * We work with int64_t internally for simplicity. 1922 */ 1923 #define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \ 1924 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 1925 uint32_t ra_in) \ 1926 { \ 1927 uint16_t mask = mve_element_mask(env); \ 1928 unsigned e; \ 1929 TYPE *m = vm; \ 1930 int64_t ra = (RATYPE)ra_in; \ 1931 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1932 if (mask & 1) { \ 1933 ra = FN(ra, m[H##ESIZE(e)]); \ 1934 } \ 1935 } \ 1936 mve_advance_vpt(env); \ 1937 return ra; \ 1938 } \ 1939 1940 #define DO_VMAXMINV_U(INSN, FN) \ 1941 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \ 1942 DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \ 1943 DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN) 1944 #define DO_VMAXMINV_S(INSN, FN) \ 1945 DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \ 1946 DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \ 1947 DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN) 1948 1949 /* 1950 * Helpers for max and min of absolute values across vector: 1951 * note that we only take the absolute value of 'm', not 'n' 1952 */ 1953 static int64_t do_maxa(int64_t n, int64_t m) 1954 { 1955 if (m < 0) { 1956 m = -m; 1957 } 1958 return MAX(n, m); 1959 } 1960 1961 static int64_t do_mina(int64_t n, int64_t m) 1962 { 1963 if (m < 0) { 1964 m = -m; 1965 } 1966 return MIN(n, m); 1967 } 1968 1969 DO_VMAXMINV_S(vmaxvs, DO_MAX) 1970 DO_VMAXMINV_U(vmaxvu, DO_MAX) 1971 DO_VMAXMINV_S(vminvs, DO_MIN) 1972 DO_VMAXMINV_U(vminvu, DO_MIN) 1973 /* 1974 * VMAXAV, VMINAV treat the general purpose input as unsigned 1975 * and the vector elements as signed. 1976 */ 1977 DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa) 1978 DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa) 1979 DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa) 1980 DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina) 1981 DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina) 1982 DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina) 1983 1984 #define DO_VABAV(OP, ESIZE, TYPE) \ 1985 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 1986 void *vm, uint32_t ra) \ 1987 { \ 1988 uint16_t mask = mve_element_mask(env); \ 1989 unsigned e; \ 1990 TYPE *m = vm, *n = vn; \ 1991 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 1992 if (mask & 1) { \ 1993 int64_t n0 = n[H##ESIZE(e)]; \ 1994 int64_t m0 = m[H##ESIZE(e)]; \ 1995 uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \ 1996 ra += r; \ 1997 } \ 1998 } \ 1999 mve_advance_vpt(env); \ 2000 return ra; \ 2001 } 2002 2003 DO_VABAV(vabavsb, 1, int8_t) 2004 DO_VABAV(vabavsh, 2, int16_t) 2005 DO_VABAV(vabavsw, 4, int32_t) 2006 DO_VABAV(vabavub, 1, uint8_t) 2007 DO_VABAV(vabavuh, 2, uint16_t) 2008 DO_VABAV(vabavuw, 4, uint32_t) 2009 2010 #define DO_VADDLV(OP, TYPE, LTYPE) \ 2011 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 2012 uint64_t ra) \ 2013 { \ 2014 uint16_t mask = mve_element_mask(env); \ 2015 unsigned e; \ 2016 TYPE *m = vm; \ 2017 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ 2018 if (mask & 1) { \ 2019 ra += (LTYPE)m[H4(e)]; \ 2020 } \ 2021 } \ 2022 mve_advance_vpt(env); \ 2023 return ra; \ 2024 } \ 2025 2026 DO_VADDLV(vaddlv_s, int32_t, int64_t) 2027 DO_VADDLV(vaddlv_u, uint32_t, uint64_t) 2028 2029 /* Shifts by immediate */ 2030 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ 2031 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2032 void *vm, uint32_t shift) \ 2033 { \ 2034 TYPE *d = vd, *m = vm; \ 2035 uint16_t mask = mve_element_mask(env); \ 2036 unsigned e; \ 2037 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2038 mergemask(&d[H##ESIZE(e)], \ 2039 FN(m[H##ESIZE(e)], shift), mask); \ 2040 } \ 2041 mve_advance_vpt(env); \ 2042 } 2043 2044 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ 2045 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2046 void *vm, uint32_t shift) \ 2047 { \ 2048 TYPE *d = vd, *m = vm; \ 2049 uint16_t mask = mve_element_mask(env); \ 2050 unsigned e; \ 2051 bool qc = false; \ 2052 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2053 bool sat = false; \ 2054 mergemask(&d[H##ESIZE(e)], \ 2055 FN(m[H##ESIZE(e)], shift, &sat), mask); \ 2056 qc |= sat & mask & 1; \ 2057 } \ 2058 if (qc) { \ 2059 env->vfp.qc[0] = qc; \ 2060 } \ 2061 mve_advance_vpt(env); \ 2062 } 2063 2064 /* provide unsigned 2-op shift helpers for all sizes */ 2065 #define DO_2SHIFT_U(OP, FN) \ 2066 DO_2SHIFT(OP##b, 1, uint8_t, FN) \ 2067 DO_2SHIFT(OP##h, 2, uint16_t, FN) \ 2068 DO_2SHIFT(OP##w, 4, uint32_t, FN) 2069 #define DO_2SHIFT_S(OP, FN) \ 2070 DO_2SHIFT(OP##b, 1, int8_t, FN) \ 2071 DO_2SHIFT(OP##h, 2, int16_t, FN) \ 2072 DO_2SHIFT(OP##w, 4, int32_t, FN) 2073 2074 #define DO_2SHIFT_SAT_U(OP, FN) \ 2075 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ 2076 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ 2077 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) 2078 #define DO_2SHIFT_SAT_S(OP, FN) \ 2079 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ 2080 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ 2081 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) 2082 2083 DO_2SHIFT_U(vshli_u, DO_VSHLU) 2084 DO_2SHIFT_S(vshli_s, DO_VSHLS) 2085 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) 2086 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) 2087 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) 2088 DO_2SHIFT_U(vrshli_u, DO_VRSHLU) 2089 DO_2SHIFT_S(vrshli_s, DO_VRSHLS) 2090 DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP) 2091 DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP) 2092 2093 /* Shift-and-insert; we always work with 64 bits at a time */ 2094 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ 2095 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2096 void *vm, uint32_t shift) \ 2097 { \ 2098 uint64_t *d = vd, *m = vm; \ 2099 uint16_t mask; \ 2100 uint64_t shiftmask; \ 2101 unsigned e; \ 2102 if (shift == ESIZE * 8) { \ 2103 /* \ 2104 * Only VSRI can shift by <dt>; it should mean "don't \ 2105 * update the destination". The generic logic can't handle \ 2106 * this because it would try to shift by an out-of-range \ 2107 * amount, so special case it here. \ 2108 */ \ 2109 goto done; \ 2110 } \ 2111 assert(shift < ESIZE * 8); \ 2112 mask = mve_element_mask(env); \ 2113 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ 2114 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ 2115 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ 2116 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ 2117 (d[H8(e)] & ~shiftmask); \ 2118 mergemask(&d[H8(e)], r, mask); \ 2119 } \ 2120 done: \ 2121 mve_advance_vpt(env); \ 2122 } 2123 2124 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) 2125 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) 2126 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) 2127 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) 2128 2129 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) 2130 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) 2131 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) 2132 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) 2133 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) 2134 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) 2135 2136 /* 2137 * Long shifts taking half-sized inputs from top or bottom of the input 2138 * vector and producing a double-width result. ESIZE, TYPE are for 2139 * the input, and LESIZE, LTYPE for the output. 2140 * Unlike the normal shift helpers, we do not handle negative shift counts, 2141 * because the long shift is strictly left-only. 2142 */ 2143 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2144 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2145 void *vm, uint32_t shift) \ 2146 { \ 2147 LTYPE *d = vd; \ 2148 TYPE *m = vm; \ 2149 uint16_t mask = mve_element_mask(env); \ 2150 unsigned le; \ 2151 assert(shift <= 16); \ 2152 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2153 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ 2154 mergemask(&d[H##LESIZE(le)], r, mask); \ 2155 } \ 2156 mve_advance_vpt(env); \ 2157 } 2158 2159 #define DO_VSHLL_ALL(OP, TOP) \ 2160 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ 2161 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ 2162 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ 2163 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ 2164 2165 DO_VSHLL_ALL(vshllb, false) 2166 DO_VSHLL_ALL(vshllt, true) 2167 2168 /* 2169 * Narrowing right shifts, taking a double sized input, shifting it 2170 * and putting the result in either the top or bottom half of the output. 2171 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. 2172 */ 2173 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2174 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2175 void *vm, uint32_t shift) \ 2176 { \ 2177 LTYPE *m = vm; \ 2178 TYPE *d = vd; \ 2179 uint16_t mask = mve_element_mask(env); \ 2180 unsigned le; \ 2181 mask >>= ESIZE * TOP; \ 2182 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2183 TYPE r = FN(m[H##LESIZE(le)], shift); \ 2184 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2185 } \ 2186 mve_advance_vpt(env); \ 2187 } 2188 2189 #define DO_VSHRN_ALL(OP, FN) \ 2190 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ 2191 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ 2192 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ 2193 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) 2194 2195 static inline uint64_t do_urshr(uint64_t x, unsigned sh) 2196 { 2197 if (likely(sh < 64)) { 2198 return (x >> sh) + ((x >> (sh - 1)) & 1); 2199 } else if (sh == 64) { 2200 return x >> 63; 2201 } else { 2202 return 0; 2203 } 2204 } 2205 2206 static inline int64_t do_srshr(int64_t x, unsigned sh) 2207 { 2208 if (likely(sh < 64)) { 2209 return (x >> sh) + ((x >> (sh - 1)) & 1); 2210 } else { 2211 /* Rounding the sign bit always produces 0. */ 2212 return 0; 2213 } 2214 } 2215 2216 DO_VSHRN_ALL(vshrn, DO_SHR) 2217 DO_VSHRN_ALL(vrshrn, do_urshr) 2218 2219 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, 2220 bool *satp) 2221 { 2222 if (val > max) { 2223 *satp = true; 2224 return max; 2225 } else if (val < min) { 2226 *satp = true; 2227 return min; 2228 } else { 2229 return val; 2230 } 2231 } 2232 2233 /* Saturating narrowing right shifts */ 2234 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2235 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ 2236 void *vm, uint32_t shift) \ 2237 { \ 2238 LTYPE *m = vm; \ 2239 TYPE *d = vd; \ 2240 uint16_t mask = mve_element_mask(env); \ 2241 bool qc = false; \ 2242 unsigned le; \ 2243 mask >>= ESIZE * TOP; \ 2244 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2245 bool sat = false; \ 2246 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ 2247 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2248 qc |= sat & mask & 1; \ 2249 } \ 2250 if (qc) { \ 2251 env->vfp.qc[0] = qc; \ 2252 } \ 2253 mve_advance_vpt(env); \ 2254 } 2255 2256 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ 2257 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2258 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2259 2260 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ 2261 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2262 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2263 2264 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ 2265 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2266 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2267 2268 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ 2269 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2270 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2271 2272 #define DO_SHRN_SB(N, M, SATP) \ 2273 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) 2274 #define DO_SHRN_UB(N, M, SATP) \ 2275 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2276 #define DO_SHRUN_B(N, M, SATP) \ 2277 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) 2278 2279 #define DO_SHRN_SH(N, M, SATP) \ 2280 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) 2281 #define DO_SHRN_UH(N, M, SATP) \ 2282 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2283 #define DO_SHRUN_H(N, M, SATP) \ 2284 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) 2285 2286 #define DO_RSHRN_SB(N, M, SATP) \ 2287 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) 2288 #define DO_RSHRN_UB(N, M, SATP) \ 2289 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) 2290 #define DO_RSHRUN_B(N, M, SATP) \ 2291 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) 2292 2293 #define DO_RSHRN_SH(N, M, SATP) \ 2294 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) 2295 #define DO_RSHRN_UH(N, M, SATP) \ 2296 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) 2297 #define DO_RSHRUN_H(N, M, SATP) \ 2298 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) 2299 2300 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) 2301 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) 2302 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) 2303 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) 2304 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) 2305 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) 2306 2307 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) 2308 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) 2309 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) 2310 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) 2311 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) 2312 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) 2313 2314 #define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ 2315 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2316 { \ 2317 LTYPE *m = vm; \ 2318 TYPE *d = vd; \ 2319 uint16_t mask = mve_element_mask(env); \ 2320 unsigned le; \ 2321 mask >>= ESIZE * TOP; \ 2322 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2323 mergemask(&d[H##ESIZE(le * 2 + TOP)], \ 2324 m[H##LESIZE(le)], mask); \ 2325 } \ 2326 mve_advance_vpt(env); \ 2327 } 2328 2329 DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t) 2330 DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t) 2331 DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t) 2332 DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t) 2333 2334 #define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ 2335 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2336 { \ 2337 LTYPE *m = vm; \ 2338 TYPE *d = vd; \ 2339 uint16_t mask = mve_element_mask(env); \ 2340 bool qc = false; \ 2341 unsigned le; \ 2342 mask >>= ESIZE * TOP; \ 2343 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ 2344 bool sat = false; \ 2345 TYPE r = FN(m[H##LESIZE(le)], &sat); \ 2346 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ 2347 qc |= sat & mask & 1; \ 2348 } \ 2349 if (qc) { \ 2350 env->vfp.qc[0] = qc; \ 2351 } \ 2352 mve_advance_vpt(env); \ 2353 } 2354 2355 #define DO_VMOVN_SAT_UB(BOP, TOP, FN) \ 2356 DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ 2357 DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) 2358 2359 #define DO_VMOVN_SAT_UH(BOP, TOP, FN) \ 2360 DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ 2361 DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) 2362 2363 #define DO_VMOVN_SAT_SB(BOP, TOP, FN) \ 2364 DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ 2365 DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) 2366 2367 #define DO_VMOVN_SAT_SH(BOP, TOP, FN) \ 2368 DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ 2369 DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) 2370 2371 #define DO_VQMOVN_SB(N, SATP) \ 2372 do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP) 2373 #define DO_VQMOVN_UB(N, SATP) \ 2374 do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP) 2375 #define DO_VQMOVUN_B(N, SATP) \ 2376 do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP) 2377 2378 #define DO_VQMOVN_SH(N, SATP) \ 2379 do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP) 2380 #define DO_VQMOVN_UH(N, SATP) \ 2381 do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP) 2382 #define DO_VQMOVUN_H(N, SATP) \ 2383 do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP) 2384 2385 DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB) 2386 DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH) 2387 DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB) 2388 DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH) 2389 DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B) 2390 DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H) 2391 2392 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, 2393 uint32_t shift) 2394 { 2395 uint32_t *d = vd; 2396 uint16_t mask = mve_element_mask(env); 2397 unsigned e; 2398 uint32_t r; 2399 2400 /* 2401 * For each 32-bit element, we shift it left, bringing in the 2402 * low 'shift' bits of rdm at the bottom. Bits shifted out at 2403 * the top become the new rdm, if the predicate mask permits. 2404 * The final rdm value is returned to update the register. 2405 * shift == 0 here means "shift by 32 bits". 2406 */ 2407 if (shift == 0) { 2408 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2409 r = rdm; 2410 if (mask & 1) { 2411 rdm = d[H4(e)]; 2412 } 2413 mergemask(&d[H4(e)], r, mask); 2414 } 2415 } else { 2416 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); 2417 2418 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 2419 r = (d[H4(e)] << shift) | (rdm & shiftmask); 2420 if (mask & 1) { 2421 rdm = d[H4(e)] >> (32 - shift); 2422 } 2423 mergemask(&d[H4(e)], r, mask); 2424 } 2425 } 2426 mve_advance_vpt(env); 2427 return rdm; 2428 } 2429 2430 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2431 { 2432 return do_sqrshl_d(n, -(int8_t)shift, false, NULL); 2433 } 2434 2435 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) 2436 { 2437 return do_uqrshl_d(n, (int8_t)shift, false, NULL); 2438 } 2439 2440 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2441 { 2442 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); 2443 } 2444 2445 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2446 { 2447 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); 2448 } 2449 2450 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) 2451 { 2452 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); 2453 } 2454 2455 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) 2456 { 2457 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); 2458 } 2459 2460 /* Operate on 64-bit values, but saturate at 48 bits */ 2461 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, 2462 bool round, uint32_t *sat) 2463 { 2464 int64_t val, extval; 2465 2466 if (shift <= -48) { 2467 /* Rounding the sign bit always produces 0. */ 2468 if (round) { 2469 return 0; 2470 } 2471 return src >> 63; 2472 } else if (shift < 0) { 2473 if (round) { 2474 src >>= -shift - 1; 2475 val = (src >> 1) + (src & 1); 2476 } else { 2477 val = src >> -shift; 2478 } 2479 extval = sextract64(val, 0, 48); 2480 if (!sat || val == extval) { 2481 return extval; 2482 } 2483 } else if (shift < 48) { 2484 extval = sextract64(src << shift, 0, 48); 2485 if (!sat || src == (extval >> shift)) { 2486 return extval; 2487 } 2488 } else if (!sat || src == 0) { 2489 return 0; 2490 } 2491 2492 *sat = 1; 2493 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); 2494 } 2495 2496 /* Operate on 64-bit values, but saturate at 48 bits */ 2497 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, 2498 bool round, uint32_t *sat) 2499 { 2500 uint64_t val, extval; 2501 2502 if (shift <= -(48 + round)) { 2503 return 0; 2504 } else if (shift < 0) { 2505 if (round) { 2506 val = src >> (-shift - 1); 2507 val = (val >> 1) + (val & 1); 2508 } else { 2509 val = src >> -shift; 2510 } 2511 extval = extract64(val, 0, 48); 2512 if (!sat || val == extval) { 2513 return extval; 2514 } 2515 } else if (shift < 48) { 2516 extval = extract64(src << shift, 0, 48); 2517 if (!sat || src == (extval >> shift)) { 2518 return extval; 2519 } 2520 } else if (!sat || src == 0) { 2521 return 0; 2522 } 2523 2524 *sat = 1; 2525 return MAKE_64BIT_MASK(0, 48); 2526 } 2527 2528 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) 2529 { 2530 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); 2531 } 2532 2533 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) 2534 { 2535 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); 2536 } 2537 2538 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2539 { 2540 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2541 } 2542 2543 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2544 { 2545 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); 2546 } 2547 2548 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) 2549 { 2550 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); 2551 } 2552 2553 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) 2554 { 2555 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); 2556 } 2557 2558 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \ 2559 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2560 uint32_t offset, uint32_t imm) \ 2561 { \ 2562 TYPE *d = vd; \ 2563 uint16_t mask = mve_element_mask(env); \ 2564 unsigned e; \ 2565 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2566 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2567 offset = FN(offset, imm); \ 2568 } \ 2569 mve_advance_vpt(env); \ 2570 return offset; \ 2571 } 2572 2573 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \ 2574 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \ 2575 uint32_t offset, uint32_t wrap, \ 2576 uint32_t imm) \ 2577 { \ 2578 TYPE *d = vd; \ 2579 uint16_t mask = mve_element_mask(env); \ 2580 unsigned e; \ 2581 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2582 mergemask(&d[H##ESIZE(e)], offset, mask); \ 2583 offset = FN(offset, wrap, imm); \ 2584 } \ 2585 mve_advance_vpt(env); \ 2586 return offset; \ 2587 } 2588 2589 #define DO_VIDUP_ALL(OP, FN) \ 2590 DO_VIDUP(OP##b, 1, int8_t, FN) \ 2591 DO_VIDUP(OP##h, 2, int16_t, FN) \ 2592 DO_VIDUP(OP##w, 4, int32_t, FN) 2593 2594 #define DO_VIWDUP_ALL(OP, FN) \ 2595 DO_VIWDUP(OP##b, 1, int8_t, FN) \ 2596 DO_VIWDUP(OP##h, 2, int16_t, FN) \ 2597 DO_VIWDUP(OP##w, 4, int32_t, FN) 2598 2599 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2600 { 2601 offset += imm; 2602 if (offset == wrap) { 2603 offset = 0; 2604 } 2605 return offset; 2606 } 2607 2608 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm) 2609 { 2610 if (offset == 0) { 2611 offset = wrap; 2612 } 2613 offset -= imm; 2614 return offset; 2615 } 2616 2617 DO_VIDUP_ALL(vidup, DO_ADD) 2618 DO_VIWDUP_ALL(viwdup, do_add_wrap) 2619 DO_VIWDUP_ALL(vdwdup, do_sub_wrap) 2620 2621 /* 2622 * Vector comparison. 2623 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged. 2624 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0. 2625 * P0 bits otherwise are updated with the results of the comparisons. 2626 * We must also keep unchanged the MASK fields at the top of v7m.vpr. 2627 */ 2628 #define DO_VCMP(OP, ESIZE, TYPE, FN) \ 2629 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 2630 { \ 2631 TYPE *n = vn, *m = vm; \ 2632 uint16_t mask = mve_element_mask(env); \ 2633 uint16_t eci_mask = mve_eci_mask(env); \ 2634 uint16_t beatpred = 0; \ 2635 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2636 unsigned e; \ 2637 for (e = 0; e < 16 / ESIZE; e++) { \ 2638 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \ 2639 /* Comparison sets 0/1 bits for each byte in the element */ \ 2640 beatpred |= r * emask; \ 2641 emask <<= ESIZE; \ 2642 } \ 2643 beatpred &= mask; \ 2644 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2645 (beatpred & eci_mask); \ 2646 mve_advance_vpt(env); \ 2647 } 2648 2649 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \ 2650 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 2651 uint32_t rm) \ 2652 { \ 2653 TYPE *n = vn; \ 2654 uint16_t mask = mve_element_mask(env); \ 2655 uint16_t eci_mask = mve_eci_mask(env); \ 2656 uint16_t beatpred = 0; \ 2657 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 2658 unsigned e; \ 2659 for (e = 0; e < 16 / ESIZE; e++) { \ 2660 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \ 2661 /* Comparison sets 0/1 bits for each byte in the element */ \ 2662 beatpred |= r * emask; \ 2663 emask <<= ESIZE; \ 2664 } \ 2665 beatpred &= mask; \ 2666 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 2667 (beatpred & eci_mask); \ 2668 mve_advance_vpt(env); \ 2669 } 2670 2671 #define DO_VCMP_S(OP, FN) \ 2672 DO_VCMP(OP##b, 1, int8_t, FN) \ 2673 DO_VCMP(OP##h, 2, int16_t, FN) \ 2674 DO_VCMP(OP##w, 4, int32_t, FN) \ 2675 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \ 2676 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \ 2677 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN) 2678 2679 #define DO_VCMP_U(OP, FN) \ 2680 DO_VCMP(OP##b, 1, uint8_t, FN) \ 2681 DO_VCMP(OP##h, 2, uint16_t, FN) \ 2682 DO_VCMP(OP##w, 4, uint32_t, FN) \ 2683 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \ 2684 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \ 2685 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN) 2686 2687 #define DO_EQ(N, M) ((N) == (M)) 2688 #define DO_NE(N, M) ((N) != (M)) 2689 #define DO_EQ(N, M) ((N) == (M)) 2690 #define DO_EQ(N, M) ((N) == (M)) 2691 #define DO_GE(N, M) ((N) >= (M)) 2692 #define DO_LT(N, M) ((N) < (M)) 2693 #define DO_GT(N, M) ((N) > (M)) 2694 #define DO_LE(N, M) ((N) <= (M)) 2695 2696 DO_VCMP_U(vcmpeq, DO_EQ) 2697 DO_VCMP_U(vcmpne, DO_NE) 2698 DO_VCMP_U(vcmpcs, DO_GE) 2699 DO_VCMP_U(vcmphi, DO_GT) 2700 DO_VCMP_S(vcmpge, DO_GE) 2701 DO_VCMP_S(vcmplt, DO_LT) 2702 DO_VCMP_S(vcmpgt, DO_GT) 2703 DO_VCMP_S(vcmple, DO_LE) 2704 2705 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm) 2706 { 2707 /* 2708 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n] 2709 * but note that whether bytes are written to Qd is still subject 2710 * to (all forms of) predication in the usual way. 2711 */ 2712 uint64_t *d = vd, *n = vn, *m = vm; 2713 uint16_t mask = mve_element_mask(env); 2714 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); 2715 unsigned e; 2716 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) { 2717 uint64_t r = m[H8(e)]; 2718 mergemask(&r, n[H8(e)], p0); 2719 mergemask(&d[H8(e)], r, mask); 2720 } 2721 mve_advance_vpt(env); 2722 } 2723 2724 void HELPER(mve_vpnot)(CPUARMState *env) 2725 { 2726 /* 2727 * P0 bits for unexecuted beats (where eci_mask is 0) are unchanged. 2728 * P0 bits for predicated lanes in executed bits (where mask is 0) are 0. 2729 * P0 bits otherwise are inverted. 2730 * (This is the same logic as VCMP.) 2731 * This insn is itself subject to predication and to beat-wise execution, 2732 * and after it executes VPT state advances in the usual way. 2733 */ 2734 uint16_t mask = mve_element_mask(env); 2735 uint16_t eci_mask = mve_eci_mask(env); 2736 uint16_t beatpred = ~env->v7m.vpr & mask; 2737 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask); 2738 mve_advance_vpt(env); 2739 } 2740 2741 /* 2742 * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed, 2743 * otherwise set according to value of Rn. The calculation of 2744 * newmask here works in the same way as the calculation of the 2745 * ltpmask in mve_element_mask(), but we have pre-calculated 2746 * the masklen in the generated code. 2747 */ 2748 void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen) 2749 { 2750 uint16_t mask = mve_element_mask(env); 2751 uint16_t eci_mask = mve_eci_mask(env); 2752 uint16_t newmask; 2753 2754 assert(masklen <= 16); 2755 newmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; 2756 newmask &= mask; 2757 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask); 2758 mve_advance_vpt(env); 2759 } 2760 2761 #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \ 2762 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2763 { \ 2764 TYPE *d = vd, *m = vm; \ 2765 uint16_t mask = mve_element_mask(env); \ 2766 unsigned e; \ 2767 bool qc = false; \ 2768 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2769 bool sat = false; \ 2770 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)], &sat), mask); \ 2771 qc |= sat & mask & 1; \ 2772 } \ 2773 if (qc) { \ 2774 env->vfp.qc[0] = qc; \ 2775 } \ 2776 mve_advance_vpt(env); \ 2777 } 2778 2779 #define DO_VQABS_B(N, SATP) \ 2780 do_sat_bhs(DO_ABS((int64_t)N), INT8_MIN, INT8_MAX, SATP) 2781 #define DO_VQABS_H(N, SATP) \ 2782 do_sat_bhs(DO_ABS((int64_t)N), INT16_MIN, INT16_MAX, SATP) 2783 #define DO_VQABS_W(N, SATP) \ 2784 do_sat_bhs(DO_ABS((int64_t)N), INT32_MIN, INT32_MAX, SATP) 2785 2786 #define DO_VQNEG_B(N, SATP) do_sat_bhs(-(int64_t)N, INT8_MIN, INT8_MAX, SATP) 2787 #define DO_VQNEG_H(N, SATP) do_sat_bhs(-(int64_t)N, INT16_MIN, INT16_MAX, SATP) 2788 #define DO_VQNEG_W(N, SATP) do_sat_bhs(-(int64_t)N, INT32_MIN, INT32_MAX, SATP) 2789 2790 DO_1OP_SAT(vqabsb, 1, int8_t, DO_VQABS_B) 2791 DO_1OP_SAT(vqabsh, 2, int16_t, DO_VQABS_H) 2792 DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W) 2793 2794 DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B) 2795 DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H) 2796 DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W) 2797 2798 /* 2799 * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its 2800 * absolute value; we then do an unsigned comparison. 2801 */ 2802 #define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \ 2803 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ 2804 { \ 2805 UTYPE *d = vd; \ 2806 STYPE *m = vm; \ 2807 uint16_t mask = mve_element_mask(env); \ 2808 unsigned e; \ 2809 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2810 UTYPE r = DO_ABS(m[H##ESIZE(e)]); \ 2811 r = FN(d[H##ESIZE(e)], r); \ 2812 mergemask(&d[H##ESIZE(e)], r, mask); \ 2813 } \ 2814 mve_advance_vpt(env); \ 2815 } 2816 2817 DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX) 2818 DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX) 2819 DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX) 2820 DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN) 2821 DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN) 2822 DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN) 2823 2824 /* 2825 * 2-operand floating point. Note that if an element is partially 2826 * predicated we must do the FP operation to update the non-predicated 2827 * bytes, but we must be careful to avoid updating the FP exception 2828 * state unless byte 0 of the element was unpredicated. 2829 */ 2830 #define DO_2OP_FP(OP, ESIZE, TYPE, FN) \ 2831 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2832 void *vd, void *vn, void *vm) \ 2833 { \ 2834 TYPE *d = vd, *n = vn, *m = vm; \ 2835 TYPE r; \ 2836 uint16_t mask = mve_element_mask(env); \ 2837 unsigned e; \ 2838 float_status *fpst; \ 2839 float_status scratch_fpst; \ 2840 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2841 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2842 continue; \ 2843 } \ 2844 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2845 if (!(mask & 1)) { \ 2846 /* We need the result but without updating flags */ \ 2847 scratch_fpst = *fpst; \ 2848 fpst = &scratch_fpst; \ 2849 } \ 2850 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 2851 mergemask(&d[H##ESIZE(e)], r, mask); \ 2852 } \ 2853 mve_advance_vpt(env); \ 2854 } 2855 2856 #define DO_2OP_FP_ALL(OP, FN) \ 2857 DO_2OP_FP(OP##h, 2, float16, float16_##FN) \ 2858 DO_2OP_FP(OP##s, 4, float32, float32_##FN) 2859 2860 DO_2OP_FP_ALL(vfadd, add) 2861 DO_2OP_FP_ALL(vfsub, sub) 2862 DO_2OP_FP_ALL(vfmul, mul) 2863 2864 static inline float16 float16_abd(float16 a, float16 b, float_status *s) 2865 { 2866 return float16_abs(float16_sub(a, b, s)); 2867 } 2868 2869 static inline float32 float32_abd(float32 a, float32 b, float_status *s) 2870 { 2871 return float32_abs(float32_sub(a, b, s)); 2872 } 2873 2874 DO_2OP_FP_ALL(vfabd, abd) 2875 DO_2OP_FP_ALL(vmaxnm, maxnum) 2876 DO_2OP_FP_ALL(vminnm, minnum) 2877 2878 static inline float16 float16_maxnuma(float16 a, float16 b, float_status *s) 2879 { 2880 return float16_maxnum(float16_abs(a), float16_abs(b), s); 2881 } 2882 2883 static inline float32 float32_maxnuma(float32 a, float32 b, float_status *s) 2884 { 2885 return float32_maxnum(float32_abs(a), float32_abs(b), s); 2886 } 2887 2888 static inline float16 float16_minnuma(float16 a, float16 b, float_status *s) 2889 { 2890 return float16_minnum(float16_abs(a), float16_abs(b), s); 2891 } 2892 2893 static inline float32 float32_minnuma(float32 a, float32 b, float_status *s) 2894 { 2895 return float32_minnum(float32_abs(a), float32_abs(b), s); 2896 } 2897 2898 DO_2OP_FP_ALL(vmaxnma, maxnuma) 2899 DO_2OP_FP_ALL(vminnma, minnuma) 2900 2901 #define DO_VCADD_FP(OP, ESIZE, TYPE, FN0, FN1) \ 2902 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2903 void *vd, void *vn, void *vm) \ 2904 { \ 2905 TYPE *d = vd, *n = vn, *m = vm; \ 2906 TYPE r[16 / ESIZE]; \ 2907 uint16_t tm, mask = mve_element_mask(env); \ 2908 unsigned e; \ 2909 float_status *fpst; \ 2910 float_status scratch_fpst; \ 2911 /* Calculate all results first to avoid overwriting inputs */ \ 2912 for (e = 0, tm = mask; e < 16 / ESIZE; e++, tm >>= ESIZE) { \ 2913 if ((tm & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2914 r[e] = 0; \ 2915 continue; \ 2916 } \ 2917 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2918 if (!(tm & 1)) { \ 2919 /* We need the result but without updating flags */ \ 2920 scratch_fpst = *fpst; \ 2921 fpst = &scratch_fpst; \ 2922 } \ 2923 if (!(e & 1)) { \ 2924 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)], fpst); \ 2925 } else { \ 2926 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)], fpst); \ 2927 } \ 2928 } \ 2929 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2930 mergemask(&d[H##ESIZE(e)], r[e], mask); \ 2931 } \ 2932 mve_advance_vpt(env); \ 2933 } 2934 2935 DO_VCADD_FP(vfcadd90h, 2, float16, float16_sub, float16_add) 2936 DO_VCADD_FP(vfcadd90s, 4, float32, float32_sub, float32_add) 2937 DO_VCADD_FP(vfcadd270h, 2, float16, float16_add, float16_sub) 2938 DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub) 2939 2940 #define DO_VFMA(OP, ESIZE, TYPE, CHS) \ 2941 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2942 void *vd, void *vn, void *vm) \ 2943 { \ 2944 TYPE *d = vd, *n = vn, *m = vm; \ 2945 TYPE r; \ 2946 uint16_t mask = mve_element_mask(env); \ 2947 unsigned e; \ 2948 float_status *fpst; \ 2949 float_status scratch_fpst; \ 2950 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 2951 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 2952 continue; \ 2953 } \ 2954 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2955 if (!(mask & 1)) { \ 2956 /* We need the result but without updating flags */ \ 2957 scratch_fpst = *fpst; \ 2958 fpst = &scratch_fpst; \ 2959 } \ 2960 r = n[H##ESIZE(e)]; \ 2961 if (CHS) { \ 2962 r = TYPE##_chs(r); \ 2963 } \ 2964 r = TYPE##_muladd(r, m[H##ESIZE(e)], d[H##ESIZE(e)], \ 2965 0, fpst); \ 2966 mergemask(&d[H##ESIZE(e)], r, mask); \ 2967 } \ 2968 mve_advance_vpt(env); \ 2969 } 2970 2971 DO_VFMA(vfmah, 2, float16, false) 2972 DO_VFMA(vfmas, 4, float32, false) 2973 DO_VFMA(vfmsh, 2, float16, true) 2974 DO_VFMA(vfmss, 4, float32, true) 2975 2976 #define DO_VCMLA(OP, ESIZE, TYPE, ROT, FN) \ 2977 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 2978 void *vd, void *vn, void *vm) \ 2979 { \ 2980 TYPE *d = vd, *n = vn, *m = vm; \ 2981 TYPE r0, r1, e1, e2, e3, e4; \ 2982 uint16_t mask = mve_element_mask(env); \ 2983 unsigned e; \ 2984 float_status *fpst0, *fpst1; \ 2985 float_status scratch_fpst; \ 2986 /* We loop through pairs of elements at a time */ \ 2987 for (e = 0; e < 16 / ESIZE; e += 2, mask >>= ESIZE * 2) { \ 2988 if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) == 0) { \ 2989 continue; \ 2990 } \ 2991 fpst0 = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 2992 fpst1 = fpst0; \ 2993 if (!(mask & 1)) { \ 2994 scratch_fpst = *fpst0; \ 2995 fpst0 = &scratch_fpst; \ 2996 } \ 2997 if (!(mask & (1 << ESIZE))) { \ 2998 scratch_fpst = *fpst1; \ 2999 fpst1 = &scratch_fpst; \ 3000 } \ 3001 switch (ROT) { \ 3002 case 0: \ 3003 e1 = m[H##ESIZE(e)]; \ 3004 e2 = n[H##ESIZE(e)]; \ 3005 e3 = m[H##ESIZE(e + 1)]; \ 3006 e4 = n[H##ESIZE(e)]; \ 3007 break; \ 3008 case 1: \ 3009 e1 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 3010 e2 = n[H##ESIZE(e + 1)]; \ 3011 e3 = m[H##ESIZE(e)]; \ 3012 e4 = n[H##ESIZE(e + 1)]; \ 3013 break; \ 3014 case 2: \ 3015 e1 = TYPE##_chs(m[H##ESIZE(e)]); \ 3016 e2 = n[H##ESIZE(e)]; \ 3017 e3 = TYPE##_chs(m[H##ESIZE(e + 1)]); \ 3018 e4 = n[H##ESIZE(e)]; \ 3019 break; \ 3020 case 3: \ 3021 e1 = m[H##ESIZE(e + 1)]; \ 3022 e2 = n[H##ESIZE(e + 1)]; \ 3023 e3 = TYPE##_chs(m[H##ESIZE(e)]); \ 3024 e4 = n[H##ESIZE(e + 1)]; \ 3025 break; \ 3026 default: \ 3027 g_assert_not_reached(); \ 3028 } \ 3029 r0 = FN(e2, e1, d[H##ESIZE(e)], fpst0); \ 3030 r1 = FN(e4, e3, d[H##ESIZE(e + 1)], fpst1); \ 3031 mergemask(&d[H##ESIZE(e)], r0, mask); \ 3032 mergemask(&d[H##ESIZE(e + 1)], r1, mask >> ESIZE); \ 3033 } \ 3034 mve_advance_vpt(env); \ 3035 } 3036 3037 #define DO_VCMULH(N, M, D, S) float16_mul(N, M, S) 3038 #define DO_VCMULS(N, M, D, S) float32_mul(N, M, S) 3039 3040 #define DO_VCMLAH(N, M, D, S) float16_muladd(N, M, D, 0, S) 3041 #define DO_VCMLAS(N, M, D, S) float32_muladd(N, M, D, 0, S) 3042 3043 DO_VCMLA(vcmul0h, 2, float16, 0, DO_VCMULH) 3044 DO_VCMLA(vcmul0s, 4, float32, 0, DO_VCMULS) 3045 DO_VCMLA(vcmul90h, 2, float16, 1, DO_VCMULH) 3046 DO_VCMLA(vcmul90s, 4, float32, 1, DO_VCMULS) 3047 DO_VCMLA(vcmul180h, 2, float16, 2, DO_VCMULH) 3048 DO_VCMLA(vcmul180s, 4, float32, 2, DO_VCMULS) 3049 DO_VCMLA(vcmul270h, 2, float16, 3, DO_VCMULH) 3050 DO_VCMLA(vcmul270s, 4, float32, 3, DO_VCMULS) 3051 3052 DO_VCMLA(vcmla0h, 2, float16, 0, DO_VCMLAH) 3053 DO_VCMLA(vcmla0s, 4, float32, 0, DO_VCMLAS) 3054 DO_VCMLA(vcmla90h, 2, float16, 1, DO_VCMLAH) 3055 DO_VCMLA(vcmla90s, 4, float32, 1, DO_VCMLAS) 3056 DO_VCMLA(vcmla180h, 2, float16, 2, DO_VCMLAH) 3057 DO_VCMLA(vcmla180s, 4, float32, 2, DO_VCMLAS) 3058 DO_VCMLA(vcmla270h, 2, float16, 3, DO_VCMLAH) 3059 DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS) 3060 3061 #define DO_2OP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3062 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3063 void *vd, void *vn, uint32_t rm) \ 3064 { \ 3065 TYPE *d = vd, *n = vn; \ 3066 TYPE r, m = rm; \ 3067 uint16_t mask = mve_element_mask(env); \ 3068 unsigned e; \ 3069 float_status *fpst; \ 3070 float_status scratch_fpst; \ 3071 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3072 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3073 continue; \ 3074 } \ 3075 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3076 if (!(mask & 1)) { \ 3077 /* We need the result but without updating flags */ \ 3078 scratch_fpst = *fpst; \ 3079 fpst = &scratch_fpst; \ 3080 } \ 3081 r = FN(n[H##ESIZE(e)], m, fpst); \ 3082 mergemask(&d[H##ESIZE(e)], r, mask); \ 3083 } \ 3084 mve_advance_vpt(env); \ 3085 } 3086 3087 #define DO_2OP_FP_SCALAR_ALL(OP, FN) \ 3088 DO_2OP_FP_SCALAR(OP##h, 2, float16, float16_##FN) \ 3089 DO_2OP_FP_SCALAR(OP##s, 4, float32, float32_##FN) 3090 3091 DO_2OP_FP_SCALAR_ALL(vfadd_scalar, add) 3092 DO_2OP_FP_SCALAR_ALL(vfsub_scalar, sub) 3093 DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul) 3094 3095 #define DO_2OP_FP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \ 3096 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3097 void *vd, void *vn, uint32_t rm) \ 3098 { \ 3099 TYPE *d = vd, *n = vn; \ 3100 TYPE r, m = rm; \ 3101 uint16_t mask = mve_element_mask(env); \ 3102 unsigned e; \ 3103 float_status *fpst; \ 3104 float_status scratch_fpst; \ 3105 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3106 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3107 continue; \ 3108 } \ 3109 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3110 if (!(mask & 1)) { \ 3111 /* We need the result but without updating flags */ \ 3112 scratch_fpst = *fpst; \ 3113 fpst = &scratch_fpst; \ 3114 } \ 3115 r = FN(n[H##ESIZE(e)], m, d[H##ESIZE(e)], 0, fpst); \ 3116 mergemask(&d[H##ESIZE(e)], r, mask); \ 3117 } \ 3118 mve_advance_vpt(env); \ 3119 } 3120 3121 /* VFMAS is vector * vector + scalar, so swap op2 and op3 */ 3122 #define DO_VFMAS_SCALARH(N, M, D, F, S) float16_muladd(N, D, M, F, S) 3123 #define DO_VFMAS_SCALARS(N, M, D, F, S) float32_muladd(N, D, M, F, S) 3124 3125 /* VFMA is vector * scalar + vector */ 3126 DO_2OP_FP_ACC_SCALAR(vfma_scalarh, 2, float16, float16_muladd) 3127 DO_2OP_FP_ACC_SCALAR(vfma_scalars, 4, float32, float32_muladd) 3128 DO_2OP_FP_ACC_SCALAR(vfmas_scalarh, 2, float16, DO_VFMAS_SCALARH) 3129 DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS) 3130 3131 /* Floating point max/min across vector. */ 3132 #define DO_FP_VMAXMINV(OP, ESIZE, TYPE, ABS, FN) \ 3133 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ 3134 uint32_t ra_in) \ 3135 { \ 3136 uint16_t mask = mve_element_mask(env); \ 3137 unsigned e; \ 3138 TYPE *m = vm; \ 3139 TYPE ra = (TYPE)ra_in; \ 3140 float_status *fpst = \ 3141 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3142 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3143 if (mask & 1) { \ 3144 TYPE v = m[H##ESIZE(e)]; \ 3145 if (TYPE##_is_signaling_nan(ra, fpst)) { \ 3146 ra = TYPE##_silence_nan(ra, fpst); \ 3147 float_raise(float_flag_invalid, fpst); \ 3148 } \ 3149 if (TYPE##_is_signaling_nan(v, fpst)) { \ 3150 v = TYPE##_silence_nan(v, fpst); \ 3151 float_raise(float_flag_invalid, fpst); \ 3152 } \ 3153 if (ABS) { \ 3154 v = TYPE##_abs(v); \ 3155 } \ 3156 ra = FN(ra, v, fpst); \ 3157 } \ 3158 } \ 3159 mve_advance_vpt(env); \ 3160 return ra; \ 3161 } \ 3162 3163 #define NOP(X) (X) 3164 3165 DO_FP_VMAXMINV(vmaxnmvh, 2, float16, false, float16_maxnum) 3166 DO_FP_VMAXMINV(vmaxnmvs, 4, float32, false, float32_maxnum) 3167 DO_FP_VMAXMINV(vminnmvh, 2, float16, false, float16_minnum) 3168 DO_FP_VMAXMINV(vminnmvs, 4, float32, false, float32_minnum) 3169 DO_FP_VMAXMINV(vmaxnmavh, 2, float16, true, float16_maxnum) 3170 DO_FP_VMAXMINV(vmaxnmavs, 4, float32, true, float32_maxnum) 3171 DO_FP_VMAXMINV(vminnmavh, 2, float16, true, float16_minnum) 3172 DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum) 3173 3174 /* FP compares; note that all comparisons signal InvalidOp for QNaNs */ 3175 #define DO_VCMP_FP(OP, ESIZE, TYPE, FN) \ 3176 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \ 3177 { \ 3178 TYPE *n = vn, *m = vm; \ 3179 uint16_t mask = mve_element_mask(env); \ 3180 uint16_t eci_mask = mve_eci_mask(env); \ 3181 uint16_t beatpred = 0; \ 3182 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3183 unsigned e; \ 3184 float_status *fpst; \ 3185 float_status scratch_fpst; \ 3186 bool r; \ 3187 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3188 if ((mask & emask) == 0) { \ 3189 continue; \ 3190 } \ 3191 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3192 if (!(mask & (1 << (e * ESIZE)))) { \ 3193 /* We need the result but without updating flags */ \ 3194 scratch_fpst = *fpst; \ 3195 fpst = &scratch_fpst; \ 3196 } \ 3197 r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], fpst); \ 3198 /* Comparison sets 0/1 bits for each byte in the element */ \ 3199 beatpred |= r * emask; \ 3200 } \ 3201 beatpred &= mask; \ 3202 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3203 (beatpred & eci_mask); \ 3204 mve_advance_vpt(env); \ 3205 } 3206 3207 #define DO_VCMP_FP_SCALAR(OP, ESIZE, TYPE, FN) \ 3208 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ 3209 uint32_t rm) \ 3210 { \ 3211 TYPE *n = vn; \ 3212 uint16_t mask = mve_element_mask(env); \ 3213 uint16_t eci_mask = mve_eci_mask(env); \ 3214 uint16_t beatpred = 0; \ 3215 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ 3216 unsigned e; \ 3217 float_status *fpst; \ 3218 float_status scratch_fpst; \ 3219 bool r; \ 3220 for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \ 3221 if ((mask & emask) == 0) { \ 3222 continue; \ 3223 } \ 3224 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3225 if (!(mask & (1 << (e * ESIZE)))) { \ 3226 /* We need the result but without updating flags */ \ 3227 scratch_fpst = *fpst; \ 3228 fpst = &scratch_fpst; \ 3229 } \ 3230 r = FN(n[H##ESIZE(e)], (TYPE)rm, fpst); \ 3231 /* Comparison sets 0/1 bits for each byte in the element */ \ 3232 beatpred |= r * emask; \ 3233 } \ 3234 beatpred &= mask; \ 3235 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ 3236 (beatpred & eci_mask); \ 3237 mve_advance_vpt(env); \ 3238 } 3239 3240 #define DO_VCMP_FP_BOTH(VOP, SOP, ESIZE, TYPE, FN) \ 3241 DO_VCMP_FP(VOP, ESIZE, TYPE, FN) \ 3242 DO_VCMP_FP_SCALAR(SOP, ESIZE, TYPE, FN) 3243 3244 /* 3245 * Some care is needed here to get the correct result for the unordered case. 3246 * Architecturally EQ, GE and GT are defined to be false for unordered, but 3247 * the NE, LT and LE comparisons are defined as simple logical inverses of 3248 * EQ, GE and GT and so they must return true for unordered. The softfloat 3249 * comparison functions float*_{eq,le,lt} all return false for unordered. 3250 */ 3251 #define DO_GE16(X, Y, S) float16_le(Y, X, S) 3252 #define DO_GE32(X, Y, S) float32_le(Y, X, S) 3253 #define DO_GT16(X, Y, S) float16_lt(Y, X, S) 3254 #define DO_GT32(X, Y, S) float32_lt(Y, X, S) 3255 3256 DO_VCMP_FP_BOTH(vfcmpeqh, vfcmpeq_scalarh, 2, float16, float16_eq) 3257 DO_VCMP_FP_BOTH(vfcmpeqs, vfcmpeq_scalars, 4, float32, float32_eq) 3258 3259 DO_VCMP_FP_BOTH(vfcmpneh, vfcmpne_scalarh, 2, float16, !float16_eq) 3260 DO_VCMP_FP_BOTH(vfcmpnes, vfcmpne_scalars, 4, float32, !float32_eq) 3261 3262 DO_VCMP_FP_BOTH(vfcmpgeh, vfcmpge_scalarh, 2, float16, DO_GE16) 3263 DO_VCMP_FP_BOTH(vfcmpges, vfcmpge_scalars, 4, float32, DO_GE32) 3264 3265 DO_VCMP_FP_BOTH(vfcmplth, vfcmplt_scalarh, 2, float16, !DO_GE16) 3266 DO_VCMP_FP_BOTH(vfcmplts, vfcmplt_scalars, 4, float32, !DO_GE32) 3267 3268 DO_VCMP_FP_BOTH(vfcmpgth, vfcmpgt_scalarh, 2, float16, DO_GT16) 3269 DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float32, DO_GT32) 3270 3271 DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16) 3272 DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32) 3273 3274 #define DO_VCVT_FIXED(OP, ESIZE, TYPE, FN) \ 3275 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm, \ 3276 uint32_t shift) \ 3277 { \ 3278 TYPE *d = vd, *m = vm; \ 3279 TYPE r; \ 3280 uint16_t mask = mve_element_mask(env); \ 3281 unsigned e; \ 3282 float_status *fpst; \ 3283 float_status scratch_fpst; \ 3284 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3285 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3286 continue; \ 3287 } \ 3288 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3289 if (!(mask & 1)) { \ 3290 /* We need the result but without updating flags */ \ 3291 scratch_fpst = *fpst; \ 3292 fpst = &scratch_fpst; \ 3293 } \ 3294 r = FN(m[H##ESIZE(e)], shift, fpst); \ 3295 mergemask(&d[H##ESIZE(e)], r, mask); \ 3296 } \ 3297 mve_advance_vpt(env); \ 3298 } 3299 3300 DO_VCVT_FIXED(vcvt_sh, 2, int16_t, helper_vfp_shtoh) 3301 DO_VCVT_FIXED(vcvt_uh, 2, uint16_t, helper_vfp_uhtoh) 3302 DO_VCVT_FIXED(vcvt_hs, 2, int16_t, helper_vfp_toshh_round_to_zero) 3303 DO_VCVT_FIXED(vcvt_hu, 2, uint16_t, helper_vfp_touhh_round_to_zero) 3304 DO_VCVT_FIXED(vcvt_sf, 4, int32_t, helper_vfp_sltos) 3305 DO_VCVT_FIXED(vcvt_uf, 4, uint32_t, helper_vfp_ultos) 3306 DO_VCVT_FIXED(vcvt_fs, 4, int32_t, helper_vfp_tosls_round_to_zero) 3307 DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero) 3308 3309 /* VCVT with specified rmode */ 3310 #define DO_VCVT_RMODE(OP, ESIZE, TYPE, FN) \ 3311 void HELPER(glue(mve_, OP))(CPUARMState *env, \ 3312 void *vd, void *vm, uint32_t rmode) \ 3313 { \ 3314 TYPE *d = vd, *m = vm; \ 3315 TYPE r; \ 3316 uint16_t mask = mve_element_mask(env); \ 3317 unsigned e; \ 3318 float_status *fpst; \ 3319 float_status scratch_fpst; \ 3320 float_status *base_fpst = \ 3321 &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3322 uint32_t prev_rmode = get_float_rounding_mode(base_fpst); \ 3323 set_float_rounding_mode(rmode, base_fpst); \ 3324 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3325 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3326 continue; \ 3327 } \ 3328 fpst = base_fpst; \ 3329 if (!(mask & 1)) { \ 3330 /* We need the result but without updating flags */ \ 3331 scratch_fpst = *fpst; \ 3332 fpst = &scratch_fpst; \ 3333 } \ 3334 r = FN(m[H##ESIZE(e)], 0, fpst); \ 3335 mergemask(&d[H##ESIZE(e)], r, mask); \ 3336 } \ 3337 set_float_rounding_mode(prev_rmode, base_fpst); \ 3338 mve_advance_vpt(env); \ 3339 } 3340 3341 DO_VCVT_RMODE(vcvt_rm_sh, 2, uint16_t, helper_vfp_toshh) 3342 DO_VCVT_RMODE(vcvt_rm_uh, 2, uint16_t, helper_vfp_touhh) 3343 DO_VCVT_RMODE(vcvt_rm_ss, 4, uint32_t, helper_vfp_tosls) 3344 DO_VCVT_RMODE(vcvt_rm_us, 4, uint32_t, helper_vfp_touls) 3345 3346 #define DO_VRINT_RM_H(M, F, S) helper_rinth(M, S) 3347 #define DO_VRINT_RM_S(M, F, S) helper_rints(M, S) 3348 3349 DO_VCVT_RMODE(vrint_rm_h, 2, uint16_t, DO_VRINT_RM_H) 3350 DO_VCVT_RMODE(vrint_rm_s, 4, uint32_t, DO_VRINT_RM_S) 3351 3352 /* 3353 * VCVT between halfprec and singleprec. As usual for halfprec 3354 * conversions, FZ16 is ignored and AHP is observed. 3355 */ 3356 static void do_vcvt_sh(CPUARMState *env, void *vd, void *vm, int top) 3357 { 3358 uint16_t *d = vd; 3359 uint32_t *m = vm; 3360 uint16_t r; 3361 uint16_t mask = mve_element_mask(env); 3362 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3363 unsigned e; 3364 float_status *fpst; 3365 float_status scratch_fpst; 3366 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3367 bool old_fz = get_flush_to_zero(base_fpst); 3368 set_flush_to_zero(false, base_fpst); 3369 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3370 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3371 continue; 3372 } 3373 fpst = base_fpst; 3374 if (!(mask & 1)) { 3375 /* We need the result but without updating flags */ 3376 scratch_fpst = *fpst; 3377 fpst = &scratch_fpst; 3378 } 3379 r = float32_to_float16(m[H4(e)], ieee, fpst); 3380 mergemask(&d[H2(e * 2 + top)], r, mask >> (top * 2)); 3381 } 3382 set_flush_to_zero(old_fz, base_fpst); 3383 mve_advance_vpt(env); 3384 } 3385 3386 static void do_vcvt_hs(CPUARMState *env, void *vd, void *vm, int top) 3387 { 3388 uint32_t *d = vd; 3389 uint16_t *m = vm; 3390 uint32_t r; 3391 uint16_t mask = mve_element_mask(env); 3392 bool ieee = !(env->vfp.fpcr & FPCR_AHP); 3393 unsigned e; 3394 float_status *fpst; 3395 float_status scratch_fpst; 3396 float_status *base_fpst = &env->vfp.fp_status[FPST_STD]; 3397 bool old_fiz = get_flush_inputs_to_zero(base_fpst); 3398 set_flush_inputs_to_zero(false, base_fpst); 3399 for (e = 0; e < 16 / 4; e++, mask >>= 4) { 3400 if ((mask & MAKE_64BIT_MASK(0, 4)) == 0) { 3401 continue; 3402 } 3403 fpst = base_fpst; 3404 if (!(mask & (1 << (top * 2)))) { 3405 /* We need the result but without updating flags */ 3406 scratch_fpst = *fpst; 3407 fpst = &scratch_fpst; 3408 } 3409 r = float16_to_float32(m[H2(e * 2 + top)], ieee, fpst); 3410 mergemask(&d[H4(e)], r, mask); 3411 } 3412 set_flush_inputs_to_zero(old_fiz, base_fpst); 3413 mve_advance_vpt(env); 3414 } 3415 3416 void HELPER(mve_vcvtb_sh)(CPUARMState *env, void *vd, void *vm) 3417 { 3418 do_vcvt_sh(env, vd, vm, 0); 3419 } 3420 void HELPER(mve_vcvtt_sh)(CPUARMState *env, void *vd, void *vm) 3421 { 3422 do_vcvt_sh(env, vd, vm, 1); 3423 } 3424 void HELPER(mve_vcvtb_hs)(CPUARMState *env, void *vd, void *vm) 3425 { 3426 do_vcvt_hs(env, vd, vm, 0); 3427 } 3428 void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm) 3429 { 3430 do_vcvt_hs(env, vd, vm, 1); 3431 } 3432 3433 #define DO_1OP_FP(OP, ESIZE, TYPE, FN) \ 3434 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vm) \ 3435 { \ 3436 TYPE *d = vd, *m = vm; \ 3437 TYPE r; \ 3438 uint16_t mask = mve_element_mask(env); \ 3439 unsigned e; \ 3440 float_status *fpst; \ 3441 float_status scratch_fpst; \ 3442 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ 3443 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \ 3444 continue; \ 3445 } \ 3446 fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \ 3447 if (!(mask & 1)) { \ 3448 /* We need the result but without updating flags */ \ 3449 scratch_fpst = *fpst; \ 3450 fpst = &scratch_fpst; \ 3451 } \ 3452 r = FN(m[H##ESIZE(e)], fpst); \ 3453 mergemask(&d[H##ESIZE(e)], r, mask); \ 3454 } \ 3455 mve_advance_vpt(env); \ 3456 } 3457 3458 DO_1OP_FP(vrintx_h, 2, float16, float16_round_to_int) 3459 DO_1OP_FP(vrintx_s, 4, float32, float32_round_to_int) 3460