1 /* 2 * ARM hflags 3 * 4 * This code is licensed under the GNU GPL v2 or later. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 #include "qemu/osdep.h" 9 #include "cpu.h" 10 #include "internals.h" 11 #include "cpu-features.h" 12 #include "exec/helper-proto.h" 13 #include "exec/translation-block.h" 14 #include "accel/tcg/cpu-ops.h" 15 #include "cpregs.h" 16 17 static inline bool fgt_svc(CPUARMState *env, int el) 18 { 19 /* 20 * Assuming fine-grained-traps are active, return true if we 21 * should be trapping on SVC instructions. Only AArch64 can 22 * trap on an SVC at EL1, but we don't need to special-case this 23 * because if this is AArch32 EL1 then arm_fgt_active() is false. 24 * We also know el is 0 or 1. 25 */ 26 return el == 0 ? 27 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : 28 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); 29 } 30 31 /* Return true if memory alignment should be enforced. */ 32 static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) 33 { 34 #ifdef CONFIG_USER_ONLY 35 return false; 36 #else 37 /* Check the alignment enable bit. */ 38 if (sctlr & SCTLR_A) { 39 return true; 40 } 41 42 /* 43 * With PMSA, when the MPU is disabled, all memory types in the 44 * default map are Normal, so don't need aligment enforcing. 45 */ 46 if (arm_feature(env, ARM_FEATURE_PMSA)) { 47 return false; 48 } 49 50 /* 51 * With VMSA, if translation is disabled, then the default memory type 52 * is Device(-nGnRnE) instead of Normal, which requires that alignment 53 * be enforced. Since this affects all ram, it is most efficient 54 * to handle this during translation. 55 */ 56 if (sctlr & SCTLR_M) { 57 /* Translation enabled: memory type in PTE via MAIR_ELx. */ 58 return false; 59 } 60 if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) { 61 /* Stage 2 translation enabled: memory type in PTE. */ 62 return false; 63 } 64 return true; 65 #endif 66 } 67 68 bool access_secure_reg(CPUARMState *env) 69 { 70 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 71 !arm_el_is_aa64(env, 3) && 72 !(env->cp15.scr_el3 & SCR_NS)); 73 74 return ret; 75 } 76 77 static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, 78 ARMMMUIdx mmu_idx, 79 CPUARMTBFlags flags) 80 { 81 DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); 82 DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); 83 84 if (arm_singlestep_active(env)) { 85 DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); 86 } 87 88 return flags; 89 } 90 91 static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, 92 ARMMMUIdx mmu_idx, 93 CPUARMTBFlags flags) 94 { 95 bool sctlr_b = arm_sctlr_b(env); 96 97 if (sctlr_b) { 98 DP_TBFLAG_A32(flags, SCTLR__B, 1); 99 } 100 if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { 101 DP_TBFLAG_ANY(flags, BE_DATA, 1); 102 } 103 DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); 104 105 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 106 } 107 108 static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, 109 ARMMMUIdx mmu_idx) 110 { 111 CPUARMTBFlags flags = {}; 112 uint32_t ccr = env->v7m.ccr[env->v7m.secure]; 113 114 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ 115 if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { 116 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 117 } 118 119 if (arm_v7m_is_handler_mode(env)) { 120 DP_TBFLAG_M32(flags, HANDLER, 1); 121 } 122 123 /* 124 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN 125 * is suppressing them because the requested execution priority 126 * is less than 0. 127 */ 128 if (arm_feature(env, ARM_FEATURE_V8) && 129 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && 130 (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { 131 DP_TBFLAG_M32(flags, STACKCHECK, 1); 132 } 133 134 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { 135 DP_TBFLAG_M32(flags, SECURE, 1); 136 } 137 138 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 139 } 140 141 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ 142 static bool sme_fa64(CPUARMState *env, int el) 143 { 144 if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { 145 return false; 146 } 147 148 if (el <= 1 && !el_is_in_host(env, el)) { 149 if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { 150 return false; 151 } 152 } 153 if (el <= 2 && arm_is_el2_enabled(env)) { 154 if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { 155 return false; 156 } 157 } 158 if (arm_feature(env, ARM_FEATURE_EL3)) { 159 if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { 160 return false; 161 } 162 } 163 164 return true; 165 } 166 167 static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, 168 ARMMMUIdx mmu_idx) 169 { 170 CPUARMTBFlags flags = {}; 171 int el = arm_current_el(env); 172 uint64_t sctlr = arm_sctlr(env, el); 173 174 if (aprofile_require_alignment(env, el, sctlr)) { 175 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 176 } 177 178 if (arm_el_is_aa64(env, 1)) { 179 DP_TBFLAG_A32(flags, VFPEN, 1); 180 } 181 182 if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && 183 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 184 DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); 185 } 186 187 if (arm_fgt_active(env, el)) { 188 DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); 189 if (fgt_svc(env, el)) { 190 DP_TBFLAG_ANY(flags, FGT_SVC, 1); 191 } 192 } 193 194 if (env->uncached_cpsr & CPSR_IL) { 195 DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 196 } 197 198 /* 199 * The SME exception we are testing for is raised via 200 * AArch64.CheckFPAdvSIMDEnabled(), as called from 201 * AArch32.CheckAdvSIMDOrFPEnabled(). 202 */ 203 if (el == 0 204 && FIELD_EX64(env->svcr, SVCR, SM) 205 && (!arm_is_el2_enabled(env) 206 || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) 207 && arm_el_is_aa64(env, 1) 208 && !sme_fa64(env, el)) { 209 DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); 210 } 211 212 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 213 } 214 215 static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, 216 ARMMMUIdx mmu_idx) 217 { 218 CPUARMTBFlags flags = {}; 219 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); 220 uint64_t tcr = regime_tcr(env, mmu_idx); 221 uint64_t hcr = arm_hcr_el2_eff(env); 222 uint64_t sctlr; 223 int tbii, tbid; 224 225 DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); 226 227 /* Get control bits for tagged addresses. */ 228 tbid = aa64_va_parameter_tbi(tcr, mmu_idx); 229 tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); 230 231 DP_TBFLAG_A64(flags, TBII, tbii); 232 DP_TBFLAG_A64(flags, TBID, tbid); 233 234 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { 235 int sve_el = sve_exception_el(env, el); 236 237 /* 238 * If either FP or SVE are disabled, translator does not need len. 239 * If SVE EL > FP EL, FP exception has precedence, and translator 240 * does not need SVE EL. Save potential re-translations by forcing 241 * the unneeded data to zero. 242 */ 243 if (fp_el != 0) { 244 if (sve_el > fp_el) { 245 sve_el = 0; 246 } 247 } else if (sve_el == 0) { 248 DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); 249 } 250 DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); 251 } 252 if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { 253 int sme_el = sme_exception_el(env, el); 254 bool sm = FIELD_EX64(env->svcr, SVCR, SM); 255 256 DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); 257 if (sme_el == 0) { 258 /* Similarly, do not compute SVL if SME is disabled. */ 259 int svl = sve_vqm1_for_el_sm(env, el, true); 260 DP_TBFLAG_A64(flags, SVL, svl); 261 if (sm) { 262 /* If SVE is disabled, we will not have set VL above. */ 263 DP_TBFLAG_A64(flags, VL, svl); 264 } 265 } 266 if (sm) { 267 DP_TBFLAG_A64(flags, PSTATE_SM, 1); 268 DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); 269 } 270 DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); 271 } 272 273 sctlr = regime_sctlr(env, stage1); 274 275 if (aprofile_require_alignment(env, el, sctlr)) { 276 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 277 } 278 279 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { 280 DP_TBFLAG_ANY(flags, BE_DATA, 1); 281 } 282 283 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { 284 /* 285 * In order to save space in flags, we record only whether 286 * pauth is "inactive", meaning all insns are implemented as 287 * a nop, or "active" when some action must be performed. 288 * The decision of which action to take is left to a helper. 289 */ 290 if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { 291 DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); 292 } 293 } 294 295 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { 296 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ 297 if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { 298 DP_TBFLAG_A64(flags, BT, 1); 299 } 300 } 301 302 if (cpu_isar_feature(aa64_lse2, env_archcpu(env))) { 303 if (sctlr & SCTLR_nAA) { 304 DP_TBFLAG_A64(flags, NAA, 1); 305 } 306 } 307 308 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ 309 if (!(env->pstate & PSTATE_UAO)) { 310 switch (mmu_idx) { 311 case ARMMMUIdx_E10_1: 312 case ARMMMUIdx_E10_1_PAN: 313 /* FEAT_NV: NV,NV1 == 1,1 means we don't do UNPRIV accesses */ 314 if ((hcr & (HCR_NV | HCR_NV1)) != (HCR_NV | HCR_NV1)) { 315 DP_TBFLAG_A64(flags, UNPRIV, 1); 316 } 317 break; 318 case ARMMMUIdx_E20_2: 319 case ARMMMUIdx_E20_2_PAN: 320 /* 321 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is 322 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. 323 */ 324 if (env->cp15.hcr_el2 & HCR_TGE) { 325 DP_TBFLAG_A64(flags, UNPRIV, 1); 326 } 327 break; 328 default: 329 break; 330 } 331 } 332 333 if (env->pstate & PSTATE_IL) { 334 DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 335 } 336 337 if (arm_fgt_active(env, el)) { 338 DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); 339 if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { 340 DP_TBFLAG_A64(flags, TRAP_ERET, 1); 341 } 342 if (fgt_svc(env, el)) { 343 DP_TBFLAG_ANY(flags, FGT_SVC, 1); 344 } 345 } 346 347 /* 348 * ERET can also be trapped for FEAT_NV. arm_hcr_el2_eff() takes care 349 * of "is EL2 enabled" and the NV bit can only be set if FEAT_NV is present. 350 */ 351 if (el == 1 && (hcr & HCR_NV)) { 352 DP_TBFLAG_A64(flags, TRAP_ERET, 1); 353 DP_TBFLAG_A64(flags, NV, 1); 354 if (hcr & HCR_NV1) { 355 DP_TBFLAG_A64(flags, NV1, 1); 356 } 357 if (hcr & HCR_NV2) { 358 DP_TBFLAG_A64(flags, NV2, 1); 359 if (hcr & HCR_E2H) { 360 DP_TBFLAG_A64(flags, NV2_MEM_E20, 1); 361 } 362 if (env->cp15.sctlr_el[2] & SCTLR_EE) { 363 DP_TBFLAG_A64(flags, NV2_MEM_BE, 1); 364 } 365 } 366 } 367 368 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { 369 /* 370 * Set MTE_ACTIVE if any access may be Checked, and leave clear 371 * if all accesses must be Unchecked: 372 * 1) If no TBI, then there are no tags in the address to check, 373 * 2) If Tag Check Override, then all accesses are Unchecked, 374 * 3) If Tag Check Fail == 0, then Checked access have no effect, 375 * 4) If no Allocation Tag Access, then all accesses are Unchecked. 376 */ 377 if (allocation_tag_access_enabled(env, el, sctlr)) { 378 DP_TBFLAG_A64(flags, ATA, 1); 379 if (tbid 380 && !(env->pstate & PSTATE_TCO) 381 && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { 382 DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); 383 if (!EX_TBFLAG_A64(flags, UNPRIV)) { 384 /* 385 * In non-unpriv contexts (eg EL0), unpriv load/stores 386 * act like normal ones; duplicate the MTE info to 387 * avoid translate-a64.c having to check UNPRIV to see 388 * whether it is OK to index into MTE_ACTIVE[]. 389 */ 390 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); 391 } 392 } 393 } 394 /* And again for unprivileged accesses, if required. */ 395 if (EX_TBFLAG_A64(flags, UNPRIV) 396 && tbid 397 && !(env->pstate & PSTATE_TCO) 398 && (sctlr & SCTLR_TCF0) 399 && allocation_tag_access_enabled(env, 0, sctlr)) { 400 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); 401 } 402 /* 403 * For unpriv tag-setting accesses we also need ATA0. Again, in 404 * contexts where unpriv and normal insns are the same we 405 * duplicate the ATA bit to save effort for translate-a64.c. 406 */ 407 if (EX_TBFLAG_A64(flags, UNPRIV)) { 408 if (allocation_tag_access_enabled(env, 0, sctlr)) { 409 DP_TBFLAG_A64(flags, ATA0, 1); 410 } 411 } else { 412 DP_TBFLAG_A64(flags, ATA0, EX_TBFLAG_A64(flags, ATA)); 413 } 414 /* Cache TCMA as well as TBI. */ 415 DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); 416 } 417 418 if (env->vfp.fpcr & FPCR_AH) { 419 DP_TBFLAG_A64(flags, AH, 1); 420 } 421 if (env->vfp.fpcr & FPCR_NEP) { 422 /* 423 * In streaming-SVE without FA64, NEP behaves as if zero; 424 * compare pseudocode IsMerging() 425 */ 426 if (!(EX_TBFLAG_A64(flags, PSTATE_SM) && !sme_fa64(env, el))) { 427 DP_TBFLAG_A64(flags, NEP, 1); 428 } 429 } 430 431 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 432 } 433 434 static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) 435 { 436 int el = arm_current_el(env); 437 int fp_el = fp_exception_el(env, el); 438 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 439 440 if (is_a64(env)) { 441 return rebuild_hflags_a64(env, el, fp_el, mmu_idx); 442 } else if (arm_feature(env, ARM_FEATURE_M)) { 443 return rebuild_hflags_m32(env, fp_el, mmu_idx); 444 } else { 445 return rebuild_hflags_a32(env, fp_el, mmu_idx); 446 } 447 } 448 449 void arm_rebuild_hflags(CPUARMState *env) 450 { 451 env->hflags = rebuild_hflags_internal(env); 452 } 453 454 /* 455 * If we have triggered a EL state change we can't rely on the 456 * translator having passed it to us, we need to recompute. 457 */ 458 void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) 459 { 460 int el = arm_current_el(env); 461 int fp_el = fp_exception_el(env, el); 462 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 463 464 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 465 } 466 467 void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) 468 { 469 int fp_el = fp_exception_el(env, el); 470 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 471 472 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 473 } 474 475 /* 476 * If we have triggered a EL state change we can't rely on the 477 * translator having passed it to us, we need to recompute. 478 */ 479 void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) 480 { 481 int el = arm_current_el(env); 482 int fp_el = fp_exception_el(env, el); 483 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 484 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 485 } 486 487 void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) 488 { 489 int fp_el = fp_exception_el(env, el); 490 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 491 492 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 493 } 494 495 void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) 496 { 497 int fp_el = fp_exception_el(env, el); 498 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 499 500 env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); 501 } 502 503 static void assert_hflags_rebuild_correctly(CPUARMState *env) 504 { 505 #ifdef CONFIG_DEBUG_TCG 506 CPUARMTBFlags c = env->hflags; 507 CPUARMTBFlags r = rebuild_hflags_internal(env); 508 509 if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { 510 fprintf(stderr, "TCG hflags mismatch " 511 "(current:(0x%08x,0x%016" PRIx64 ")" 512 " rebuilt:(0x%08x,0x%016" PRIx64 ")\n", 513 c.flags, c.flags2, r.flags, r.flags2); 514 abort(); 515 } 516 #endif 517 } 518 519 static bool mve_no_pred(CPUARMState *env) 520 { 521 /* 522 * Return true if there is definitely no predication of MVE 523 * instructions by VPR or LTPSIZE. (Returning false even if there 524 * isn't any predication is OK; generated code will just be 525 * a little worse.) 526 * If the CPU does not implement MVE then this TB flag is always 0. 527 * 528 * NOTE: if you change this logic, the "recalculate s->mve_no_pred" 529 * logic in gen_update_fp_context() needs to be updated to match. 530 * 531 * We do not include the effect of the ECI bits here -- they are 532 * tracked in other TB flags. This simplifies the logic for 533 * "when did we emit code that changes the MVE_NO_PRED TB flag 534 * and thus need to end the TB?". 535 */ 536 if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { 537 return false; 538 } 539 if (env->v7m.vpr) { 540 return false; 541 } 542 if (env->v7m.ltpsize < 4) { 543 return false; 544 } 545 return true; 546 } 547 548 TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs) 549 { 550 CPUARMState *env = cpu_env(cs); 551 CPUARMTBFlags flags; 552 vaddr pc; 553 554 assert_hflags_rebuild_correctly(env); 555 flags = env->hflags; 556 557 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { 558 pc = env->pc; 559 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { 560 DP_TBFLAG_A64(flags, BTYPE, env->btype); 561 } 562 } else { 563 pc = env->regs[15]; 564 565 if (arm_feature(env, ARM_FEATURE_M)) { 566 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && 567 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) 568 != env->v7m.secure) { 569 DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); 570 } 571 572 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && 573 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || 574 (env->v7m.secure && 575 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { 576 /* 577 * ASPEN is set, but FPCA/SFPA indicate that there is no 578 * active FP context; we must create a new FP context before 579 * executing any FP insn. 580 */ 581 DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); 582 } 583 584 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; 585 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { 586 DP_TBFLAG_M32(flags, LSPACT, 1); 587 } 588 589 if (mve_no_pred(env)) { 590 DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); 591 } 592 } else { 593 /* 594 * Note that XSCALE_CPAR shares bits with VECSTRIDE. 595 * Note that VECLEN+VECSTRIDE are RES0 for M-profile. 596 */ 597 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 598 DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); 599 } else { 600 DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); 601 DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); 602 } 603 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { 604 DP_TBFLAG_A32(flags, VFPEN, 1); 605 } 606 } 607 608 DP_TBFLAG_AM32(flags, THUMB, env->thumb); 609 DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); 610 } 611 612 /* 613 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 614 * states defined in the ARM ARM for software singlestep: 615 * SS_ACTIVE PSTATE.SS State 616 * 0 x Inactive (the TB flag for SS is always 0) 617 * 1 0 Active-pending 618 * 1 1 Active-not-pending 619 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. 620 */ 621 if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { 622 DP_TBFLAG_ANY(flags, PSTATE__SS, 1); 623 } 624 625 return (TCGTBCPUState){ 626 .pc = pc, 627 .flags = flags.flags, 628 .cs_base = flags.flags2, 629 }; 630 } 631