1 /* 2 * ARM hflags 3 * 4 * This code is licensed under the GNU GPL v2 or later. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 #include "qemu/osdep.h" 9 #include "cpu.h" 10 #include "internals.h" 11 #include "cpu-features.h" 12 #include "exec/translation-block.h" 13 #include "accel/tcg/cpu-ops.h" 14 #include "cpregs.h" 15 16 #define HELPER_H "tcg/helper.h" 17 #include "exec/helper-proto.h.inc" 18 19 static inline bool fgt_svc(CPUARMState *env, int el) 20 { 21 /* 22 * Assuming fine-grained-traps are active, return true if we 23 * should be trapping on SVC instructions. Only AArch64 can 24 * trap on an SVC at EL1, but we don't need to special-case this 25 * because if this is AArch32 EL1 then arm_fgt_active() is false. 26 * We also know el is 0 or 1. 27 */ 28 return el == 0 ? 29 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : 30 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); 31 } 32 33 /* Return true if memory alignment should be enforced. */ 34 static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) 35 { 36 #ifdef CONFIG_USER_ONLY 37 return false; 38 #else 39 /* Check the alignment enable bit. */ 40 if (sctlr & SCTLR_A) { 41 return true; 42 } 43 44 /* 45 * With PMSA, when the MPU is disabled, all memory types in the 46 * default map are Normal, so don't need aligment enforcing. 47 */ 48 if (arm_feature(env, ARM_FEATURE_PMSA)) { 49 return false; 50 } 51 52 /* 53 * With VMSA, if translation is disabled, then the default memory type 54 * is Device(-nGnRnE) instead of Normal, which requires that alignment 55 * be enforced. Since this affects all ram, it is most efficient 56 * to handle this during translation. 57 */ 58 if (sctlr & SCTLR_M) { 59 /* Translation enabled: memory type in PTE via MAIR_ELx. */ 60 return false; 61 } 62 if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) { 63 /* Stage 2 translation enabled: memory type in PTE. */ 64 return false; 65 } 66 return true; 67 #endif 68 } 69 70 bool access_secure_reg(CPUARMState *env) 71 { 72 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 73 !arm_el_is_aa64(env, 3) && 74 !(env->cp15.scr_el3 & SCR_NS)); 75 76 return ret; 77 } 78 79 static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, 80 ARMMMUIdx mmu_idx, 81 CPUARMTBFlags flags) 82 { 83 DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); 84 DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); 85 86 if (arm_singlestep_active(env)) { 87 DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); 88 } 89 90 return flags; 91 } 92 93 static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, 94 ARMMMUIdx mmu_idx, 95 CPUARMTBFlags flags) 96 { 97 bool sctlr_b = arm_sctlr_b(env); 98 99 if (sctlr_b) { 100 DP_TBFLAG_A32(flags, SCTLR__B, 1); 101 } 102 if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { 103 DP_TBFLAG_ANY(flags, BE_DATA, 1); 104 } 105 DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); 106 107 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 108 } 109 110 static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, 111 ARMMMUIdx mmu_idx) 112 { 113 CPUARMTBFlags flags = {}; 114 uint32_t ccr = env->v7m.ccr[env->v7m.secure]; 115 116 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ 117 if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { 118 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 119 } 120 121 if (arm_v7m_is_handler_mode(env)) { 122 DP_TBFLAG_M32(flags, HANDLER, 1); 123 } 124 125 /* 126 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN 127 * is suppressing them because the requested execution priority 128 * is less than 0. 129 */ 130 if (arm_feature(env, ARM_FEATURE_V8) && 131 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && 132 (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { 133 DP_TBFLAG_M32(flags, STACKCHECK, 1); 134 } 135 136 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { 137 DP_TBFLAG_M32(flags, SECURE, 1); 138 } 139 140 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 141 } 142 143 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ 144 static bool sme_fa64(CPUARMState *env, int el) 145 { 146 if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { 147 return false; 148 } 149 150 if (el <= 1 && !el_is_in_host(env, el)) { 151 if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { 152 return false; 153 } 154 } 155 if (el <= 2 && arm_is_el2_enabled(env)) { 156 if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { 157 return false; 158 } 159 } 160 if (arm_feature(env, ARM_FEATURE_EL3)) { 161 if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { 162 return false; 163 } 164 } 165 166 return true; 167 } 168 169 static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, 170 ARMMMUIdx mmu_idx) 171 { 172 CPUARMTBFlags flags = {}; 173 int el = arm_current_el(env); 174 uint64_t sctlr = arm_sctlr(env, el); 175 176 if (aprofile_require_alignment(env, el, sctlr)) { 177 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 178 } 179 180 if (arm_el_is_aa64(env, 1)) { 181 DP_TBFLAG_A32(flags, VFPEN, 1); 182 } 183 184 if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && 185 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 186 DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); 187 } 188 189 if (arm_fgt_active(env, el)) { 190 DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); 191 if (fgt_svc(env, el)) { 192 DP_TBFLAG_ANY(flags, FGT_SVC, 1); 193 } 194 } 195 196 if (env->uncached_cpsr & CPSR_IL) { 197 DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 198 } 199 200 /* 201 * The SME exception we are testing for is raised via 202 * AArch64.CheckFPAdvSIMDEnabled(), as called from 203 * AArch32.CheckAdvSIMDOrFPEnabled(). 204 */ 205 if (el == 0 206 && FIELD_EX64(env->svcr, SVCR, SM) 207 && (!arm_is_el2_enabled(env) 208 || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) 209 && arm_el_is_aa64(env, 1) 210 && !sme_fa64(env, el)) { 211 DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); 212 } 213 214 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 215 } 216 217 static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, 218 ARMMMUIdx mmu_idx) 219 { 220 CPUARMTBFlags flags = {}; 221 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); 222 uint64_t tcr = regime_tcr(env, mmu_idx); 223 uint64_t hcr = arm_hcr_el2_eff(env); 224 uint64_t sctlr; 225 int tbii, tbid; 226 227 DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); 228 229 /* Get control bits for tagged addresses. */ 230 tbid = aa64_va_parameter_tbi(tcr, mmu_idx); 231 tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); 232 233 DP_TBFLAG_A64(flags, TBII, tbii); 234 DP_TBFLAG_A64(flags, TBID, tbid); 235 236 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { 237 int sve_el = sve_exception_el(env, el); 238 239 /* 240 * If either FP or SVE are disabled, translator does not need len. 241 * If SVE EL > FP EL, FP exception has precedence, and translator 242 * does not need SVE EL. Save potential re-translations by forcing 243 * the unneeded data to zero. 244 */ 245 if (fp_el != 0) { 246 if (sve_el > fp_el) { 247 sve_el = 0; 248 } 249 } else if (sve_el == 0) { 250 DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); 251 } 252 DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); 253 } 254 if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { 255 int sme_el = sme_exception_el(env, el); 256 bool sm = FIELD_EX64(env->svcr, SVCR, SM); 257 258 DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); 259 if (sme_el == 0) { 260 /* Similarly, do not compute SVL if SME is disabled. */ 261 int svl = sve_vqm1_for_el_sm(env, el, true); 262 DP_TBFLAG_A64(flags, SVL, svl); 263 if (sm) { 264 /* If SVE is disabled, we will not have set VL above. */ 265 DP_TBFLAG_A64(flags, VL, svl); 266 } 267 } 268 if (sm) { 269 DP_TBFLAG_A64(flags, PSTATE_SM, 1); 270 DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); 271 } 272 DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); 273 } 274 275 sctlr = regime_sctlr(env, stage1); 276 277 if (aprofile_require_alignment(env, el, sctlr)) { 278 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 279 } 280 281 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { 282 DP_TBFLAG_ANY(flags, BE_DATA, 1); 283 } 284 285 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { 286 /* 287 * In order to save space in flags, we record only whether 288 * pauth is "inactive", meaning all insns are implemented as 289 * a nop, or "active" when some action must be performed. 290 * The decision of which action to take is left to a helper. 291 */ 292 if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { 293 DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); 294 } 295 } 296 297 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { 298 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ 299 if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { 300 DP_TBFLAG_A64(flags, BT, 1); 301 } 302 } 303 304 if (cpu_isar_feature(aa64_lse2, env_archcpu(env))) { 305 if (sctlr & SCTLR_nAA) { 306 DP_TBFLAG_A64(flags, NAA, 1); 307 } 308 } 309 310 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ 311 if (!(env->pstate & PSTATE_UAO)) { 312 switch (mmu_idx) { 313 case ARMMMUIdx_E10_1: 314 case ARMMMUIdx_E10_1_PAN: 315 /* FEAT_NV: NV,NV1 == 1,1 means we don't do UNPRIV accesses */ 316 if ((hcr & (HCR_NV | HCR_NV1)) != (HCR_NV | HCR_NV1)) { 317 DP_TBFLAG_A64(flags, UNPRIV, 1); 318 } 319 break; 320 case ARMMMUIdx_E20_2: 321 case ARMMMUIdx_E20_2_PAN: 322 /* 323 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is 324 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. 325 */ 326 if (env->cp15.hcr_el2 & HCR_TGE) { 327 DP_TBFLAG_A64(flags, UNPRIV, 1); 328 } 329 break; 330 default: 331 break; 332 } 333 } 334 335 if (env->pstate & PSTATE_IL) { 336 DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 337 } 338 339 if (arm_fgt_active(env, el)) { 340 DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); 341 if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { 342 DP_TBFLAG_A64(flags, TRAP_ERET, 1); 343 } 344 if (fgt_svc(env, el)) { 345 DP_TBFLAG_ANY(flags, FGT_SVC, 1); 346 } 347 } 348 349 /* 350 * ERET can also be trapped for FEAT_NV. arm_hcr_el2_eff() takes care 351 * of "is EL2 enabled" and the NV bit can only be set if FEAT_NV is present. 352 */ 353 if (el == 1 && (hcr & HCR_NV)) { 354 DP_TBFLAG_A64(flags, TRAP_ERET, 1); 355 DP_TBFLAG_A64(flags, NV, 1); 356 if (hcr & HCR_NV1) { 357 DP_TBFLAG_A64(flags, NV1, 1); 358 } 359 if (hcr & HCR_NV2) { 360 DP_TBFLAG_A64(flags, NV2, 1); 361 if (hcr & HCR_E2H) { 362 DP_TBFLAG_A64(flags, NV2_MEM_E20, 1); 363 } 364 if (env->cp15.sctlr_el[2] & SCTLR_EE) { 365 DP_TBFLAG_A64(flags, NV2_MEM_BE, 1); 366 } 367 } 368 } 369 370 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { 371 /* 372 * Set MTE_ACTIVE if any access may be Checked, and leave clear 373 * if all accesses must be Unchecked: 374 * 1) If no TBI, then there are no tags in the address to check, 375 * 2) If Tag Check Override, then all accesses are Unchecked, 376 * 3) If Tag Check Fail == 0, then Checked access have no effect, 377 * 4) If no Allocation Tag Access, then all accesses are Unchecked. 378 */ 379 if (allocation_tag_access_enabled(env, el, sctlr)) { 380 DP_TBFLAG_A64(flags, ATA, 1); 381 if (tbid 382 && !(env->pstate & PSTATE_TCO) 383 && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { 384 DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); 385 if (!EX_TBFLAG_A64(flags, UNPRIV)) { 386 /* 387 * In non-unpriv contexts (eg EL0), unpriv load/stores 388 * act like normal ones; duplicate the MTE info to 389 * avoid translate-a64.c having to check UNPRIV to see 390 * whether it is OK to index into MTE_ACTIVE[]. 391 */ 392 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); 393 } 394 } 395 } 396 /* And again for unprivileged accesses, if required. */ 397 if (EX_TBFLAG_A64(flags, UNPRIV) 398 && tbid 399 && !(env->pstate & PSTATE_TCO) 400 && (sctlr & SCTLR_TCF0) 401 && allocation_tag_access_enabled(env, 0, sctlr)) { 402 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); 403 } 404 /* 405 * For unpriv tag-setting accesses we also need ATA0. Again, in 406 * contexts where unpriv and normal insns are the same we 407 * duplicate the ATA bit to save effort for translate-a64.c. 408 */ 409 if (EX_TBFLAG_A64(flags, UNPRIV)) { 410 if (allocation_tag_access_enabled(env, 0, sctlr)) { 411 DP_TBFLAG_A64(flags, ATA0, 1); 412 } 413 } else { 414 DP_TBFLAG_A64(flags, ATA0, EX_TBFLAG_A64(flags, ATA)); 415 } 416 /* Cache TCMA as well as TBI. */ 417 DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); 418 } 419 420 if (env->vfp.fpcr & FPCR_AH) { 421 DP_TBFLAG_A64(flags, AH, 1); 422 } 423 if (env->vfp.fpcr & FPCR_NEP) { 424 /* 425 * In streaming-SVE without FA64, NEP behaves as if zero; 426 * compare pseudocode IsMerging() 427 */ 428 if (!(EX_TBFLAG_A64(flags, PSTATE_SM) && !sme_fa64(env, el))) { 429 DP_TBFLAG_A64(flags, NEP, 1); 430 } 431 } 432 433 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 434 } 435 436 static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) 437 { 438 int el = arm_current_el(env); 439 int fp_el = fp_exception_el(env, el); 440 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 441 442 if (is_a64(env)) { 443 return rebuild_hflags_a64(env, el, fp_el, mmu_idx); 444 } else if (arm_feature(env, ARM_FEATURE_M)) { 445 return rebuild_hflags_m32(env, fp_el, mmu_idx); 446 } else { 447 return rebuild_hflags_a32(env, fp_el, mmu_idx); 448 } 449 } 450 451 void arm_rebuild_hflags(CPUARMState *env) 452 { 453 env->hflags = rebuild_hflags_internal(env); 454 } 455 456 /* 457 * If we have triggered a EL state change we can't rely on the 458 * translator having passed it to us, we need to recompute. 459 */ 460 void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) 461 { 462 int el = arm_current_el(env); 463 int fp_el = fp_exception_el(env, el); 464 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 465 466 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 467 } 468 469 void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) 470 { 471 int fp_el = fp_exception_el(env, el); 472 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 473 474 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 475 } 476 477 /* 478 * If we have triggered a EL state change we can't rely on the 479 * translator having passed it to us, we need to recompute. 480 */ 481 void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) 482 { 483 int el = arm_current_el(env); 484 int fp_el = fp_exception_el(env, el); 485 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 486 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 487 } 488 489 void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) 490 { 491 int fp_el = fp_exception_el(env, el); 492 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 493 494 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 495 } 496 497 void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) 498 { 499 int fp_el = fp_exception_el(env, el); 500 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 501 502 env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); 503 } 504 505 static void assert_hflags_rebuild_correctly(CPUARMState *env) 506 { 507 #ifdef CONFIG_DEBUG_TCG 508 CPUARMTBFlags c = env->hflags; 509 CPUARMTBFlags r = rebuild_hflags_internal(env); 510 511 if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { 512 fprintf(stderr, "TCG hflags mismatch " 513 "(current:(0x%08x,0x%016" PRIx64 ")" 514 " rebuilt:(0x%08x,0x%016" PRIx64 ")\n", 515 c.flags, c.flags2, r.flags, r.flags2); 516 abort(); 517 } 518 #endif 519 } 520 521 static bool mve_no_pred(CPUARMState *env) 522 { 523 /* 524 * Return true if there is definitely no predication of MVE 525 * instructions by VPR or LTPSIZE. (Returning false even if there 526 * isn't any predication is OK; generated code will just be 527 * a little worse.) 528 * If the CPU does not implement MVE then this TB flag is always 0. 529 * 530 * NOTE: if you change this logic, the "recalculate s->mve_no_pred" 531 * logic in gen_update_fp_context() needs to be updated to match. 532 * 533 * We do not include the effect of the ECI bits here -- they are 534 * tracked in other TB flags. This simplifies the logic for 535 * "when did we emit code that changes the MVE_NO_PRED TB flag 536 * and thus need to end the TB?". 537 */ 538 if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { 539 return false; 540 } 541 if (env->v7m.vpr) { 542 return false; 543 } 544 if (env->v7m.ltpsize < 4) { 545 return false; 546 } 547 return true; 548 } 549 550 TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs) 551 { 552 CPUARMState *env = cpu_env(cs); 553 CPUARMTBFlags flags; 554 vaddr pc; 555 556 assert_hflags_rebuild_correctly(env); 557 flags = env->hflags; 558 559 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { 560 pc = env->pc; 561 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { 562 DP_TBFLAG_A64(flags, BTYPE, env->btype); 563 } 564 } else { 565 pc = env->regs[15]; 566 567 if (arm_feature(env, ARM_FEATURE_M)) { 568 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && 569 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) 570 != env->v7m.secure) { 571 DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); 572 } 573 574 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && 575 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || 576 (env->v7m.secure && 577 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { 578 /* 579 * ASPEN is set, but FPCA/SFPA indicate that there is no 580 * active FP context; we must create a new FP context before 581 * executing any FP insn. 582 */ 583 DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); 584 } 585 586 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; 587 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { 588 DP_TBFLAG_M32(flags, LSPACT, 1); 589 } 590 591 if (mve_no_pred(env)) { 592 DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); 593 } 594 } else { 595 /* 596 * Note that XSCALE_CPAR shares bits with VECSTRIDE. 597 * Note that VECLEN+VECSTRIDE are RES0 for M-profile. 598 */ 599 if (arm_feature(env, ARM_FEATURE_XSCALE)) { 600 DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); 601 } else { 602 DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); 603 DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); 604 } 605 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { 606 DP_TBFLAG_A32(flags, VFPEN, 1); 607 } 608 } 609 610 DP_TBFLAG_AM32(flags, THUMB, env->thumb); 611 DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); 612 } 613 614 /* 615 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine 616 * states defined in the ARM ARM for software singlestep: 617 * SS_ACTIVE PSTATE.SS State 618 * 0 x Inactive (the TB flag for SS is always 0) 619 * 1 0 Active-pending 620 * 1 1 Active-not-pending 621 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. 622 */ 623 if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { 624 DP_TBFLAG_ANY(flags, PSTATE__SS, 1); 625 } 626 627 return (TCGTBCPUState){ 628 .pc = pc, 629 .flags = flags.flags, 630 .cs_base = flags.flags2, 631 }; 632 } 633