1 /* 2 * ARM implementation of KVM hooks 3 * 4 * Copyright Christoffer Dall 2009-2010 5 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems 6 * Copyright Alex Bennée 2014, Linaro 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include <sys/ioctl.h> 15 16 #include <linux/kvm.h> 17 18 #include "qemu/timer.h" 19 #include "qemu/error-report.h" 20 #include "qemu/main-loop.h" 21 #include "qom/object.h" 22 #include "qapi/error.h" 23 #include "system/system.h" 24 #include "system/runstate.h" 25 #include "system/kvm.h" 26 #include "system/kvm_int.h" 27 #include "kvm_arm.h" 28 #include "cpu.h" 29 #include "trace.h" 30 #include "internals.h" 31 #include "hw/pci/pci.h" 32 #include "exec/memattrs.h" 33 #include "system/address-spaces.h" 34 #include "gdbstub/enums.h" 35 #include "hw/boards.h" 36 #include "hw/irq.h" 37 #include "qapi/visitor.h" 38 #include "qemu/log.h" 39 #include "hw/acpi/acpi.h" 40 #include "hw/acpi/ghes.h" 41 #include "target/arm/gtimer.h" 42 #include "migration/blocker.h" 43 44 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 45 KVM_CAP_INFO(DEVICE_CTRL), 46 KVM_CAP_LAST_INFO 47 }; 48 49 static bool cap_has_mp_state; 50 static bool cap_has_inject_serror_esr; 51 static bool cap_has_inject_ext_dabt; 52 53 /** 54 * ARMHostCPUFeatures: information about the host CPU (identified 55 * by asking the host kernel) 56 */ 57 typedef struct ARMHostCPUFeatures { 58 ARMISARegisters isar; 59 uint64_t features; 60 uint32_t target; 61 const char *dtb_compatible; 62 } ARMHostCPUFeatures; 63 64 static ARMHostCPUFeatures arm_host_cpu_features; 65 66 /** 67 * kvm_arm_vcpu_init: 68 * @cpu: ARMCPU 69 * 70 * Initialize (or reinitialize) the VCPU by invoking the 71 * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature 72 * bitmask specified in the CPUState. 73 * 74 * Returns: 0 if success else < 0 error code 75 */ 76 static int kvm_arm_vcpu_init(ARMCPU *cpu) 77 { 78 struct kvm_vcpu_init init; 79 80 init.target = cpu->kvm_target; 81 memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); 82 83 return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_INIT, &init); 84 } 85 86 /** 87 * kvm_arm_vcpu_finalize: 88 * @cpu: ARMCPU 89 * @feature: feature to finalize 90 * 91 * Finalizes the configuration of the specified VCPU feature by 92 * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring 93 * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of 94 * KVM's API documentation. 95 * 96 * Returns: 0 if success else < 0 error code 97 */ 98 static int kvm_arm_vcpu_finalize(ARMCPU *cpu, int feature) 99 { 100 return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_FINALIZE, &feature); 101 } 102 103 bool kvm_arm_create_scratch_host_vcpu(int *fdarray, 104 struct kvm_vcpu_init *init) 105 { 106 int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1; 107 int max_vm_pa_size; 108 109 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 110 if (kvmfd < 0) { 111 goto err; 112 } 113 max_vm_pa_size = ioctl(kvmfd, KVM_CHECK_EXTENSION, KVM_CAP_ARM_VM_IPA_SIZE); 114 if (max_vm_pa_size < 0) { 115 max_vm_pa_size = 0; 116 } 117 do { 118 vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size); 119 } while (vmfd == -1 && errno == EINTR); 120 if (vmfd < 0) { 121 goto err; 122 } 123 124 /* 125 * The MTE capability must be enabled by the VMM before creating 126 * any VCPUs in order to allow the MTE bits of the ID_AA64PFR1 127 * register to be probed correctly, as they are masked if MTE 128 * is not enabled. 129 */ 130 if (kvm_arm_mte_supported()) { 131 KVMState kvm_state; 132 133 kvm_state.fd = kvmfd; 134 kvm_state.vmfd = vmfd; 135 kvm_vm_enable_cap(&kvm_state, KVM_CAP_ARM_MTE, 0); 136 } 137 138 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 139 if (cpufd < 0) { 140 goto err; 141 } 142 143 if (!init) { 144 /* Caller doesn't want the VCPU to be initialized, so skip it */ 145 goto finish; 146 } 147 148 if (init->target == -1) { 149 struct kvm_vcpu_init preferred; 150 151 ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred); 152 if (ret < 0) { 153 goto err; 154 } 155 init->target = preferred.target; 156 } 157 ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init); 158 if (ret < 0) { 159 goto err; 160 } 161 162 finish: 163 fdarray[0] = kvmfd; 164 fdarray[1] = vmfd; 165 fdarray[2] = cpufd; 166 167 return true; 168 169 err: 170 if (cpufd >= 0) { 171 close(cpufd); 172 } 173 if (vmfd >= 0) { 174 close(vmfd); 175 } 176 if (kvmfd >= 0) { 177 close(kvmfd); 178 } 179 180 return false; 181 } 182 183 void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) 184 { 185 int i; 186 187 for (i = 2; i >= 0; i--) { 188 close(fdarray[i]); 189 } 190 } 191 192 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) 193 { 194 uint64_t ret; 195 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; 196 int err; 197 198 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 199 err = ioctl(fd, KVM_GET_ONE_REG, &idreg); 200 if (err < 0) { 201 return -1; 202 } 203 *pret = ret; 204 return 0; 205 } 206 207 static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) 208 { 209 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; 210 211 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); 212 return ioctl(fd, KVM_GET_ONE_REG, &idreg); 213 } 214 215 static bool kvm_arm_pauth_supported(void) 216 { 217 return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && 218 kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); 219 } 220 221 static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 222 { 223 /* Identify the feature bits corresponding to the host CPU, and 224 * fill out the ARMHostCPUClass fields accordingly. To do this 225 * we have to create a scratch VM, create a single CPU inside it, 226 * and then query that CPU for the relevant ID registers. 227 */ 228 int fdarray[3]; 229 bool sve_supported; 230 bool pmu_supported = false; 231 uint64_t features = 0; 232 int err; 233 234 /* 235 * target = -1 informs kvm_arm_create_scratch_host_vcpu() 236 * to use the preferred target 237 */ 238 struct kvm_vcpu_init init = { .target = -1, }; 239 240 /* 241 * Ask for SVE if supported, so that we can query ID_AA64ZFR0, 242 * which is otherwise RAZ. 243 */ 244 sve_supported = kvm_arm_sve_supported(); 245 if (sve_supported) { 246 init.features[0] |= 1 << KVM_ARM_VCPU_SVE; 247 } 248 249 /* 250 * Ask for Pointer Authentication if supported, so that we get 251 * the unsanitized field values for AA64ISAR1_EL1. 252 */ 253 if (kvm_arm_pauth_supported()) { 254 init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 255 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 256 } 257 258 if (kvm_arm_pmu_supported()) { 259 init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 260 pmu_supported = true; 261 features |= 1ULL << ARM_FEATURE_PMU; 262 } 263 264 if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) { 265 return false; 266 } 267 268 ahcf->target = init.target; 269 ahcf->dtb_compatible = "arm,arm-v8"; 270 271 err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, 272 ARM64_SYS_REG(3, 0, 0, 4, 0)); 273 if (unlikely(err < 0)) { 274 /* 275 * Before v4.15, the kernel only exposed a limited number of system 276 * registers, not including any of the interesting AArch64 ID regs. 277 * For the most part we could leave these fields as zero with minimal 278 * effect, since this does not affect the values seen by the guest. 279 * 280 * However, it could cause problems down the line for QEMU, 281 * so provide a minimal v8.0 default. 282 * 283 * ??? Could read MIDR and use knowledge from cpu64.c. 284 * ??? Could map a page of memory into our temp guest and 285 * run the tiniest of hand-crafted kernels to extract 286 * the values seen by the guest. 287 * ??? Either of these sounds like too much effort just 288 * to work around running a modern host kernel. 289 */ 290 ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */ 291 err = 0; 292 } else { 293 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, 294 ARM64_SYS_REG(3, 0, 0, 4, 1)); 295 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, 296 ARM64_SYS_REG(3, 0, 0, 4, 5)); 297 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, 298 ARM64_SYS_REG(3, 0, 0, 5, 0)); 299 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, 300 ARM64_SYS_REG(3, 0, 0, 5, 1)); 301 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, 302 ARM64_SYS_REG(3, 0, 0, 6, 0)); 303 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, 304 ARM64_SYS_REG(3, 0, 0, 6, 1)); 305 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, 306 ARM64_SYS_REG(3, 0, 0, 6, 2)); 307 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, 308 ARM64_SYS_REG(3, 0, 0, 7, 0)); 309 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, 310 ARM64_SYS_REG(3, 0, 0, 7, 1)); 311 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, 312 ARM64_SYS_REG(3, 0, 0, 7, 2)); 313 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3, 314 ARM64_SYS_REG(3, 0, 0, 7, 3)); 315 316 /* 317 * Note that if AArch32 support is not present in the host, 318 * the AArch32 sysregs are present to be read, but will 319 * return UNKNOWN values. This is neither better nor worse 320 * than skipping the reads and leaving 0, as we must avoid 321 * considering the values in every case. 322 */ 323 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, 324 ARM64_SYS_REG(3, 0, 0, 1, 0)); 325 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, 326 ARM64_SYS_REG(3, 0, 0, 1, 1)); 327 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, 328 ARM64_SYS_REG(3, 0, 0, 1, 2)); 329 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, 330 ARM64_SYS_REG(3, 0, 0, 1, 4)); 331 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, 332 ARM64_SYS_REG(3, 0, 0, 1, 5)); 333 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, 334 ARM64_SYS_REG(3, 0, 0, 1, 6)); 335 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, 336 ARM64_SYS_REG(3, 0, 0, 1, 7)); 337 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, 338 ARM64_SYS_REG(3, 0, 0, 2, 0)); 339 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, 340 ARM64_SYS_REG(3, 0, 0, 2, 1)); 341 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, 342 ARM64_SYS_REG(3, 0, 0, 2, 2)); 343 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, 344 ARM64_SYS_REG(3, 0, 0, 2, 3)); 345 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, 346 ARM64_SYS_REG(3, 0, 0, 2, 4)); 347 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, 348 ARM64_SYS_REG(3, 0, 0, 2, 5)); 349 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, 350 ARM64_SYS_REG(3, 0, 0, 2, 6)); 351 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, 352 ARM64_SYS_REG(3, 0, 0, 2, 7)); 353 354 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, 355 ARM64_SYS_REG(3, 0, 0, 3, 0)); 356 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, 357 ARM64_SYS_REG(3, 0, 0, 3, 1)); 358 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, 359 ARM64_SYS_REG(3, 0, 0, 3, 2)); 360 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, 361 ARM64_SYS_REG(3, 0, 0, 3, 4)); 362 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, 363 ARM64_SYS_REG(3, 0, 0, 3, 5)); 364 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, 365 ARM64_SYS_REG(3, 0, 0, 3, 6)); 366 367 /* 368 * DBGDIDR is a bit complicated because the kernel doesn't 369 * provide an accessor for it in 64-bit mode, which is what this 370 * scratch VM is in, and there's no architected "64-bit sysreg 371 * which reads the same as the 32-bit register" the way there is 372 * for other ID registers. Instead we synthesize a value from the 373 * AArch64 ID_AA64DFR0, the same way the kernel code in 374 * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. 375 * We only do this if the CPU supports AArch32 at EL1. 376 */ 377 if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) { 378 int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS); 379 int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS); 380 int ctx_cmps = 381 FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); 382 int version = 6; /* ARMv8 debug architecture */ 383 bool has_el3 = 384 !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); 385 uint32_t dbgdidr = 0; 386 387 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); 388 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); 389 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); 390 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); 391 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); 392 dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); 393 dbgdidr |= (1 << 15); /* RES1 bit */ 394 ahcf->isar.dbgdidr = dbgdidr; 395 } 396 397 if (pmu_supported) { 398 /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */ 399 err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, 400 ARM64_SYS_REG(3, 3, 9, 12, 0)); 401 } 402 403 if (sve_supported) { 404 /* 405 * There is a range of kernels between kernel commit 73433762fcae 406 * and f81cb2c3ad41 which have a bug where the kernel doesn't 407 * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has 408 * enabled SVE support, which resulted in an error rather than RAZ. 409 * So only read the register if we set KVM_ARM_VCPU_SVE above. 410 */ 411 err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, 412 ARM64_SYS_REG(3, 0, 0, 4, 4)); 413 } 414 } 415 416 kvm_arm_destroy_scratch_host_vcpu(fdarray); 417 418 if (err < 0) { 419 return false; 420 } 421 422 /* 423 * We can assume any KVM supporting CPU is at least a v8 424 * with VFPv4+Neon; this in turn implies most of the other 425 * feature bits. 426 */ 427 features |= 1ULL << ARM_FEATURE_V8; 428 features |= 1ULL << ARM_FEATURE_NEON; 429 features |= 1ULL << ARM_FEATURE_AARCH64; 430 features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; 431 432 ahcf->features = features; 433 434 return true; 435 } 436 437 void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) 438 { 439 CPUARMState *env = &cpu->env; 440 441 if (!arm_host_cpu_features.dtb_compatible) { 442 if (!kvm_enabled() || 443 !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) { 444 /* We can't report this error yet, so flag that we need to 445 * in arm_cpu_realizefn(). 446 */ 447 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 448 cpu->host_cpu_probe_failed = true; 449 return; 450 } 451 } 452 453 cpu->kvm_target = arm_host_cpu_features.target; 454 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 455 cpu->isar = arm_host_cpu_features.isar; 456 env->features = arm_host_cpu_features.features; 457 } 458 459 static bool kvm_no_adjvtime_get(Object *obj, Error **errp) 460 { 461 return !ARM_CPU(obj)->kvm_adjvtime; 462 } 463 464 static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp) 465 { 466 ARM_CPU(obj)->kvm_adjvtime = !value; 467 } 468 469 static bool kvm_steal_time_get(Object *obj, Error **errp) 470 { 471 return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF; 472 } 473 474 static void kvm_steal_time_set(Object *obj, bool value, Error **errp) 475 { 476 ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; 477 } 478 479 /* KVM VCPU properties should be prefixed with "kvm-". */ 480 void kvm_arm_add_vcpu_properties(ARMCPU *cpu) 481 { 482 CPUARMState *env = &cpu->env; 483 Object *obj = OBJECT(cpu); 484 485 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 486 cpu->kvm_adjvtime = true; 487 object_property_add_bool(obj, "kvm-no-adjvtime", kvm_no_adjvtime_get, 488 kvm_no_adjvtime_set); 489 object_property_set_description(obj, "kvm-no-adjvtime", 490 "Set on to disable the adjustment of " 491 "the virtual counter. VM stopped time " 492 "will be counted."); 493 } 494 495 cpu->kvm_steal_time = ON_OFF_AUTO_AUTO; 496 object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get, 497 kvm_steal_time_set); 498 object_property_set_description(obj, "kvm-steal-time", 499 "Set off to disable KVM steal time."); 500 } 501 502 bool kvm_arm_pmu_supported(void) 503 { 504 return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3); 505 } 506 507 int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) 508 { 509 KVMState *s = KVM_STATE(ms->accelerator); 510 int ret; 511 512 ret = kvm_check_extension(s, KVM_CAP_ARM_VM_IPA_SIZE); 513 *fixed_ipa = ret <= 0; 514 515 return ret > 0 ? ret : 40; 516 } 517 518 int kvm_arch_get_default_type(MachineState *ms) 519 { 520 bool fixed_ipa; 521 int size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 522 return fixed_ipa ? 0 : size; 523 } 524 525 int kvm_arch_init(MachineState *ms, KVMState *s) 526 { 527 int ret = 0; 528 /* For ARM interrupt delivery is always asynchronous, 529 * whether we are using an in-kernel VGIC or not. 530 */ 531 kvm_async_interrupts_allowed = true; 532 533 /* 534 * PSCI wakes up secondary cores, so we always need to 535 * have vCPUs waiting in kernel space 536 */ 537 kvm_halt_in_kernel_allowed = true; 538 539 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 540 541 /* Check whether user space can specify guest syndrome value */ 542 cap_has_inject_serror_esr = 543 kvm_check_extension(s, KVM_CAP_ARM_INJECT_SERROR_ESR); 544 545 if (ms->smp.cpus > 256 && 546 !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { 547 error_report("Using more than 256 vcpus requires a host kernel " 548 "with KVM_CAP_ARM_IRQ_LINE_LAYOUT_2"); 549 ret = -EINVAL; 550 } 551 552 if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) { 553 if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { 554 error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap"); 555 } else { 556 /* Set status for supporting the external dabt injection */ 557 cap_has_inject_ext_dabt = kvm_check_extension(s, 558 KVM_CAP_ARM_INJECT_EXT_DABT); 559 } 560 } 561 562 if (s->kvm_eager_split_size) { 563 uint32_t sizes; 564 565 sizes = kvm_vm_check_extension(s, KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES); 566 if (!sizes) { 567 s->kvm_eager_split_size = 0; 568 warn_report("Eager Page Split support not available"); 569 } else if (!(s->kvm_eager_split_size & sizes)) { 570 error_report("Eager Page Split requested chunk size not valid"); 571 ret = -EINVAL; 572 } else { 573 ret = kvm_vm_enable_cap(s, KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE, 0, 574 s->kvm_eager_split_size); 575 if (ret < 0) { 576 error_report("Enabling of Eager Page Split failed: %s", 577 strerror(-ret)); 578 } 579 } 580 } 581 582 max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); 583 hw_watchpoints = g_array_sized_new(true, true, 584 sizeof(HWWatchpoint), max_hw_wps); 585 586 max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); 587 hw_breakpoints = g_array_sized_new(true, true, 588 sizeof(HWBreakpoint), max_hw_bps); 589 590 return ret; 591 } 592 593 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 594 { 595 return cpu->cpu_index; 596 } 597 598 /* We track all the KVM devices which need their memory addresses 599 * passing to the kernel in a list of these structures. 600 * When board init is complete we run through the list and 601 * tell the kernel the base addresses of the memory regions. 602 * We use a MemoryListener to track mapping and unmapping of 603 * the regions during board creation, so the board models don't 604 * need to do anything special for the KVM case. 605 * 606 * Sometimes the address must be OR'ed with some other fields 607 * (for example for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION). 608 * @kda_addr_ormask aims at storing the value of those fields. 609 */ 610 typedef struct KVMDevice { 611 struct kvm_arm_device_addr kda; 612 struct kvm_device_attr kdattr; 613 uint64_t kda_addr_ormask; 614 MemoryRegion *mr; 615 QSLIST_ENTRY(KVMDevice) entries; 616 int dev_fd; 617 } KVMDevice; 618 619 static QSLIST_HEAD(, KVMDevice) kvm_devices_head; 620 621 static void kvm_arm_devlistener_add(MemoryListener *listener, 622 MemoryRegionSection *section) 623 { 624 KVMDevice *kd; 625 626 QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 627 if (section->mr == kd->mr) { 628 kd->kda.addr = section->offset_within_address_space; 629 } 630 } 631 } 632 633 static void kvm_arm_devlistener_del(MemoryListener *listener, 634 MemoryRegionSection *section) 635 { 636 KVMDevice *kd; 637 638 QSLIST_FOREACH(kd, &kvm_devices_head, entries) { 639 if (section->mr == kd->mr) { 640 kd->kda.addr = -1; 641 } 642 } 643 } 644 645 static MemoryListener devlistener = { 646 .name = "kvm-arm", 647 .region_add = kvm_arm_devlistener_add, 648 .region_del = kvm_arm_devlistener_del, 649 .priority = MEMORY_LISTENER_PRIORITY_MIN, 650 }; 651 652 static void kvm_arm_set_device_addr(KVMDevice *kd) 653 { 654 struct kvm_device_attr *attr = &kd->kdattr; 655 int ret; 656 uint64_t addr = kd->kda.addr; 657 658 addr |= kd->kda_addr_ormask; 659 attr->addr = (uintptr_t)&addr; 660 ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr); 661 662 if (ret < 0) { 663 fprintf(stderr, "Failed to set device address: %s\n", 664 strerror(-ret)); 665 abort(); 666 } 667 } 668 669 static void kvm_arm_machine_init_done(Notifier *notifier, void *data) 670 { 671 KVMDevice *kd, *tkd; 672 673 QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) { 674 if (kd->kda.addr != -1) { 675 kvm_arm_set_device_addr(kd); 676 } 677 memory_region_unref(kd->mr); 678 QSLIST_REMOVE_HEAD(&kvm_devices_head, entries); 679 g_free(kd); 680 } 681 memory_listener_unregister(&devlistener); 682 } 683 684 static Notifier notify = { 685 .notify = kvm_arm_machine_init_done, 686 }; 687 688 void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, 689 uint64_t attr, int dev_fd, uint64_t addr_ormask) 690 { 691 KVMDevice *kd; 692 693 if (!kvm_irqchip_in_kernel()) { 694 return; 695 } 696 697 if (QSLIST_EMPTY(&kvm_devices_head)) { 698 memory_listener_register(&devlistener, &address_space_memory); 699 qemu_add_machine_init_done_notifier(¬ify); 700 } 701 kd = g_new0(KVMDevice, 1); 702 kd->mr = mr; 703 kd->kda.id = devid; 704 kd->kda.addr = -1; 705 kd->kdattr.flags = 0; 706 kd->kdattr.group = group; 707 kd->kdattr.attr = attr; 708 kd->dev_fd = dev_fd; 709 kd->kda_addr_ormask = addr_ormask; 710 QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries); 711 memory_region_ref(kd->mr); 712 } 713 714 static int compare_u64(const void *a, const void *b) 715 { 716 if (*(uint64_t *)a > *(uint64_t *)b) { 717 return 1; 718 } 719 if (*(uint64_t *)a < *(uint64_t *)b) { 720 return -1; 721 } 722 return 0; 723 } 724 725 /* 726 * cpreg_values are sorted in ascending order by KVM register ID 727 * (see kvm_arm_init_cpreg_list). This allows us to cheaply find 728 * the storage for a KVM register by ID with a binary search. 729 */ 730 static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) 731 { 732 uint64_t *res; 733 734 res = bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len, 735 sizeof(uint64_t), compare_u64); 736 assert(res); 737 738 return &cpu->cpreg_values[res - cpu->cpreg_indexes]; 739 } 740 741 /** 742 * kvm_arm_reg_syncs_via_cpreg_list: 743 * @regidx: KVM register index 744 * 745 * Return true if this KVM register should be synchronized via the 746 * cpreg list of arbitrary system registers, false if it is synchronized 747 * by hand using code in kvm_arch_get/put_registers(). 748 */ 749 static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) 750 { 751 switch (regidx & KVM_REG_ARM_COPROC_MASK) { 752 case KVM_REG_ARM_CORE: 753 case KVM_REG_ARM64_SVE: 754 return false; 755 default: 756 return true; 757 } 758 } 759 760 /** 761 * kvm_arm_init_cpreg_list: 762 * @cpu: ARMCPU 763 * 764 * Initialize the ARMCPU cpreg list according to the kernel's 765 * definition of what CPU registers it knows about (and throw away 766 * the previous TCG-created cpreg list). 767 * 768 * Returns: 0 if success, else < 0 error code 769 */ 770 static int kvm_arm_init_cpreg_list(ARMCPU *cpu) 771 { 772 struct kvm_reg_list rl; 773 struct kvm_reg_list *rlp; 774 int i, ret, arraylen; 775 CPUState *cs = CPU(cpu); 776 777 rl.n = 0; 778 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); 779 if (ret != -E2BIG) { 780 return ret; 781 } 782 rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)); 783 rlp->n = rl.n; 784 ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp); 785 if (ret) { 786 goto out; 787 } 788 /* Sort the list we get back from the kernel, since cpreg_tuples 789 * must be in strictly ascending order. 790 */ 791 qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64); 792 793 for (i = 0, arraylen = 0; i < rlp->n; i++) { 794 if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) { 795 continue; 796 } 797 switch (rlp->reg[i] & KVM_REG_SIZE_MASK) { 798 case KVM_REG_SIZE_U32: 799 case KVM_REG_SIZE_U64: 800 break; 801 default: 802 fprintf(stderr, "Can't handle size of register in kernel list\n"); 803 ret = -EINVAL; 804 goto out; 805 } 806 807 arraylen++; 808 } 809 810 cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen); 811 cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen); 812 cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes, 813 arraylen); 814 cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values, 815 arraylen); 816 cpu->cpreg_array_len = arraylen; 817 cpu->cpreg_vmstate_array_len = arraylen; 818 819 for (i = 0, arraylen = 0; i < rlp->n; i++) { 820 uint64_t regidx = rlp->reg[i]; 821 if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) { 822 continue; 823 } 824 cpu->cpreg_indexes[arraylen] = regidx; 825 arraylen++; 826 } 827 assert(cpu->cpreg_array_len == arraylen); 828 829 if (!write_kvmstate_to_list(cpu)) { 830 /* Shouldn't happen unless kernel is inconsistent about 831 * what registers exist. 832 */ 833 fprintf(stderr, "Initial read of kernel register state failed\n"); 834 ret = -EINVAL; 835 goto out; 836 } 837 838 out: 839 g_free(rlp); 840 return ret; 841 } 842 843 /** 844 * kvm_arm_cpreg_level: 845 * @regidx: KVM register index 846 * 847 * Return the level of this coprocessor/system register. Return value is 848 * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. 849 */ 850 static int kvm_arm_cpreg_level(uint64_t regidx) 851 { 852 /* 853 * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. 854 * If a register should be written less often, you must add it here 855 * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. 856 */ 857 switch (regidx) { 858 case KVM_REG_ARM_TIMER_CNT: 859 case KVM_REG_ARM_PTIMER_CNT: 860 return KVM_PUT_FULL_STATE; 861 } 862 return KVM_PUT_RUNTIME_STATE; 863 } 864 865 bool write_kvmstate_to_list(ARMCPU *cpu) 866 { 867 CPUState *cs = CPU(cpu); 868 int i; 869 bool ok = true; 870 871 for (i = 0; i < cpu->cpreg_array_len; i++) { 872 uint64_t regidx = cpu->cpreg_indexes[i]; 873 uint32_t v32; 874 int ret; 875 876 switch (regidx & KVM_REG_SIZE_MASK) { 877 case KVM_REG_SIZE_U32: 878 ret = kvm_get_one_reg(cs, regidx, &v32); 879 if (!ret) { 880 cpu->cpreg_values[i] = v32; 881 } 882 break; 883 case KVM_REG_SIZE_U64: 884 ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i); 885 break; 886 default: 887 g_assert_not_reached(); 888 } 889 if (ret) { 890 ok = false; 891 } 892 } 893 return ok; 894 } 895 896 bool write_list_to_kvmstate(ARMCPU *cpu, int level) 897 { 898 CPUState *cs = CPU(cpu); 899 int i; 900 bool ok = true; 901 902 for (i = 0; i < cpu->cpreg_array_len; i++) { 903 uint64_t regidx = cpu->cpreg_indexes[i]; 904 uint32_t v32; 905 int ret; 906 907 if (kvm_arm_cpreg_level(regidx) > level) { 908 continue; 909 } 910 911 switch (regidx & KVM_REG_SIZE_MASK) { 912 case KVM_REG_SIZE_U32: 913 v32 = cpu->cpreg_values[i]; 914 ret = kvm_set_one_reg(cs, regidx, &v32); 915 break; 916 case KVM_REG_SIZE_U64: 917 ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i); 918 break; 919 default: 920 g_assert_not_reached(); 921 } 922 if (ret) { 923 /* We might fail for "unknown register" and also for 924 * "you tried to set a register which is constant with 925 * a different value from what it actually contains". 926 */ 927 ok = false; 928 } 929 } 930 return ok; 931 } 932 933 void kvm_arm_cpu_pre_save(ARMCPU *cpu) 934 { 935 /* KVM virtual time adjustment */ 936 if (cpu->kvm_vtime_dirty) { 937 *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT) = cpu->kvm_vtime; 938 } 939 } 940 941 bool kvm_arm_cpu_post_load(ARMCPU *cpu) 942 { 943 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 944 return false; 945 } 946 /* Note that it's OK for the TCG side not to know about 947 * every register in the list; KVM is authoritative if 948 * we're using it. 949 */ 950 write_list_to_cpustate(cpu); 951 952 /* KVM virtual time adjustment */ 953 if (cpu->kvm_adjvtime) { 954 cpu->kvm_vtime = *kvm_arm_get_cpreg_ptr(cpu, KVM_REG_ARM_TIMER_CNT); 955 cpu->kvm_vtime_dirty = true; 956 } 957 958 return true; 959 } 960 961 void kvm_arm_reset_vcpu(ARMCPU *cpu) 962 { 963 int ret; 964 965 /* Re-init VCPU so that all registers are set to 966 * their respective reset values. 967 */ 968 ret = kvm_arm_vcpu_init(cpu); 969 if (ret < 0) { 970 fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); 971 abort(); 972 } 973 if (!write_kvmstate_to_list(cpu)) { 974 fprintf(stderr, "write_kvmstate_to_list failed\n"); 975 abort(); 976 } 977 /* 978 * Sync the reset values also into the CPUState. This is necessary 979 * because the next thing we do will be a kvm_arch_put_registers() 980 * which will update the list values from the CPUState before copying 981 * the list values back to KVM. It's OK to ignore failure returns here 982 * for the same reason we do so in kvm_arch_get_registers(). 983 */ 984 write_list_to_cpustate(cpu); 985 } 986 987 /* 988 * Update KVM's MP_STATE based on what QEMU thinks it is 989 */ 990 static int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) 991 { 992 if (cap_has_mp_state) { 993 struct kvm_mp_state mp_state = { 994 .mp_state = (cpu->power_state == PSCI_OFF) ? 995 KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE 996 }; 997 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 998 } 999 return 0; 1000 } 1001 1002 /* 1003 * Sync the KVM MP_STATE into QEMU 1004 */ 1005 static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) 1006 { 1007 if (cap_has_mp_state) { 1008 struct kvm_mp_state mp_state; 1009 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); 1010 if (ret) { 1011 return ret; 1012 } 1013 cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ? 1014 PSCI_OFF : PSCI_ON; 1015 } 1016 return 0; 1017 } 1018 1019 /** 1020 * kvm_arm_get_virtual_time: 1021 * @cpu: ARMCPU 1022 * 1023 * Gets the VCPU's virtual counter and stores it in the KVM CPU state. 1024 */ 1025 static void kvm_arm_get_virtual_time(ARMCPU *cpu) 1026 { 1027 int ret; 1028 1029 if (cpu->kvm_vtime_dirty) { 1030 return; 1031 } 1032 1033 ret = kvm_get_one_reg(CPU(cpu), KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1034 if (ret) { 1035 error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); 1036 abort(); 1037 } 1038 1039 cpu->kvm_vtime_dirty = true; 1040 } 1041 1042 /** 1043 * kvm_arm_put_virtual_time: 1044 * @cpu: ARMCPU 1045 * 1046 * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. 1047 */ 1048 static void kvm_arm_put_virtual_time(ARMCPU *cpu) 1049 { 1050 int ret; 1051 1052 if (!cpu->kvm_vtime_dirty) { 1053 return; 1054 } 1055 1056 ret = kvm_set_one_reg(CPU(cpu), KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); 1057 if (ret) { 1058 error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); 1059 abort(); 1060 } 1061 1062 cpu->kvm_vtime_dirty = false; 1063 } 1064 1065 /** 1066 * kvm_put_vcpu_events: 1067 * @cpu: ARMCPU 1068 * 1069 * Put VCPU related state to kvm. 1070 * 1071 * Returns: 0 if success else < 0 error code 1072 */ 1073 static int kvm_put_vcpu_events(ARMCPU *cpu) 1074 { 1075 CPUARMState *env = &cpu->env; 1076 struct kvm_vcpu_events events; 1077 int ret; 1078 1079 if (!kvm_has_vcpu_events()) { 1080 return 0; 1081 } 1082 1083 memset(&events, 0, sizeof(events)); 1084 events.exception.serror_pending = env->serror.pending; 1085 1086 /* Inject SError to guest with specified syndrome if host kernel 1087 * supports it, otherwise inject SError without syndrome. 1088 */ 1089 if (cap_has_inject_serror_esr) { 1090 events.exception.serror_has_esr = env->serror.has_esr; 1091 events.exception.serror_esr = env->serror.esr; 1092 } 1093 1094 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); 1095 if (ret) { 1096 error_report("failed to put vcpu events"); 1097 } 1098 1099 return ret; 1100 } 1101 1102 /** 1103 * kvm_get_vcpu_events: 1104 * @cpu: ARMCPU 1105 * 1106 * Get VCPU related state from kvm. 1107 * 1108 * Returns: 0 if success else < 0 error code 1109 */ 1110 static int kvm_get_vcpu_events(ARMCPU *cpu) 1111 { 1112 CPUARMState *env = &cpu->env; 1113 struct kvm_vcpu_events events; 1114 int ret; 1115 1116 if (!kvm_has_vcpu_events()) { 1117 return 0; 1118 } 1119 1120 memset(&events, 0, sizeof(events)); 1121 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); 1122 if (ret) { 1123 error_report("failed to get vcpu events"); 1124 return ret; 1125 } 1126 1127 env->serror.pending = events.exception.serror_pending; 1128 env->serror.has_esr = events.exception.serror_has_esr; 1129 env->serror.esr = events.exception.serror_esr; 1130 1131 return 0; 1132 } 1133 1134 #define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) 1135 #define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) 1136 1137 /* 1138 * ESR_EL1 1139 * ISS encoding 1140 * AARCH64: DFSC, bits [5:0] 1141 * AARCH32: 1142 * TTBCR.EAE == 0 1143 * FS[4] - DFSR[10] 1144 * FS[3:0] - DFSR[3:0] 1145 * TTBCR.EAE == 1 1146 * FS, bits [5:0] 1147 */ 1148 #define ESR_DFSC(aarch64, lpae, v) \ 1149 ((aarch64 || (lpae)) ? ((v) & 0x3F) \ 1150 : (((v) >> 6) | ((v) & 0x1F))) 1151 1152 #define ESR_DFSC_EXTABT(aarch64, lpae) \ 1153 ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) 1154 1155 /** 1156 * kvm_arm_verify_ext_dabt_pending: 1157 * @cpu: ARMCPU 1158 * 1159 * Verify the fault status code wrt the Ext DABT injection 1160 * 1161 * Returns: true if the fault status code is as expected, false otherwise 1162 */ 1163 static bool kvm_arm_verify_ext_dabt_pending(ARMCPU *cpu) 1164 { 1165 CPUState *cs = CPU(cpu); 1166 uint64_t dfsr_val; 1167 1168 if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { 1169 CPUARMState *env = &cpu->env; 1170 int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); 1171 int lpae = 0; 1172 1173 if (!aarch64_mode) { 1174 uint64_t ttbcr; 1175 1176 if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { 1177 lpae = arm_feature(env, ARM_FEATURE_LPAE) 1178 && (ttbcr & TTBCR_EAE); 1179 } 1180 } 1181 /* 1182 * The verification here is based on the DFSC bits 1183 * of the ESR_EL1 reg only 1184 */ 1185 return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == 1186 ESR_DFSC_EXTABT(aarch64_mode, lpae)); 1187 } 1188 return false; 1189 } 1190 1191 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1192 { 1193 ARMCPU *cpu = ARM_CPU(cs); 1194 CPUARMState *env = &cpu->env; 1195 1196 if (unlikely(env->ext_dabt_raised)) { 1197 /* 1198 * Verifying that the ext DABT has been properly injected, 1199 * otherwise risking indefinitely re-running the faulting instruction 1200 * Covering a very narrow case for kernels 5.5..5.5.4 1201 * when injected abort was misconfigured to be 1202 * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) 1203 */ 1204 if (!arm_feature(env, ARM_FEATURE_AARCH64) && 1205 unlikely(!kvm_arm_verify_ext_dabt_pending(cpu))) { 1206 1207 error_report("Data abort exception with no valid ISS generated by " 1208 "guest memory access. KVM unable to emulate faulting " 1209 "instruction. Failed to inject an external data abort " 1210 "into the guest."); 1211 abort(); 1212 } 1213 /* Clear the status */ 1214 env->ext_dabt_raised = 0; 1215 } 1216 } 1217 1218 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1219 { 1220 ARMCPU *cpu; 1221 uint32_t switched_level; 1222 1223 if (kvm_irqchip_in_kernel()) { 1224 /* 1225 * We only need to sync timer states with user-space interrupt 1226 * controllers, so return early and save cycles if we don't. 1227 */ 1228 return MEMTXATTRS_UNSPECIFIED; 1229 } 1230 1231 cpu = ARM_CPU(cs); 1232 1233 /* Synchronize our shadowed in-kernel device irq lines with the kvm ones */ 1234 if (run->s.regs.device_irq_level != cpu->device_irq_level) { 1235 switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level; 1236 1237 bql_lock(); 1238 1239 if (switched_level & KVM_ARM_DEV_EL1_VTIMER) { 1240 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT], 1241 !!(run->s.regs.device_irq_level & 1242 KVM_ARM_DEV_EL1_VTIMER)); 1243 switched_level &= ~KVM_ARM_DEV_EL1_VTIMER; 1244 } 1245 1246 if (switched_level & KVM_ARM_DEV_EL1_PTIMER) { 1247 qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS], 1248 !!(run->s.regs.device_irq_level & 1249 KVM_ARM_DEV_EL1_PTIMER)); 1250 switched_level &= ~KVM_ARM_DEV_EL1_PTIMER; 1251 } 1252 1253 if (switched_level & KVM_ARM_DEV_PMU) { 1254 qemu_set_irq(cpu->pmu_interrupt, 1255 !!(run->s.regs.device_irq_level & KVM_ARM_DEV_PMU)); 1256 switched_level &= ~KVM_ARM_DEV_PMU; 1257 } 1258 1259 if (switched_level) { 1260 qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n", 1261 __func__, switched_level); 1262 } 1263 1264 /* We also mark unknown levels as processed to not waste cycles */ 1265 cpu->device_irq_level = run->s.regs.device_irq_level; 1266 bql_unlock(); 1267 } 1268 1269 return MEMTXATTRS_UNSPECIFIED; 1270 } 1271 1272 static void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) 1273 { 1274 ARMCPU *cpu = opaque; 1275 1276 if (running) { 1277 if (cpu->kvm_adjvtime) { 1278 kvm_arm_put_virtual_time(cpu); 1279 } 1280 } else { 1281 if (cpu->kvm_adjvtime) { 1282 kvm_arm_get_virtual_time(cpu); 1283 } 1284 } 1285 } 1286 1287 /** 1288 * kvm_arm_handle_dabt_nisv: 1289 * @cpu: ARMCPU 1290 * @esr_iss: ISS encoding (limited) for the exception from Data Abort 1291 * ISV bit set to '0b0' -> no valid instruction syndrome 1292 * @fault_ipa: faulting address for the synchronous data abort 1293 * 1294 * Returns: 0 if the exception has been handled, < 0 otherwise 1295 */ 1296 static int kvm_arm_handle_dabt_nisv(ARMCPU *cpu, uint64_t esr_iss, 1297 uint64_t fault_ipa) 1298 { 1299 CPUARMState *env = &cpu->env; 1300 /* 1301 * Request KVM to inject the external data abort into the guest 1302 */ 1303 if (cap_has_inject_ext_dabt) { 1304 struct kvm_vcpu_events events = { }; 1305 /* 1306 * The external data abort event will be handled immediately by KVM 1307 * using the address fault that triggered the exit on given VCPU. 1308 * Requesting injection of the external data abort does not rely 1309 * on any other VCPU state. Therefore, in this particular case, the VCPU 1310 * synchronization can be exceptionally skipped. 1311 */ 1312 events.exception.ext_dabt_pending = 1; 1313 /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ 1314 if (!kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events)) { 1315 env->ext_dabt_raised = 1; 1316 return 0; 1317 } 1318 } else { 1319 error_report("Data abort exception triggered by guest memory access " 1320 "at physical address: 0x" TARGET_FMT_lx, 1321 (target_ulong)fault_ipa); 1322 error_printf("KVM unable to emulate faulting instruction.\n"); 1323 } 1324 return -1; 1325 } 1326 1327 /** 1328 * kvm_arm_handle_debug: 1329 * @cpu: ARMCPU 1330 * @debug_exit: debug part of the KVM exit structure 1331 * 1332 * Returns: TRUE if the debug exception was handled. 1333 * 1334 * See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register 1335 * 1336 * To minimise translating between kernel and user-space the kernel 1337 * ABI just provides user-space with the full exception syndrome 1338 * register value to be decoded in QEMU. 1339 */ 1340 static bool kvm_arm_handle_debug(ARMCPU *cpu, 1341 struct kvm_debug_exit_arch *debug_exit) 1342 { 1343 int hsr_ec = syn_get_ec(debug_exit->hsr); 1344 CPUState *cs = CPU(cpu); 1345 CPUARMState *env = &cpu->env; 1346 1347 /* Ensure PC is synchronised */ 1348 kvm_cpu_synchronize_state(cs); 1349 1350 switch (hsr_ec) { 1351 case EC_SOFTWARESTEP: 1352 if (cs->singlestep_enabled) { 1353 return true; 1354 } else { 1355 /* 1356 * The kernel should have suppressed the guest's ability to 1357 * single step at this point so something has gone wrong. 1358 */ 1359 error_report("%s: guest single-step while debugging unsupported" 1360 " (%"PRIx64", %"PRIx32")", 1361 __func__, env->pc, debug_exit->hsr); 1362 return false; 1363 } 1364 break; 1365 case EC_AA64_BKPT: 1366 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1367 return true; 1368 } 1369 break; 1370 case EC_BREAKPOINT: 1371 if (find_hw_breakpoint(cs, env->pc)) { 1372 return true; 1373 } 1374 break; 1375 case EC_WATCHPOINT: 1376 { 1377 CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far); 1378 if (wp) { 1379 cs->watchpoint_hit = wp; 1380 return true; 1381 } 1382 break; 1383 } 1384 default: 1385 error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", 1386 __func__, debug_exit->hsr, env->pc); 1387 } 1388 1389 /* If we are not handling the debug exception it must belong to 1390 * the guest. Let's re-use the existing TCG interrupt code to set 1391 * everything up properly. 1392 */ 1393 cs->exception_index = EXCP_BKPT; 1394 env->exception.syndrome = debug_exit->hsr; 1395 env->exception.vaddress = debug_exit->far; 1396 env->exception.target_el = 1; 1397 bql_lock(); 1398 arm_cpu_do_interrupt(cs); 1399 bql_unlock(); 1400 1401 return false; 1402 } 1403 1404 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1405 { 1406 ARMCPU *cpu = ARM_CPU(cs); 1407 int ret = 0; 1408 1409 switch (run->exit_reason) { 1410 case KVM_EXIT_DEBUG: 1411 if (kvm_arm_handle_debug(cpu, &run->debug.arch)) { 1412 ret = EXCP_DEBUG; 1413 } /* otherwise return to guest */ 1414 break; 1415 case KVM_EXIT_ARM_NISV: 1416 /* External DABT with no valid iss to decode */ 1417 ret = kvm_arm_handle_dabt_nisv(cpu, run->arm_nisv.esr_iss, 1418 run->arm_nisv.fault_ipa); 1419 break; 1420 default: 1421 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1422 __func__, run->exit_reason); 1423 break; 1424 } 1425 return ret; 1426 } 1427 1428 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1429 { 1430 return true; 1431 } 1432 1433 int kvm_arch_process_async_events(CPUState *cs) 1434 { 1435 return 0; 1436 } 1437 1438 /** 1439 * kvm_arm_hw_debug_active: 1440 * @cpu: ARMCPU 1441 * 1442 * Return: TRUE if any hardware breakpoints in use. 1443 */ 1444 static bool kvm_arm_hw_debug_active(ARMCPU *cpu) 1445 { 1446 return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); 1447 } 1448 1449 /** 1450 * kvm_arm_copy_hw_debug_data: 1451 * @ptr: kvm_guest_debug_arch structure 1452 * 1453 * Copy the architecture specific debug registers into the 1454 * kvm_guest_debug ioctl structure. 1455 */ 1456 static void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) 1457 { 1458 int i; 1459 memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); 1460 1461 for (i = 0; i < max_hw_wps; i++) { 1462 HWWatchpoint *wp = get_hw_wp(i); 1463 ptr->dbg_wcr[i] = wp->wcr; 1464 ptr->dbg_wvr[i] = wp->wvr; 1465 } 1466 for (i = 0; i < max_hw_bps; i++) { 1467 HWBreakpoint *bp = get_hw_bp(i); 1468 ptr->dbg_bcr[i] = bp->bcr; 1469 ptr->dbg_bvr[i] = bp->bvr; 1470 } 1471 } 1472 1473 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1474 { 1475 if (kvm_sw_breakpoints_active(cs)) { 1476 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1477 } 1478 if (kvm_arm_hw_debug_active(ARM_CPU(cs))) { 1479 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW; 1480 kvm_arm_copy_hw_debug_data(&dbg->arch); 1481 } 1482 } 1483 1484 void kvm_arch_init_irq_routing(KVMState *s) 1485 { 1486 } 1487 1488 int kvm_arch_irqchip_create(KVMState *s) 1489 { 1490 if (kvm_kernel_irqchip_split()) { 1491 error_report("-machine kernel_irqchip=split is not supported on ARM."); 1492 exit(1); 1493 } 1494 1495 /* If we can create the VGIC using the newer device control API, we 1496 * let the device do this when it initializes itself, otherwise we 1497 * fall back to the old API */ 1498 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1499 } 1500 1501 int kvm_arm_vgic_probe(void) 1502 { 1503 int val = 0; 1504 1505 if (kvm_create_device(kvm_state, 1506 KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) { 1507 val |= KVM_ARM_VGIC_V3; 1508 } 1509 if (kvm_create_device(kvm_state, 1510 KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) { 1511 val |= KVM_ARM_VGIC_V2; 1512 } 1513 return val; 1514 } 1515 1516 int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level) 1517 { 1518 int kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) | irq; 1519 int cpu_idx1 = cpu % 256; 1520 int cpu_idx2 = cpu / 256; 1521 1522 kvm_irq |= (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) | 1523 (cpu_idx2 << KVM_ARM_IRQ_VCPU2_SHIFT); 1524 1525 return kvm_set_irq(kvm_state, kvm_irq, !!level); 1526 } 1527 1528 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1529 uint64_t address, uint32_t data, PCIDevice *dev) 1530 { 1531 AddressSpace *as = pci_device_iommu_address_space(dev); 1532 hwaddr xlat, len, doorbell_gpa; 1533 MemoryRegionSection mrs; 1534 MemoryRegion *mr; 1535 1536 if (as == &address_space_memory) { 1537 return 0; 1538 } 1539 1540 /* MSI doorbell address is translated by an IOMMU */ 1541 1542 RCU_READ_LOCK_GUARD(); 1543 1544 mr = address_space_translate(as, address, &xlat, &len, true, 1545 MEMTXATTRS_UNSPECIFIED); 1546 1547 if (!mr) { 1548 return 1; 1549 } 1550 1551 mrs = memory_region_find(mr, xlat, 1); 1552 1553 if (!mrs.mr) { 1554 return 1; 1555 } 1556 1557 doorbell_gpa = mrs.offset_within_address_space; 1558 memory_region_unref(mrs.mr); 1559 1560 route->u.msi.address_lo = doorbell_gpa; 1561 route->u.msi.address_hi = doorbell_gpa >> 32; 1562 1563 trace_kvm_arm_fixup_msi_route(address, doorbell_gpa); 1564 1565 return 0; 1566 } 1567 1568 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1569 int vector, PCIDevice *dev) 1570 { 1571 return 0; 1572 } 1573 1574 int kvm_arch_release_virq_post(int virq) 1575 { 1576 return 0; 1577 } 1578 1579 int kvm_arch_msi_data_to_gsi(uint32_t data) 1580 { 1581 return (data - 32) & 0xffff; 1582 } 1583 1584 static void kvm_arch_get_eager_split_size(Object *obj, Visitor *v, 1585 const char *name, void *opaque, 1586 Error **errp) 1587 { 1588 KVMState *s = KVM_STATE(obj); 1589 uint64_t value = s->kvm_eager_split_size; 1590 1591 visit_type_size(v, name, &value, errp); 1592 } 1593 1594 static void kvm_arch_set_eager_split_size(Object *obj, Visitor *v, 1595 const char *name, void *opaque, 1596 Error **errp) 1597 { 1598 KVMState *s = KVM_STATE(obj); 1599 uint64_t value; 1600 1601 if (s->fd != -1) { 1602 error_setg(errp, "Unable to set early-split-size after KVM has been initialized"); 1603 return; 1604 } 1605 1606 if (!visit_type_size(v, name, &value, errp)) { 1607 return; 1608 } 1609 1610 if (value && !is_power_of_2(value)) { 1611 error_setg(errp, "early-split-size must be a power of two"); 1612 return; 1613 } 1614 1615 s->kvm_eager_split_size = value; 1616 } 1617 1618 void kvm_arch_accel_class_init(ObjectClass *oc) 1619 { 1620 object_class_property_add(oc, "eager-split-size", "size", 1621 kvm_arch_get_eager_split_size, 1622 kvm_arch_set_eager_split_size, NULL, NULL); 1623 1624 object_class_property_set_description(oc, "eager-split-size", 1625 "Eager Page Split chunk size for hugepages. (default: 0, disabled)"); 1626 } 1627 1628 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 1629 { 1630 switch (type) { 1631 case GDB_BREAKPOINT_HW: 1632 return insert_hw_breakpoint(addr); 1633 break; 1634 case GDB_WATCHPOINT_READ: 1635 case GDB_WATCHPOINT_WRITE: 1636 case GDB_WATCHPOINT_ACCESS: 1637 return insert_hw_watchpoint(addr, len, type); 1638 default: 1639 return -ENOSYS; 1640 } 1641 } 1642 1643 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 1644 { 1645 switch (type) { 1646 case GDB_BREAKPOINT_HW: 1647 return delete_hw_breakpoint(addr); 1648 case GDB_WATCHPOINT_READ: 1649 case GDB_WATCHPOINT_WRITE: 1650 case GDB_WATCHPOINT_ACCESS: 1651 return delete_hw_watchpoint(addr, len, type); 1652 default: 1653 return -ENOSYS; 1654 } 1655 } 1656 1657 void kvm_arch_remove_all_hw_breakpoints(void) 1658 { 1659 if (cur_hw_wps > 0) { 1660 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 1661 } 1662 if (cur_hw_bps > 0) { 1663 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 1664 } 1665 } 1666 1667 static bool kvm_arm_set_device_attr(ARMCPU *cpu, struct kvm_device_attr *attr, 1668 const char *name) 1669 { 1670 int err; 1671 1672 err = kvm_vcpu_ioctl(CPU(cpu), KVM_HAS_DEVICE_ATTR, attr); 1673 if (err != 0) { 1674 error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); 1675 return false; 1676 } 1677 1678 err = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEVICE_ATTR, attr); 1679 if (err != 0) { 1680 error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); 1681 return false; 1682 } 1683 1684 return true; 1685 } 1686 1687 void kvm_arm_pmu_init(ARMCPU *cpu) 1688 { 1689 struct kvm_device_attr attr = { 1690 .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1691 .attr = KVM_ARM_VCPU_PMU_V3_INIT, 1692 }; 1693 1694 if (!cpu->has_pmu) { 1695 return; 1696 } 1697 if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { 1698 error_report("failed to init PMU"); 1699 abort(); 1700 } 1701 } 1702 1703 void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) 1704 { 1705 struct kvm_device_attr attr = { 1706 .group = KVM_ARM_VCPU_PMU_V3_CTRL, 1707 .addr = (intptr_t)&irq, 1708 .attr = KVM_ARM_VCPU_PMU_V3_IRQ, 1709 }; 1710 1711 if (!cpu->has_pmu) { 1712 return; 1713 } 1714 if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { 1715 error_report("failed to set irq for PMU"); 1716 abort(); 1717 } 1718 } 1719 1720 void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) 1721 { 1722 struct kvm_device_attr attr = { 1723 .group = KVM_ARM_VCPU_PVTIME_CTRL, 1724 .attr = KVM_ARM_VCPU_PVTIME_IPA, 1725 .addr = (uint64_t)&ipa, 1726 }; 1727 1728 if (cpu->kvm_steal_time == ON_OFF_AUTO_OFF) { 1729 return; 1730 } 1731 if (!kvm_arm_set_device_attr(cpu, &attr, "PVTIME IPA")) { 1732 error_report("failed to init PVTIME IPA"); 1733 abort(); 1734 } 1735 } 1736 1737 void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) 1738 { 1739 bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); 1740 1741 if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) { 1742 if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1743 cpu->kvm_steal_time = ON_OFF_AUTO_OFF; 1744 } else { 1745 cpu->kvm_steal_time = ON_OFF_AUTO_ON; 1746 } 1747 } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) { 1748 if (!has_steal_time) { 1749 error_setg(errp, "'kvm-steal-time' cannot be enabled " 1750 "on this host"); 1751 return; 1752 } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1753 /* 1754 * DEN0057A chapter 2 says "This specification only covers 1755 * systems in which the Execution state of the hypervisor 1756 * as well as EL1 of virtual machines is AArch64.". And, 1757 * to ensure that, the smc/hvc calls are only specified as 1758 * smc64/hvc64. 1759 */ 1760 error_setg(errp, "'kvm-steal-time' cannot be enabled " 1761 "for AArch32 guests"); 1762 return; 1763 } 1764 } 1765 } 1766 1767 bool kvm_arm_aarch32_supported(void) 1768 { 1769 return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); 1770 } 1771 1772 bool kvm_arm_sve_supported(void) 1773 { 1774 return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); 1775 } 1776 1777 bool kvm_arm_mte_supported(void) 1778 { 1779 return kvm_check_extension(kvm_state, KVM_CAP_ARM_MTE); 1780 } 1781 1782 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); 1783 1784 uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) 1785 { 1786 /* Only call this function if kvm_arm_sve_supported() returns true. */ 1787 static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; 1788 static bool probed; 1789 uint32_t vq = 0; 1790 int i; 1791 1792 /* 1793 * KVM ensures all host CPUs support the same set of vector lengths. 1794 * So we only need to create the scratch VCPUs once and then cache 1795 * the results. 1796 */ 1797 if (!probed) { 1798 struct kvm_vcpu_init init = { 1799 .target = -1, 1800 .features[0] = (1 << KVM_ARM_VCPU_SVE), 1801 }; 1802 struct kvm_one_reg reg = { 1803 .id = KVM_REG_ARM64_SVE_VLS, 1804 .addr = (uint64_t)&vls[0], 1805 }; 1806 int fdarray[3], ret; 1807 1808 probed = true; 1809 1810 if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) { 1811 error_report("failed to create scratch VCPU with SVE enabled"); 1812 abort(); 1813 } 1814 ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®); 1815 kvm_arm_destroy_scratch_host_vcpu(fdarray); 1816 if (ret) { 1817 error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", 1818 strerror(errno)); 1819 abort(); 1820 } 1821 1822 for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) { 1823 if (vls[i]) { 1824 vq = 64 - clz64(vls[i]) + i * 64; 1825 break; 1826 } 1827 } 1828 if (vq > ARM_MAX_VQ) { 1829 warn_report("KVM supports vector lengths larger than " 1830 "QEMU can enable"); 1831 vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1832 } 1833 } 1834 1835 return vls[0]; 1836 } 1837 1838 static int kvm_arm_sve_set_vls(ARMCPU *cpu) 1839 { 1840 uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; 1841 1842 assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); 1843 1844 return kvm_set_one_reg(CPU(cpu), KVM_REG_ARM64_SVE_VLS, &vls[0]); 1845 } 1846 1847 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 1848 1849 int kvm_arch_init_vcpu(CPUState *cs) 1850 { 1851 int ret; 1852 uint64_t mpidr; 1853 ARMCPU *cpu = ARM_CPU(cs); 1854 CPUARMState *env = &cpu->env; 1855 uint64_t psciver; 1856 1857 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) { 1858 error_report("KVM is not supported for this guest CPU type"); 1859 return -EINVAL; 1860 } 1861 1862 qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cpu); 1863 1864 /* Determine init features for this CPU */ 1865 memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); 1866 if (cs->start_powered_off) { 1867 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; 1868 } 1869 if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { 1870 cpu->psci_version = QEMU_PSCI_VERSION_0_2; 1871 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; 1872 } 1873 if (!arm_feature(env, ARM_FEATURE_AARCH64)) { 1874 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; 1875 } 1876 if (cpu->has_pmu) { 1877 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; 1878 } 1879 if (cpu_isar_feature(aa64_sve, cpu)) { 1880 assert(kvm_arm_sve_supported()); 1881 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; 1882 } 1883 if (cpu_isar_feature(aa64_pauth, cpu)) { 1884 cpu->kvm_init_features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 1885 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); 1886 } 1887 1888 /* Do KVM_ARM_VCPU_INIT ioctl */ 1889 ret = kvm_arm_vcpu_init(cpu); 1890 if (ret) { 1891 return ret; 1892 } 1893 1894 if (cpu_isar_feature(aa64_sve, cpu)) { 1895 ret = kvm_arm_sve_set_vls(cpu); 1896 if (ret) { 1897 return ret; 1898 } 1899 ret = kvm_arm_vcpu_finalize(cpu, KVM_ARM_VCPU_SVE); 1900 if (ret) { 1901 return ret; 1902 } 1903 } 1904 1905 /* 1906 * KVM reports the exact PSCI version it is implementing via a 1907 * special sysreg. If it is present, use its contents to determine 1908 * what to report to the guest in the dtb (it is the PSCI version, 1909 * in the same 15-bits major 16-bits minor format that PSCI_VERSION 1910 * returns). 1911 */ 1912 if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { 1913 cpu->psci_version = psciver; 1914 } 1915 1916 /* 1917 * When KVM is in use, PSCI is emulated in-kernel and not by qemu. 1918 * Currently KVM has its own idea about MPIDR assignment, so we 1919 * override our defaults with what we get from KVM. 1920 */ 1921 ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); 1922 if (ret) { 1923 return ret; 1924 } 1925 cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; 1926 1927 return kvm_arm_init_cpreg_list(cpu); 1928 } 1929 1930 int kvm_arch_destroy_vcpu(CPUState *cs) 1931 { 1932 return 0; 1933 } 1934 1935 /* Callers must hold the iothread mutex lock */ 1936 static void kvm_inject_arm_sea(CPUState *c) 1937 { 1938 ARMCPU *cpu = ARM_CPU(c); 1939 CPUARMState *env = &cpu->env; 1940 uint32_t esr; 1941 bool same_el; 1942 1943 c->exception_index = EXCP_DATA_ABORT; 1944 env->exception.target_el = 1; 1945 1946 /* 1947 * Set the DFSC to synchronous external abort and set FnV to not valid, 1948 * this will tell guest the FAR_ELx is UNKNOWN for this abort. 1949 */ 1950 same_el = arm_current_el(env) == env->exception.target_el; 1951 esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); 1952 1953 env->exception.syndrome = esr; 1954 1955 arm_cpu_do_interrupt(c); 1956 } 1957 1958 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 1959 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1960 1961 #define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ 1962 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1963 1964 #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ 1965 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) 1966 1967 static int kvm_arch_put_fpsimd(CPUState *cs) 1968 { 1969 CPUARMState *env = &ARM_CPU(cs)->env; 1970 int i, ret; 1971 1972 for (i = 0; i < 32; i++) { 1973 uint64_t *q = aa64_vfp_qreg(env, i); 1974 #if HOST_BIG_ENDIAN 1975 uint64_t fp_val[2] = { q[1], q[0] }; 1976 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), 1977 fp_val); 1978 #else 1979 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 1980 #endif 1981 if (ret) { 1982 return ret; 1983 } 1984 } 1985 1986 return 0; 1987 } 1988 1989 /* 1990 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 1991 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 1992 * code the slice index to zero for now as it's unlikely we'll need more than 1993 * one slice for quite some time. 1994 */ 1995 static int kvm_arch_put_sve(CPUState *cs) 1996 { 1997 ARMCPU *cpu = ARM_CPU(cs); 1998 CPUARMState *env = &cpu->env; 1999 uint64_t tmp[ARM_MAX_VQ * 2]; 2000 uint64_t *r; 2001 int n, ret; 2002 2003 for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2004 r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2); 2005 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2006 if (ret) { 2007 return ret; 2008 } 2009 } 2010 2011 for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2012 r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0], 2013 DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2014 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2015 if (ret) { 2016 return ret; 2017 } 2018 } 2019 2020 r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], 2021 DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2022 ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2023 if (ret) { 2024 return ret; 2025 } 2026 2027 return 0; 2028 } 2029 2030 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 2031 { 2032 uint64_t val; 2033 uint32_t fpr; 2034 int i, ret; 2035 unsigned int el; 2036 2037 ARMCPU *cpu = ARM_CPU(cs); 2038 CPUARMState *env = &cpu->env; 2039 2040 /* If we are in AArch32 mode then we need to copy the AArch32 regs to the 2041 * AArch64 registers before pushing them out to 64-bit KVM. 2042 */ 2043 if (!is_a64(env)) { 2044 aarch64_sync_32_to_64(env); 2045 } 2046 2047 for (i = 0; i < 31; i++) { 2048 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2049 &env->xregs[i]); 2050 if (ret) { 2051 return ret; 2052 } 2053 } 2054 2055 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2056 * QEMU side we keep the current SP in xregs[31] as well. 2057 */ 2058 aarch64_save_sp(env, 1); 2059 2060 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2061 if (ret) { 2062 return ret; 2063 } 2064 2065 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2066 if (ret) { 2067 return ret; 2068 } 2069 2070 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ 2071 if (is_a64(env)) { 2072 val = pstate_read(env); 2073 } else { 2074 val = cpsr_read(env); 2075 } 2076 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2077 if (ret) { 2078 return ret; 2079 } 2080 2081 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2082 if (ret) { 2083 return ret; 2084 } 2085 2086 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2087 if (ret) { 2088 return ret; 2089 } 2090 2091 /* Saved Program State Registers 2092 * 2093 * Before we restore from the banked_spsr[] array we need to 2094 * ensure that any modifications to env->spsr are correctly 2095 * reflected in the banks. 2096 */ 2097 el = arm_current_el(env); 2098 if (el > 0 && !is_a64(env)) { 2099 i = bank_number(env->uncached_cpsr & CPSR_M); 2100 env->banked_spsr[i] = env->spsr; 2101 } 2102 2103 /* KVM 0-4 map to QEMU banks 1-5 */ 2104 for (i = 0; i < KVM_NR_SPSR; i++) { 2105 ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2106 &env->banked_spsr[i + 1]); 2107 if (ret) { 2108 return ret; 2109 } 2110 } 2111 2112 if (cpu_isar_feature(aa64_sve, cpu)) { 2113 ret = kvm_arch_put_sve(cs); 2114 } else { 2115 ret = kvm_arch_put_fpsimd(cs); 2116 } 2117 if (ret) { 2118 return ret; 2119 } 2120 2121 fpr = vfp_get_fpsr(env); 2122 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2123 if (ret) { 2124 return ret; 2125 } 2126 2127 fpr = vfp_get_fpcr(env); 2128 ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2129 if (ret) { 2130 return ret; 2131 } 2132 2133 write_cpustate_to_list(cpu, true); 2134 2135 if (!write_list_to_kvmstate(cpu, level)) { 2136 return -EINVAL; 2137 } 2138 2139 /* 2140 * Setting VCPU events should be triggered after syncing the registers 2141 * to avoid overwriting potential changes made by KVM upon calling 2142 * KVM_SET_VCPU_EVENTS ioctl 2143 */ 2144 ret = kvm_put_vcpu_events(cpu); 2145 if (ret) { 2146 return ret; 2147 } 2148 2149 return kvm_arm_sync_mpstate_to_kvm(cpu); 2150 } 2151 2152 static int kvm_arch_get_fpsimd(CPUState *cs) 2153 { 2154 CPUARMState *env = &ARM_CPU(cs)->env; 2155 int i, ret; 2156 2157 for (i = 0; i < 32; i++) { 2158 uint64_t *q = aa64_vfp_qreg(env, i); 2159 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); 2160 if (ret) { 2161 return ret; 2162 } else { 2163 #if HOST_BIG_ENDIAN 2164 uint64_t t; 2165 t = q[0], q[0] = q[1], q[1] = t; 2166 #endif 2167 } 2168 } 2169 2170 return 0; 2171 } 2172 2173 /* 2174 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits 2175 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard 2176 * code the slice index to zero for now as it's unlikely we'll need more than 2177 * one slice for quite some time. 2178 */ 2179 static int kvm_arch_get_sve(CPUState *cs) 2180 { 2181 ARMCPU *cpu = ARM_CPU(cs); 2182 CPUARMState *env = &cpu->env; 2183 uint64_t *r; 2184 int n, ret; 2185 2186 for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { 2187 r = &env->vfp.zregs[n].d[0]; 2188 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); 2189 if (ret) { 2190 return ret; 2191 } 2192 sve_bswap64(r, r, cpu->sve_max_vq * 2); 2193 } 2194 2195 for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { 2196 r = &env->vfp.pregs[n].p[0]; 2197 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); 2198 if (ret) { 2199 return ret; 2200 } 2201 sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2202 } 2203 2204 r = &env->vfp.pregs[FFR_PRED_NUM].p[0]; 2205 ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); 2206 if (ret) { 2207 return ret; 2208 } 2209 sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); 2210 2211 return 0; 2212 } 2213 2214 int kvm_arch_get_registers(CPUState *cs, Error **errp) 2215 { 2216 uint64_t val; 2217 unsigned int el; 2218 uint32_t fpr; 2219 int i, ret; 2220 2221 ARMCPU *cpu = ARM_CPU(cs); 2222 CPUARMState *env = &cpu->env; 2223 2224 for (i = 0; i < 31; i++) { 2225 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), 2226 &env->xregs[i]); 2227 if (ret) { 2228 return ret; 2229 } 2230 } 2231 2232 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); 2233 if (ret) { 2234 return ret; 2235 } 2236 2237 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); 2238 if (ret) { 2239 return ret; 2240 } 2241 2242 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); 2243 if (ret) { 2244 return ret; 2245 } 2246 2247 env->aarch64 = ((val & PSTATE_nRW) == 0); 2248 if (is_a64(env)) { 2249 pstate_write(env, val); 2250 } else { 2251 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 2252 } 2253 2254 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the 2255 * QEMU side we keep the current SP in xregs[31] as well. 2256 */ 2257 aarch64_restore_sp(env, 1); 2258 2259 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); 2260 if (ret) { 2261 return ret; 2262 } 2263 2264 /* If we are in AArch32 mode then we need to sync the AArch32 regs with the 2265 * incoming AArch64 regs received from 64-bit KVM. 2266 * We must perform this after all of the registers have been acquired from 2267 * the kernel. 2268 */ 2269 if (!is_a64(env)) { 2270 aarch64_sync_64_to_32(env); 2271 } 2272 2273 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); 2274 if (ret) { 2275 return ret; 2276 } 2277 2278 /* Fetch the SPSR registers 2279 * 2280 * KVM SPSRs 0-4 map to QEMU banks 1-5 2281 */ 2282 for (i = 0; i < KVM_NR_SPSR; i++) { 2283 ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), 2284 &env->banked_spsr[i + 1]); 2285 if (ret) { 2286 return ret; 2287 } 2288 } 2289 2290 el = arm_current_el(env); 2291 if (el > 0 && !is_a64(env)) { 2292 i = bank_number(env->uncached_cpsr & CPSR_M); 2293 env->spsr = env->banked_spsr[i]; 2294 } 2295 2296 if (cpu_isar_feature(aa64_sve, cpu)) { 2297 ret = kvm_arch_get_sve(cs); 2298 } else { 2299 ret = kvm_arch_get_fpsimd(cs); 2300 } 2301 if (ret) { 2302 return ret; 2303 } 2304 2305 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); 2306 if (ret) { 2307 return ret; 2308 } 2309 vfp_set_fpsr(env, fpr); 2310 2311 ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); 2312 if (ret) { 2313 return ret; 2314 } 2315 vfp_set_fpcr(env, fpr); 2316 2317 ret = kvm_get_vcpu_events(cpu); 2318 if (ret) { 2319 return ret; 2320 } 2321 2322 if (!write_kvmstate_to_list(cpu)) { 2323 return -EINVAL; 2324 } 2325 /* Note that it's OK to have registers which aren't in CPUState, 2326 * so we can ignore a failure return here. 2327 */ 2328 write_list_to_cpustate(cpu); 2329 2330 ret = kvm_arm_sync_mpstate_to_qemu(cpu); 2331 2332 /* TODO: other registers */ 2333 return ret; 2334 } 2335 2336 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) 2337 { 2338 ram_addr_t ram_addr; 2339 hwaddr paddr; 2340 2341 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); 2342 2343 if (acpi_ghes_present() && addr) { 2344 ram_addr = qemu_ram_addr_from_host(addr); 2345 if (ram_addr != RAM_ADDR_INVALID && 2346 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { 2347 kvm_hwpoison_page_add(ram_addr); 2348 /* 2349 * If this is a BUS_MCEERR_AR, we know we have been called 2350 * synchronously from the vCPU thread, so we can easily 2351 * synchronize the state and inject an error. 2352 * 2353 * TODO: we currently don't tell the guest at all about 2354 * BUS_MCEERR_AO. In that case we might either be being 2355 * called synchronously from the vCPU thread, or a bit 2356 * later from the main thread, so doing the injection of 2357 * the error would be more complicated. 2358 */ 2359 if (code == BUS_MCEERR_AR) { 2360 kvm_cpu_synchronize_state(c); 2361 if (!acpi_ghes_memory_errors(ACPI_HEST_SRC_ID_SEA, paddr)) { 2362 kvm_inject_arm_sea(c); 2363 } else { 2364 error_report("failed to record the error"); 2365 abort(); 2366 } 2367 } 2368 return; 2369 } 2370 if (code == BUS_MCEERR_AO) { 2371 error_report("Hardware memory error at addr %p for memory used by " 2372 "QEMU itself instead of guest system!", addr); 2373 } 2374 } 2375 2376 if (code == BUS_MCEERR_AR) { 2377 error_report("Hardware memory error!"); 2378 exit(1); 2379 } 2380 } 2381 2382 /* C6.6.29 BRK instruction */ 2383 static const uint32_t brk_insn = 0xd4200000; 2384 2385 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2386 { 2387 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 2388 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 2389 return -EINVAL; 2390 } 2391 return 0; 2392 } 2393 2394 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2395 { 2396 static uint32_t brk; 2397 2398 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || 2399 brk != brk_insn || 2400 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2401 return -EINVAL; 2402 } 2403 return 0; 2404 } 2405 2406 void kvm_arm_enable_mte(Object *cpuobj, Error **errp) 2407 { 2408 static bool tried_to_enable; 2409 static bool succeeded_to_enable; 2410 Error *mte_migration_blocker = NULL; 2411 ARMCPU *cpu = ARM_CPU(cpuobj); 2412 int ret; 2413 2414 if (!tried_to_enable) { 2415 /* 2416 * MTE on KVM is enabled on a per-VM basis (and retrying doesn't make 2417 * sense), and we only want a single migration blocker as well. 2418 */ 2419 tried_to_enable = true; 2420 2421 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_ARM_MTE, 0); 2422 if (ret) { 2423 error_setg_errno(errp, -ret, "Failed to enable KVM_CAP_ARM_MTE"); 2424 return; 2425 } 2426 2427 /* TODO: Add migration support with MTE enabled */ 2428 error_setg(&mte_migration_blocker, 2429 "Live migration disabled due to MTE enabled"); 2430 if (migrate_add_blocker(&mte_migration_blocker, errp)) { 2431 error_free(mte_migration_blocker); 2432 return; 2433 } 2434 2435 succeeded_to_enable = true; 2436 } 2437 2438 if (succeeded_to_enable) { 2439 cpu->kvm_mte = true; 2440 } 2441 } 2442 2443 void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) 2444 { 2445 ARMCPU *cpu = arm_cpu; 2446 CPUARMState *env = &cpu->env; 2447 CPUState *cs = CPU(cpu); 2448 uint32_t linestate_bit; 2449 int irq_id; 2450 2451 switch (irq) { 2452 case ARM_CPU_IRQ: 2453 irq_id = KVM_ARM_IRQ_CPU_IRQ; 2454 linestate_bit = CPU_INTERRUPT_HARD; 2455 break; 2456 case ARM_CPU_FIQ: 2457 irq_id = KVM_ARM_IRQ_CPU_FIQ; 2458 linestate_bit = CPU_INTERRUPT_FIQ; 2459 break; 2460 default: 2461 g_assert_not_reached(); 2462 } 2463 2464 if (level) { 2465 env->irq_line_state |= linestate_bit; 2466 } else { 2467 env->irq_line_state &= ~linestate_bit; 2468 } 2469 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 2470 } 2471