1 /* 2 * QEMU Hypervisor.framework support for Apple Silicon 3 4 * Copyright 2020 Alexander Graf <agraf@csgraf.de> 5 * Copyright 2020 Google LLC 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or later. 8 * See the COPYING file in the top-level directory. 9 * 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 #include "qemu/log.h" 15 16 #include "system/runstate.h" 17 #include "system/hvf.h" 18 #include "system/hvf_int.h" 19 #include "system/hw_accel.h" 20 #include "hvf_arm.h" 21 #include "cpregs.h" 22 23 #include <mach/mach_time.h> 24 25 #include "system/address-spaces.h" 26 #include "system/memory.h" 27 #include "hw/boards.h" 28 #include "hw/irq.h" 29 #include "qemu/main-loop.h" 30 #include "system/cpus.h" 31 #include "arm-powerctl.h" 32 #include "target/arm/cpu.h" 33 #include "target/arm/internals.h" 34 #include "target/arm/multiprocessing.h" 35 #include "target/arm/gtimer.h" 36 #include "trace.h" 37 #include "migration/vmstate.h" 38 39 #include "gdbstub/enums.h" 40 41 #define MDSCR_EL1_SS_SHIFT 0 42 #define MDSCR_EL1_MDE_SHIFT 15 43 44 static const uint16_t dbgbcr_regs[] = { 45 HV_SYS_REG_DBGBCR0_EL1, 46 HV_SYS_REG_DBGBCR1_EL1, 47 HV_SYS_REG_DBGBCR2_EL1, 48 HV_SYS_REG_DBGBCR3_EL1, 49 HV_SYS_REG_DBGBCR4_EL1, 50 HV_SYS_REG_DBGBCR5_EL1, 51 HV_SYS_REG_DBGBCR6_EL1, 52 HV_SYS_REG_DBGBCR7_EL1, 53 HV_SYS_REG_DBGBCR8_EL1, 54 HV_SYS_REG_DBGBCR9_EL1, 55 HV_SYS_REG_DBGBCR10_EL1, 56 HV_SYS_REG_DBGBCR11_EL1, 57 HV_SYS_REG_DBGBCR12_EL1, 58 HV_SYS_REG_DBGBCR13_EL1, 59 HV_SYS_REG_DBGBCR14_EL1, 60 HV_SYS_REG_DBGBCR15_EL1, 61 }; 62 63 static const uint16_t dbgbvr_regs[] = { 64 HV_SYS_REG_DBGBVR0_EL1, 65 HV_SYS_REG_DBGBVR1_EL1, 66 HV_SYS_REG_DBGBVR2_EL1, 67 HV_SYS_REG_DBGBVR3_EL1, 68 HV_SYS_REG_DBGBVR4_EL1, 69 HV_SYS_REG_DBGBVR5_EL1, 70 HV_SYS_REG_DBGBVR6_EL1, 71 HV_SYS_REG_DBGBVR7_EL1, 72 HV_SYS_REG_DBGBVR8_EL1, 73 HV_SYS_REG_DBGBVR9_EL1, 74 HV_SYS_REG_DBGBVR10_EL1, 75 HV_SYS_REG_DBGBVR11_EL1, 76 HV_SYS_REG_DBGBVR12_EL1, 77 HV_SYS_REG_DBGBVR13_EL1, 78 HV_SYS_REG_DBGBVR14_EL1, 79 HV_SYS_REG_DBGBVR15_EL1, 80 }; 81 82 static const uint16_t dbgwcr_regs[] = { 83 HV_SYS_REG_DBGWCR0_EL1, 84 HV_SYS_REG_DBGWCR1_EL1, 85 HV_SYS_REG_DBGWCR2_EL1, 86 HV_SYS_REG_DBGWCR3_EL1, 87 HV_SYS_REG_DBGWCR4_EL1, 88 HV_SYS_REG_DBGWCR5_EL1, 89 HV_SYS_REG_DBGWCR6_EL1, 90 HV_SYS_REG_DBGWCR7_EL1, 91 HV_SYS_REG_DBGWCR8_EL1, 92 HV_SYS_REG_DBGWCR9_EL1, 93 HV_SYS_REG_DBGWCR10_EL1, 94 HV_SYS_REG_DBGWCR11_EL1, 95 HV_SYS_REG_DBGWCR12_EL1, 96 HV_SYS_REG_DBGWCR13_EL1, 97 HV_SYS_REG_DBGWCR14_EL1, 98 HV_SYS_REG_DBGWCR15_EL1, 99 }; 100 101 static const uint16_t dbgwvr_regs[] = { 102 HV_SYS_REG_DBGWVR0_EL1, 103 HV_SYS_REG_DBGWVR1_EL1, 104 HV_SYS_REG_DBGWVR2_EL1, 105 HV_SYS_REG_DBGWVR3_EL1, 106 HV_SYS_REG_DBGWVR4_EL1, 107 HV_SYS_REG_DBGWVR5_EL1, 108 HV_SYS_REG_DBGWVR6_EL1, 109 HV_SYS_REG_DBGWVR7_EL1, 110 HV_SYS_REG_DBGWVR8_EL1, 111 HV_SYS_REG_DBGWVR9_EL1, 112 HV_SYS_REG_DBGWVR10_EL1, 113 HV_SYS_REG_DBGWVR11_EL1, 114 HV_SYS_REG_DBGWVR12_EL1, 115 HV_SYS_REG_DBGWVR13_EL1, 116 HV_SYS_REG_DBGWVR14_EL1, 117 HV_SYS_REG_DBGWVR15_EL1, 118 }; 119 120 static inline int hvf_arm_num_brps(hv_vcpu_config_t config) 121 { 122 uint64_t val; 123 hv_return_t ret; 124 ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1, 125 &val); 126 assert_hvf_ok(ret); 127 return FIELD_EX64(val, ID_AA64DFR0, BRPS) + 1; 128 } 129 130 static inline int hvf_arm_num_wrps(hv_vcpu_config_t config) 131 { 132 uint64_t val; 133 hv_return_t ret; 134 ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1, 135 &val); 136 assert_hvf_ok(ret); 137 return FIELD_EX64(val, ID_AA64DFR0, WRPS) + 1; 138 } 139 140 void hvf_arm_init_debug(void) 141 { 142 hv_vcpu_config_t config; 143 config = hv_vcpu_config_create(); 144 145 max_hw_bps = hvf_arm_num_brps(config); 146 hw_breakpoints = 147 g_array_sized_new(true, true, sizeof(HWBreakpoint), max_hw_bps); 148 149 max_hw_wps = hvf_arm_num_wrps(config); 150 hw_watchpoints = 151 g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); 152 } 153 154 #define HVF_SYSREG(crn, crm, op0, op1, op2) \ 155 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) 156 157 #define SYSREG_OP0_SHIFT 20 158 #define SYSREG_OP0_MASK 0x3 159 #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK) 160 #define SYSREG_OP1_SHIFT 14 161 #define SYSREG_OP1_MASK 0x7 162 #define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK) 163 #define SYSREG_CRN_SHIFT 10 164 #define SYSREG_CRN_MASK 0xf 165 #define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK) 166 #define SYSREG_CRM_SHIFT 1 167 #define SYSREG_CRM_MASK 0xf 168 #define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK) 169 #define SYSREG_OP2_SHIFT 17 170 #define SYSREG_OP2_MASK 0x7 171 #define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK) 172 173 #define SYSREG(op0, op1, crn, crm, op2) \ 174 ((op0 << SYSREG_OP0_SHIFT) | \ 175 (op1 << SYSREG_OP1_SHIFT) | \ 176 (crn << SYSREG_CRN_SHIFT) | \ 177 (crm << SYSREG_CRM_SHIFT) | \ 178 (op2 << SYSREG_OP2_SHIFT)) 179 #define SYSREG_MASK \ 180 SYSREG(SYSREG_OP0_MASK, \ 181 SYSREG_OP1_MASK, \ 182 SYSREG_CRN_MASK, \ 183 SYSREG_CRM_MASK, \ 184 SYSREG_OP2_MASK) 185 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) 186 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) 187 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) 188 #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) 189 #define SYSREG_CNTP_CTL_EL0 SYSREG(3, 3, 14, 2, 1) 190 #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0) 191 #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0) 192 #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1) 193 #define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2) 194 #define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2) 195 #define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3) 196 #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4) 197 #define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5) 198 #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) 199 #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) 200 #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) 201 #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) 202 203 #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) 204 #define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5) 205 #define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6) 206 #define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7) 207 #define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0) 208 #define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1) 209 #define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2) 210 #define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3) 211 #define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6) 212 #define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3) 213 #define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3) 214 #define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4) 215 #define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1) 216 #define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1) 217 #define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1) 218 #define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2) 219 #define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2) 220 #define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0) 221 #define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0) 222 #define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6) 223 #define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7) 224 #define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0) 225 #define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3) 226 #define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7) 227 #define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5) 228 #define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5) 229 230 #define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2) 231 #define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4) 232 #define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5) 233 #define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6) 234 #define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7) 235 #define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4) 236 #define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5) 237 #define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6) 238 #define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7) 239 #define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4) 240 #define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5) 241 #define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6) 242 #define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7) 243 #define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4) 244 #define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5) 245 #define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6) 246 #define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7) 247 #define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4) 248 #define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5) 249 #define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6) 250 #define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7) 251 #define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4) 252 #define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5) 253 #define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6) 254 #define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7) 255 #define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4) 256 #define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5) 257 #define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6) 258 #define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7) 259 #define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4) 260 #define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5) 261 #define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6) 262 #define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7) 263 #define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4) 264 #define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5) 265 #define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6) 266 #define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7) 267 #define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4) 268 #define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5) 269 #define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6) 270 #define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7) 271 #define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4) 272 #define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5) 273 #define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6) 274 #define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7) 275 #define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4) 276 #define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5) 277 #define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6) 278 #define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7) 279 #define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4) 280 #define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5) 281 #define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6) 282 #define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7) 283 #define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4) 284 #define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5) 285 #define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6) 286 #define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7) 287 #define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4) 288 #define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5) 289 #define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6) 290 #define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7) 291 #define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4) 292 #define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5) 293 #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6) 294 #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7) 295 296 #define WFX_IS_WFE (1 << 0) 297 298 #define TMR_CTL_ENABLE (1 << 0) 299 #define TMR_CTL_IMASK (1 << 1) 300 #define TMR_CTL_ISTATUS (1 << 2) 301 302 static void hvf_wfi(CPUState *cpu); 303 304 static uint32_t chosen_ipa_bit_size; 305 306 typedef struct HVFVTimer { 307 /* Vtimer value during migration and paused state */ 308 uint64_t vtimer_val; 309 } HVFVTimer; 310 311 static HVFVTimer vtimer; 312 313 typedef struct ARMHostCPUFeatures { 314 ARMISARegisters isar; 315 uint64_t features; 316 uint64_t midr; 317 uint32_t reset_sctlr; 318 const char *dtb_compatible; 319 } ARMHostCPUFeatures; 320 321 static ARMHostCPUFeatures arm_host_cpu_features; 322 323 struct hvf_reg_match { 324 int reg; 325 uint64_t offset; 326 }; 327 328 static const struct hvf_reg_match hvf_reg_match[] = { 329 { HV_REG_X0, offsetof(CPUARMState, xregs[0]) }, 330 { HV_REG_X1, offsetof(CPUARMState, xregs[1]) }, 331 { HV_REG_X2, offsetof(CPUARMState, xregs[2]) }, 332 { HV_REG_X3, offsetof(CPUARMState, xregs[3]) }, 333 { HV_REG_X4, offsetof(CPUARMState, xregs[4]) }, 334 { HV_REG_X5, offsetof(CPUARMState, xregs[5]) }, 335 { HV_REG_X6, offsetof(CPUARMState, xregs[6]) }, 336 { HV_REG_X7, offsetof(CPUARMState, xregs[7]) }, 337 { HV_REG_X8, offsetof(CPUARMState, xregs[8]) }, 338 { HV_REG_X9, offsetof(CPUARMState, xregs[9]) }, 339 { HV_REG_X10, offsetof(CPUARMState, xregs[10]) }, 340 { HV_REG_X11, offsetof(CPUARMState, xregs[11]) }, 341 { HV_REG_X12, offsetof(CPUARMState, xregs[12]) }, 342 { HV_REG_X13, offsetof(CPUARMState, xregs[13]) }, 343 { HV_REG_X14, offsetof(CPUARMState, xregs[14]) }, 344 { HV_REG_X15, offsetof(CPUARMState, xregs[15]) }, 345 { HV_REG_X16, offsetof(CPUARMState, xregs[16]) }, 346 { HV_REG_X17, offsetof(CPUARMState, xregs[17]) }, 347 { HV_REG_X18, offsetof(CPUARMState, xregs[18]) }, 348 { HV_REG_X19, offsetof(CPUARMState, xregs[19]) }, 349 { HV_REG_X20, offsetof(CPUARMState, xregs[20]) }, 350 { HV_REG_X21, offsetof(CPUARMState, xregs[21]) }, 351 { HV_REG_X22, offsetof(CPUARMState, xregs[22]) }, 352 { HV_REG_X23, offsetof(CPUARMState, xregs[23]) }, 353 { HV_REG_X24, offsetof(CPUARMState, xregs[24]) }, 354 { HV_REG_X25, offsetof(CPUARMState, xregs[25]) }, 355 { HV_REG_X26, offsetof(CPUARMState, xregs[26]) }, 356 { HV_REG_X27, offsetof(CPUARMState, xregs[27]) }, 357 { HV_REG_X28, offsetof(CPUARMState, xregs[28]) }, 358 { HV_REG_X29, offsetof(CPUARMState, xregs[29]) }, 359 { HV_REG_X30, offsetof(CPUARMState, xregs[30]) }, 360 { HV_REG_PC, offsetof(CPUARMState, pc) }, 361 }; 362 363 static const struct hvf_reg_match hvf_fpreg_match[] = { 364 { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) }, 365 { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) }, 366 { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) }, 367 { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) }, 368 { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) }, 369 { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) }, 370 { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) }, 371 { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) }, 372 { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) }, 373 { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) }, 374 { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) }, 375 { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) }, 376 { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) }, 377 { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) }, 378 { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) }, 379 { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) }, 380 { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) }, 381 { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) }, 382 { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) }, 383 { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) }, 384 { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) }, 385 { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) }, 386 { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) }, 387 { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) }, 388 { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) }, 389 { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) }, 390 { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) }, 391 { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) }, 392 { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) }, 393 { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) }, 394 { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) }, 395 { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, 396 }; 397 398 struct hvf_sreg_match { 399 int reg; 400 uint32_t key; 401 uint32_t cp_idx; 402 }; 403 404 static struct hvf_sreg_match hvf_sreg_match[] = { 405 { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 4) }, 406 { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 5) }, 407 { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 2, 0, 6) }, 408 { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 2, 0, 7) }, 409 410 { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 4) }, 411 { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 5) }, 412 { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 2, 0, 6) }, 413 { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 2, 0, 7) }, 414 415 { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 4) }, 416 { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 5) }, 417 { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 2, 0, 6) }, 418 { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 2, 0, 7) }, 419 420 { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 4) }, 421 { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 5) }, 422 { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 2, 0, 6) }, 423 { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 2, 0, 7) }, 424 425 { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 4) }, 426 { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 5) }, 427 { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 2, 0, 6) }, 428 { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 2, 0, 7) }, 429 430 { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 4) }, 431 { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 5) }, 432 { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 2, 0, 6) }, 433 { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 2, 0, 7) }, 434 435 { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 4) }, 436 { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 5) }, 437 { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 2, 0, 6) }, 438 { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 2, 0, 7) }, 439 440 { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 4) }, 441 { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 5) }, 442 { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 2, 0, 6) }, 443 { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 2, 0, 7) }, 444 445 { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 4) }, 446 { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 5) }, 447 { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 2, 0, 6) }, 448 { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 2, 0, 7) }, 449 450 { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 4) }, 451 { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 5) }, 452 { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 2, 0, 6) }, 453 { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 2, 0, 7) }, 454 455 { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 4) }, 456 { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 5) }, 457 { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 2, 0, 6) }, 458 { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 2, 0, 7) }, 459 460 { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 4) }, 461 { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 5) }, 462 { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 2, 0, 6) }, 463 { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 2, 0, 7) }, 464 465 { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 4) }, 466 { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 5) }, 467 { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 2, 0, 6) }, 468 { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 2, 0, 7) }, 469 470 { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 4) }, 471 { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 5) }, 472 { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 2, 0, 6) }, 473 { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 2, 0, 7) }, 474 475 { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 4) }, 476 { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 5) }, 477 { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 2, 0, 6) }, 478 { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 2, 0, 7) }, 479 480 { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 4) }, 481 { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 5) }, 482 { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 2, 0, 6) }, 483 { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 2, 0, 7) }, 484 485 #ifdef SYNC_NO_RAW_REGS 486 /* 487 * The registers below are manually synced on init because they are 488 * marked as NO_RAW. We still list them to make number space sync easier. 489 */ 490 { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, 491 { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, 492 { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, 493 { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, 494 #endif 495 { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 1) }, 496 { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, 497 { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, 498 { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, 499 { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, 500 #ifdef SYNC_NO_MMFR0 501 /* We keep the hardware MMFR0 around. HW limits are there anyway */ 502 { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, 503 #endif 504 { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, 505 { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, 506 /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ 507 508 { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, 509 { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, 510 { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, 511 { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, 512 { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, 513 { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, 514 515 { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, 516 { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, 517 { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, 518 { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, 519 { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, 520 { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, 521 { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, 522 { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, 523 { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, 524 { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, 525 526 { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, 527 { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, 528 { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, 529 { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, 530 { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, 531 { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, 532 { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, 533 { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, 534 { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, 535 { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, 536 { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, 537 { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, 538 { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, 539 { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, 540 { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, 541 { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, 542 { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, 543 { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, 544 { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, 545 { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, 546 }; 547 548 int hvf_get_registers(CPUState *cpu) 549 { 550 ARMCPU *arm_cpu = ARM_CPU(cpu); 551 CPUARMState *env = &arm_cpu->env; 552 hv_return_t ret; 553 uint64_t val; 554 hv_simd_fp_uchar16_t fpval; 555 int i; 556 557 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 558 ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val); 559 *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; 560 assert_hvf_ok(ret); 561 } 562 563 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 564 ret = hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, 565 &fpval); 566 memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval)); 567 assert_hvf_ok(ret); 568 } 569 570 val = 0; 571 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); 572 assert_hvf_ok(ret); 573 vfp_set_fpcr(env, val); 574 575 val = 0; 576 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); 577 assert_hvf_ok(ret); 578 vfp_set_fpsr(env, val); 579 580 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); 581 assert_hvf_ok(ret); 582 pstate_write(env, val); 583 584 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 585 if (hvf_sreg_match[i].cp_idx == -1) { 586 continue; 587 } 588 589 if (cpu->accel->guest_debug_enabled) { 590 /* Handle debug registers */ 591 switch (hvf_sreg_match[i].reg) { 592 case HV_SYS_REG_DBGBVR0_EL1: 593 case HV_SYS_REG_DBGBCR0_EL1: 594 case HV_SYS_REG_DBGWVR0_EL1: 595 case HV_SYS_REG_DBGWCR0_EL1: 596 case HV_SYS_REG_DBGBVR1_EL1: 597 case HV_SYS_REG_DBGBCR1_EL1: 598 case HV_SYS_REG_DBGWVR1_EL1: 599 case HV_SYS_REG_DBGWCR1_EL1: 600 case HV_SYS_REG_DBGBVR2_EL1: 601 case HV_SYS_REG_DBGBCR2_EL1: 602 case HV_SYS_REG_DBGWVR2_EL1: 603 case HV_SYS_REG_DBGWCR2_EL1: 604 case HV_SYS_REG_DBGBVR3_EL1: 605 case HV_SYS_REG_DBGBCR3_EL1: 606 case HV_SYS_REG_DBGWVR3_EL1: 607 case HV_SYS_REG_DBGWCR3_EL1: 608 case HV_SYS_REG_DBGBVR4_EL1: 609 case HV_SYS_REG_DBGBCR4_EL1: 610 case HV_SYS_REG_DBGWVR4_EL1: 611 case HV_SYS_REG_DBGWCR4_EL1: 612 case HV_SYS_REG_DBGBVR5_EL1: 613 case HV_SYS_REG_DBGBCR5_EL1: 614 case HV_SYS_REG_DBGWVR5_EL1: 615 case HV_SYS_REG_DBGWCR5_EL1: 616 case HV_SYS_REG_DBGBVR6_EL1: 617 case HV_SYS_REG_DBGBCR6_EL1: 618 case HV_SYS_REG_DBGWVR6_EL1: 619 case HV_SYS_REG_DBGWCR6_EL1: 620 case HV_SYS_REG_DBGBVR7_EL1: 621 case HV_SYS_REG_DBGBCR7_EL1: 622 case HV_SYS_REG_DBGWVR7_EL1: 623 case HV_SYS_REG_DBGWCR7_EL1: 624 case HV_SYS_REG_DBGBVR8_EL1: 625 case HV_SYS_REG_DBGBCR8_EL1: 626 case HV_SYS_REG_DBGWVR8_EL1: 627 case HV_SYS_REG_DBGWCR8_EL1: 628 case HV_SYS_REG_DBGBVR9_EL1: 629 case HV_SYS_REG_DBGBCR9_EL1: 630 case HV_SYS_REG_DBGWVR9_EL1: 631 case HV_SYS_REG_DBGWCR9_EL1: 632 case HV_SYS_REG_DBGBVR10_EL1: 633 case HV_SYS_REG_DBGBCR10_EL1: 634 case HV_SYS_REG_DBGWVR10_EL1: 635 case HV_SYS_REG_DBGWCR10_EL1: 636 case HV_SYS_REG_DBGBVR11_EL1: 637 case HV_SYS_REG_DBGBCR11_EL1: 638 case HV_SYS_REG_DBGWVR11_EL1: 639 case HV_SYS_REG_DBGWCR11_EL1: 640 case HV_SYS_REG_DBGBVR12_EL1: 641 case HV_SYS_REG_DBGBCR12_EL1: 642 case HV_SYS_REG_DBGWVR12_EL1: 643 case HV_SYS_REG_DBGWCR12_EL1: 644 case HV_SYS_REG_DBGBVR13_EL1: 645 case HV_SYS_REG_DBGBCR13_EL1: 646 case HV_SYS_REG_DBGWVR13_EL1: 647 case HV_SYS_REG_DBGWCR13_EL1: 648 case HV_SYS_REG_DBGBVR14_EL1: 649 case HV_SYS_REG_DBGBCR14_EL1: 650 case HV_SYS_REG_DBGWVR14_EL1: 651 case HV_SYS_REG_DBGWCR14_EL1: 652 case HV_SYS_REG_DBGBVR15_EL1: 653 case HV_SYS_REG_DBGBCR15_EL1: 654 case HV_SYS_REG_DBGWVR15_EL1: 655 case HV_SYS_REG_DBGWCR15_EL1: { 656 /* 657 * If the guest is being debugged, the vCPU's debug registers 658 * are holding the gdbstub's view of the registers (set in 659 * hvf_arch_update_guest_debug()). 660 * Since the environment is used to store only the guest's view 661 * of the registers, don't update it with the values from the 662 * vCPU but simply keep the values from the previous 663 * environment. 664 */ 665 const ARMCPRegInfo *ri; 666 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key); 667 val = read_raw_cp_reg(env, ri); 668 669 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 670 continue; 671 } 672 } 673 } 674 675 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val); 676 assert_hvf_ok(ret); 677 678 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 679 } 680 assert(write_list_to_cpustate(arm_cpu)); 681 682 aarch64_restore_sp(env, arm_current_el(env)); 683 684 return 0; 685 } 686 687 int hvf_put_registers(CPUState *cpu) 688 { 689 ARMCPU *arm_cpu = ARM_CPU(cpu); 690 CPUARMState *env = &arm_cpu->env; 691 hv_return_t ret; 692 uint64_t val; 693 hv_simd_fp_uchar16_t fpval; 694 int i; 695 696 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 697 val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset); 698 ret = hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); 699 assert_hvf_ok(ret); 700 } 701 702 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 703 memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval)); 704 ret = hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, 705 fpval); 706 assert_hvf_ok(ret); 707 } 708 709 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)); 710 assert_hvf_ok(ret); 711 712 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env)); 713 assert_hvf_ok(ret); 714 715 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env)); 716 assert_hvf_ok(ret); 717 718 aarch64_save_sp(env, arm_current_el(env)); 719 720 assert(write_cpustate_to_list(arm_cpu, false)); 721 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 722 if (hvf_sreg_match[i].cp_idx == -1) { 723 continue; 724 } 725 726 if (cpu->accel->guest_debug_enabled) { 727 /* Handle debug registers */ 728 switch (hvf_sreg_match[i].reg) { 729 case HV_SYS_REG_DBGBVR0_EL1: 730 case HV_SYS_REG_DBGBCR0_EL1: 731 case HV_SYS_REG_DBGWVR0_EL1: 732 case HV_SYS_REG_DBGWCR0_EL1: 733 case HV_SYS_REG_DBGBVR1_EL1: 734 case HV_SYS_REG_DBGBCR1_EL1: 735 case HV_SYS_REG_DBGWVR1_EL1: 736 case HV_SYS_REG_DBGWCR1_EL1: 737 case HV_SYS_REG_DBGBVR2_EL1: 738 case HV_SYS_REG_DBGBCR2_EL1: 739 case HV_SYS_REG_DBGWVR2_EL1: 740 case HV_SYS_REG_DBGWCR2_EL1: 741 case HV_SYS_REG_DBGBVR3_EL1: 742 case HV_SYS_REG_DBGBCR3_EL1: 743 case HV_SYS_REG_DBGWVR3_EL1: 744 case HV_SYS_REG_DBGWCR3_EL1: 745 case HV_SYS_REG_DBGBVR4_EL1: 746 case HV_SYS_REG_DBGBCR4_EL1: 747 case HV_SYS_REG_DBGWVR4_EL1: 748 case HV_SYS_REG_DBGWCR4_EL1: 749 case HV_SYS_REG_DBGBVR5_EL1: 750 case HV_SYS_REG_DBGBCR5_EL1: 751 case HV_SYS_REG_DBGWVR5_EL1: 752 case HV_SYS_REG_DBGWCR5_EL1: 753 case HV_SYS_REG_DBGBVR6_EL1: 754 case HV_SYS_REG_DBGBCR6_EL1: 755 case HV_SYS_REG_DBGWVR6_EL1: 756 case HV_SYS_REG_DBGWCR6_EL1: 757 case HV_SYS_REG_DBGBVR7_EL1: 758 case HV_SYS_REG_DBGBCR7_EL1: 759 case HV_SYS_REG_DBGWVR7_EL1: 760 case HV_SYS_REG_DBGWCR7_EL1: 761 case HV_SYS_REG_DBGBVR8_EL1: 762 case HV_SYS_REG_DBGBCR8_EL1: 763 case HV_SYS_REG_DBGWVR8_EL1: 764 case HV_SYS_REG_DBGWCR8_EL1: 765 case HV_SYS_REG_DBGBVR9_EL1: 766 case HV_SYS_REG_DBGBCR9_EL1: 767 case HV_SYS_REG_DBGWVR9_EL1: 768 case HV_SYS_REG_DBGWCR9_EL1: 769 case HV_SYS_REG_DBGBVR10_EL1: 770 case HV_SYS_REG_DBGBCR10_EL1: 771 case HV_SYS_REG_DBGWVR10_EL1: 772 case HV_SYS_REG_DBGWCR10_EL1: 773 case HV_SYS_REG_DBGBVR11_EL1: 774 case HV_SYS_REG_DBGBCR11_EL1: 775 case HV_SYS_REG_DBGWVR11_EL1: 776 case HV_SYS_REG_DBGWCR11_EL1: 777 case HV_SYS_REG_DBGBVR12_EL1: 778 case HV_SYS_REG_DBGBCR12_EL1: 779 case HV_SYS_REG_DBGWVR12_EL1: 780 case HV_SYS_REG_DBGWCR12_EL1: 781 case HV_SYS_REG_DBGBVR13_EL1: 782 case HV_SYS_REG_DBGBCR13_EL1: 783 case HV_SYS_REG_DBGWVR13_EL1: 784 case HV_SYS_REG_DBGWCR13_EL1: 785 case HV_SYS_REG_DBGBVR14_EL1: 786 case HV_SYS_REG_DBGBCR14_EL1: 787 case HV_SYS_REG_DBGWVR14_EL1: 788 case HV_SYS_REG_DBGWCR14_EL1: 789 case HV_SYS_REG_DBGBVR15_EL1: 790 case HV_SYS_REG_DBGBCR15_EL1: 791 case HV_SYS_REG_DBGWVR15_EL1: 792 case HV_SYS_REG_DBGWCR15_EL1: 793 /* 794 * If the guest is being debugged, the vCPU's debug registers 795 * are already holding the gdbstub's view of the registers (set 796 * in hvf_arch_update_guest_debug()). 797 */ 798 continue; 799 } 800 } 801 802 val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; 803 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val); 804 assert_hvf_ok(ret); 805 } 806 807 ret = hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_offset); 808 assert_hvf_ok(ret); 809 810 return 0; 811 } 812 813 static void flush_cpu_state(CPUState *cpu) 814 { 815 if (cpu->accel->dirty) { 816 hvf_put_registers(cpu); 817 cpu->accel->dirty = false; 818 } 819 } 820 821 static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) 822 { 823 hv_return_t r; 824 825 flush_cpu_state(cpu); 826 827 if (rt < 31) { 828 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val); 829 assert_hvf_ok(r); 830 } 831 } 832 833 static uint64_t hvf_get_reg(CPUState *cpu, int rt) 834 { 835 uint64_t val = 0; 836 hv_return_t r; 837 838 flush_cpu_state(cpu); 839 840 if (rt < 31) { 841 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val); 842 assert_hvf_ok(r); 843 } 844 845 return val; 846 } 847 848 static void clamp_id_aa64mmfr0_parange_to_ipa_size(uint64_t *id_aa64mmfr0) 849 { 850 uint32_t ipa_size = chosen_ipa_bit_size ? 851 chosen_ipa_bit_size : hvf_arm_get_max_ipa_bit_size(); 852 853 /* Clamp down the PARange to the IPA size the kernel supports. */ 854 uint8_t index = round_down_to_parange_index(ipa_size); 855 *id_aa64mmfr0 = (*id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index; 856 } 857 858 static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 859 { 860 ARMISARegisters host_isar = {}; 861 const struct isar_regs { 862 int reg; 863 uint64_t *val; 864 } regs[] = { 865 { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, 866 { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, 867 { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, 868 { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, 869 { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, 870 { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, 871 /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ 872 { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, 873 { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, 874 { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, 875 /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ 876 }; 877 hv_vcpu_t fd; 878 hv_return_t r = HV_SUCCESS; 879 hv_vcpu_exit_t *exit; 880 int i; 881 882 ahcf->dtb_compatible = "arm,arm-v8"; 883 ahcf->features = (1ULL << ARM_FEATURE_V8) | 884 (1ULL << ARM_FEATURE_NEON) | 885 (1ULL << ARM_FEATURE_AARCH64) | 886 (1ULL << ARM_FEATURE_PMU) | 887 (1ULL << ARM_FEATURE_GENERIC_TIMER); 888 889 /* We set up a small vcpu to extract host registers */ 890 891 if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { 892 return false; 893 } 894 895 for (i = 0; i < ARRAY_SIZE(regs); i++) { 896 r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); 897 } 898 r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); 899 r |= hv_vcpu_destroy(fd); 900 901 clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar.id_aa64mmfr0); 902 903 /* 904 * Disable SME, which is not properly handled by QEMU hvf yet. 905 * To allow this through we would need to: 906 * - make sure that the SME state is correctly handled in the 907 * get_registers/put_registers functions 908 * - get the SME-specific CPU properties to work with accelerators 909 * other than TCG 910 * - fix any assumptions we made that SME implies SVE (since 911 * on the M4 there is SME but not SVE) 912 */ 913 host_isar.id_aa64pfr1 &= ~R_ID_AA64PFR1_SME_MASK; 914 915 ahcf->isar = host_isar; 916 917 /* 918 * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1 919 * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97 920 */ 921 ahcf->reset_sctlr = 0x30100180; 922 /* 923 * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility, 924 * let's disable it on boot and then allow guest software to turn it on by 925 * setting it to 0. 926 */ 927 ahcf->reset_sctlr |= 0x00800000; 928 929 /* Make sure we don't advertise AArch32 support for EL0/EL1 */ 930 if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) { 931 return false; 932 } 933 934 return r == HV_SUCCESS; 935 } 936 937 uint32_t hvf_arm_get_default_ipa_bit_size(void) 938 { 939 uint32_t default_ipa_size; 940 hv_return_t ret = hv_vm_config_get_default_ipa_size(&default_ipa_size); 941 assert_hvf_ok(ret); 942 943 return default_ipa_size; 944 } 945 946 uint32_t hvf_arm_get_max_ipa_bit_size(void) 947 { 948 uint32_t max_ipa_size; 949 hv_return_t ret = hv_vm_config_get_max_ipa_size(&max_ipa_size); 950 assert_hvf_ok(ret); 951 952 /* 953 * We clamp any IPA size we want to back the VM with to a valid PARange 954 * value so the guest doesn't try and map memory outside of the valid range. 955 * This logic just clamps the passed in IPA bit size to the first valid 956 * PARange value <= to it. 957 */ 958 return round_down_to_parange_bit_size(max_ipa_size); 959 } 960 961 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) 962 { 963 if (!arm_host_cpu_features.dtb_compatible) { 964 if (!hvf_enabled() || 965 !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) { 966 /* 967 * We can't report this error yet, so flag that we need to 968 * in arm_cpu_realizefn(). 969 */ 970 cpu->host_cpu_probe_failed = true; 971 return; 972 } 973 } 974 975 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 976 cpu->isar = arm_host_cpu_features.isar; 977 cpu->env.features = arm_host_cpu_features.features; 978 cpu->midr = arm_host_cpu_features.midr; 979 cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; 980 } 981 982 void hvf_arch_vcpu_destroy(CPUState *cpu) 983 { 984 } 985 986 hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range) 987 { 988 hv_return_t ret; 989 hv_vm_config_t config = hv_vm_config_create(); 990 991 ret = hv_vm_config_set_ipa_size(config, pa_range); 992 if (ret != HV_SUCCESS) { 993 goto cleanup; 994 } 995 chosen_ipa_bit_size = pa_range; 996 997 ret = hv_vm_create(config); 998 999 cleanup: 1000 os_release(config); 1001 1002 return ret; 1003 } 1004 1005 int hvf_arch_init_vcpu(CPUState *cpu) 1006 { 1007 ARMCPU *arm_cpu = ARM_CPU(cpu); 1008 CPUARMState *env = &arm_cpu->env; 1009 uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); 1010 uint32_t sregs_cnt = 0; 1011 uint64_t pfr; 1012 hv_return_t ret; 1013 int i; 1014 1015 env->aarch64 = true; 1016 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); 1017 1018 /* Allocate enough space for our sysreg sync */ 1019 arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, 1020 sregs_match_len); 1021 arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, 1022 sregs_match_len); 1023 arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, 1024 arm_cpu->cpreg_vmstate_indexes, 1025 sregs_match_len); 1026 arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, 1027 arm_cpu->cpreg_vmstate_values, 1028 sregs_match_len); 1029 1030 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); 1031 1032 /* Populate cp list for all known sysregs */ 1033 for (i = 0; i < sregs_match_len; i++) { 1034 const ARMCPRegInfo *ri; 1035 uint32_t key = hvf_sreg_match[i].key; 1036 1037 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); 1038 if (ri) { 1039 assert(!(ri->type & ARM_CP_NO_RAW)); 1040 hvf_sreg_match[i].cp_idx = sregs_cnt; 1041 arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); 1042 } else { 1043 hvf_sreg_match[i].cp_idx = -1; 1044 } 1045 } 1046 arm_cpu->cpreg_array_len = sregs_cnt; 1047 arm_cpu->cpreg_vmstate_array_len = sregs_cnt; 1048 1049 assert(write_cpustate_to_list(arm_cpu, false)); 1050 1051 /* Set CP_NO_RAW system registers on init */ 1052 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, 1053 arm_cpu->midr); 1054 assert_hvf_ok(ret); 1055 1056 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, 1057 arm_cpu->mp_affinity); 1058 assert_hvf_ok(ret); 1059 1060 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); 1061 assert_hvf_ok(ret); 1062 pfr |= env->gicv3state ? (1 << 24) : 0; 1063 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); 1064 assert_hvf_ok(ret); 1065 1066 /* We're limited to underlying hardware caps, override internal versions */ 1067 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, 1068 &arm_cpu->isar.id_aa64mmfr0); 1069 assert_hvf_ok(ret); 1070 1071 clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar.id_aa64mmfr0); 1072 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, 1073 arm_cpu->isar.id_aa64mmfr0); 1074 assert_hvf_ok(ret); 1075 1076 return 0; 1077 } 1078 1079 void hvf_kick_vcpu_thread(CPUState *cpu) 1080 { 1081 cpus_kick_thread(cpu); 1082 hv_vcpus_exit(&cpu->accel->fd, 1); 1083 } 1084 1085 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, 1086 uint32_t syndrome) 1087 { 1088 ARMCPU *arm_cpu = ARM_CPU(cpu); 1089 CPUARMState *env = &arm_cpu->env; 1090 1091 cpu->exception_index = excp; 1092 env->exception.target_el = 1; 1093 env->exception.syndrome = syndrome; 1094 1095 arm_cpu_do_interrupt(cpu); 1096 } 1097 1098 static void hvf_psci_cpu_off(ARMCPU *arm_cpu) 1099 { 1100 int32_t ret = arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu)); 1101 assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); 1102 } 1103 1104 /* 1105 * Handle a PSCI call. 1106 * 1107 * Returns 0 on success 1108 * -1 when the PSCI call is unknown, 1109 */ 1110 static bool hvf_handle_psci_call(CPUState *cpu) 1111 { 1112 ARMCPU *arm_cpu = ARM_CPU(cpu); 1113 CPUARMState *env = &arm_cpu->env; 1114 uint64_t param[4] = { 1115 env->xregs[0], 1116 env->xregs[1], 1117 env->xregs[2], 1118 env->xregs[3] 1119 }; 1120 uint64_t context_id, mpidr; 1121 bool target_aarch64 = true; 1122 CPUState *target_cpu_state; 1123 ARMCPU *target_cpu; 1124 target_ulong entry; 1125 int target_el = 1; 1126 int32_t ret = 0; 1127 1128 trace_hvf_psci_call(param[0], param[1], param[2], param[3], 1129 arm_cpu_mp_affinity(arm_cpu)); 1130 1131 switch (param[0]) { 1132 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 1133 ret = QEMU_PSCI_VERSION_1_1; 1134 break; 1135 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 1136 ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ 1137 break; 1138 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 1139 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 1140 mpidr = param[1]; 1141 1142 switch (param[2]) { 1143 case 0: 1144 target_cpu_state = arm_get_cpu_by_id(mpidr); 1145 if (!target_cpu_state) { 1146 ret = QEMU_PSCI_RET_INVALID_PARAMS; 1147 break; 1148 } 1149 target_cpu = ARM_CPU(target_cpu_state); 1150 1151 ret = target_cpu->power_state; 1152 break; 1153 default: 1154 /* Everything above affinity level 0 is always on. */ 1155 ret = 0; 1156 } 1157 break; 1158 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 1159 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1160 /* 1161 * QEMU reset and shutdown are async requests, but PSCI 1162 * mandates that we never return from the reset/shutdown 1163 * call, so power the CPU off now so it doesn't execute 1164 * anything further. 1165 */ 1166 hvf_psci_cpu_off(arm_cpu); 1167 break; 1168 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 1169 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1170 hvf_psci_cpu_off(arm_cpu); 1171 break; 1172 case QEMU_PSCI_0_1_FN_CPU_ON: 1173 case QEMU_PSCI_0_2_FN_CPU_ON: 1174 case QEMU_PSCI_0_2_FN64_CPU_ON: 1175 mpidr = param[1]; 1176 entry = param[2]; 1177 context_id = param[3]; 1178 ret = arm_set_cpu_on(mpidr, entry, context_id, 1179 target_el, target_aarch64); 1180 break; 1181 case QEMU_PSCI_0_1_FN_CPU_OFF: 1182 case QEMU_PSCI_0_2_FN_CPU_OFF: 1183 hvf_psci_cpu_off(arm_cpu); 1184 break; 1185 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 1186 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 1187 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 1188 /* Affinity levels are not supported in QEMU */ 1189 if (param[1] & 0xfffe0000) { 1190 ret = QEMU_PSCI_RET_INVALID_PARAMS; 1191 break; 1192 } 1193 /* Powerdown is not supported, we always go into WFI */ 1194 env->xregs[0] = 0; 1195 hvf_wfi(cpu); 1196 break; 1197 case QEMU_PSCI_0_1_FN_MIGRATE: 1198 case QEMU_PSCI_0_2_FN_MIGRATE: 1199 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 1200 break; 1201 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 1202 switch (param[1]) { 1203 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 1204 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 1205 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 1206 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 1207 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 1208 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 1209 case QEMU_PSCI_0_1_FN_CPU_ON: 1210 case QEMU_PSCI_0_2_FN_CPU_ON: 1211 case QEMU_PSCI_0_2_FN64_CPU_ON: 1212 case QEMU_PSCI_0_1_FN_CPU_OFF: 1213 case QEMU_PSCI_0_2_FN_CPU_OFF: 1214 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 1215 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 1216 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 1217 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 1218 ret = 0; 1219 break; 1220 case QEMU_PSCI_0_1_FN_MIGRATE: 1221 case QEMU_PSCI_0_2_FN_MIGRATE: 1222 default: 1223 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 1224 } 1225 break; 1226 default: 1227 return false; 1228 } 1229 1230 env->xregs[0] = ret; 1231 return true; 1232 } 1233 1234 static bool is_id_sysreg(uint32_t reg) 1235 { 1236 return SYSREG_OP0(reg) == 3 && 1237 SYSREG_OP1(reg) == 0 && 1238 SYSREG_CRN(reg) == 0 && 1239 SYSREG_CRM(reg) >= 1 && 1240 SYSREG_CRM(reg) < 8; 1241 } 1242 1243 static uint32_t hvf_reg2cp_reg(uint32_t reg) 1244 { 1245 return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, 1246 (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, 1247 (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, 1248 (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, 1249 (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, 1250 (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); 1251 } 1252 1253 static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) 1254 { 1255 ARMCPU *arm_cpu = ARM_CPU(cpu); 1256 CPUARMState *env = &arm_cpu->env; 1257 const ARMCPRegInfo *ri; 1258 1259 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1260 if (ri) { 1261 if (ri->accessfn) { 1262 if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) { 1263 return false; 1264 } 1265 } 1266 if (ri->type & ARM_CP_CONST) { 1267 *val = ri->resetvalue; 1268 } else if (ri->readfn) { 1269 *val = ri->readfn(env, ri); 1270 } else { 1271 *val = CPREG_FIELD64(env, ri); 1272 } 1273 trace_hvf_vgic_read(ri->name, *val); 1274 return true; 1275 } 1276 1277 return false; 1278 } 1279 1280 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val) 1281 { 1282 ARMCPU *arm_cpu = ARM_CPU(cpu); 1283 CPUARMState *env = &arm_cpu->env; 1284 1285 if (arm_feature(env, ARM_FEATURE_PMU)) { 1286 switch (reg) { 1287 case SYSREG_PMCR_EL0: 1288 *val = env->cp15.c9_pmcr; 1289 return 0; 1290 case SYSREG_PMCCNTR_EL0: 1291 pmu_op_start(env); 1292 *val = env->cp15.c15_ccnt; 1293 pmu_op_finish(env); 1294 return 0; 1295 case SYSREG_PMCNTENCLR_EL0: 1296 *val = env->cp15.c9_pmcnten; 1297 return 0; 1298 case SYSREG_PMOVSCLR_EL0: 1299 *val = env->cp15.c9_pmovsr; 1300 return 0; 1301 case SYSREG_PMSELR_EL0: 1302 *val = env->cp15.c9_pmselr; 1303 return 0; 1304 case SYSREG_PMINTENCLR_EL1: 1305 *val = env->cp15.c9_pminten; 1306 return 0; 1307 case SYSREG_PMCCFILTR_EL0: 1308 *val = env->cp15.pmccfiltr_el0; 1309 return 0; 1310 case SYSREG_PMCNTENSET_EL0: 1311 *val = env->cp15.c9_pmcnten; 1312 return 0; 1313 case SYSREG_PMUSERENR_EL0: 1314 *val = env->cp15.c9_pmuserenr; 1315 return 0; 1316 case SYSREG_PMCEID0_EL0: 1317 case SYSREG_PMCEID1_EL0: 1318 /* We can't really count anything yet, declare all events invalid */ 1319 *val = 0; 1320 return 0; 1321 } 1322 } 1323 1324 switch (reg) { 1325 case SYSREG_CNTPCT_EL0: 1326 *val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 1327 gt_cntfrq_period_ns(arm_cpu); 1328 return 0; 1329 case SYSREG_OSLSR_EL1: 1330 *val = env->cp15.oslsr_el1; 1331 return 0; 1332 case SYSREG_OSDLR_EL1: 1333 /* Dummy register */ 1334 return 0; 1335 case SYSREG_ICC_AP0R0_EL1: 1336 case SYSREG_ICC_AP0R1_EL1: 1337 case SYSREG_ICC_AP0R2_EL1: 1338 case SYSREG_ICC_AP0R3_EL1: 1339 case SYSREG_ICC_AP1R0_EL1: 1340 case SYSREG_ICC_AP1R1_EL1: 1341 case SYSREG_ICC_AP1R2_EL1: 1342 case SYSREG_ICC_AP1R3_EL1: 1343 case SYSREG_ICC_ASGI1R_EL1: 1344 case SYSREG_ICC_BPR0_EL1: 1345 case SYSREG_ICC_BPR1_EL1: 1346 case SYSREG_ICC_DIR_EL1: 1347 case SYSREG_ICC_EOIR0_EL1: 1348 case SYSREG_ICC_EOIR1_EL1: 1349 case SYSREG_ICC_HPPIR0_EL1: 1350 case SYSREG_ICC_HPPIR1_EL1: 1351 case SYSREG_ICC_IAR0_EL1: 1352 case SYSREG_ICC_IAR1_EL1: 1353 case SYSREG_ICC_IGRPEN0_EL1: 1354 case SYSREG_ICC_IGRPEN1_EL1: 1355 case SYSREG_ICC_PMR_EL1: 1356 case SYSREG_ICC_SGI0R_EL1: 1357 case SYSREG_ICC_SGI1R_EL1: 1358 case SYSREG_ICC_SRE_EL1: 1359 case SYSREG_ICC_CTLR_EL1: 1360 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1361 if (hvf_sysreg_read_cp(cpu, reg, val)) { 1362 return 0; 1363 } 1364 break; 1365 case SYSREG_DBGBVR0_EL1: 1366 case SYSREG_DBGBVR1_EL1: 1367 case SYSREG_DBGBVR2_EL1: 1368 case SYSREG_DBGBVR3_EL1: 1369 case SYSREG_DBGBVR4_EL1: 1370 case SYSREG_DBGBVR5_EL1: 1371 case SYSREG_DBGBVR6_EL1: 1372 case SYSREG_DBGBVR7_EL1: 1373 case SYSREG_DBGBVR8_EL1: 1374 case SYSREG_DBGBVR9_EL1: 1375 case SYSREG_DBGBVR10_EL1: 1376 case SYSREG_DBGBVR11_EL1: 1377 case SYSREG_DBGBVR12_EL1: 1378 case SYSREG_DBGBVR13_EL1: 1379 case SYSREG_DBGBVR14_EL1: 1380 case SYSREG_DBGBVR15_EL1: 1381 *val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; 1382 return 0; 1383 case SYSREG_DBGBCR0_EL1: 1384 case SYSREG_DBGBCR1_EL1: 1385 case SYSREG_DBGBCR2_EL1: 1386 case SYSREG_DBGBCR3_EL1: 1387 case SYSREG_DBGBCR4_EL1: 1388 case SYSREG_DBGBCR5_EL1: 1389 case SYSREG_DBGBCR6_EL1: 1390 case SYSREG_DBGBCR7_EL1: 1391 case SYSREG_DBGBCR8_EL1: 1392 case SYSREG_DBGBCR9_EL1: 1393 case SYSREG_DBGBCR10_EL1: 1394 case SYSREG_DBGBCR11_EL1: 1395 case SYSREG_DBGBCR12_EL1: 1396 case SYSREG_DBGBCR13_EL1: 1397 case SYSREG_DBGBCR14_EL1: 1398 case SYSREG_DBGBCR15_EL1: 1399 *val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; 1400 return 0; 1401 case SYSREG_DBGWVR0_EL1: 1402 case SYSREG_DBGWVR1_EL1: 1403 case SYSREG_DBGWVR2_EL1: 1404 case SYSREG_DBGWVR3_EL1: 1405 case SYSREG_DBGWVR4_EL1: 1406 case SYSREG_DBGWVR5_EL1: 1407 case SYSREG_DBGWVR6_EL1: 1408 case SYSREG_DBGWVR7_EL1: 1409 case SYSREG_DBGWVR8_EL1: 1410 case SYSREG_DBGWVR9_EL1: 1411 case SYSREG_DBGWVR10_EL1: 1412 case SYSREG_DBGWVR11_EL1: 1413 case SYSREG_DBGWVR12_EL1: 1414 case SYSREG_DBGWVR13_EL1: 1415 case SYSREG_DBGWVR14_EL1: 1416 case SYSREG_DBGWVR15_EL1: 1417 *val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; 1418 return 0; 1419 case SYSREG_DBGWCR0_EL1: 1420 case SYSREG_DBGWCR1_EL1: 1421 case SYSREG_DBGWCR2_EL1: 1422 case SYSREG_DBGWCR3_EL1: 1423 case SYSREG_DBGWCR4_EL1: 1424 case SYSREG_DBGWCR5_EL1: 1425 case SYSREG_DBGWCR6_EL1: 1426 case SYSREG_DBGWCR7_EL1: 1427 case SYSREG_DBGWCR8_EL1: 1428 case SYSREG_DBGWCR9_EL1: 1429 case SYSREG_DBGWCR10_EL1: 1430 case SYSREG_DBGWCR11_EL1: 1431 case SYSREG_DBGWCR12_EL1: 1432 case SYSREG_DBGWCR13_EL1: 1433 case SYSREG_DBGWCR14_EL1: 1434 case SYSREG_DBGWCR15_EL1: 1435 *val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; 1436 return 0; 1437 default: 1438 if (is_id_sysreg(reg)) { 1439 /* ID system registers read as RES0 */ 1440 *val = 0; 1441 return 0; 1442 } 1443 } 1444 1445 cpu_synchronize_state(cpu); 1446 trace_hvf_unhandled_sysreg_read(env->pc, reg, 1447 SYSREG_OP0(reg), 1448 SYSREG_OP1(reg), 1449 SYSREG_CRN(reg), 1450 SYSREG_CRM(reg), 1451 SYSREG_OP2(reg)); 1452 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1453 return 1; 1454 } 1455 1456 static void pmu_update_irq(CPUARMState *env) 1457 { 1458 ARMCPU *cpu = env_archcpu(env); 1459 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && 1460 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); 1461 } 1462 1463 static bool pmu_event_supported(uint16_t number) 1464 { 1465 return false; 1466 } 1467 1468 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using 1469 * the current EL, security state, and register configuration. 1470 */ 1471 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) 1472 { 1473 uint64_t filter; 1474 bool enabled, filtered = true; 1475 int el = arm_current_el(env); 1476 1477 enabled = (env->cp15.c9_pmcr & PMCRE) && 1478 (env->cp15.c9_pmcnten & (1 << counter)); 1479 1480 if (counter == 31) { 1481 filter = env->cp15.pmccfiltr_el0; 1482 } else { 1483 filter = env->cp15.c14_pmevtyper[counter]; 1484 } 1485 1486 if (el == 0) { 1487 filtered = filter & PMXEVTYPER_U; 1488 } else if (el == 1) { 1489 filtered = filter & PMXEVTYPER_P; 1490 } 1491 1492 if (counter != 31) { 1493 /* 1494 * If not checking PMCCNTR, ensure the counter is setup to an event we 1495 * support 1496 */ 1497 uint16_t event = filter & PMXEVTYPER_EVTCOUNT; 1498 if (!pmu_event_supported(event)) { 1499 return false; 1500 } 1501 } 1502 1503 return enabled && !filtered; 1504 } 1505 1506 static void pmswinc_write(CPUARMState *env, uint64_t value) 1507 { 1508 unsigned int i; 1509 for (i = 0; i < pmu_num_counters(env); i++) { 1510 /* Increment a counter's count iff: */ 1511 if ((value & (1 << i)) && /* counter's bit is set */ 1512 /* counter is enabled and not filtered */ 1513 pmu_counter_enabled(env, i) && 1514 /* counter is SW_INCR */ 1515 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { 1516 /* 1517 * Detect if this write causes an overflow since we can't predict 1518 * PMSWINC overflows like we can for other events 1519 */ 1520 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; 1521 1522 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { 1523 env->cp15.c9_pmovsr |= (1 << i); 1524 pmu_update_irq(env); 1525 } 1526 1527 env->cp15.c14_pmevcntr[i] = new_pmswinc; 1528 } 1529 } 1530 } 1531 1532 static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) 1533 { 1534 ARMCPU *arm_cpu = ARM_CPU(cpu); 1535 CPUARMState *env = &arm_cpu->env; 1536 const ARMCPRegInfo *ri; 1537 1538 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1539 1540 if (ri) { 1541 if (ri->accessfn) { 1542 if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) { 1543 return false; 1544 } 1545 } 1546 if (ri->writefn) { 1547 ri->writefn(env, ri, val); 1548 } else { 1549 CPREG_FIELD64(env, ri) = val; 1550 } 1551 1552 trace_hvf_vgic_write(ri->name, val); 1553 return true; 1554 } 1555 1556 return false; 1557 } 1558 1559 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) 1560 { 1561 ARMCPU *arm_cpu = ARM_CPU(cpu); 1562 CPUARMState *env = &arm_cpu->env; 1563 1564 trace_hvf_sysreg_write(reg, 1565 SYSREG_OP0(reg), 1566 SYSREG_OP1(reg), 1567 SYSREG_CRN(reg), 1568 SYSREG_CRM(reg), 1569 SYSREG_OP2(reg), 1570 val); 1571 1572 if (arm_feature(env, ARM_FEATURE_PMU)) { 1573 switch (reg) { 1574 case SYSREG_PMCCNTR_EL0: 1575 pmu_op_start(env); 1576 env->cp15.c15_ccnt = val; 1577 pmu_op_finish(env); 1578 return 0; 1579 case SYSREG_PMCR_EL0: 1580 pmu_op_start(env); 1581 1582 if (val & PMCRC) { 1583 /* The counter has been reset */ 1584 env->cp15.c15_ccnt = 0; 1585 } 1586 1587 if (val & PMCRP) { 1588 unsigned int i; 1589 for (i = 0; i < pmu_num_counters(env); i++) { 1590 env->cp15.c14_pmevcntr[i] = 0; 1591 } 1592 } 1593 1594 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; 1595 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); 1596 1597 pmu_op_finish(env); 1598 return 0; 1599 case SYSREG_PMUSERENR_EL0: 1600 env->cp15.c9_pmuserenr = val & 0xf; 1601 return 0; 1602 case SYSREG_PMCNTENSET_EL0: 1603 env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); 1604 return 0; 1605 case SYSREG_PMCNTENCLR_EL0: 1606 env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); 1607 return 0; 1608 case SYSREG_PMINTENCLR_EL1: 1609 pmu_op_start(env); 1610 env->cp15.c9_pminten |= val; 1611 pmu_op_finish(env); 1612 return 0; 1613 case SYSREG_PMOVSCLR_EL0: 1614 pmu_op_start(env); 1615 env->cp15.c9_pmovsr &= ~val; 1616 pmu_op_finish(env); 1617 return 0; 1618 case SYSREG_PMSWINC_EL0: 1619 pmu_op_start(env); 1620 pmswinc_write(env, val); 1621 pmu_op_finish(env); 1622 return 0; 1623 case SYSREG_PMSELR_EL0: 1624 env->cp15.c9_pmselr = val & 0x1f; 1625 return 0; 1626 case SYSREG_PMCCFILTR_EL0: 1627 pmu_op_start(env); 1628 env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; 1629 pmu_op_finish(env); 1630 return 0; 1631 } 1632 } 1633 1634 switch (reg) { 1635 case SYSREG_OSLAR_EL1: 1636 env->cp15.oslsr_el1 = val & 1; 1637 return 0; 1638 case SYSREG_CNTP_CTL_EL0: 1639 /* 1640 * Guests should not rely on the physical counter, but macOS emits 1641 * disable writes to it. Let it do so, but ignore the requests. 1642 */ 1643 qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CTL_EL0\n"); 1644 return 0; 1645 case SYSREG_OSDLR_EL1: 1646 /* Dummy register */ 1647 return 0; 1648 case SYSREG_ICC_AP0R0_EL1: 1649 case SYSREG_ICC_AP0R1_EL1: 1650 case SYSREG_ICC_AP0R2_EL1: 1651 case SYSREG_ICC_AP0R3_EL1: 1652 case SYSREG_ICC_AP1R0_EL1: 1653 case SYSREG_ICC_AP1R1_EL1: 1654 case SYSREG_ICC_AP1R2_EL1: 1655 case SYSREG_ICC_AP1R3_EL1: 1656 case SYSREG_ICC_ASGI1R_EL1: 1657 case SYSREG_ICC_BPR0_EL1: 1658 case SYSREG_ICC_BPR1_EL1: 1659 case SYSREG_ICC_CTLR_EL1: 1660 case SYSREG_ICC_DIR_EL1: 1661 case SYSREG_ICC_EOIR0_EL1: 1662 case SYSREG_ICC_EOIR1_EL1: 1663 case SYSREG_ICC_HPPIR0_EL1: 1664 case SYSREG_ICC_HPPIR1_EL1: 1665 case SYSREG_ICC_IAR0_EL1: 1666 case SYSREG_ICC_IAR1_EL1: 1667 case SYSREG_ICC_IGRPEN0_EL1: 1668 case SYSREG_ICC_IGRPEN1_EL1: 1669 case SYSREG_ICC_PMR_EL1: 1670 case SYSREG_ICC_SGI0R_EL1: 1671 case SYSREG_ICC_SGI1R_EL1: 1672 case SYSREG_ICC_SRE_EL1: 1673 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1674 if (hvf_sysreg_write_cp(cpu, reg, val)) { 1675 return 0; 1676 } 1677 break; 1678 case SYSREG_MDSCR_EL1: 1679 env->cp15.mdscr_el1 = val; 1680 return 0; 1681 case SYSREG_DBGBVR0_EL1: 1682 case SYSREG_DBGBVR1_EL1: 1683 case SYSREG_DBGBVR2_EL1: 1684 case SYSREG_DBGBVR3_EL1: 1685 case SYSREG_DBGBVR4_EL1: 1686 case SYSREG_DBGBVR5_EL1: 1687 case SYSREG_DBGBVR6_EL1: 1688 case SYSREG_DBGBVR7_EL1: 1689 case SYSREG_DBGBVR8_EL1: 1690 case SYSREG_DBGBVR9_EL1: 1691 case SYSREG_DBGBVR10_EL1: 1692 case SYSREG_DBGBVR11_EL1: 1693 case SYSREG_DBGBVR12_EL1: 1694 case SYSREG_DBGBVR13_EL1: 1695 case SYSREG_DBGBVR14_EL1: 1696 case SYSREG_DBGBVR15_EL1: 1697 env->cp15.dbgbvr[SYSREG_CRM(reg)] = val; 1698 return 0; 1699 case SYSREG_DBGBCR0_EL1: 1700 case SYSREG_DBGBCR1_EL1: 1701 case SYSREG_DBGBCR2_EL1: 1702 case SYSREG_DBGBCR3_EL1: 1703 case SYSREG_DBGBCR4_EL1: 1704 case SYSREG_DBGBCR5_EL1: 1705 case SYSREG_DBGBCR6_EL1: 1706 case SYSREG_DBGBCR7_EL1: 1707 case SYSREG_DBGBCR8_EL1: 1708 case SYSREG_DBGBCR9_EL1: 1709 case SYSREG_DBGBCR10_EL1: 1710 case SYSREG_DBGBCR11_EL1: 1711 case SYSREG_DBGBCR12_EL1: 1712 case SYSREG_DBGBCR13_EL1: 1713 case SYSREG_DBGBCR14_EL1: 1714 case SYSREG_DBGBCR15_EL1: 1715 env->cp15.dbgbcr[SYSREG_CRM(reg)] = val; 1716 return 0; 1717 case SYSREG_DBGWVR0_EL1: 1718 case SYSREG_DBGWVR1_EL1: 1719 case SYSREG_DBGWVR2_EL1: 1720 case SYSREG_DBGWVR3_EL1: 1721 case SYSREG_DBGWVR4_EL1: 1722 case SYSREG_DBGWVR5_EL1: 1723 case SYSREG_DBGWVR6_EL1: 1724 case SYSREG_DBGWVR7_EL1: 1725 case SYSREG_DBGWVR8_EL1: 1726 case SYSREG_DBGWVR9_EL1: 1727 case SYSREG_DBGWVR10_EL1: 1728 case SYSREG_DBGWVR11_EL1: 1729 case SYSREG_DBGWVR12_EL1: 1730 case SYSREG_DBGWVR13_EL1: 1731 case SYSREG_DBGWVR14_EL1: 1732 case SYSREG_DBGWVR15_EL1: 1733 env->cp15.dbgwvr[SYSREG_CRM(reg)] = val; 1734 return 0; 1735 case SYSREG_DBGWCR0_EL1: 1736 case SYSREG_DBGWCR1_EL1: 1737 case SYSREG_DBGWCR2_EL1: 1738 case SYSREG_DBGWCR3_EL1: 1739 case SYSREG_DBGWCR4_EL1: 1740 case SYSREG_DBGWCR5_EL1: 1741 case SYSREG_DBGWCR6_EL1: 1742 case SYSREG_DBGWCR7_EL1: 1743 case SYSREG_DBGWCR8_EL1: 1744 case SYSREG_DBGWCR9_EL1: 1745 case SYSREG_DBGWCR10_EL1: 1746 case SYSREG_DBGWCR11_EL1: 1747 case SYSREG_DBGWCR12_EL1: 1748 case SYSREG_DBGWCR13_EL1: 1749 case SYSREG_DBGWCR14_EL1: 1750 case SYSREG_DBGWCR15_EL1: 1751 env->cp15.dbgwcr[SYSREG_CRM(reg)] = val; 1752 return 0; 1753 } 1754 1755 cpu_synchronize_state(cpu); 1756 trace_hvf_unhandled_sysreg_write(env->pc, reg, 1757 SYSREG_OP0(reg), 1758 SYSREG_OP1(reg), 1759 SYSREG_CRN(reg), 1760 SYSREG_CRM(reg), 1761 SYSREG_OP2(reg)); 1762 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1763 return 1; 1764 } 1765 1766 static int hvf_inject_interrupts(CPUState *cpu) 1767 { 1768 if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { 1769 trace_hvf_inject_fiq(); 1770 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FIQ, 1771 true); 1772 } 1773 1774 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { 1775 trace_hvf_inject_irq(); 1776 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IRQ, 1777 true); 1778 } 1779 1780 return 0; 1781 } 1782 1783 static uint64_t hvf_vtimer_val_raw(void) 1784 { 1785 /* 1786 * mach_absolute_time() returns the vtimer value without the VM 1787 * offset that we define. Add our own offset on top. 1788 */ 1789 return mach_absolute_time() - hvf_state->vtimer_offset; 1790 } 1791 1792 static uint64_t hvf_vtimer_val(void) 1793 { 1794 if (!runstate_is_running()) { 1795 /* VM is paused, the vtimer value is in vtimer.vtimer_val */ 1796 return vtimer.vtimer_val; 1797 } 1798 1799 return hvf_vtimer_val_raw(); 1800 } 1801 1802 static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) 1803 { 1804 /* 1805 * Use pselect to sleep so that other threads can IPI us while we're 1806 * sleeping. 1807 */ 1808 qatomic_set_mb(&cpu->thread_kicked, false); 1809 bql_unlock(); 1810 pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask); 1811 bql_lock(); 1812 } 1813 1814 static void hvf_wfi(CPUState *cpu) 1815 { 1816 ARMCPU *arm_cpu = ARM_CPU(cpu); 1817 struct timespec ts; 1818 hv_return_t r; 1819 uint64_t ctl; 1820 uint64_t cval; 1821 int64_t ticks_to_sleep; 1822 uint64_t seconds; 1823 uint64_t nanos; 1824 uint32_t cntfrq; 1825 1826 if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { 1827 /* Interrupt pending, no need to wait */ 1828 return; 1829 } 1830 1831 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1832 assert_hvf_ok(r); 1833 1834 if (!(ctl & 1) || (ctl & 2)) { 1835 /* Timer disabled or masked, just wait for an IPI. */ 1836 hvf_wait_for_ipi(cpu, NULL); 1837 return; 1838 } 1839 1840 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); 1841 assert_hvf_ok(r); 1842 1843 ticks_to_sleep = cval - hvf_vtimer_val(); 1844 if (ticks_to_sleep < 0) { 1845 return; 1846 } 1847 1848 cntfrq = gt_cntfrq_period_ns(arm_cpu); 1849 seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND); 1850 ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); 1851 nanos = ticks_to_sleep * cntfrq; 1852 1853 /* 1854 * Don't sleep for less than the time a context switch would take, 1855 * so that we can satisfy fast timer requests on the same CPU. 1856 * Measurements on M1 show the sweet spot to be ~2ms. 1857 */ 1858 if (!seconds && nanos < (2 * SCALE_MS)) { 1859 return; 1860 } 1861 1862 ts = (struct timespec) { seconds, nanos }; 1863 hvf_wait_for_ipi(cpu, &ts); 1864 } 1865 1866 static void hvf_sync_vtimer(CPUState *cpu) 1867 { 1868 ARMCPU *arm_cpu = ARM_CPU(cpu); 1869 hv_return_t r; 1870 uint64_t ctl; 1871 bool irq_state; 1872 1873 if (!cpu->accel->vtimer_masked) { 1874 /* We will get notified on vtimer changes by hvf, nothing to do */ 1875 return; 1876 } 1877 1878 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1879 assert_hvf_ok(r); 1880 1881 irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) == 1882 (TMR_CTL_ENABLE | TMR_CTL_ISTATUS); 1883 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); 1884 1885 if (!irq_state) { 1886 /* Timer no longer asserting, we can unmask it */ 1887 hv_vcpu_set_vtimer_mask(cpu->accel->fd, false); 1888 cpu->accel->vtimer_masked = false; 1889 } 1890 } 1891 1892 int hvf_vcpu_exec(CPUState *cpu) 1893 { 1894 ARMCPU *arm_cpu = ARM_CPU(cpu); 1895 CPUARMState *env = &arm_cpu->env; 1896 int ret; 1897 hv_vcpu_exit_t *hvf_exit = cpu->accel->exit; 1898 hv_return_t r; 1899 bool advance_pc = false; 1900 1901 if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) && 1902 hvf_inject_interrupts(cpu)) { 1903 return EXCP_INTERRUPT; 1904 } 1905 1906 if (cpu->halted) { 1907 return EXCP_HLT; 1908 } 1909 1910 flush_cpu_state(cpu); 1911 1912 bql_unlock(); 1913 assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); 1914 1915 /* handle VMEXIT */ 1916 uint64_t exit_reason = hvf_exit->reason; 1917 uint64_t syndrome = hvf_exit->exception.syndrome; 1918 uint32_t ec = syn_get_ec(syndrome); 1919 1920 ret = 0; 1921 bql_lock(); 1922 switch (exit_reason) { 1923 case HV_EXIT_REASON_EXCEPTION: 1924 /* This is the main one, handle below. */ 1925 break; 1926 case HV_EXIT_REASON_VTIMER_ACTIVATED: 1927 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); 1928 cpu->accel->vtimer_masked = true; 1929 return 0; 1930 case HV_EXIT_REASON_CANCELED: 1931 /* we got kicked, no exit to process */ 1932 return 0; 1933 default: 1934 g_assert_not_reached(); 1935 } 1936 1937 hvf_sync_vtimer(cpu); 1938 1939 switch (ec) { 1940 case EC_SOFTWARESTEP: { 1941 ret = EXCP_DEBUG; 1942 1943 if (!cpu->singlestep_enabled) { 1944 error_report("EC_SOFTWARESTEP but single-stepping not enabled"); 1945 } 1946 break; 1947 } 1948 case EC_AA64_BKPT: { 1949 ret = EXCP_DEBUG; 1950 1951 cpu_synchronize_state(cpu); 1952 1953 if (!hvf_find_sw_breakpoint(cpu, env->pc)) { 1954 /* Re-inject into the guest */ 1955 ret = 0; 1956 hvf_raise_exception(cpu, EXCP_BKPT, syn_aa64_bkpt(0)); 1957 } 1958 break; 1959 } 1960 case EC_BREAKPOINT: { 1961 ret = EXCP_DEBUG; 1962 1963 cpu_synchronize_state(cpu); 1964 1965 if (!find_hw_breakpoint(cpu, env->pc)) { 1966 error_report("EC_BREAKPOINT but unknown hw breakpoint"); 1967 } 1968 break; 1969 } 1970 case EC_WATCHPOINT: { 1971 ret = EXCP_DEBUG; 1972 1973 cpu_synchronize_state(cpu); 1974 1975 CPUWatchpoint *wp = 1976 find_hw_watchpoint(cpu, hvf_exit->exception.virtual_address); 1977 if (!wp) { 1978 error_report("EXCP_DEBUG but unknown hw watchpoint"); 1979 } 1980 cpu->watchpoint_hit = wp; 1981 break; 1982 } 1983 case EC_DATAABORT: { 1984 bool isv = syndrome & ARM_EL_ISV; 1985 bool iswrite = (syndrome >> 6) & 1; 1986 bool s1ptw = (syndrome >> 7) & 1; 1987 bool sse = (syndrome >> 21) & 1; 1988 uint32_t sas = (syndrome >> 22) & 3; 1989 uint32_t len = 1 << sas; 1990 uint32_t srt = (syndrome >> 16) & 0x1f; 1991 uint32_t cm = (syndrome >> 8) & 0x1; 1992 uint64_t val = 0; 1993 1994 trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, 1995 hvf_exit->exception.physical_address, isv, 1996 iswrite, s1ptw, len, srt); 1997 1998 if (cm) { 1999 /* We don't cache MMIO regions */ 2000 advance_pc = true; 2001 break; 2002 } 2003 2004 assert(isv); 2005 2006 if (iswrite) { 2007 val = hvf_get_reg(cpu, srt); 2008 address_space_write(&address_space_memory, 2009 hvf_exit->exception.physical_address, 2010 MEMTXATTRS_UNSPECIFIED, &val, len); 2011 } else { 2012 address_space_read(&address_space_memory, 2013 hvf_exit->exception.physical_address, 2014 MEMTXATTRS_UNSPECIFIED, &val, len); 2015 if (sse) { 2016 val = sextract64(val, 0, len * 8); 2017 } 2018 hvf_set_reg(cpu, srt, val); 2019 } 2020 2021 advance_pc = true; 2022 break; 2023 } 2024 case EC_SYSTEMREGISTERTRAP: { 2025 bool isread = (syndrome >> 0) & 1; 2026 uint32_t rt = (syndrome >> 5) & 0x1f; 2027 uint32_t reg = syndrome & SYSREG_MASK; 2028 uint64_t val; 2029 int sysreg_ret = 0; 2030 2031 if (isread) { 2032 sysreg_ret = hvf_sysreg_read(cpu, reg, &val); 2033 if (!sysreg_ret) { 2034 trace_hvf_sysreg_read(reg, 2035 SYSREG_OP0(reg), 2036 SYSREG_OP1(reg), 2037 SYSREG_CRN(reg), 2038 SYSREG_CRM(reg), 2039 SYSREG_OP2(reg), 2040 val); 2041 hvf_set_reg(cpu, rt, val); 2042 } 2043 } else { 2044 val = hvf_get_reg(cpu, rt); 2045 sysreg_ret = hvf_sysreg_write(cpu, reg, val); 2046 } 2047 2048 advance_pc = !sysreg_ret; 2049 break; 2050 } 2051 case EC_WFX_TRAP: 2052 advance_pc = true; 2053 if (!(syndrome & WFX_IS_WFE)) { 2054 hvf_wfi(cpu); 2055 } 2056 break; 2057 case EC_AA64_HVC: 2058 cpu_synchronize_state(cpu); 2059 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { 2060 if (!hvf_handle_psci_call(cpu)) { 2061 trace_hvf_unknown_hvc(env->xregs[0]); 2062 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 2063 env->xregs[0] = -1; 2064 } 2065 } else { 2066 trace_hvf_unknown_hvc(env->xregs[0]); 2067 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 2068 } 2069 break; 2070 case EC_AA64_SMC: 2071 cpu_synchronize_state(cpu); 2072 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { 2073 advance_pc = true; 2074 2075 if (!hvf_handle_psci_call(cpu)) { 2076 trace_hvf_unknown_smc(env->xregs[0]); 2077 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 2078 env->xregs[0] = -1; 2079 } 2080 } else { 2081 trace_hvf_unknown_smc(env->xregs[0]); 2082 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 2083 } 2084 break; 2085 default: 2086 cpu_synchronize_state(cpu); 2087 trace_hvf_exit(syndrome, ec, env->pc); 2088 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); 2089 } 2090 2091 if (advance_pc) { 2092 uint64_t pc; 2093 2094 flush_cpu_state(cpu); 2095 2096 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); 2097 assert_hvf_ok(r); 2098 pc += 4; 2099 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc); 2100 assert_hvf_ok(r); 2101 2102 /* Handle single-stepping over instructions which trigger a VM exit */ 2103 if (cpu->singlestep_enabled) { 2104 ret = EXCP_DEBUG; 2105 } 2106 } 2107 2108 return ret; 2109 } 2110 2111 static const VMStateDescription vmstate_hvf_vtimer = { 2112 .name = "hvf-vtimer", 2113 .version_id = 1, 2114 .minimum_version_id = 1, 2115 .fields = (const VMStateField[]) { 2116 VMSTATE_UINT64(vtimer_val, HVFVTimer), 2117 VMSTATE_END_OF_LIST() 2118 }, 2119 }; 2120 2121 static void hvf_vm_state_change(void *opaque, bool running, RunState state) 2122 { 2123 HVFVTimer *s = opaque; 2124 2125 if (running) { 2126 /* Update vtimer offset on all CPUs */ 2127 hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; 2128 cpu_synchronize_all_states(); 2129 } else { 2130 /* Remember vtimer value on every pause */ 2131 s->vtimer_val = hvf_vtimer_val_raw(); 2132 } 2133 } 2134 2135 int hvf_arch_init(void) 2136 { 2137 hvf_state->vtimer_offset = mach_absolute_time(); 2138 vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); 2139 qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); 2140 2141 hvf_arm_init_debug(); 2142 2143 return 0; 2144 } 2145 2146 static const uint32_t brk_insn = 0xd4200000; 2147 2148 int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 2149 { 2150 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 2151 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 2152 return -EINVAL; 2153 } 2154 return 0; 2155 } 2156 2157 int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 2158 { 2159 static uint32_t brk; 2160 2161 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) || 2162 brk != brk_insn || 2163 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2164 return -EINVAL; 2165 } 2166 return 0; 2167 } 2168 2169 int hvf_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2170 { 2171 switch (type) { 2172 case GDB_BREAKPOINT_HW: 2173 return insert_hw_breakpoint(addr); 2174 case GDB_WATCHPOINT_READ: 2175 case GDB_WATCHPOINT_WRITE: 2176 case GDB_WATCHPOINT_ACCESS: 2177 return insert_hw_watchpoint(addr, len, type); 2178 default: 2179 return -ENOSYS; 2180 } 2181 } 2182 2183 int hvf_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2184 { 2185 switch (type) { 2186 case GDB_BREAKPOINT_HW: 2187 return delete_hw_breakpoint(addr); 2188 case GDB_WATCHPOINT_READ: 2189 case GDB_WATCHPOINT_WRITE: 2190 case GDB_WATCHPOINT_ACCESS: 2191 return delete_hw_watchpoint(addr, len, type); 2192 default: 2193 return -ENOSYS; 2194 } 2195 } 2196 2197 void hvf_arch_remove_all_hw_breakpoints(void) 2198 { 2199 if (cur_hw_wps > 0) { 2200 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 2201 } 2202 if (cur_hw_bps > 0) { 2203 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 2204 } 2205 } 2206 2207 /* 2208 * Update the vCPU with the gdbstub's view of debug registers. This view 2209 * consists of all hardware breakpoints and watchpoints inserted so far while 2210 * debugging the guest. 2211 */ 2212 static void hvf_put_gdbstub_debug_registers(CPUState *cpu) 2213 { 2214 hv_return_t r = HV_SUCCESS; 2215 int i; 2216 2217 for (i = 0; i < cur_hw_bps; i++) { 2218 HWBreakpoint *bp = get_hw_bp(i); 2219 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr); 2220 assert_hvf_ok(r); 2221 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr); 2222 assert_hvf_ok(r); 2223 } 2224 for (i = cur_hw_bps; i < max_hw_bps; i++) { 2225 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0); 2226 assert_hvf_ok(r); 2227 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0); 2228 assert_hvf_ok(r); 2229 } 2230 2231 for (i = 0; i < cur_hw_wps; i++) { 2232 HWWatchpoint *wp = get_hw_wp(i); 2233 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr); 2234 assert_hvf_ok(r); 2235 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr); 2236 assert_hvf_ok(r); 2237 } 2238 for (i = cur_hw_wps; i < max_hw_wps; i++) { 2239 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0); 2240 assert_hvf_ok(r); 2241 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0); 2242 assert_hvf_ok(r); 2243 } 2244 } 2245 2246 /* 2247 * Update the vCPU with the guest's view of debug registers. This view is kept 2248 * in the environment at all times. 2249 */ 2250 static void hvf_put_guest_debug_registers(CPUState *cpu) 2251 { 2252 ARMCPU *arm_cpu = ARM_CPU(cpu); 2253 CPUARMState *env = &arm_cpu->env; 2254 hv_return_t r = HV_SUCCESS; 2255 int i; 2256 2257 for (i = 0; i < max_hw_bps; i++) { 2258 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 2259 env->cp15.dbgbcr[i]); 2260 assert_hvf_ok(r); 2261 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 2262 env->cp15.dbgbvr[i]); 2263 assert_hvf_ok(r); 2264 } 2265 2266 for (i = 0; i < max_hw_wps; i++) { 2267 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 2268 env->cp15.dbgwcr[i]); 2269 assert_hvf_ok(r); 2270 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 2271 env->cp15.dbgwvr[i]); 2272 assert_hvf_ok(r); 2273 } 2274 } 2275 2276 static inline bool hvf_arm_hw_debug_active(CPUState *cpu) 2277 { 2278 return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); 2279 } 2280 2281 static void hvf_arch_set_traps(void) 2282 { 2283 CPUState *cpu; 2284 bool should_enable_traps = false; 2285 hv_return_t r = HV_SUCCESS; 2286 2287 /* Check whether guest debugging is enabled for at least one vCPU; if it 2288 * is, enable exiting the guest on all vCPUs */ 2289 CPU_FOREACH(cpu) { 2290 should_enable_traps |= cpu->accel->guest_debug_enabled; 2291 } 2292 CPU_FOREACH(cpu) { 2293 /* Set whether debug exceptions exit the guest */ 2294 r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd, 2295 should_enable_traps); 2296 assert_hvf_ok(r); 2297 2298 /* Set whether accesses to debug registers exit the guest */ 2299 r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd, 2300 should_enable_traps); 2301 assert_hvf_ok(r); 2302 } 2303 } 2304 2305 void hvf_arch_update_guest_debug(CPUState *cpu) 2306 { 2307 ARMCPU *arm_cpu = ARM_CPU(cpu); 2308 CPUARMState *env = &arm_cpu->env; 2309 2310 /* Check whether guest debugging is enabled */ 2311 cpu->accel->guest_debug_enabled = cpu->singlestep_enabled || 2312 hvf_sw_breakpoints_active(cpu) || 2313 hvf_arm_hw_debug_active(cpu); 2314 2315 /* Update debug registers */ 2316 if (cpu->accel->guest_debug_enabled) { 2317 hvf_put_gdbstub_debug_registers(cpu); 2318 } else { 2319 hvf_put_guest_debug_registers(cpu); 2320 } 2321 2322 cpu_synchronize_state(cpu); 2323 2324 /* Enable/disable single-stepping */ 2325 if (cpu->singlestep_enabled) { 2326 env->cp15.mdscr_el1 = 2327 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1); 2328 pstate_write(env, pstate_read(env) | PSTATE_SS); 2329 } else { 2330 env->cp15.mdscr_el1 = 2331 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0); 2332 } 2333 2334 /* Enable/disable Breakpoint exceptions */ 2335 if (hvf_arm_hw_debug_active(cpu)) { 2336 env->cp15.mdscr_el1 = 2337 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1); 2338 } else { 2339 env->cp15.mdscr_el1 = 2340 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0); 2341 } 2342 2343 hvf_arch_set_traps(); 2344 } 2345 2346 bool hvf_arch_supports_guest_debug(void) 2347 { 2348 return true; 2349 } 2350