1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "hw/registerfields.h" 25 26 #if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28 # define TARGET_LONG_BITS 64 29 #else 30 # define TARGET_LONG_BITS 32 31 #endif 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #define CPUArchState struct CPUARMState 37 38 #include "qemu-common.h" 39 #include "cpu-qom.h" 40 #include "exec/cpu-defs.h" 41 42 #define EXCP_UDEF 1 /* undefined instruction */ 43 #define EXCP_SWI 2 /* software interrupt */ 44 #define EXCP_PREFETCH_ABORT 3 45 #define EXCP_DATA_ABORT 4 46 #define EXCP_IRQ 5 47 #define EXCP_FIQ 6 48 #define EXCP_BKPT 7 49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 51 #define EXCP_HVC 11 /* HyperVisor Call */ 52 #define EXCP_HYP_TRAP 12 53 #define EXCP_SMC 13 /* Secure Monitor Call */ 54 #define EXCP_VIRQ 14 55 #define EXCP_VFIQ 15 56 #define EXCP_SEMIHOST 16 /* semihosting call */ 57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 59 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 94 /* The usual mapping for an AArch64 system register to its AArch32 95 * counterpart is for the 32 bit world to have access to the lower 96 * half only (with writes leaving the upper half untouched). It's 97 * therefore useful to be able to pass TCG the offset of the least 98 * significant half of a uint64_t struct member. 99 */ 100 #ifdef HOST_WORDS_BIGENDIAN 101 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 102 #define offsetofhigh32(S, M) offsetof(S, M) 103 #else 104 #define offsetoflow32(S, M) offsetof(S, M) 105 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 106 #endif 107 108 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 109 #define ARM_CPU_IRQ 0 110 #define ARM_CPU_FIQ 1 111 #define ARM_CPU_VIRQ 2 112 #define ARM_CPU_VFIQ 3 113 114 #define NB_MMU_MODES 8 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num_cpregs: Number of the Coprocessor registers seen by GDB. 141 * @cpregs_keys: Array that contains the corresponding Key of 142 * a given cpreg with the same order of the cpreg in the XML description. 143 */ 144 typedef struct DynamicGDBXMLInfo { 145 char *desc; 146 int num_cpregs; 147 uint32_t *cpregs_keys; 148 } DynamicGDBXMLInfo; 149 150 /* CPU state for each instance of a generic timer (in cp15 c14) */ 151 typedef struct ARMGenericTimer { 152 uint64_t cval; /* Timer CompareValue register */ 153 uint64_t ctl; /* Timer Control register */ 154 } ARMGenericTimer; 155 156 #define GTIMER_PHYS 0 157 #define GTIMER_VIRT 1 158 #define GTIMER_HYP 2 159 #define GTIMER_SEC 3 160 #define NUM_GTIMERS 4 161 162 typedef struct { 163 uint64_t raw_tcr; 164 uint32_t mask; 165 uint32_t base_mask; 166 } TCR; 167 168 /* Define a maximum sized vector register. 169 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 170 * For 64-bit, this is a 2048-bit SVE register. 171 * 172 * Note that the mapping between S, D, and Q views of the register bank 173 * differs between AArch64 and AArch32. 174 * In AArch32: 175 * Qn = regs[n].d[1]:regs[n].d[0] 176 * Dn = regs[n / 2].d[n & 1] 177 * Sn = regs[n / 4].d[n % 4 / 2], 178 * bits 31..0 for even n, and bits 63..32 for odd n 179 * (and regs[16] to regs[31] are inaccessible) 180 * In AArch64: 181 * Zn = regs[n].d[*] 182 * Qn = regs[n].d[1]:regs[n].d[0] 183 * Dn = regs[n].d[0] 184 * Sn = regs[n].d[0] bits 31..0 185 * Hn = regs[n].d[0] bits 15..0 186 * 187 * This corresponds to the architecturally defined mapping between 188 * the two execution states, and means we do not need to explicitly 189 * map these registers when changing states. 190 * 191 * Align the data for use with TCG host vector operations. 192 */ 193 194 #ifdef TARGET_AARCH64 195 # define ARM_MAX_VQ 16 196 #else 197 # define ARM_MAX_VQ 1 198 #endif 199 200 typedef struct ARMVectorReg { 201 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 202 } ARMVectorReg; 203 204 #ifdef TARGET_AARCH64 205 /* In AArch32 mode, predicate registers do not exist at all. */ 206 typedef struct ARMPredicateReg { 207 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); 208 } ARMPredicateReg; 209 210 /* In AArch32 mode, PAC keys do not exist at all. */ 211 typedef struct ARMPACKey { 212 uint64_t lo, hi; 213 } ARMPACKey; 214 #endif 215 216 217 typedef struct CPUARMState { 218 /* Regs for current mode. */ 219 uint32_t regs[16]; 220 221 /* 32/64 switch only happens when taking and returning from 222 * exceptions so the overlap semantics are taken care of then 223 * instead of having a complicated union. 224 */ 225 /* Regs for A64 mode. */ 226 uint64_t xregs[32]; 227 uint64_t pc; 228 /* PSTATE isn't an architectural register for ARMv8. However, it is 229 * convenient for us to assemble the underlying state into a 32 bit format 230 * identical to the architectural format used for the SPSR. (This is also 231 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 232 * 'pstate' register are.) Of the PSTATE bits: 233 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 234 * semantics as for AArch32, as described in the comments on each field) 235 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 236 * DAIF (exception masks) are kept in env->daif 237 * all other bits are stored in their correct places in env->pstate 238 */ 239 uint32_t pstate; 240 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ 241 242 /* Frequently accessed CPSR bits are stored separately for efficiency. 243 This contains all the other bits. Use cpsr_{read,write} to access 244 the whole CPSR. */ 245 uint32_t uncached_cpsr; 246 uint32_t spsr; 247 248 /* Banked registers. */ 249 uint64_t banked_spsr[8]; 250 uint32_t banked_r13[8]; 251 uint32_t banked_r14[8]; 252 253 /* These hold r8-r12. */ 254 uint32_t usr_regs[5]; 255 uint32_t fiq_regs[5]; 256 257 /* cpsr flag cache for faster execution */ 258 uint32_t CF; /* 0 or 1 */ 259 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 260 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 261 uint32_t ZF; /* Z set if zero. */ 262 uint32_t QF; /* 0 or 1 */ 263 uint32_t GE; /* cpsr[19:16] */ 264 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 265 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 266 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 267 268 uint64_t elr_el[4]; /* AArch64 exception link regs */ 269 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 270 271 /* System control coprocessor (cp15) */ 272 struct { 273 uint32_t c0_cpuid; 274 union { /* Cache size selection */ 275 struct { 276 uint64_t _unused_csselr0; 277 uint64_t csselr_ns; 278 uint64_t _unused_csselr1; 279 uint64_t csselr_s; 280 }; 281 uint64_t csselr_el[4]; 282 }; 283 union { /* System control register. */ 284 struct { 285 uint64_t _unused_sctlr; 286 uint64_t sctlr_ns; 287 uint64_t hsctlr; 288 uint64_t sctlr_s; 289 }; 290 uint64_t sctlr_el[4]; 291 }; 292 uint64_t cpacr_el1; /* Architectural feature access control register */ 293 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 294 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 295 uint64_t sder; /* Secure debug enable register. */ 296 uint32_t nsacr; /* Non-secure access control register. */ 297 union { /* MMU translation table base 0. */ 298 struct { 299 uint64_t _unused_ttbr0_0; 300 uint64_t ttbr0_ns; 301 uint64_t _unused_ttbr0_1; 302 uint64_t ttbr0_s; 303 }; 304 uint64_t ttbr0_el[4]; 305 }; 306 union { /* MMU translation table base 1. */ 307 struct { 308 uint64_t _unused_ttbr1_0; 309 uint64_t ttbr1_ns; 310 uint64_t _unused_ttbr1_1; 311 uint64_t ttbr1_s; 312 }; 313 uint64_t ttbr1_el[4]; 314 }; 315 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 316 /* MMU translation table base control. */ 317 TCR tcr_el[4]; 318 TCR vtcr_el2; /* Virtualization Translation Control. */ 319 uint32_t c2_data; /* MPU data cacheable bits. */ 320 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 321 union { /* MMU domain access control register 322 * MPU write buffer control. 323 */ 324 struct { 325 uint64_t dacr_ns; 326 uint64_t dacr_s; 327 }; 328 struct { 329 uint64_t dacr32_el2; 330 }; 331 }; 332 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 333 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 334 uint64_t hcr_el2; /* Hypervisor configuration register */ 335 uint64_t scr_el3; /* Secure configuration register. */ 336 union { /* Fault status registers. */ 337 struct { 338 uint64_t ifsr_ns; 339 uint64_t ifsr_s; 340 }; 341 struct { 342 uint64_t ifsr32_el2; 343 }; 344 }; 345 union { 346 struct { 347 uint64_t _unused_dfsr; 348 uint64_t dfsr_ns; 349 uint64_t hsr; 350 uint64_t dfsr_s; 351 }; 352 uint64_t esr_el[4]; 353 }; 354 uint32_t c6_region[8]; /* MPU base/size registers. */ 355 union { /* Fault address registers. */ 356 struct { 357 uint64_t _unused_far0; 358 #ifdef HOST_WORDS_BIGENDIAN 359 uint32_t ifar_ns; 360 uint32_t dfar_ns; 361 uint32_t ifar_s; 362 uint32_t dfar_s; 363 #else 364 uint32_t dfar_ns; 365 uint32_t ifar_ns; 366 uint32_t dfar_s; 367 uint32_t ifar_s; 368 #endif 369 uint64_t _unused_far3; 370 }; 371 uint64_t far_el[4]; 372 }; 373 uint64_t hpfar_el2; 374 uint64_t hstr_el2; 375 union { /* Translation result. */ 376 struct { 377 uint64_t _unused_par_0; 378 uint64_t par_ns; 379 uint64_t _unused_par_1; 380 uint64_t par_s; 381 }; 382 uint64_t par_el[4]; 383 }; 384 385 uint32_t c9_insn; /* Cache lockdown registers. */ 386 uint32_t c9_data; 387 uint64_t c9_pmcr; /* performance monitor control register */ 388 uint64_t c9_pmcnten; /* perf monitor counter enables */ 389 uint64_t c9_pmovsr; /* perf monitor overflow status */ 390 uint64_t c9_pmuserenr; /* perf monitor user enable */ 391 uint64_t c9_pmselr; /* perf monitor counter selection register */ 392 uint64_t c9_pminten; /* perf monitor interrupt enables */ 393 union { /* Memory attribute redirection */ 394 struct { 395 #ifdef HOST_WORDS_BIGENDIAN 396 uint64_t _unused_mair_0; 397 uint32_t mair1_ns; 398 uint32_t mair0_ns; 399 uint64_t _unused_mair_1; 400 uint32_t mair1_s; 401 uint32_t mair0_s; 402 #else 403 uint64_t _unused_mair_0; 404 uint32_t mair0_ns; 405 uint32_t mair1_ns; 406 uint64_t _unused_mair_1; 407 uint32_t mair0_s; 408 uint32_t mair1_s; 409 #endif 410 }; 411 uint64_t mair_el[4]; 412 }; 413 union { /* vector base address register */ 414 struct { 415 uint64_t _unused_vbar; 416 uint64_t vbar_ns; 417 uint64_t hvbar; 418 uint64_t vbar_s; 419 }; 420 uint64_t vbar_el[4]; 421 }; 422 uint32_t mvbar; /* (monitor) vector base address register */ 423 struct { /* FCSE PID. */ 424 uint32_t fcseidr_ns; 425 uint32_t fcseidr_s; 426 }; 427 union { /* Context ID. */ 428 struct { 429 uint64_t _unused_contextidr_0; 430 uint64_t contextidr_ns; 431 uint64_t _unused_contextidr_1; 432 uint64_t contextidr_s; 433 }; 434 uint64_t contextidr_el[4]; 435 }; 436 union { /* User RW Thread register. */ 437 struct { 438 uint64_t tpidrurw_ns; 439 uint64_t tpidrprw_ns; 440 uint64_t htpidr; 441 uint64_t _tpidr_el3; 442 }; 443 uint64_t tpidr_el[4]; 444 }; 445 /* The secure banks of these registers don't map anywhere */ 446 uint64_t tpidrurw_s; 447 uint64_t tpidrprw_s; 448 uint64_t tpidruro_s; 449 450 union { /* User RO Thread register. */ 451 uint64_t tpidruro_ns; 452 uint64_t tpidrro_el[1]; 453 }; 454 uint64_t c14_cntfrq; /* Counter Frequency register */ 455 uint64_t c14_cntkctl; /* Timer Control register */ 456 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 457 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 458 ARMGenericTimer c14_timer[NUM_GTIMERS]; 459 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 460 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 461 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 462 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 463 uint32_t c15_threadid; /* TI debugger thread-ID. */ 464 uint32_t c15_config_base_address; /* SCU base address. */ 465 uint32_t c15_diagnostic; /* diagnostic register */ 466 uint32_t c15_power_diagnostic; 467 uint32_t c15_power_control; /* power control */ 468 uint64_t dbgbvr[16]; /* breakpoint value registers */ 469 uint64_t dbgbcr[16]; /* breakpoint control registers */ 470 uint64_t dbgwvr[16]; /* watchpoint value registers */ 471 uint64_t dbgwcr[16]; /* watchpoint control registers */ 472 uint64_t mdscr_el1; 473 uint64_t oslsr_el1; /* OS Lock Status */ 474 uint64_t mdcr_el2; 475 uint64_t mdcr_el3; 476 /* Stores the architectural value of the counter *the last time it was 477 * updated* by pmccntr_op_start. Accesses should always be surrounded 478 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 479 * architecturally-correct value is being read/set. 480 */ 481 uint64_t c15_ccnt; 482 /* Stores the delta between the architectural value and the underlying 483 * cycle count during normal operation. It is used to update c15_ccnt 484 * to be the correct architectural value before accesses. During 485 * accesses, c15_ccnt_delta contains the underlying count being used 486 * for the access, after which it reverts to the delta value in 487 * pmccntr_op_finish. 488 */ 489 uint64_t c15_ccnt_delta; 490 uint64_t c14_pmevcntr[31]; 491 uint64_t c14_pmevcntr_delta[31]; 492 uint64_t c14_pmevtyper[31]; 493 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 494 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 495 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 496 } cp15; 497 498 struct { 499 /* M profile has up to 4 stack pointers: 500 * a Main Stack Pointer and a Process Stack Pointer for each 501 * of the Secure and Non-Secure states. (If the CPU doesn't support 502 * the security extension then it has only two SPs.) 503 * In QEMU we always store the currently active SP in regs[13], 504 * and the non-active SP for the current security state in 505 * v7m.other_sp. The stack pointers for the inactive security state 506 * are stored in other_ss_msp and other_ss_psp. 507 * switch_v7m_security_state() is responsible for rearranging them 508 * when we change security state. 509 */ 510 uint32_t other_sp; 511 uint32_t other_ss_msp; 512 uint32_t other_ss_psp; 513 uint32_t vecbase[M_REG_NUM_BANKS]; 514 uint32_t basepri[M_REG_NUM_BANKS]; 515 uint32_t control[M_REG_NUM_BANKS]; 516 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 517 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 518 uint32_t hfsr; /* HardFault Status */ 519 uint32_t dfsr; /* Debug Fault Status Register */ 520 uint32_t sfsr; /* Secure Fault Status Register */ 521 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 522 uint32_t bfar; /* BusFault Address */ 523 uint32_t sfar; /* Secure Fault Address Register */ 524 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 525 int exception; 526 uint32_t primask[M_REG_NUM_BANKS]; 527 uint32_t faultmask[M_REG_NUM_BANKS]; 528 uint32_t aircr; /* only holds r/w state if security extn implemented */ 529 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 530 uint32_t csselr[M_REG_NUM_BANKS]; 531 uint32_t scr[M_REG_NUM_BANKS]; 532 uint32_t msplim[M_REG_NUM_BANKS]; 533 uint32_t psplim[M_REG_NUM_BANKS]; 534 } v7m; 535 536 /* Information associated with an exception about to be taken: 537 * code which raises an exception must set cs->exception_index and 538 * the relevant parts of this structure; the cpu_do_interrupt function 539 * will then set the guest-visible registers as part of the exception 540 * entry process. 541 */ 542 struct { 543 uint32_t syndrome; /* AArch64 format syndrome register */ 544 uint32_t fsr; /* AArch32 format fault status register info */ 545 uint64_t vaddress; /* virtual addr associated with exception, if any */ 546 uint32_t target_el; /* EL the exception should be targeted for */ 547 /* If we implement EL2 we will also need to store information 548 * about the intermediate physical address for stage 2 faults. 549 */ 550 } exception; 551 552 /* Information associated with an SError */ 553 struct { 554 uint8_t pending; 555 uint8_t has_esr; 556 uint64_t esr; 557 } serror; 558 559 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 560 uint32_t irq_line_state; 561 562 /* Thumb-2 EE state. */ 563 uint32_t teecr; 564 uint32_t teehbr; 565 566 /* VFP coprocessor state. */ 567 struct { 568 ARMVectorReg zregs[32]; 569 570 #ifdef TARGET_AARCH64 571 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 572 #define FFR_PRED_NUM 16 573 ARMPredicateReg pregs[17]; 574 /* Scratch space for aa64 sve predicate temporary. */ 575 ARMPredicateReg preg_tmp; 576 #endif 577 578 uint32_t xregs[16]; 579 /* We store these fpcsr fields separately for convenience. */ 580 int vec_len; 581 int vec_stride; 582 583 /* Scratch space for aa32 neon expansion. */ 584 uint32_t scratch[8]; 585 586 /* There are a number of distinct float control structures: 587 * 588 * fp_status: is the "normal" fp status. 589 * fp_status_fp16: used for half-precision calculations 590 * standard_fp_status : the ARM "Standard FPSCR Value" 591 * 592 * Half-precision operations are governed by a separate 593 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 594 * status structure to control this. 595 * 596 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 597 * round-to-nearest and is used by any operations (generally 598 * Neon) which the architecture defines as controlled by the 599 * standard FPSCR value rather than the FPSCR. 600 * 601 * To avoid having to transfer exception bits around, we simply 602 * say that the FPSCR cumulative exception flags are the logical 603 * OR of the flags in the three fp statuses. This relies on the 604 * only thing which needs to read the exception flags being 605 * an explicit FPSCR read. 606 */ 607 float_status fp_status; 608 float_status fp_status_f16; 609 float_status standard_fp_status; 610 611 /* ZCR_EL[1-3] */ 612 uint64_t zcr_el[4]; 613 } vfp; 614 uint64_t exclusive_addr; 615 uint64_t exclusive_val; 616 uint64_t exclusive_high; 617 618 /* iwMMXt coprocessor state. */ 619 struct { 620 uint64_t regs[16]; 621 uint64_t val; 622 623 uint32_t cregs[16]; 624 } iwmmxt; 625 626 #ifdef TARGET_AARCH64 627 ARMPACKey apia_key; 628 ARMPACKey apib_key; 629 ARMPACKey apda_key; 630 ARMPACKey apdb_key; 631 ARMPACKey apga_key; 632 #endif 633 634 #if defined(CONFIG_USER_ONLY) 635 /* For usermode syscall translation. */ 636 int eabi; 637 #endif 638 639 struct CPUBreakpoint *cpu_breakpoint[16]; 640 struct CPUWatchpoint *cpu_watchpoint[16]; 641 642 /* Fields up to this point are cleared by a CPU reset */ 643 struct {} end_reset_fields; 644 645 CPU_COMMON 646 647 /* Fields after CPU_COMMON are preserved across CPU reset. */ 648 649 /* Internal CPU feature flags. */ 650 uint64_t features; 651 652 /* PMSAv7 MPU */ 653 struct { 654 uint32_t *drbar; 655 uint32_t *drsr; 656 uint32_t *dracr; 657 uint32_t rnr[M_REG_NUM_BANKS]; 658 } pmsav7; 659 660 /* PMSAv8 MPU */ 661 struct { 662 /* The PMSAv8 implementation also shares some PMSAv7 config 663 * and state: 664 * pmsav7.rnr (region number register) 665 * pmsav7_dregion (number of configured regions) 666 */ 667 uint32_t *rbar[M_REG_NUM_BANKS]; 668 uint32_t *rlar[M_REG_NUM_BANKS]; 669 uint32_t mair0[M_REG_NUM_BANKS]; 670 uint32_t mair1[M_REG_NUM_BANKS]; 671 } pmsav8; 672 673 /* v8M SAU */ 674 struct { 675 uint32_t *rbar; 676 uint32_t *rlar; 677 uint32_t rnr; 678 uint32_t ctrl; 679 } sau; 680 681 void *nvic; 682 const struct arm_boot_info *boot_info; 683 /* Store GICv3CPUState to access from this struct */ 684 void *gicv3state; 685 } CPUARMState; 686 687 /** 688 * ARMELChangeHookFn: 689 * type of a function which can be registered via arm_register_el_change_hook() 690 * to get callbacks when the CPU changes its exception level or mode. 691 */ 692 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 693 typedef struct ARMELChangeHook ARMELChangeHook; 694 struct ARMELChangeHook { 695 ARMELChangeHookFn *hook; 696 void *opaque; 697 QLIST_ENTRY(ARMELChangeHook) node; 698 }; 699 700 /* These values map onto the return values for 701 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 702 typedef enum ARMPSCIState { 703 PSCI_ON = 0, 704 PSCI_OFF = 1, 705 PSCI_ON_PENDING = 2 706 } ARMPSCIState; 707 708 typedef struct ARMISARegisters ARMISARegisters; 709 710 /** 711 * ARMCPU: 712 * @env: #CPUARMState 713 * 714 * An ARM CPU core. 715 */ 716 struct ARMCPU { 717 /*< private >*/ 718 CPUState parent_obj; 719 /*< public >*/ 720 721 CPUARMState env; 722 723 /* Coprocessor information */ 724 GHashTable *cp_regs; 725 /* For marshalling (mostly coprocessor) register state between the 726 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 727 * we use these arrays. 728 */ 729 /* List of register indexes managed via these arrays; (full KVM style 730 * 64 bit indexes, not CPRegInfo 32 bit indexes) 731 */ 732 uint64_t *cpreg_indexes; 733 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 734 uint64_t *cpreg_values; 735 /* Length of the indexes, values, reset_values arrays */ 736 int32_t cpreg_array_len; 737 /* These are used only for migration: incoming data arrives in 738 * these fields and is sanity checked in post_load before copying 739 * to the working data structures above. 740 */ 741 uint64_t *cpreg_vmstate_indexes; 742 uint64_t *cpreg_vmstate_values; 743 int32_t cpreg_vmstate_array_len; 744 745 DynamicGDBXMLInfo dyn_xml; 746 747 /* Timers used by the generic (architected) timer */ 748 QEMUTimer *gt_timer[NUM_GTIMERS]; 749 /* GPIO outputs for generic timer */ 750 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 751 /* GPIO output for GICv3 maintenance interrupt signal */ 752 qemu_irq gicv3_maintenance_interrupt; 753 /* GPIO output for the PMU interrupt */ 754 qemu_irq pmu_interrupt; 755 756 /* MemoryRegion to use for secure physical accesses */ 757 MemoryRegion *secure_memory; 758 759 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 760 Object *idau; 761 762 /* 'compatible' string for this CPU for Linux device trees */ 763 const char *dtb_compatible; 764 765 /* PSCI version for this CPU 766 * Bits[31:16] = Major Version 767 * Bits[15:0] = Minor Version 768 */ 769 uint32_t psci_version; 770 771 /* Should CPU start in PSCI powered-off state? */ 772 bool start_powered_off; 773 774 /* Current power state, access guarded by BQL */ 775 ARMPSCIState power_state; 776 777 /* CPU has virtualization extension */ 778 bool has_el2; 779 /* CPU has security extension */ 780 bool has_el3; 781 /* CPU has PMU (Performance Monitor Unit) */ 782 bool has_pmu; 783 784 /* CPU has memory protection unit */ 785 bool has_mpu; 786 /* PMSAv7 MPU number of supported regions */ 787 uint32_t pmsav7_dregion; 788 /* v8M SAU number of supported regions */ 789 uint32_t sau_sregion; 790 791 /* PSCI conduit used to invoke PSCI methods 792 * 0 - disabled, 1 - smc, 2 - hvc 793 */ 794 uint32_t psci_conduit; 795 796 /* For v8M, initial value of the Secure VTOR */ 797 uint32_t init_svtor; 798 799 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 800 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 801 */ 802 uint32_t kvm_target; 803 804 /* KVM init features for this CPU */ 805 uint32_t kvm_init_features[7]; 806 807 /* Uniprocessor system with MP extensions */ 808 bool mp_is_up; 809 810 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 811 * and the probe failed (so we need to report the error in realize) 812 */ 813 bool host_cpu_probe_failed; 814 815 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 816 * register. 817 */ 818 int32_t core_count; 819 820 /* The instance init functions for implementation-specific subclasses 821 * set these fields to specify the implementation-dependent values of 822 * various constant registers and reset values of non-constant 823 * registers. 824 * Some of these might become QOM properties eventually. 825 * Field names match the official register names as defined in the 826 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 827 * is used for reset values of non-constant registers; no reset_ 828 * prefix means a constant register. 829 * Some of these registers are split out into a substructure that 830 * is shared with the translators to control the ISA. 831 */ 832 struct ARMISARegisters { 833 uint32_t id_isar0; 834 uint32_t id_isar1; 835 uint32_t id_isar2; 836 uint32_t id_isar3; 837 uint32_t id_isar4; 838 uint32_t id_isar5; 839 uint32_t id_isar6; 840 uint32_t mvfr0; 841 uint32_t mvfr1; 842 uint32_t mvfr2; 843 uint64_t id_aa64isar0; 844 uint64_t id_aa64isar1; 845 uint64_t id_aa64pfr0; 846 uint64_t id_aa64pfr1; 847 uint64_t id_aa64mmfr0; 848 uint64_t id_aa64mmfr1; 849 } isar; 850 uint32_t midr; 851 uint32_t revidr; 852 uint32_t reset_fpsid; 853 uint32_t ctr; 854 uint32_t reset_sctlr; 855 uint32_t id_pfr0; 856 uint32_t id_pfr1; 857 uint32_t id_dfr0; 858 uint64_t pmceid0; 859 uint64_t pmceid1; 860 uint32_t id_afr0; 861 uint32_t id_mmfr0; 862 uint32_t id_mmfr1; 863 uint32_t id_mmfr2; 864 uint32_t id_mmfr3; 865 uint32_t id_mmfr4; 866 uint64_t id_aa64dfr0; 867 uint64_t id_aa64dfr1; 868 uint64_t id_aa64afr0; 869 uint64_t id_aa64afr1; 870 uint32_t dbgdidr; 871 uint32_t clidr; 872 uint64_t mp_affinity; /* MP ID without feature bits */ 873 /* The elements of this array are the CCSIDR values for each cache, 874 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 875 */ 876 uint32_t ccsidr[16]; 877 uint64_t reset_cbar; 878 uint32_t reset_auxcr; 879 bool reset_hivecs; 880 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 881 uint32_t dcz_blocksize; 882 uint64_t rvbar; 883 884 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 885 int gic_num_lrs; /* number of list registers */ 886 int gic_vpribits; /* number of virtual priority bits */ 887 int gic_vprebits; /* number of virtual preemption bits */ 888 889 /* Whether the cfgend input is high (i.e. this CPU should reset into 890 * big-endian mode). This setting isn't used directly: instead it modifies 891 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 892 * architecture version. 893 */ 894 bool cfgend; 895 896 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 897 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 898 899 int32_t node_id; /* NUMA node this CPU belongs to */ 900 901 /* Used to synchronize KVM and QEMU in-kernel device levels */ 902 uint8_t device_irq_level; 903 904 /* Used to set the maximum vector length the cpu will support. */ 905 uint32_t sve_max_vq; 906 }; 907 908 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) 909 { 910 return container_of(env, ARMCPU, env); 911 } 912 913 void arm_cpu_post_init(Object *obj); 914 915 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 916 917 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) 918 919 #define ENV_OFFSET offsetof(ARMCPU, env) 920 921 #ifndef CONFIG_USER_ONLY 922 extern const struct VMStateDescription vmstate_arm_cpu; 923 #endif 924 925 void arm_cpu_do_interrupt(CPUState *cpu); 926 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 927 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); 928 929 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 930 int flags); 931 932 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 933 MemTxAttrs *attrs); 934 935 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 936 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 937 938 /* Dynamically generates for gdb stub an XML description of the sysregs from 939 * the cp_regs hashtable. Returns the registered sysregs number. 940 */ 941 int arm_gen_dynamic_xml(CPUState *cpu); 942 943 /* Returns the dynamically generated XML for the gdb stub. 944 * Returns a pointer to the XML contents for the specified XML file or NULL 945 * if the XML name doesn't match the predefined one. 946 */ 947 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 948 949 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 950 int cpuid, void *opaque); 951 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 952 int cpuid, void *opaque); 953 954 #ifdef TARGET_AARCH64 955 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 956 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 957 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 958 void aarch64_sve_change_el(CPUARMState *env, int old_el, 959 int new_el, bool el0_a64); 960 #else 961 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 962 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 963 int n, bool a) 964 { } 965 #endif 966 967 target_ulong do_arm_semihosting(CPUARMState *env); 968 void aarch64_sync_32_to_64(CPUARMState *env); 969 void aarch64_sync_64_to_32(CPUARMState *env); 970 971 int fp_exception_el(CPUARMState *env, int cur_el); 972 int sve_exception_el(CPUARMState *env, int cur_el); 973 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 974 975 static inline bool is_a64(CPUARMState *env) 976 { 977 return env->aarch64; 978 } 979 980 /* you can call this signal handler from your SIGBUS and SIGSEGV 981 signal handlers to inform the virtual CPU of exceptions. non zero 982 is returned if the signal was handled by the virtual CPU. */ 983 int cpu_arm_signal_handler(int host_signum, void *pinfo, 984 void *puc); 985 986 /** 987 * pmccntr_op_start/finish 988 * @env: CPUARMState 989 * 990 * Convert the counter in the PMCCNTR between its delta form (the typical mode 991 * when it's enabled) and the guest-visible value. These two calls must always 992 * surround any action which might affect the counter. 993 */ 994 void pmccntr_op_start(CPUARMState *env); 995 void pmccntr_op_finish(CPUARMState *env); 996 997 /** 998 * pmu_op_start/finish 999 * @env: CPUARMState 1000 * 1001 * Convert all PMU counters between their delta form (the typical mode when 1002 * they are enabled) and the guest-visible values. These two calls must 1003 * surround any action which might affect the counters. 1004 */ 1005 void pmu_op_start(CPUARMState *env); 1006 void pmu_op_finish(CPUARMState *env); 1007 1008 /** 1009 * Functions to register as EL change hooks for PMU mode filtering 1010 */ 1011 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1012 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1013 1014 /* 1015 * pmu_init 1016 * @cpu: ARMCPU 1017 * 1018 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1019 * for the current configuration 1020 */ 1021 void pmu_init(ARMCPU *cpu); 1022 1023 /* SCTLR bit meanings. Several bits have been reused in newer 1024 * versions of the architecture; in that case we define constants 1025 * for both old and new bit meanings. Code which tests against those 1026 * bits should probably check or otherwise arrange that the CPU 1027 * is the architectural version it expects. 1028 */ 1029 #define SCTLR_M (1U << 0) 1030 #define SCTLR_A (1U << 1) 1031 #define SCTLR_C (1U << 2) 1032 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1033 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1034 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1035 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1036 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1037 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1038 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1039 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1040 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1041 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1042 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1043 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1044 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1045 #define SCTLR_SED (1U << 8) /* v8 onward */ 1046 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1047 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1048 #define SCTLR_F (1U << 10) /* up to v6 */ 1049 #define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ 1050 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1051 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1052 #define SCTLR_I (1U << 12) 1053 #define SCTLR_V (1U << 13) /* AArch32 only */ 1054 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1055 #define SCTLR_RR (1U << 14) /* up to v7 */ 1056 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1057 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1058 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1059 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1060 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1061 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1062 #define SCTLR_BR (1U << 17) /* PMSA only */ 1063 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1064 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1065 #define SCTLR_WXN (1U << 19) 1066 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1067 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1068 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1069 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1070 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1071 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1072 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1073 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1074 #define SCTLR_VE (1U << 24) /* up to v7 */ 1075 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1076 #define SCTLR_EE (1U << 25) 1077 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1078 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1079 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1080 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1081 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1082 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1083 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1084 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1085 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1086 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1087 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1088 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1089 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1090 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1091 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1092 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1093 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1094 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1095 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ 1096 1097 #define CPTR_TCPAC (1U << 31) 1098 #define CPTR_TTA (1U << 20) 1099 #define CPTR_TFP (1U << 10) 1100 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1101 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1102 1103 #define MDCR_EPMAD (1U << 21) 1104 #define MDCR_EDAD (1U << 20) 1105 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1106 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1107 #define MDCR_SDD (1U << 16) 1108 #define MDCR_SPD (3U << 14) 1109 #define MDCR_TDRA (1U << 11) 1110 #define MDCR_TDOSA (1U << 10) 1111 #define MDCR_TDA (1U << 9) 1112 #define MDCR_TDE (1U << 8) 1113 #define MDCR_HPME (1U << 7) 1114 #define MDCR_TPM (1U << 6) 1115 #define MDCR_TPMCR (1U << 5) 1116 #define MDCR_HPMN (0x1fU) 1117 1118 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1119 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1120 1121 #define CPSR_M (0x1fU) 1122 #define CPSR_T (1U << 5) 1123 #define CPSR_F (1U << 6) 1124 #define CPSR_I (1U << 7) 1125 #define CPSR_A (1U << 8) 1126 #define CPSR_E (1U << 9) 1127 #define CPSR_IT_2_7 (0xfc00U) 1128 #define CPSR_GE (0xfU << 16) 1129 #define CPSR_IL (1U << 20) 1130 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in 1131 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use 1132 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, 1133 * where it is live state but not accessible to the AArch32 code. 1134 */ 1135 #define CPSR_RESERVED (0x7U << 21) 1136 #define CPSR_J (1U << 24) 1137 #define CPSR_IT_0_1 (3U << 25) 1138 #define CPSR_Q (1U << 27) 1139 #define CPSR_V (1U << 28) 1140 #define CPSR_C (1U << 29) 1141 #define CPSR_Z (1U << 30) 1142 #define CPSR_N (1U << 31) 1143 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1144 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1145 1146 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1147 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1148 | CPSR_NZCV) 1149 /* Bits writable in user mode. */ 1150 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 1151 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1152 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1153 /* Mask of bits which may be set by exception return copying them from SPSR */ 1154 #define CPSR_ERET_MASK (~CPSR_RESERVED) 1155 1156 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1157 #define XPSR_EXCP 0x1ffU 1158 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1159 #define XPSR_IT_2_7 CPSR_IT_2_7 1160 #define XPSR_GE CPSR_GE 1161 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1162 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1163 #define XPSR_IT_0_1 CPSR_IT_0_1 1164 #define XPSR_Q CPSR_Q 1165 #define XPSR_V CPSR_V 1166 #define XPSR_C CPSR_C 1167 #define XPSR_Z CPSR_Z 1168 #define XPSR_N CPSR_N 1169 #define XPSR_NZCV CPSR_NZCV 1170 #define XPSR_IT CPSR_IT 1171 1172 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1173 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1174 #define TTBCR_PD0 (1U << 4) 1175 #define TTBCR_PD1 (1U << 5) 1176 #define TTBCR_EPD0 (1U << 7) 1177 #define TTBCR_IRGN0 (3U << 8) 1178 #define TTBCR_ORGN0 (3U << 10) 1179 #define TTBCR_SH0 (3U << 12) 1180 #define TTBCR_T1SZ (3U << 16) 1181 #define TTBCR_A1 (1U << 22) 1182 #define TTBCR_EPD1 (1U << 23) 1183 #define TTBCR_IRGN1 (3U << 24) 1184 #define TTBCR_ORGN1 (3U << 26) 1185 #define TTBCR_SH1 (1U << 28) 1186 #define TTBCR_EAE (1U << 31) 1187 1188 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1189 * Only these are valid when in AArch64 mode; in 1190 * AArch32 mode SPSRs are basically CPSR-format. 1191 */ 1192 #define PSTATE_SP (1U) 1193 #define PSTATE_M (0xFU) 1194 #define PSTATE_nRW (1U << 4) 1195 #define PSTATE_F (1U << 6) 1196 #define PSTATE_I (1U << 7) 1197 #define PSTATE_A (1U << 8) 1198 #define PSTATE_D (1U << 9) 1199 #define PSTATE_IL (1U << 20) 1200 #define PSTATE_SS (1U << 21) 1201 #define PSTATE_V (1U << 28) 1202 #define PSTATE_C (1U << 29) 1203 #define PSTATE_Z (1U << 30) 1204 #define PSTATE_N (1U << 31) 1205 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1206 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1207 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) 1208 /* Mode values for AArch64 */ 1209 #define PSTATE_MODE_EL3h 13 1210 #define PSTATE_MODE_EL3t 12 1211 #define PSTATE_MODE_EL2h 9 1212 #define PSTATE_MODE_EL2t 8 1213 #define PSTATE_MODE_EL1h 5 1214 #define PSTATE_MODE_EL1t 4 1215 #define PSTATE_MODE_EL0t 0 1216 1217 /* Write a new value to v7m.exception, thus transitioning into or out 1218 * of Handler mode; this may result in a change of active stack pointer. 1219 */ 1220 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1221 1222 /* Map EL and handler into a PSTATE_MODE. */ 1223 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1224 { 1225 return (el << 2) | handler; 1226 } 1227 1228 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1229 * interprocessing, so we don't attempt to sync with the cpsr state used by 1230 * the 32 bit decoder. 1231 */ 1232 static inline uint32_t pstate_read(CPUARMState *env) 1233 { 1234 int ZF; 1235 1236 ZF = (env->ZF == 0); 1237 return (env->NF & 0x80000000) | (ZF << 30) 1238 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1239 | env->pstate | env->daif; 1240 } 1241 1242 static inline void pstate_write(CPUARMState *env, uint32_t val) 1243 { 1244 env->ZF = (~val) & PSTATE_Z; 1245 env->NF = val; 1246 env->CF = (val >> 29) & 1; 1247 env->VF = (val << 3) & 0x80000000; 1248 env->daif = val & PSTATE_DAIF; 1249 env->pstate = val & ~CACHED_PSTATE_BITS; 1250 } 1251 1252 /* Return the current CPSR value. */ 1253 uint32_t cpsr_read(CPUARMState *env); 1254 1255 typedef enum CPSRWriteType { 1256 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1257 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1258 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ 1259 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1260 } CPSRWriteType; 1261 1262 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ 1263 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1264 CPSRWriteType write_type); 1265 1266 /* Return the current xPSR value. */ 1267 static inline uint32_t xpsr_read(CPUARMState *env) 1268 { 1269 int ZF; 1270 ZF = (env->ZF == 0); 1271 return (env->NF & 0x80000000) | (ZF << 30) 1272 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1273 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1274 | ((env->condexec_bits & 0xfc) << 8) 1275 | env->v7m.exception; 1276 } 1277 1278 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1279 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1280 { 1281 if (mask & XPSR_NZCV) { 1282 env->ZF = (~val) & XPSR_Z; 1283 env->NF = val; 1284 env->CF = (val >> 29) & 1; 1285 env->VF = (val << 3) & 0x80000000; 1286 } 1287 if (mask & XPSR_Q) { 1288 env->QF = ((val & XPSR_Q) != 0); 1289 } 1290 if (mask & XPSR_T) { 1291 env->thumb = ((val & XPSR_T) != 0); 1292 } 1293 if (mask & XPSR_IT_0_1) { 1294 env->condexec_bits &= ~3; 1295 env->condexec_bits |= (val >> 25) & 3; 1296 } 1297 if (mask & XPSR_IT_2_7) { 1298 env->condexec_bits &= 3; 1299 env->condexec_bits |= (val >> 8) & 0xfc; 1300 } 1301 if (mask & XPSR_EXCP) { 1302 /* Note that this only happens on exception exit */ 1303 write_v7m_exception(env, val & XPSR_EXCP); 1304 } 1305 } 1306 1307 #define HCR_VM (1ULL << 0) 1308 #define HCR_SWIO (1ULL << 1) 1309 #define HCR_PTW (1ULL << 2) 1310 #define HCR_FMO (1ULL << 3) 1311 #define HCR_IMO (1ULL << 4) 1312 #define HCR_AMO (1ULL << 5) 1313 #define HCR_VF (1ULL << 6) 1314 #define HCR_VI (1ULL << 7) 1315 #define HCR_VSE (1ULL << 8) 1316 #define HCR_FB (1ULL << 9) 1317 #define HCR_BSU_MASK (3ULL << 10) 1318 #define HCR_DC (1ULL << 12) 1319 #define HCR_TWI (1ULL << 13) 1320 #define HCR_TWE (1ULL << 14) 1321 #define HCR_TID0 (1ULL << 15) 1322 #define HCR_TID1 (1ULL << 16) 1323 #define HCR_TID2 (1ULL << 17) 1324 #define HCR_TID3 (1ULL << 18) 1325 #define HCR_TSC (1ULL << 19) 1326 #define HCR_TIDCP (1ULL << 20) 1327 #define HCR_TACR (1ULL << 21) 1328 #define HCR_TSW (1ULL << 22) 1329 #define HCR_TPCP (1ULL << 23) 1330 #define HCR_TPU (1ULL << 24) 1331 #define HCR_TTLB (1ULL << 25) 1332 #define HCR_TVM (1ULL << 26) 1333 #define HCR_TGE (1ULL << 27) 1334 #define HCR_TDZ (1ULL << 28) 1335 #define HCR_HCD (1ULL << 29) 1336 #define HCR_TRVM (1ULL << 30) 1337 #define HCR_RW (1ULL << 31) 1338 #define HCR_CD (1ULL << 32) 1339 #define HCR_ID (1ULL << 33) 1340 #define HCR_E2H (1ULL << 34) 1341 #define HCR_TLOR (1ULL << 35) 1342 #define HCR_TERR (1ULL << 36) 1343 #define HCR_TEA (1ULL << 37) 1344 #define HCR_MIOCNCE (1ULL << 38) 1345 #define HCR_APK (1ULL << 40) 1346 #define HCR_API (1ULL << 41) 1347 #define HCR_NV (1ULL << 42) 1348 #define HCR_NV1 (1ULL << 43) 1349 #define HCR_AT (1ULL << 44) 1350 #define HCR_NV2 (1ULL << 45) 1351 #define HCR_FWB (1ULL << 46) 1352 #define HCR_FIEN (1ULL << 47) 1353 #define HCR_TID4 (1ULL << 49) 1354 #define HCR_TICAB (1ULL << 50) 1355 #define HCR_TOCU (1ULL << 52) 1356 #define HCR_TTLBIS (1ULL << 54) 1357 #define HCR_TTLBOS (1ULL << 55) 1358 #define HCR_ATA (1ULL << 56) 1359 #define HCR_DCT (1ULL << 57) 1360 1361 /* 1362 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to 1363 * HCR_MASK and then clear it again if the feature bit is not set in 1364 * hcr_write(). 1365 */ 1366 #define HCR_MASK ((1ULL << 34) - 1) 1367 1368 #define SCR_NS (1U << 0) 1369 #define SCR_IRQ (1U << 1) 1370 #define SCR_FIQ (1U << 2) 1371 #define SCR_EA (1U << 3) 1372 #define SCR_FW (1U << 4) 1373 #define SCR_AW (1U << 5) 1374 #define SCR_NET (1U << 6) 1375 #define SCR_SMD (1U << 7) 1376 #define SCR_HCE (1U << 8) 1377 #define SCR_SIF (1U << 9) 1378 #define SCR_RW (1U << 10) 1379 #define SCR_ST (1U << 11) 1380 #define SCR_TWI (1U << 12) 1381 #define SCR_TWE (1U << 13) 1382 #define SCR_TLOR (1U << 14) 1383 #define SCR_TERR (1U << 15) 1384 #define SCR_APK (1U << 16) 1385 #define SCR_API (1U << 17) 1386 #define SCR_EEL2 (1U << 18) 1387 #define SCR_EASE (1U << 19) 1388 #define SCR_NMEA (1U << 20) 1389 #define SCR_FIEN (1U << 21) 1390 #define SCR_ENSCXT (1U << 25) 1391 #define SCR_ATA (1U << 26) 1392 1393 /* Return the current FPSCR value. */ 1394 uint32_t vfp_get_fpscr(CPUARMState *env); 1395 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1396 1397 /* FPCR, Floating Point Control Register 1398 * FPSR, Floating Poiht Status Register 1399 * 1400 * For A64 the FPSCR is split into two logically distinct registers, 1401 * FPCR and FPSR. However since they still use non-overlapping bits 1402 * we store the underlying state in fpscr and just mask on read/write. 1403 */ 1404 #define FPSR_MASK 0xf800009f 1405 #define FPCR_MASK 0x07ff9f00 1406 1407 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1408 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1409 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1410 1411 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1412 { 1413 return vfp_get_fpscr(env) & FPSR_MASK; 1414 } 1415 1416 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1417 { 1418 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1419 vfp_set_fpscr(env, new_fpscr); 1420 } 1421 1422 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1423 { 1424 return vfp_get_fpscr(env) & FPCR_MASK; 1425 } 1426 1427 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1428 { 1429 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1430 vfp_set_fpscr(env, new_fpscr); 1431 } 1432 1433 enum arm_cpu_mode { 1434 ARM_CPU_MODE_USR = 0x10, 1435 ARM_CPU_MODE_FIQ = 0x11, 1436 ARM_CPU_MODE_IRQ = 0x12, 1437 ARM_CPU_MODE_SVC = 0x13, 1438 ARM_CPU_MODE_MON = 0x16, 1439 ARM_CPU_MODE_ABT = 0x17, 1440 ARM_CPU_MODE_HYP = 0x1a, 1441 ARM_CPU_MODE_UND = 0x1b, 1442 ARM_CPU_MODE_SYS = 0x1f 1443 }; 1444 1445 /* VFP system registers. */ 1446 #define ARM_VFP_FPSID 0 1447 #define ARM_VFP_FPSCR 1 1448 #define ARM_VFP_MVFR2 5 1449 #define ARM_VFP_MVFR1 6 1450 #define ARM_VFP_MVFR0 7 1451 #define ARM_VFP_FPEXC 8 1452 #define ARM_VFP_FPINST 9 1453 #define ARM_VFP_FPINST2 10 1454 1455 /* iwMMXt coprocessor control registers. */ 1456 #define ARM_IWMMXT_wCID 0 1457 #define ARM_IWMMXT_wCon 1 1458 #define ARM_IWMMXT_wCSSF 2 1459 #define ARM_IWMMXT_wCASF 3 1460 #define ARM_IWMMXT_wCGR0 8 1461 #define ARM_IWMMXT_wCGR1 9 1462 #define ARM_IWMMXT_wCGR2 10 1463 #define ARM_IWMMXT_wCGR3 11 1464 1465 /* V7M CCR bits */ 1466 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1467 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1468 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1469 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1470 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1471 FIELD(V7M_CCR, STKALIGN, 9, 1) 1472 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1473 FIELD(V7M_CCR, DC, 16, 1) 1474 FIELD(V7M_CCR, IC, 17, 1) 1475 FIELD(V7M_CCR, BP, 18, 1) 1476 1477 /* V7M SCR bits */ 1478 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1479 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1480 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1481 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1482 1483 /* V7M AIRCR bits */ 1484 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1485 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1486 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1487 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1488 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1489 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1490 FIELD(V7M_AIRCR, PRIS, 14, 1) 1491 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1492 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1493 1494 /* V7M CFSR bits for MMFSR */ 1495 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1496 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1497 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1498 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1499 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1500 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1501 1502 /* V7M CFSR bits for BFSR */ 1503 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1504 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1505 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1506 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1507 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1508 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1509 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1510 1511 /* V7M CFSR bits for UFSR */ 1512 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1513 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1514 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1515 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1516 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1517 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1518 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1519 1520 /* V7M CFSR bit masks covering all of the subregister bits */ 1521 FIELD(V7M_CFSR, MMFSR, 0, 8) 1522 FIELD(V7M_CFSR, BFSR, 8, 8) 1523 FIELD(V7M_CFSR, UFSR, 16, 16) 1524 1525 /* V7M HFSR bits */ 1526 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1527 FIELD(V7M_HFSR, FORCED, 30, 1) 1528 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1529 1530 /* V7M DFSR bits */ 1531 FIELD(V7M_DFSR, HALTED, 0, 1) 1532 FIELD(V7M_DFSR, BKPT, 1, 1) 1533 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1534 FIELD(V7M_DFSR, VCATCH, 3, 1) 1535 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1536 1537 /* V7M SFSR bits */ 1538 FIELD(V7M_SFSR, INVEP, 0, 1) 1539 FIELD(V7M_SFSR, INVIS, 1, 1) 1540 FIELD(V7M_SFSR, INVER, 2, 1) 1541 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1542 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1543 FIELD(V7M_SFSR, LSPERR, 5, 1) 1544 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1545 FIELD(V7M_SFSR, LSERR, 7, 1) 1546 1547 /* v7M MPU_CTRL bits */ 1548 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1549 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1550 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1551 1552 /* v7M CLIDR bits */ 1553 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1554 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1555 FIELD(V7M_CLIDR, LOC, 24, 3) 1556 FIELD(V7M_CLIDR, LOUU, 27, 3) 1557 FIELD(V7M_CLIDR, ICB, 30, 2) 1558 1559 FIELD(V7M_CSSELR, IND, 0, 1) 1560 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1561 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1562 * define a mask for this and check that it doesn't permit running off 1563 * the end of the array. 1564 */ 1565 FIELD(V7M_CSSELR, INDEX, 0, 4) 1566 1567 /* 1568 * System register ID fields. 1569 */ 1570 FIELD(ID_ISAR0, SWAP, 0, 4) 1571 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1572 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1573 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1574 FIELD(ID_ISAR0, COPROC, 16, 4) 1575 FIELD(ID_ISAR0, DEBUG, 20, 4) 1576 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1577 1578 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1579 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1580 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1581 FIELD(ID_ISAR1, EXTEND, 12, 4) 1582 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1583 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1584 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1585 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1586 1587 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1588 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1589 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1590 FIELD(ID_ISAR2, MULT, 12, 4) 1591 FIELD(ID_ISAR2, MULTS, 16, 4) 1592 FIELD(ID_ISAR2, MULTU, 20, 4) 1593 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1594 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1595 1596 FIELD(ID_ISAR3, SATURATE, 0, 4) 1597 FIELD(ID_ISAR3, SIMD, 4, 4) 1598 FIELD(ID_ISAR3, SVC, 8, 4) 1599 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1600 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1601 FIELD(ID_ISAR3, T32COPY, 20, 4) 1602 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1603 FIELD(ID_ISAR3, T32EE, 28, 4) 1604 1605 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1606 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1607 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1608 FIELD(ID_ISAR4, SMC, 12, 4) 1609 FIELD(ID_ISAR4, BARRIER, 16, 4) 1610 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1611 FIELD(ID_ISAR4, PSR_M, 24, 4) 1612 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1613 1614 FIELD(ID_ISAR5, SEVL, 0, 4) 1615 FIELD(ID_ISAR5, AES, 4, 4) 1616 FIELD(ID_ISAR5, SHA1, 8, 4) 1617 FIELD(ID_ISAR5, SHA2, 12, 4) 1618 FIELD(ID_ISAR5, CRC32, 16, 4) 1619 FIELD(ID_ISAR5, RDM, 24, 4) 1620 FIELD(ID_ISAR5, VCMA, 28, 4) 1621 1622 FIELD(ID_ISAR6, JSCVT, 0, 4) 1623 FIELD(ID_ISAR6, DP, 4, 4) 1624 FIELD(ID_ISAR6, FHM, 8, 4) 1625 FIELD(ID_ISAR6, SB, 12, 4) 1626 FIELD(ID_ISAR6, SPECRES, 16, 4) 1627 1628 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1629 FIELD(ID_MMFR4, AC2, 4, 4) 1630 FIELD(ID_MMFR4, XNX, 8, 4) 1631 FIELD(ID_MMFR4, CNP, 12, 4) 1632 FIELD(ID_MMFR4, HPDS, 16, 4) 1633 FIELD(ID_MMFR4, LSM, 20, 4) 1634 FIELD(ID_MMFR4, CCIDX, 24, 4) 1635 FIELD(ID_MMFR4, EVT, 28, 4) 1636 1637 FIELD(ID_AA64ISAR0, AES, 4, 4) 1638 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 1639 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 1640 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 1641 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 1642 FIELD(ID_AA64ISAR0, RDM, 28, 4) 1643 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 1644 FIELD(ID_AA64ISAR0, SM3, 36, 4) 1645 FIELD(ID_AA64ISAR0, SM4, 40, 4) 1646 FIELD(ID_AA64ISAR0, DP, 44, 4) 1647 FIELD(ID_AA64ISAR0, FHM, 48, 4) 1648 FIELD(ID_AA64ISAR0, TS, 52, 4) 1649 FIELD(ID_AA64ISAR0, TLB, 56, 4) 1650 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 1651 1652 FIELD(ID_AA64ISAR1, DPB, 0, 4) 1653 FIELD(ID_AA64ISAR1, APA, 4, 4) 1654 FIELD(ID_AA64ISAR1, API, 8, 4) 1655 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 1656 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 1657 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 1658 FIELD(ID_AA64ISAR1, GPA, 24, 4) 1659 FIELD(ID_AA64ISAR1, GPI, 28, 4) 1660 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 1661 FIELD(ID_AA64ISAR1, SB, 36, 4) 1662 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 1663 1664 FIELD(ID_AA64PFR0, EL0, 0, 4) 1665 FIELD(ID_AA64PFR0, EL1, 4, 4) 1666 FIELD(ID_AA64PFR0, EL2, 8, 4) 1667 FIELD(ID_AA64PFR0, EL3, 12, 4) 1668 FIELD(ID_AA64PFR0, FP, 16, 4) 1669 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 1670 FIELD(ID_AA64PFR0, GIC, 24, 4) 1671 FIELD(ID_AA64PFR0, RAS, 28, 4) 1672 FIELD(ID_AA64PFR0, SVE, 32, 4) 1673 1674 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 1675 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 1676 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 1677 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 1678 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 1679 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 1680 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 1681 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 1682 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 1683 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 1684 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 1685 FIELD(ID_AA64MMFR0, EXS, 44, 4) 1686 1687 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 1688 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 1689 FIELD(ID_AA64MMFR1, VH, 8, 4) 1690 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 1691 FIELD(ID_AA64MMFR1, LO, 16, 4) 1692 FIELD(ID_AA64MMFR1, PAN, 20, 4) 1693 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 1694 FIELD(ID_AA64MMFR1, XNX, 28, 4) 1695 1696 FIELD(ID_DFR0, COPDBG, 0, 4) 1697 FIELD(ID_DFR0, COPSDBG, 4, 4) 1698 FIELD(ID_DFR0, MMAPDBG, 8, 4) 1699 FIELD(ID_DFR0, COPTRC, 12, 4) 1700 FIELD(ID_DFR0, MMAPTRC, 16, 4) 1701 FIELD(ID_DFR0, MPROFDBG, 20, 4) 1702 FIELD(ID_DFR0, PERFMON, 24, 4) 1703 FIELD(ID_DFR0, TRACEFILT, 28, 4) 1704 1705 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 1706 1707 /* If adding a feature bit which corresponds to a Linux ELF 1708 * HWCAP bit, remember to update the feature-bit-to-hwcap 1709 * mapping in linux-user/elfload.c:get_elf_hwcap(). 1710 */ 1711 enum arm_features { 1712 ARM_FEATURE_VFP, 1713 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 1714 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 1715 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 1716 ARM_FEATURE_V6, 1717 ARM_FEATURE_V6K, 1718 ARM_FEATURE_V7, 1719 ARM_FEATURE_THUMB2, 1720 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 1721 ARM_FEATURE_VFP3, 1722 ARM_FEATURE_VFP_FP16, 1723 ARM_FEATURE_NEON, 1724 ARM_FEATURE_M, /* Microcontroller profile. */ 1725 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 1726 ARM_FEATURE_THUMB2EE, 1727 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 1728 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 1729 ARM_FEATURE_V4T, 1730 ARM_FEATURE_V5, 1731 ARM_FEATURE_STRONGARM, 1732 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 1733 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ 1734 ARM_FEATURE_GENERIC_TIMER, 1735 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 1736 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 1737 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 1738 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 1739 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 1740 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 1741 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ 1742 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 1743 ARM_FEATURE_V8, 1744 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 1745 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 1746 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ 1747 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 1748 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 1749 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 1750 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 1751 ARM_FEATURE_PMU, /* has PMU support */ 1752 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 1753 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 1754 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 1755 }; 1756 1757 static inline int arm_feature(CPUARMState *env, int feature) 1758 { 1759 return (env->features & (1ULL << feature)) != 0; 1760 } 1761 1762 #if !defined(CONFIG_USER_ONLY) 1763 /* Return true if exception levels below EL3 are in secure state, 1764 * or would be following an exception return to that level. 1765 * Unlike arm_is_secure() (which is always a question about the 1766 * _current_ state of the CPU) this doesn't care about the current 1767 * EL or mode. 1768 */ 1769 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1770 { 1771 if (arm_feature(env, ARM_FEATURE_EL3)) { 1772 return !(env->cp15.scr_el3 & SCR_NS); 1773 } else { 1774 /* If EL3 is not supported then the secure state is implementation 1775 * defined, in which case QEMU defaults to non-secure. 1776 */ 1777 return false; 1778 } 1779 } 1780 1781 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 1782 static inline bool arm_is_el3_or_mon(CPUARMState *env) 1783 { 1784 if (arm_feature(env, ARM_FEATURE_EL3)) { 1785 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 1786 /* CPU currently in AArch64 state and EL3 */ 1787 return true; 1788 } else if (!is_a64(env) && 1789 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 1790 /* CPU currently in AArch32 state and monitor mode */ 1791 return true; 1792 } 1793 } 1794 return false; 1795 } 1796 1797 /* Return true if the processor is in secure state */ 1798 static inline bool arm_is_secure(CPUARMState *env) 1799 { 1800 if (arm_is_el3_or_mon(env)) { 1801 return true; 1802 } 1803 return arm_is_secure_below_el3(env); 1804 } 1805 1806 #else 1807 static inline bool arm_is_secure_below_el3(CPUARMState *env) 1808 { 1809 return false; 1810 } 1811 1812 static inline bool arm_is_secure(CPUARMState *env) 1813 { 1814 return false; 1815 } 1816 #endif 1817 1818 /** 1819 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 1820 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 1821 * "for all purposes other than a direct read or write access of HCR_EL2." 1822 * Not included here is HCR_RW. 1823 */ 1824 uint64_t arm_hcr_el2_eff(CPUARMState *env); 1825 1826 /* Return true if the specified exception level is running in AArch64 state. */ 1827 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 1828 { 1829 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 1830 * and if we're not in EL0 then the state of EL0 isn't well defined.) 1831 */ 1832 assert(el >= 1 && el <= 3); 1833 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 1834 1835 /* The highest exception level is always at the maximum supported 1836 * register width, and then lower levels have a register width controlled 1837 * by bits in the SCR or HCR registers. 1838 */ 1839 if (el == 3) { 1840 return aa64; 1841 } 1842 1843 if (arm_feature(env, ARM_FEATURE_EL3)) { 1844 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 1845 } 1846 1847 if (el == 2) { 1848 return aa64; 1849 } 1850 1851 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { 1852 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 1853 } 1854 1855 return aa64; 1856 } 1857 1858 /* Function for determing whether guest cp register reads and writes should 1859 * access the secure or non-secure bank of a cp register. When EL3 is 1860 * operating in AArch32 state, the NS-bit determines whether the secure 1861 * instance of a cp register should be used. When EL3 is AArch64 (or if 1862 * it doesn't exist at all) then there is no register banking, and all 1863 * accesses are to the non-secure version. 1864 */ 1865 static inline bool access_secure_reg(CPUARMState *env) 1866 { 1867 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 1868 !arm_el_is_aa64(env, 3) && 1869 !(env->cp15.scr_el3 & SCR_NS)); 1870 1871 return ret; 1872 } 1873 1874 /* Macros for accessing a specified CP register bank */ 1875 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1876 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1877 1878 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1879 do { \ 1880 if (_secure) { \ 1881 (_env)->cp15._regname##_s = (_val); \ 1882 } else { \ 1883 (_env)->cp15._regname##_ns = (_val); \ 1884 } \ 1885 } while (0) 1886 1887 /* Macros for automatically accessing a specific CP register bank depending on 1888 * the current secure state of the system. These macros are not intended for 1889 * supporting instruction translation reads/writes as these are dependent 1890 * solely on the SCR.NS bit and not the mode. 1891 */ 1892 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1893 A32_BANKED_REG_GET((_env), _regname, \ 1894 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1895 1896 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1897 A32_BANKED_REG_SET((_env), _regname, \ 1898 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1899 (_val)) 1900 1901 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 1902 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 1903 uint32_t cur_el, bool secure); 1904 1905 /* Interface between CPU and Interrupt controller. */ 1906 #ifndef CONFIG_USER_ONLY 1907 bool armv7m_nvic_can_take_pending_exception(void *opaque); 1908 #else 1909 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 1910 { 1911 return true; 1912 } 1913 #endif 1914 /** 1915 * armv7m_nvic_set_pending: mark the specified exception as pending 1916 * @opaque: the NVIC 1917 * @irq: the exception number to mark pending 1918 * @secure: false for non-banked exceptions or for the nonsecure 1919 * version of a banked exception, true for the secure version of a banked 1920 * exception. 1921 * 1922 * Marks the specified exception as pending. Note that we will assert() 1923 * if @secure is true and @irq does not specify one of the fixed set 1924 * of architecturally banked exceptions. 1925 */ 1926 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 1927 /** 1928 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 1929 * @opaque: the NVIC 1930 * @irq: the exception number to mark pending 1931 * @secure: false for non-banked exceptions or for the nonsecure 1932 * version of a banked exception, true for the secure version of a banked 1933 * exception. 1934 * 1935 * Similar to armv7m_nvic_set_pending(), but specifically for derived 1936 * exceptions (exceptions generated in the course of trying to take 1937 * a different exception). 1938 */ 1939 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 1940 /** 1941 * armv7m_nvic_get_pending_irq_info: return highest priority pending 1942 * exception, and whether it targets Secure state 1943 * @opaque: the NVIC 1944 * @pirq: set to pending exception number 1945 * @ptargets_secure: set to whether pending exception targets Secure 1946 * 1947 * This function writes the number of the highest priority pending 1948 * exception (the one which would be made active by 1949 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 1950 * to true if the current highest priority pending exception should 1951 * be taken to Secure state, false for NS. 1952 */ 1953 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 1954 bool *ptargets_secure); 1955 /** 1956 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 1957 * @opaque: the NVIC 1958 * 1959 * Move the current highest priority pending exception from the pending 1960 * state to the active state, and update v7m.exception to indicate that 1961 * it is the exception currently being handled. 1962 */ 1963 void armv7m_nvic_acknowledge_irq(void *opaque); 1964 /** 1965 * armv7m_nvic_complete_irq: complete specified interrupt or exception 1966 * @opaque: the NVIC 1967 * @irq: the exception number to complete 1968 * @secure: true if this exception was secure 1969 * 1970 * Returns: -1 if the irq was not active 1971 * 1 if completing this irq brought us back to base (no active irqs) 1972 * 0 if there is still an irq active after this one was completed 1973 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 1974 */ 1975 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 1976 /** 1977 * armv7m_nvic_raw_execution_priority: return the raw execution priority 1978 * @opaque: the NVIC 1979 * 1980 * Returns: the raw execution priority as defined by the v8M architecture. 1981 * This is the execution priority minus the effects of AIRCR.PRIS, 1982 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 1983 * (v8M ARM ARM I_PKLD.) 1984 */ 1985 int armv7m_nvic_raw_execution_priority(void *opaque); 1986 /** 1987 * armv7m_nvic_neg_prio_requested: return true if the requested execution 1988 * priority is negative for the specified security state. 1989 * @opaque: the NVIC 1990 * @secure: the security state to test 1991 * This corresponds to the pseudocode IsReqExecPriNeg(). 1992 */ 1993 #ifndef CONFIG_USER_ONLY 1994 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 1995 #else 1996 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 1997 { 1998 return false; 1999 } 2000 #endif 2001 2002 /* Interface for defining coprocessor registers. 2003 * Registers are defined in tables of arm_cp_reginfo structs 2004 * which are passed to define_arm_cp_regs(). 2005 */ 2006 2007 /* When looking up a coprocessor register we look for it 2008 * via an integer which encodes all of: 2009 * coprocessor number 2010 * Crn, Crm, opc1, opc2 fields 2011 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2012 * or via MRRC/MCRR?) 2013 * non-secure/secure bank (AArch32 only) 2014 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2015 * (In this case crn and opc2 should be zero.) 2016 * For AArch64, there is no 32/64 bit size distinction; 2017 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2018 * and 4 bit CRn and CRm. The encoding patterns are chosen 2019 * to be easy to convert to and from the KVM encodings, and also 2020 * so that the hashtable can contain both AArch32 and AArch64 2021 * registers (to allow for interprocessing where we might run 2022 * 32 bit code on a 64 bit core). 2023 */ 2024 /* This bit is private to our hashtable cpreg; in KVM register 2025 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2026 * in the upper bits of the 64 bit ID. 2027 */ 2028 #define CP_REG_AA64_SHIFT 28 2029 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2030 2031 /* To enable banking of coprocessor registers depending on ns-bit we 2032 * add a bit to distinguish between secure and non-secure cpregs in the 2033 * hashtable. 2034 */ 2035 #define CP_REG_NS_SHIFT 29 2036 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2037 2038 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2039 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2040 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2041 2042 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2043 (CP_REG_AA64_MASK | \ 2044 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2045 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2046 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2047 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2048 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2049 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2050 2051 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2052 * version used as a key for the coprocessor register hashtable 2053 */ 2054 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2055 { 2056 uint32_t cpregid = kvmid; 2057 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2058 cpregid |= CP_REG_AA64_MASK; 2059 } else { 2060 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2061 cpregid |= (1 << 15); 2062 } 2063 2064 /* KVM is always non-secure so add the NS flag on AArch32 register 2065 * entries. 2066 */ 2067 cpregid |= 1 << CP_REG_NS_SHIFT; 2068 } 2069 return cpregid; 2070 } 2071 2072 /* Convert a truncated 32 bit hashtable key into the full 2073 * 64 bit KVM register ID. 2074 */ 2075 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2076 { 2077 uint64_t kvmid; 2078 2079 if (cpregid & CP_REG_AA64_MASK) { 2080 kvmid = cpregid & ~CP_REG_AA64_MASK; 2081 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2082 } else { 2083 kvmid = cpregid & ~(1 << 15); 2084 if (cpregid & (1 << 15)) { 2085 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2086 } else { 2087 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2088 } 2089 } 2090 return kvmid; 2091 } 2092 2093 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 2094 * special-behaviour cp reg and bits [11..8] indicate what behaviour 2095 * it has. Otherwise it is a simple cp reg, where CONST indicates that 2096 * TCG can assume the value to be constant (ie load at translate time) 2097 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 2098 * indicates that the TB should not be ended after a write to this register 2099 * (the default is that the TB ends after cp writes). OVERRIDE permits 2100 * a register definition to override a previous definition for the 2101 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 2102 * old must have the OVERRIDE bit set. 2103 * ALIAS indicates that this register is an alias view of some underlying 2104 * state which is also visible via another register, and that the other 2105 * register is handling migration and reset; registers marked ALIAS will not be 2106 * migrated but may have their state set by syncing of register state from KVM. 2107 * NO_RAW indicates that this register has no underlying state and does not 2108 * support raw access for state saving/loading; it will not be used for either 2109 * migration or KVM state synchronization. (Typically this is for "registers" 2110 * which are actually used as instructions for cache maintenance and so on.) 2111 * IO indicates that this register does I/O and therefore its accesses 2112 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 2113 * registers which implement clocks or timers require this. 2114 */ 2115 #define ARM_CP_SPECIAL 0x0001 2116 #define ARM_CP_CONST 0x0002 2117 #define ARM_CP_64BIT 0x0004 2118 #define ARM_CP_SUPPRESS_TB_END 0x0008 2119 #define ARM_CP_OVERRIDE 0x0010 2120 #define ARM_CP_ALIAS 0x0020 2121 #define ARM_CP_IO 0x0040 2122 #define ARM_CP_NO_RAW 0x0080 2123 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) 2124 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) 2125 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) 2126 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) 2127 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) 2128 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA 2129 #define ARM_CP_FPU 0x1000 2130 #define ARM_CP_SVE 0x2000 2131 #define ARM_CP_NO_GDB 0x4000 2132 /* Used only as a terminator for ARMCPRegInfo lists */ 2133 #define ARM_CP_SENTINEL 0xffff 2134 /* Mask of only the flag bits in a type field */ 2135 #define ARM_CP_FLAG_MASK 0x70ff 2136 2137 /* Valid values for ARMCPRegInfo state field, indicating which of 2138 * the AArch32 and AArch64 execution states this register is visible in. 2139 * If the reginfo doesn't explicitly specify then it is AArch32 only. 2140 * If the reginfo is declared to be visible in both states then a second 2141 * reginfo is synthesised for the AArch32 view of the AArch64 register, 2142 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 2143 * Note that we rely on the values of these enums as we iterate through 2144 * the various states in some places. 2145 */ 2146 enum { 2147 ARM_CP_STATE_AA32 = 0, 2148 ARM_CP_STATE_AA64 = 1, 2149 ARM_CP_STATE_BOTH = 2, 2150 }; 2151 2152 /* ARM CP register secure state flags. These flags identify security state 2153 * attributes for a given CP register entry. 2154 * The existence of both or neither secure and non-secure flags indicates that 2155 * the register has both a secure and non-secure hash entry. A single one of 2156 * these flags causes the register to only be hashed for the specified 2157 * security state. 2158 * Although definitions may have any combination of the S/NS bits, each 2159 * registered entry will only have one to identify whether the entry is secure 2160 * or non-secure. 2161 */ 2162 enum { 2163 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 2164 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 2165 }; 2166 2167 /* Return true if cptype is a valid type field. This is used to try to 2168 * catch errors where the sentinel has been accidentally left off the end 2169 * of a list of registers. 2170 */ 2171 static inline bool cptype_valid(int cptype) 2172 { 2173 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 2174 || ((cptype & ARM_CP_SPECIAL) && 2175 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 2176 } 2177 2178 /* Access rights: 2179 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 2180 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 2181 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 2182 * (ie any of the privileged modes in Secure state, or Monitor mode). 2183 * If a register is accessible in one privilege level it's always accessible 2184 * in higher privilege levels too. Since "Secure PL1" also follows this rule 2185 * (ie anything visible in PL2 is visible in S-PL1, some things are only 2186 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 2187 * terminology a little and call this PL3. 2188 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 2189 * with the ELx exception levels. 2190 * 2191 * If access permissions for a register are more complex than can be 2192 * described with these bits, then use a laxer set of restrictions, and 2193 * do the more restrictive/complex check inside a helper function. 2194 */ 2195 #define PL3_R 0x80 2196 #define PL3_W 0x40 2197 #define PL2_R (0x20 | PL3_R) 2198 #define PL2_W (0x10 | PL3_W) 2199 #define PL1_R (0x08 | PL2_R) 2200 #define PL1_W (0x04 | PL2_W) 2201 #define PL0_R (0x02 | PL1_R) 2202 #define PL0_W (0x01 | PL1_W) 2203 2204 #define PL3_RW (PL3_R | PL3_W) 2205 #define PL2_RW (PL2_R | PL2_W) 2206 #define PL1_RW (PL1_R | PL1_W) 2207 #define PL0_RW (PL0_R | PL0_W) 2208 2209 /* Return the highest implemented Exception Level */ 2210 static inline int arm_highest_el(CPUARMState *env) 2211 { 2212 if (arm_feature(env, ARM_FEATURE_EL3)) { 2213 return 3; 2214 } 2215 if (arm_feature(env, ARM_FEATURE_EL2)) { 2216 return 2; 2217 } 2218 return 1; 2219 } 2220 2221 /* Return true if a v7M CPU is in Handler mode */ 2222 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2223 { 2224 return env->v7m.exception != 0; 2225 } 2226 2227 /* Return the current Exception Level (as per ARMv8; note that this differs 2228 * from the ARMv7 Privilege Level). 2229 */ 2230 static inline int arm_current_el(CPUARMState *env) 2231 { 2232 if (arm_feature(env, ARM_FEATURE_M)) { 2233 return arm_v7m_is_handler_mode(env) || 2234 !(env->v7m.control[env->v7m.secure] & 1); 2235 } 2236 2237 if (is_a64(env)) { 2238 return extract32(env->pstate, 2, 2); 2239 } 2240 2241 switch (env->uncached_cpsr & 0x1f) { 2242 case ARM_CPU_MODE_USR: 2243 return 0; 2244 case ARM_CPU_MODE_HYP: 2245 return 2; 2246 case ARM_CPU_MODE_MON: 2247 return 3; 2248 default: 2249 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2250 /* If EL3 is 32-bit then all secure privileged modes run in 2251 * EL3 2252 */ 2253 return 3; 2254 } 2255 2256 return 1; 2257 } 2258 } 2259 2260 typedef struct ARMCPRegInfo ARMCPRegInfo; 2261 2262 typedef enum CPAccessResult { 2263 /* Access is permitted */ 2264 CP_ACCESS_OK = 0, 2265 /* Access fails due to a configurable trap or enable which would 2266 * result in a categorized exception syndrome giving information about 2267 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 2268 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or 2269 * PL1 if in EL0, otherwise to the current EL). 2270 */ 2271 CP_ACCESS_TRAP = 1, 2272 /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). 2273 * Note that this is not a catch-all case -- the set of cases which may 2274 * result in this failure is specifically defined by the architecture. 2275 */ 2276 CP_ACCESS_TRAP_UNCATEGORIZED = 2, 2277 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ 2278 CP_ACCESS_TRAP_EL2 = 3, 2279 CP_ACCESS_TRAP_EL3 = 4, 2280 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ 2281 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, 2282 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, 2283 /* Access fails and results in an exception syndrome for an FP access, 2284 * trapped directly to EL2 or EL3 2285 */ 2286 CP_ACCESS_TRAP_FP_EL2 = 7, 2287 CP_ACCESS_TRAP_FP_EL3 = 8, 2288 } CPAccessResult; 2289 2290 /* Access functions for coprocessor registers. These cannot fail and 2291 * may not raise exceptions. 2292 */ 2293 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2294 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 2295 uint64_t value); 2296 /* Access permission check functions for coprocessor registers. */ 2297 typedef CPAccessResult CPAccessFn(CPUARMState *env, 2298 const ARMCPRegInfo *opaque, 2299 bool isread); 2300 /* Hook function for register reset */ 2301 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 2302 2303 #define CP_ANY 0xff 2304 2305 /* Definition of an ARM coprocessor register */ 2306 struct ARMCPRegInfo { 2307 /* Name of register (useful mainly for debugging, need not be unique) */ 2308 const char *name; 2309 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 2310 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 2311 * 'wildcard' field -- any value of that field in the MRC/MCR insn 2312 * will be decoded to this register. The register read and write 2313 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 2314 * used by the program, so it is possible to register a wildcard and 2315 * then behave differently on read/write if necessary. 2316 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 2317 * must both be zero. 2318 * For AArch64-visible registers, opc0 is also used. 2319 * Since there are no "coprocessors" in AArch64, cp is purely used as a 2320 * way to distinguish (for KVM's benefit) guest-visible system registers 2321 * from demuxed ones provided to preserve the "no side effects on 2322 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 2323 * visible (to match KVM's encoding); cp==0 will be converted to 2324 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 2325 */ 2326 uint8_t cp; 2327 uint8_t crn; 2328 uint8_t crm; 2329 uint8_t opc0; 2330 uint8_t opc1; 2331 uint8_t opc2; 2332 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 2333 int state; 2334 /* Register type: ARM_CP_* bits/values */ 2335 int type; 2336 /* Access rights: PL*_[RW] */ 2337 int access; 2338 /* Security state: ARM_CP_SECSTATE_* bits/values */ 2339 int secure; 2340 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 2341 * this register was defined: can be used to hand data through to the 2342 * register read/write functions, since they are passed the ARMCPRegInfo*. 2343 */ 2344 void *opaque; 2345 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 2346 * fieldoffset is non-zero, the reset value of the register. 2347 */ 2348 uint64_t resetvalue; 2349 /* Offset of the field in CPUARMState for this register. 2350 * 2351 * This is not needed if either: 2352 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 2353 * 2. both readfn and writefn are specified 2354 */ 2355 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 2356 2357 /* Offsets of the secure and non-secure fields in CPUARMState for the 2358 * register if it is banked. These fields are only used during the static 2359 * registration of a register. During hashing the bank associated 2360 * with a given security state is copied to fieldoffset which is used from 2361 * there on out. 2362 * 2363 * It is expected that register definitions use either fieldoffset or 2364 * bank_fieldoffsets in the definition but not both. It is also expected 2365 * that both bank offsets are set when defining a banked register. This 2366 * use indicates that a register is banked. 2367 */ 2368 ptrdiff_t bank_fieldoffsets[2]; 2369 2370 /* Function for making any access checks for this register in addition to 2371 * those specified by the 'access' permissions bits. If NULL, no extra 2372 * checks required. The access check is performed at runtime, not at 2373 * translate time. 2374 */ 2375 CPAccessFn *accessfn; 2376 /* Function for handling reads of this register. If NULL, then reads 2377 * will be done by loading from the offset into CPUARMState specified 2378 * by fieldoffset. 2379 */ 2380 CPReadFn *readfn; 2381 /* Function for handling writes of this register. If NULL, then writes 2382 * will be done by writing to the offset into CPUARMState specified 2383 * by fieldoffset. 2384 */ 2385 CPWriteFn *writefn; 2386 /* Function for doing a "raw" read; used when we need to copy 2387 * coprocessor state to the kernel for KVM or out for 2388 * migration. This only needs to be provided if there is also a 2389 * readfn and it has side effects (for instance clear-on-read bits). 2390 */ 2391 CPReadFn *raw_readfn; 2392 /* Function for doing a "raw" write; used when we need to copy KVM 2393 * kernel coprocessor state into userspace, or for inbound 2394 * migration. This only needs to be provided if there is also a 2395 * writefn and it masks out "unwritable" bits or has write-one-to-clear 2396 * or similar behaviour. 2397 */ 2398 CPWriteFn *raw_writefn; 2399 /* Function for resetting the register. If NULL, then reset will be done 2400 * by writing resetvalue to the field specified in fieldoffset. If 2401 * fieldoffset is 0 then no reset will be done. 2402 */ 2403 CPResetFn *resetfn; 2404 }; 2405 2406 /* Macros which are lvalues for the field in CPUARMState for the 2407 * ARMCPRegInfo *ri. 2408 */ 2409 #define CPREG_FIELD32(env, ri) \ 2410 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 2411 #define CPREG_FIELD64(env, ri) \ 2412 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 2413 2414 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 2415 2416 void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 2417 const ARMCPRegInfo *regs, void *opaque); 2418 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 2419 const ARMCPRegInfo *regs, void *opaque); 2420 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 2421 { 2422 define_arm_cp_regs_with_opaque(cpu, regs, 0); 2423 } 2424 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 2425 { 2426 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 2427 } 2428 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 2429 2430 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 2431 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 2432 uint64_t value); 2433 /* CPReadFn that can be used for read-as-zero behaviour */ 2434 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 2435 2436 /* CPResetFn that does nothing, for use if no reset is required even 2437 * if fieldoffset is non zero. 2438 */ 2439 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 2440 2441 /* Return true if this reginfo struct's field in the cpu state struct 2442 * is 64 bits wide. 2443 */ 2444 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 2445 { 2446 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 2447 } 2448 2449 static inline bool cp_access_ok(int current_el, 2450 const ARMCPRegInfo *ri, int isread) 2451 { 2452 return (ri->access >> ((current_el * 2) + isread)) & 1; 2453 } 2454 2455 /* Raw read of a coprocessor register (as needed for migration, etc) */ 2456 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 2457 2458 /** 2459 * write_list_to_cpustate 2460 * @cpu: ARMCPU 2461 * 2462 * For each register listed in the ARMCPU cpreg_indexes list, write 2463 * its value from the cpreg_values list into the ARMCPUState structure. 2464 * This updates TCG's working data structures from KVM data or 2465 * from incoming migration state. 2466 * 2467 * Returns: true if all register values were updated correctly, 2468 * false if some register was unknown or could not be written. 2469 * Note that we do not stop early on failure -- we will attempt 2470 * writing all registers in the list. 2471 */ 2472 bool write_list_to_cpustate(ARMCPU *cpu); 2473 2474 /** 2475 * write_cpustate_to_list: 2476 * @cpu: ARMCPU 2477 * 2478 * For each register listed in the ARMCPU cpreg_indexes list, write 2479 * its value from the ARMCPUState structure into the cpreg_values list. 2480 * This is used to copy info from TCG's working data structures into 2481 * KVM or for outbound migration. 2482 * 2483 * Returns: true if all register values were read correctly, 2484 * false if some register was unknown or could not be read. 2485 * Note that we do not stop early on failure -- we will attempt 2486 * reading all registers in the list. 2487 */ 2488 bool write_cpustate_to_list(ARMCPU *cpu); 2489 2490 #define ARM_CPUID_TI915T 0x54029152 2491 #define ARM_CPUID_TI925T 0x54029252 2492 2493 #if defined(CONFIG_USER_ONLY) 2494 #define TARGET_PAGE_BITS 12 2495 #else 2496 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 2497 * have to support 1K tiny pages. 2498 */ 2499 #define TARGET_PAGE_BITS_VARY 2500 #define TARGET_PAGE_BITS_MIN 10 2501 #endif 2502 2503 #if defined(TARGET_AARCH64) 2504 # define TARGET_PHYS_ADDR_SPACE_BITS 48 2505 # define TARGET_VIRT_ADDR_SPACE_BITS 64 2506 #else 2507 # define TARGET_PHYS_ADDR_SPACE_BITS 40 2508 # define TARGET_VIRT_ADDR_SPACE_BITS 32 2509 #endif 2510 2511 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 2512 unsigned int target_el) 2513 { 2514 CPUARMState *env = cs->env_ptr; 2515 unsigned int cur_el = arm_current_el(env); 2516 bool secure = arm_is_secure(env); 2517 bool pstate_unmasked; 2518 int8_t unmasked = 0; 2519 uint64_t hcr_el2; 2520 2521 /* Don't take exceptions if they target a lower EL. 2522 * This check should catch any exceptions that would not be taken but left 2523 * pending. 2524 */ 2525 if (cur_el > target_el) { 2526 return false; 2527 } 2528 2529 hcr_el2 = arm_hcr_el2_eff(env); 2530 2531 switch (excp_idx) { 2532 case EXCP_FIQ: 2533 pstate_unmasked = !(env->daif & PSTATE_F); 2534 break; 2535 2536 case EXCP_IRQ: 2537 pstate_unmasked = !(env->daif & PSTATE_I); 2538 break; 2539 2540 case EXCP_VFIQ: 2541 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 2542 /* VFIQs are only taken when hypervized and non-secure. */ 2543 return false; 2544 } 2545 return !(env->daif & PSTATE_F); 2546 case EXCP_VIRQ: 2547 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 2548 /* VIRQs are only taken when hypervized and non-secure. */ 2549 return false; 2550 } 2551 return !(env->daif & PSTATE_I); 2552 default: 2553 g_assert_not_reached(); 2554 } 2555 2556 /* Use the target EL, current execution state and SCR/HCR settings to 2557 * determine whether the corresponding CPSR bit is used to mask the 2558 * interrupt. 2559 */ 2560 if ((target_el > cur_el) && (target_el != 1)) { 2561 /* Exceptions targeting a higher EL may not be maskable */ 2562 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 2563 /* 64-bit masking rules are simple: exceptions to EL3 2564 * can't be masked, and exceptions to EL2 can only be 2565 * masked from Secure state. The HCR and SCR settings 2566 * don't affect the masking logic, only the interrupt routing. 2567 */ 2568 if (target_el == 3 || !secure) { 2569 unmasked = 1; 2570 } 2571 } else { 2572 /* The old 32-bit-only environment has a more complicated 2573 * masking setup. HCR and SCR bits not only affect interrupt 2574 * routing but also change the behaviour of masking. 2575 */ 2576 bool hcr, scr; 2577 2578 switch (excp_idx) { 2579 case EXCP_FIQ: 2580 /* If FIQs are routed to EL3 or EL2 then there are cases where 2581 * we override the CPSR.F in determining if the exception is 2582 * masked or not. If neither of these are set then we fall back 2583 * to the CPSR.F setting otherwise we further assess the state 2584 * below. 2585 */ 2586 hcr = hcr_el2 & HCR_FMO; 2587 scr = (env->cp15.scr_el3 & SCR_FIQ); 2588 2589 /* When EL3 is 32-bit, the SCR.FW bit controls whether the 2590 * CPSR.F bit masks FIQ interrupts when taken in non-secure 2591 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 2592 * when non-secure but only when FIQs are only routed to EL3. 2593 */ 2594 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 2595 break; 2596 case EXCP_IRQ: 2597 /* When EL3 execution state is 32-bit, if HCR.IMO is set then 2598 * we may override the CPSR.I masking when in non-secure state. 2599 * The SCR.IRQ setting has already been taken into consideration 2600 * when setting the target EL, so it does not have a further 2601 * affect here. 2602 */ 2603 hcr = hcr_el2 & HCR_IMO; 2604 scr = false; 2605 break; 2606 default: 2607 g_assert_not_reached(); 2608 } 2609 2610 if ((scr || hcr) && !secure) { 2611 unmasked = 1; 2612 } 2613 } 2614 } 2615 2616 /* The PSTATE bits only mask the interrupt if we have not overriden the 2617 * ability above. 2618 */ 2619 return unmasked || pstate_unmasked; 2620 } 2621 2622 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2623 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2624 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2625 2626 #define cpu_signal_handler cpu_arm_signal_handler 2627 #define cpu_list arm_cpu_list 2628 2629 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2630 * 2631 * If EL3 is 64-bit: 2632 * + NonSecure EL1 & 0 stage 1 2633 * + NonSecure EL1 & 0 stage 2 2634 * + NonSecure EL2 2635 * + Secure EL1 & EL0 2636 * + Secure EL3 2637 * If EL3 is 32-bit: 2638 * + NonSecure PL1 & 0 stage 1 2639 * + NonSecure PL1 & 0 stage 2 2640 * + NonSecure PL2 2641 * + Secure PL0 & PL1 2642 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2643 * 2644 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2645 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they 2646 * may differ in access permissions even if the VA->PA map is the same 2647 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2648 * translation, which means that we have one mmu_idx that deals with two 2649 * concatenated translation regimes [this sort of combined s1+2 TLB is 2650 * architecturally permitted] 2651 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2652 * handling via the TLB. The only way to do a stage 1 translation without 2653 * the immediate stage 2 translation is via the ATS or AT system insns, 2654 * which can be slow-pathed and always do a page table walk. 2655 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2656 * translation regimes, because they map reasonably well to each other 2657 * and they can't both be active at the same time. 2658 * This gives us the following list of mmu_idx values: 2659 * 2660 * NS EL0 (aka NS PL0) stage 1+2 2661 * NS EL1 (aka NS PL1) stage 1+2 2662 * NS EL2 (aka NS PL2) 2663 * S EL3 (aka S PL1) 2664 * S EL0 (aka S PL0) 2665 * S EL1 (not used if EL3 is 32 bit) 2666 * NS EL0+1 stage 2 2667 * 2668 * (The last of these is an mmu_idx because we want to be able to use the TLB 2669 * for the accesses done as part of a stage 1 page table walk, rather than 2670 * having to walk the stage 2 page table over and over.) 2671 * 2672 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2673 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2674 * NS EL2 if we ever model a Cortex-R52). 2675 * 2676 * M profile CPUs are rather different as they do not have a true MMU. 2677 * They have the following different MMU indexes: 2678 * User 2679 * Privileged 2680 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2681 * Privileged, execution priority negative (ditto) 2682 * If the CPU supports the v8M Security Extension then there are also: 2683 * Secure User 2684 * Secure Privileged 2685 * Secure User, execution priority negative 2686 * Secure Privileged, execution priority negative 2687 * 2688 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2689 * are not quite the same -- different CPU types (most notably M profile 2690 * vs A/R profile) would like to use MMU indexes with different semantics, 2691 * but since we don't ever need to use all of those in a single CPU we 2692 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of 2693 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2694 * the same for any particular CPU. 2695 * Variables of type ARMMUIdx are always full values, and the core 2696 * index values are in variables of type 'int'. 2697 * 2698 * Our enumeration includes at the end some entries which are not "true" 2699 * mmu_idx values in that they don't have corresponding TLBs and are only 2700 * valid for doing slow path page table walks. 2701 * 2702 * The constant names here are patterned after the general style of the names 2703 * of the AT/ATS operations. 2704 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2705 * For M profile we arrange them to have a bit for priv, a bit for negpri 2706 * and a bit for secure. 2707 */ 2708 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2709 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2710 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2711 2712 /* meanings of the bits for M profile mmu idx values */ 2713 #define ARM_MMU_IDX_M_PRIV 0x1 2714 #define ARM_MMU_IDX_M_NEGPRI 0x2 2715 #define ARM_MMU_IDX_M_S 0x4 2716 2717 #define ARM_MMU_IDX_TYPE_MASK (~0x7) 2718 #define ARM_MMU_IDX_COREIDX_MASK 0x7 2719 2720 typedef enum ARMMMUIdx { 2721 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, 2722 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, 2723 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, 2724 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, 2725 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, 2726 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, 2727 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, 2728 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, 2729 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, 2730 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, 2731 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M, 2732 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M, 2733 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M, 2734 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M, 2735 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M, 2736 /* Indexes below here don't have TLBs and are used only for AT system 2737 * instructions or for the first stage of an S12 page table walk. 2738 */ 2739 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, 2740 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, 2741 } ARMMMUIdx; 2742 2743 /* Bit macros for the core-mmu-index values for each index, 2744 * for use when calling tlb_flush_by_mmuidx() and friends. 2745 */ 2746 typedef enum ARMMMUIdxBit { 2747 ARMMMUIdxBit_S12NSE0 = 1 << 0, 2748 ARMMMUIdxBit_S12NSE1 = 1 << 1, 2749 ARMMMUIdxBit_S1E2 = 1 << 2, 2750 ARMMMUIdxBit_S1E3 = 1 << 3, 2751 ARMMMUIdxBit_S1SE0 = 1 << 4, 2752 ARMMMUIdxBit_S1SE1 = 1 << 5, 2753 ARMMMUIdxBit_S2NS = 1 << 6, 2754 ARMMMUIdxBit_MUser = 1 << 0, 2755 ARMMMUIdxBit_MPriv = 1 << 1, 2756 ARMMMUIdxBit_MUserNegPri = 1 << 2, 2757 ARMMMUIdxBit_MPrivNegPri = 1 << 3, 2758 ARMMMUIdxBit_MSUser = 1 << 4, 2759 ARMMMUIdxBit_MSPriv = 1 << 5, 2760 ARMMMUIdxBit_MSUserNegPri = 1 << 6, 2761 ARMMMUIdxBit_MSPrivNegPri = 1 << 7, 2762 } ARMMMUIdxBit; 2763 2764 #define MMU_USER_IDX 0 2765 2766 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) 2767 { 2768 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; 2769 } 2770 2771 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) 2772 { 2773 if (arm_feature(env, ARM_FEATURE_M)) { 2774 return mmu_idx | ARM_MMU_IDX_M; 2775 } else { 2776 return mmu_idx | ARM_MMU_IDX_A; 2777 } 2778 } 2779 2780 /* Return the exception level we're running at if this is our mmu_idx */ 2781 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) 2782 { 2783 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { 2784 case ARM_MMU_IDX_A: 2785 return mmu_idx & 3; 2786 case ARM_MMU_IDX_M: 2787 return mmu_idx & ARM_MMU_IDX_M_PRIV; 2788 default: 2789 g_assert_not_reached(); 2790 } 2791 } 2792 2793 /* Return the MMU index for a v7M CPU in the specified security and 2794 * privilege state. 2795 */ 2796 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, 2797 bool secstate, bool priv); 2798 2799 /* Return the MMU index for a v7M CPU in the specified security state */ 2800 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); 2801 2802 /** 2803 * cpu_mmu_index: 2804 * @env: The cpu environment 2805 * @ifetch: True for code access, false for data access. 2806 * 2807 * Return the core mmu index for the current translation regime. 2808 * This function is used by generic TCG code paths. 2809 */ 2810 int cpu_mmu_index(CPUARMState *env, bool ifetch); 2811 2812 /* Indexes used when registering address spaces with cpu_address_space_init */ 2813 typedef enum ARMASIdx { 2814 ARMASIdx_NS = 0, 2815 ARMASIdx_S = 1, 2816 } ARMASIdx; 2817 2818 /* Return the Exception Level targeted by debug exceptions. */ 2819 static inline int arm_debug_target_el(CPUARMState *env) 2820 { 2821 bool secure = arm_is_secure(env); 2822 bool route_to_el2 = false; 2823 2824 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { 2825 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2826 env->cp15.mdcr_el2 & MDCR_TDE; 2827 } 2828 2829 if (route_to_el2) { 2830 return 2; 2831 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2832 !arm_el_is_aa64(env, 3) && secure) { 2833 return 3; 2834 } else { 2835 return 1; 2836 } 2837 } 2838 2839 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2840 { 2841 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2842 * CSSELR is RAZ/WI. 2843 */ 2844 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2845 } 2846 2847 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2848 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2849 { 2850 int cur_el = arm_current_el(env); 2851 int debug_el; 2852 2853 if (cur_el == 3) { 2854 return false; 2855 } 2856 2857 /* MDCR_EL3.SDD disables debug events from Secure state */ 2858 if (arm_is_secure_below_el3(env) 2859 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2860 return false; 2861 } 2862 2863 /* 2864 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2865 * while not masking the (D)ebug bit in DAIF. 2866 */ 2867 debug_el = arm_debug_target_el(env); 2868 2869 if (cur_el == debug_el) { 2870 return extract32(env->cp15.mdscr_el1, 13, 1) 2871 && !(env->daif & PSTATE_D); 2872 } 2873 2874 /* Otherwise the debug target needs to be a higher EL */ 2875 return debug_el > cur_el; 2876 } 2877 2878 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2879 { 2880 int el = arm_current_el(env); 2881 2882 if (el == 0 && arm_el_is_aa64(env, 1)) { 2883 return aa64_generate_debug_exceptions(env); 2884 } 2885 2886 if (arm_is_secure(env)) { 2887 int spd; 2888 2889 if (el == 0 && (env->cp15.sder & 1)) { 2890 /* SDER.SUIDEN means debug exceptions from Secure EL0 2891 * are always enabled. Otherwise they are controlled by 2892 * SDCR.SPD like those from other Secure ELs. 2893 */ 2894 return true; 2895 } 2896 2897 spd = extract32(env->cp15.mdcr_el3, 14, 2); 2898 switch (spd) { 2899 case 1: 2900 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 2901 case 0: 2902 /* For 0b00 we return true if external secure invasive debug 2903 * is enabled. On real hardware this is controlled by external 2904 * signals to the core. QEMU always permits debug, and behaves 2905 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 2906 */ 2907 return true; 2908 case 2: 2909 return false; 2910 case 3: 2911 return true; 2912 } 2913 } 2914 2915 return el != 2; 2916 } 2917 2918 /* Return true if debugging exceptions are currently enabled. 2919 * This corresponds to what in ARM ARM pseudocode would be 2920 * if UsingAArch32() then 2921 * return AArch32.GenerateDebugExceptions() 2922 * else 2923 * return AArch64.GenerateDebugExceptions() 2924 * We choose to push the if() down into this function for clarity, 2925 * since the pseudocode has it at all callsites except for the one in 2926 * CheckSoftwareStep(), where it is elided because both branches would 2927 * always return the same value. 2928 */ 2929 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 2930 { 2931 if (env->aarch64) { 2932 return aa64_generate_debug_exceptions(env); 2933 } else { 2934 return aa32_generate_debug_exceptions(env); 2935 } 2936 } 2937 2938 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 2939 * implicitly means this always returns false in pre-v8 CPUs.) 2940 */ 2941 static inline bool arm_singlestep_active(CPUARMState *env) 2942 { 2943 return extract32(env->cp15.mdscr_el1, 0, 1) 2944 && arm_el_is_aa64(env, arm_debug_target_el(env)) 2945 && arm_generate_debug_exceptions(env); 2946 } 2947 2948 static inline bool arm_sctlr_b(CPUARMState *env) 2949 { 2950 return 2951 /* We need not implement SCTLR.ITD in user-mode emulation, so 2952 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2953 * This lets people run BE32 binaries with "-cpu any". 2954 */ 2955 #ifndef CONFIG_USER_ONLY 2956 !arm_feature(env, ARM_FEATURE_V7) && 2957 #endif 2958 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2959 } 2960 2961 /* Return true if the processor is in big-endian mode. */ 2962 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2963 { 2964 int cur_el; 2965 2966 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2967 if (!is_a64(env)) { 2968 return 2969 #ifdef CONFIG_USER_ONLY 2970 /* In system mode, BE32 is modelled in line with the 2971 * architecture (as word-invariant big-endianness), where loads 2972 * and stores are done little endian but from addresses which 2973 * are adjusted by XORing with the appropriate constant. So the 2974 * endianness to use for the raw data access is not affected by 2975 * SCTLR.B. 2976 * In user mode, however, we model BE32 as byte-invariant 2977 * big-endianness (because user-only code cannot tell the 2978 * difference), and so we need to use a data access endianness 2979 * that depends on SCTLR.B. 2980 */ 2981 arm_sctlr_b(env) || 2982 #endif 2983 ((env->uncached_cpsr & CPSR_E) ? 1 : 0); 2984 } 2985 2986 cur_el = arm_current_el(env); 2987 2988 if (cur_el == 0) { 2989 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; 2990 } 2991 2992 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; 2993 } 2994 2995 #include "exec/cpu-all.h" 2996 2997 /* Bit usage in the TB flags field: bit 31 indicates whether we are 2998 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 2999 * We put flags which are shared between 32 and 64 bit mode at the top 3000 * of the word, and flags which apply to only one mode at the bottom. 3001 */ 3002 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) 3003 FIELD(TBFLAG_ANY, MMUIDX, 28, 3) 3004 FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) 3005 FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) 3006 /* Target EL if we take a floating-point-disabled exception */ 3007 FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) 3008 FIELD(TBFLAG_ANY, BE_DATA, 23, 1) 3009 3010 /* Bit usage when in AArch32 state: */ 3011 FIELD(TBFLAG_A32, THUMB, 0, 1) 3012 FIELD(TBFLAG_A32, VECLEN, 1, 3) 3013 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) 3014 FIELD(TBFLAG_A32, VFPEN, 7, 1) 3015 FIELD(TBFLAG_A32, CONDEXEC, 8, 8) 3016 FIELD(TBFLAG_A32, SCTLR_B, 16, 1) 3017 /* We store the bottom two bits of the CPAR as TB flags and handle 3018 * checks on the other bits at runtime 3019 */ 3020 FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) 3021 /* Indicates whether cp register reads and writes by guest code should access 3022 * the secure or nonsecure bank of banked registers; note that this is not 3023 * the same thing as the current security state of the processor! 3024 */ 3025 FIELD(TBFLAG_A32, NS, 19, 1) 3026 /* For M profile only, Handler (ie not Thread) mode */ 3027 FIELD(TBFLAG_A32, HANDLER, 21, 1) 3028 /* For M profile only, whether we should generate stack-limit checks */ 3029 FIELD(TBFLAG_A32, STACKCHECK, 22, 1) 3030 3031 /* Bit usage when in AArch64 state */ 3032 FIELD(TBFLAG_A64, TBII, 0, 2) 3033 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3034 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3035 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3036 3037 static inline bool bswap_code(bool sctlr_b) 3038 { 3039 #ifdef CONFIG_USER_ONLY 3040 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. 3041 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 3042 * would also end up as a mixed-endian mode with BE code, LE data. 3043 */ 3044 return 3045 #ifdef TARGET_WORDS_BIGENDIAN 3046 1 ^ 3047 #endif 3048 sctlr_b; 3049 #else 3050 /* All code access in ARM is little endian, and there are no loaders 3051 * doing swaps that need to be reversed 3052 */ 3053 return 0; 3054 #endif 3055 } 3056 3057 #ifdef CONFIG_USER_ONLY 3058 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3059 { 3060 return 3061 #ifdef TARGET_WORDS_BIGENDIAN 3062 1 ^ 3063 #endif 3064 arm_cpu_data_is_big_endian(env); 3065 } 3066 #endif 3067 3068 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3069 target_ulong *cs_base, uint32_t *flags); 3070 3071 enum { 3072 QEMU_PSCI_CONDUIT_DISABLED = 0, 3073 QEMU_PSCI_CONDUIT_SMC = 1, 3074 QEMU_PSCI_CONDUIT_HVC = 2, 3075 }; 3076 3077 #ifndef CONFIG_USER_ONLY 3078 /* Return the address space index to use for a memory access */ 3079 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3080 { 3081 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3082 } 3083 3084 /* Return the AddressSpace to use for a memory access 3085 * (which depends on whether the access is S or NS, and whether 3086 * the board gave us a separate AddressSpace for S accesses). 3087 */ 3088 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3089 { 3090 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3091 } 3092 #endif 3093 3094 /** 3095 * arm_register_pre_el_change_hook: 3096 * Register a hook function which will be called immediately before this 3097 * CPU changes exception level or mode. The hook function will be 3098 * passed a pointer to the ARMCPU and the opaque data pointer passed 3099 * to this function when the hook was registered. 3100 * 3101 * Note that if a pre-change hook is called, any registered post-change hooks 3102 * are guaranteed to subsequently be called. 3103 */ 3104 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3105 void *opaque); 3106 /** 3107 * arm_register_el_change_hook: 3108 * Register a hook function which will be called immediately after this 3109 * CPU changes exception level or mode. The hook function will be 3110 * passed a pointer to the ARMCPU and the opaque data pointer passed 3111 * to this function when the hook was registered. 3112 * 3113 * Note that any registered hooks registered here are guaranteed to be called 3114 * if pre-change hooks have been. 3115 */ 3116 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3117 *opaque); 3118 3119 /** 3120 * aa32_vfp_dreg: 3121 * Return a pointer to the Dn register within env in 32-bit mode. 3122 */ 3123 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3124 { 3125 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3126 } 3127 3128 /** 3129 * aa32_vfp_qreg: 3130 * Return a pointer to the Qn register within env in 32-bit mode. 3131 */ 3132 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3133 { 3134 return &env->vfp.zregs[regno].d[0]; 3135 } 3136 3137 /** 3138 * aa64_vfp_qreg: 3139 * Return a pointer to the Qn register within env in 64-bit mode. 3140 */ 3141 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3142 { 3143 return &env->vfp.zregs[regno].d[0]; 3144 } 3145 3146 /* Shared between translate-sve.c and sve_helper.c. */ 3147 extern const uint64_t pred_esz_masks[4]; 3148 3149 /* 3150 * 32-bit feature tests via id registers. 3151 */ 3152 static inline bool isar_feature_thumb_div(const ARMISARegisters *id) 3153 { 3154 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3155 } 3156 3157 static inline bool isar_feature_arm_div(const ARMISARegisters *id) 3158 { 3159 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3160 } 3161 3162 static inline bool isar_feature_jazelle(const ARMISARegisters *id) 3163 { 3164 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3165 } 3166 3167 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3168 { 3169 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3170 } 3171 3172 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3173 { 3174 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3175 } 3176 3177 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3178 { 3179 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3180 } 3181 3182 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3183 { 3184 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3185 } 3186 3187 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3188 { 3189 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3190 } 3191 3192 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3193 { 3194 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3195 } 3196 3197 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3198 { 3199 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3200 } 3201 3202 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3203 { 3204 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3205 } 3206 3207 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3208 { 3209 /* 3210 * This is a placeholder for use by VCMA until the rest of 3211 * the ARMv8.2-FP16 extension is implemented for aa32 mode. 3212 * At which point we can properly set and check MVFR1.FPHP. 3213 */ 3214 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3215 } 3216 3217 /* 3218 * 64-bit feature tests via id registers. 3219 */ 3220 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3221 { 3222 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3223 } 3224 3225 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3226 { 3227 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3228 } 3229 3230 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3231 { 3232 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3233 } 3234 3235 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3236 { 3237 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3238 } 3239 3240 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3241 { 3242 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3243 } 3244 3245 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3246 { 3247 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3248 } 3249 3250 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3251 { 3252 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3253 } 3254 3255 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3256 { 3257 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3258 } 3259 3260 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3261 { 3262 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3263 } 3264 3265 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3266 { 3267 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3268 } 3269 3270 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3271 { 3272 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3273 } 3274 3275 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3276 { 3277 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3278 } 3279 3280 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3281 { 3282 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3283 } 3284 3285 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3286 { 3287 /* 3288 * Note that while QEMU will only implement the architected algorithm 3289 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation 3290 * defined algorithms, and thus API+GPI, and this predicate controls 3291 * migration of the 128-bit keys. 3292 */ 3293 return (id->id_aa64isar1 & 3294 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3295 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3296 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3297 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3298 } 3299 3300 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3301 { 3302 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3303 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3304 } 3305 3306 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3307 { 3308 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3309 } 3310 3311 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3312 { 3313 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3314 } 3315 3316 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3317 { 3318 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3319 } 3320 3321 /* 3322 * Forward to the above feature tests given an ARMCPU pointer. 3323 */ 3324 #define cpu_isar_feature(name, cpu) \ 3325 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 3326 3327 #endif 3328