1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 typedef struct { 170 uint64_t raw_tcr; 171 uint32_t mask; 172 uint32_t base_mask; 173 } TCR; 174 175 #define VTCR_NSW (1u << 29) 176 #define VTCR_NSA (1u << 30) 177 #define VSTCR_SW VTCR_NSW 178 #define VSTCR_SA VTCR_NSA 179 180 /* Define a maximum sized vector register. 181 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 182 * For 64-bit, this is a 2048-bit SVE register. 183 * 184 * Note that the mapping between S, D, and Q views of the register bank 185 * differs between AArch64 and AArch32. 186 * In AArch32: 187 * Qn = regs[n].d[1]:regs[n].d[0] 188 * Dn = regs[n / 2].d[n & 1] 189 * Sn = regs[n / 4].d[n % 4 / 2], 190 * bits 31..0 for even n, and bits 63..32 for odd n 191 * (and regs[16] to regs[31] are inaccessible) 192 * In AArch64: 193 * Zn = regs[n].d[*] 194 * Qn = regs[n].d[1]:regs[n].d[0] 195 * Dn = regs[n].d[0] 196 * Sn = regs[n].d[0] bits 31..0 197 * Hn = regs[n].d[0] bits 15..0 198 * 199 * This corresponds to the architecturally defined mapping between 200 * the two execution states, and means we do not need to explicitly 201 * map these registers when changing states. 202 * 203 * Align the data for use with TCG host vector operations. 204 */ 205 206 #ifdef TARGET_AARCH64 207 # define ARM_MAX_VQ 16 208 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 209 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 210 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); 211 #else 212 # define ARM_MAX_VQ 1 213 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 214 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 215 static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } 216 #endif 217 218 typedef struct ARMVectorReg { 219 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 220 } ARMVectorReg; 221 222 #ifdef TARGET_AARCH64 223 /* In AArch32 mode, predicate registers do not exist at all. */ 224 typedef struct ARMPredicateReg { 225 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 226 } ARMPredicateReg; 227 228 /* In AArch32 mode, PAC keys do not exist at all. */ 229 typedef struct ARMPACKey { 230 uint64_t lo, hi; 231 } ARMPACKey; 232 #endif 233 234 /* See the commentary above the TBFLAG field definitions. */ 235 typedef struct CPUARMTBFlags { 236 uint32_t flags; 237 target_ulong flags2; 238 } CPUARMTBFlags; 239 240 typedef struct CPUArchState { 241 /* Regs for current mode. */ 242 uint32_t regs[16]; 243 244 /* 32/64 switch only happens when taking and returning from 245 * exceptions so the overlap semantics are taken care of then 246 * instead of having a complicated union. 247 */ 248 /* Regs for A64 mode. */ 249 uint64_t xregs[32]; 250 uint64_t pc; 251 /* PSTATE isn't an architectural register for ARMv8. However, it is 252 * convenient for us to assemble the underlying state into a 32 bit format 253 * identical to the architectural format used for the SPSR. (This is also 254 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 255 * 'pstate' register are.) Of the PSTATE bits: 256 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 257 * semantics as for AArch32, as described in the comments on each field) 258 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 259 * DAIF (exception masks) are kept in env->daif 260 * BTYPE is kept in env->btype 261 * all other bits are stored in their correct places in env->pstate 262 */ 263 uint32_t pstate; 264 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 265 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 266 267 /* Cached TBFLAGS state. See below for which bits are included. */ 268 CPUARMTBFlags hflags; 269 270 /* Frequently accessed CPSR bits are stored separately for efficiency. 271 This contains all the other bits. Use cpsr_{read,write} to access 272 the whole CPSR. */ 273 uint32_t uncached_cpsr; 274 uint32_t spsr; 275 276 /* Banked registers. */ 277 uint64_t banked_spsr[8]; 278 uint32_t banked_r13[8]; 279 uint32_t banked_r14[8]; 280 281 /* These hold r8-r12. */ 282 uint32_t usr_regs[5]; 283 uint32_t fiq_regs[5]; 284 285 /* cpsr flag cache for faster execution */ 286 uint32_t CF; /* 0 or 1 */ 287 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 288 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 289 uint32_t ZF; /* Z set if zero. */ 290 uint32_t QF; /* 0 or 1 */ 291 uint32_t GE; /* cpsr[19:16] */ 292 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 293 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 294 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 295 296 uint64_t elr_el[4]; /* AArch64 exception link regs */ 297 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 298 299 /* System control coprocessor (cp15) */ 300 struct { 301 uint32_t c0_cpuid; 302 union { /* Cache size selection */ 303 struct { 304 uint64_t _unused_csselr0; 305 uint64_t csselr_ns; 306 uint64_t _unused_csselr1; 307 uint64_t csselr_s; 308 }; 309 uint64_t csselr_el[4]; 310 }; 311 union { /* System control register. */ 312 struct { 313 uint64_t _unused_sctlr; 314 uint64_t sctlr_ns; 315 uint64_t hsctlr; 316 uint64_t sctlr_s; 317 }; 318 uint64_t sctlr_el[4]; 319 }; 320 uint64_t cpacr_el1; /* Architectural feature access control register */ 321 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 322 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 323 uint64_t sder; /* Secure debug enable register. */ 324 uint32_t nsacr; /* Non-secure access control register. */ 325 union { /* MMU translation table base 0. */ 326 struct { 327 uint64_t _unused_ttbr0_0; 328 uint64_t ttbr0_ns; 329 uint64_t _unused_ttbr0_1; 330 uint64_t ttbr0_s; 331 }; 332 uint64_t ttbr0_el[4]; 333 }; 334 union { /* MMU translation table base 1. */ 335 struct { 336 uint64_t _unused_ttbr1_0; 337 uint64_t ttbr1_ns; 338 uint64_t _unused_ttbr1_1; 339 uint64_t ttbr1_s; 340 }; 341 uint64_t ttbr1_el[4]; 342 }; 343 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 344 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 345 /* MMU translation table base control. */ 346 TCR tcr_el[4]; 347 TCR vtcr_el2; /* Virtualization Translation Control. */ 348 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 349 uint32_t c2_data; /* MPU data cacheable bits. */ 350 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 351 union { /* MMU domain access control register 352 * MPU write buffer control. 353 */ 354 struct { 355 uint64_t dacr_ns; 356 uint64_t dacr_s; 357 }; 358 struct { 359 uint64_t dacr32_el2; 360 }; 361 }; 362 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 363 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 364 uint64_t hcr_el2; /* Hypervisor configuration register */ 365 uint64_t scr_el3; /* Secure configuration register. */ 366 union { /* Fault status registers. */ 367 struct { 368 uint64_t ifsr_ns; 369 uint64_t ifsr_s; 370 }; 371 struct { 372 uint64_t ifsr32_el2; 373 }; 374 }; 375 union { 376 struct { 377 uint64_t _unused_dfsr; 378 uint64_t dfsr_ns; 379 uint64_t hsr; 380 uint64_t dfsr_s; 381 }; 382 uint64_t esr_el[4]; 383 }; 384 uint32_t c6_region[8]; /* MPU base/size registers. */ 385 union { /* Fault address registers. */ 386 struct { 387 uint64_t _unused_far0; 388 #if HOST_BIG_ENDIAN 389 uint32_t ifar_ns; 390 uint32_t dfar_ns; 391 uint32_t ifar_s; 392 uint32_t dfar_s; 393 #else 394 uint32_t dfar_ns; 395 uint32_t ifar_ns; 396 uint32_t dfar_s; 397 uint32_t ifar_s; 398 #endif 399 uint64_t _unused_far3; 400 }; 401 uint64_t far_el[4]; 402 }; 403 uint64_t hpfar_el2; 404 uint64_t hstr_el2; 405 union { /* Translation result. */ 406 struct { 407 uint64_t _unused_par_0; 408 uint64_t par_ns; 409 uint64_t _unused_par_1; 410 uint64_t par_s; 411 }; 412 uint64_t par_el[4]; 413 }; 414 415 uint32_t c9_insn; /* Cache lockdown registers. */ 416 uint32_t c9_data; 417 uint64_t c9_pmcr; /* performance monitor control register */ 418 uint64_t c9_pmcnten; /* perf monitor counter enables */ 419 uint64_t c9_pmovsr; /* perf monitor overflow status */ 420 uint64_t c9_pmuserenr; /* perf monitor user enable */ 421 uint64_t c9_pmselr; /* perf monitor counter selection register */ 422 uint64_t c9_pminten; /* perf monitor interrupt enables */ 423 union { /* Memory attribute redirection */ 424 struct { 425 #if HOST_BIG_ENDIAN 426 uint64_t _unused_mair_0; 427 uint32_t mair1_ns; 428 uint32_t mair0_ns; 429 uint64_t _unused_mair_1; 430 uint32_t mair1_s; 431 uint32_t mair0_s; 432 #else 433 uint64_t _unused_mair_0; 434 uint32_t mair0_ns; 435 uint32_t mair1_ns; 436 uint64_t _unused_mair_1; 437 uint32_t mair0_s; 438 uint32_t mair1_s; 439 #endif 440 }; 441 uint64_t mair_el[4]; 442 }; 443 union { /* vector base address register */ 444 struct { 445 uint64_t _unused_vbar; 446 uint64_t vbar_ns; 447 uint64_t hvbar; 448 uint64_t vbar_s; 449 }; 450 uint64_t vbar_el[4]; 451 }; 452 uint32_t mvbar; /* (monitor) vector base address register */ 453 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 454 struct { /* FCSE PID. */ 455 uint32_t fcseidr_ns; 456 uint32_t fcseidr_s; 457 }; 458 union { /* Context ID. */ 459 struct { 460 uint64_t _unused_contextidr_0; 461 uint64_t contextidr_ns; 462 uint64_t _unused_contextidr_1; 463 uint64_t contextidr_s; 464 }; 465 uint64_t contextidr_el[4]; 466 }; 467 union { /* User RW Thread register. */ 468 struct { 469 uint64_t tpidrurw_ns; 470 uint64_t tpidrprw_ns; 471 uint64_t htpidr; 472 uint64_t _tpidr_el3; 473 }; 474 uint64_t tpidr_el[4]; 475 }; 476 /* The secure banks of these registers don't map anywhere */ 477 uint64_t tpidrurw_s; 478 uint64_t tpidrprw_s; 479 uint64_t tpidruro_s; 480 481 union { /* User RO Thread register. */ 482 uint64_t tpidruro_ns; 483 uint64_t tpidrro_el[1]; 484 }; 485 uint64_t c14_cntfrq; /* Counter Frequency register */ 486 uint64_t c14_cntkctl; /* Timer Control register */ 487 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 488 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 489 ARMGenericTimer c14_timer[NUM_GTIMERS]; 490 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 491 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 492 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 493 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 494 uint32_t c15_threadid; /* TI debugger thread-ID. */ 495 uint32_t c15_config_base_address; /* SCU base address. */ 496 uint32_t c15_diagnostic; /* diagnostic register */ 497 uint32_t c15_power_diagnostic; 498 uint32_t c15_power_control; /* power control */ 499 uint64_t dbgbvr[16]; /* breakpoint value registers */ 500 uint64_t dbgbcr[16]; /* breakpoint control registers */ 501 uint64_t dbgwvr[16]; /* watchpoint value registers */ 502 uint64_t dbgwcr[16]; /* watchpoint control registers */ 503 uint64_t mdscr_el1; 504 uint64_t oslsr_el1; /* OS Lock Status */ 505 uint64_t mdcr_el2; 506 uint64_t mdcr_el3; 507 /* Stores the architectural value of the counter *the last time it was 508 * updated* by pmccntr_op_start. Accesses should always be surrounded 509 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 510 * architecturally-correct value is being read/set. 511 */ 512 uint64_t c15_ccnt; 513 /* Stores the delta between the architectural value and the underlying 514 * cycle count during normal operation. It is used to update c15_ccnt 515 * to be the correct architectural value before accesses. During 516 * accesses, c15_ccnt_delta contains the underlying count being used 517 * for the access, after which it reverts to the delta value in 518 * pmccntr_op_finish. 519 */ 520 uint64_t c15_ccnt_delta; 521 uint64_t c14_pmevcntr[31]; 522 uint64_t c14_pmevcntr_delta[31]; 523 uint64_t c14_pmevtyper[31]; 524 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 525 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 526 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 527 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 528 uint64_t gcr_el1; 529 uint64_t rgsr_el1; 530 531 /* Minimal RAS registers */ 532 uint64_t disr_el1; 533 uint64_t vdisr_el2; 534 uint64_t vsesr_el2; 535 } cp15; 536 537 struct { 538 /* M profile has up to 4 stack pointers: 539 * a Main Stack Pointer and a Process Stack Pointer for each 540 * of the Secure and Non-Secure states. (If the CPU doesn't support 541 * the security extension then it has only two SPs.) 542 * In QEMU we always store the currently active SP in regs[13], 543 * and the non-active SP for the current security state in 544 * v7m.other_sp. The stack pointers for the inactive security state 545 * are stored in other_ss_msp and other_ss_psp. 546 * switch_v7m_security_state() is responsible for rearranging them 547 * when we change security state. 548 */ 549 uint32_t other_sp; 550 uint32_t other_ss_msp; 551 uint32_t other_ss_psp; 552 uint32_t vecbase[M_REG_NUM_BANKS]; 553 uint32_t basepri[M_REG_NUM_BANKS]; 554 uint32_t control[M_REG_NUM_BANKS]; 555 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 556 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 557 uint32_t hfsr; /* HardFault Status */ 558 uint32_t dfsr; /* Debug Fault Status Register */ 559 uint32_t sfsr; /* Secure Fault Status Register */ 560 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 561 uint32_t bfar; /* BusFault Address */ 562 uint32_t sfar; /* Secure Fault Address Register */ 563 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 564 int exception; 565 uint32_t primask[M_REG_NUM_BANKS]; 566 uint32_t faultmask[M_REG_NUM_BANKS]; 567 uint32_t aircr; /* only holds r/w state if security extn implemented */ 568 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 569 uint32_t csselr[M_REG_NUM_BANKS]; 570 uint32_t scr[M_REG_NUM_BANKS]; 571 uint32_t msplim[M_REG_NUM_BANKS]; 572 uint32_t psplim[M_REG_NUM_BANKS]; 573 uint32_t fpcar[M_REG_NUM_BANKS]; 574 uint32_t fpccr[M_REG_NUM_BANKS]; 575 uint32_t fpdscr[M_REG_NUM_BANKS]; 576 uint32_t cpacr[M_REG_NUM_BANKS]; 577 uint32_t nsacr; 578 uint32_t ltpsize; 579 uint32_t vpr; 580 } v7m; 581 582 /* Information associated with an exception about to be taken: 583 * code which raises an exception must set cs->exception_index and 584 * the relevant parts of this structure; the cpu_do_interrupt function 585 * will then set the guest-visible registers as part of the exception 586 * entry process. 587 */ 588 struct { 589 uint32_t syndrome; /* AArch64 format syndrome register */ 590 uint32_t fsr; /* AArch32 format fault status register info */ 591 uint64_t vaddress; /* virtual addr associated with exception, if any */ 592 uint32_t target_el; /* EL the exception should be targeted for */ 593 /* If we implement EL2 we will also need to store information 594 * about the intermediate physical address for stage 2 faults. 595 */ 596 } exception; 597 598 /* Information associated with an SError */ 599 struct { 600 uint8_t pending; 601 uint8_t has_esr; 602 uint64_t esr; 603 } serror; 604 605 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 606 607 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 608 uint32_t irq_line_state; 609 610 /* Thumb-2 EE state. */ 611 uint32_t teecr; 612 uint32_t teehbr; 613 614 /* VFP coprocessor state. */ 615 struct { 616 ARMVectorReg zregs[32]; 617 618 #ifdef TARGET_AARCH64 619 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 620 #define FFR_PRED_NUM 16 621 ARMPredicateReg pregs[17]; 622 /* Scratch space for aa64 sve predicate temporary. */ 623 ARMPredicateReg preg_tmp; 624 #endif 625 626 /* We store these fpcsr fields separately for convenience. */ 627 uint32_t qc[4] QEMU_ALIGNED(16); 628 int vec_len; 629 int vec_stride; 630 631 uint32_t xregs[16]; 632 633 /* Scratch space for aa32 neon expansion. */ 634 uint32_t scratch[8]; 635 636 /* There are a number of distinct float control structures: 637 * 638 * fp_status: is the "normal" fp status. 639 * fp_status_fp16: used for half-precision calculations 640 * standard_fp_status : the ARM "Standard FPSCR Value" 641 * standard_fp_status_fp16 : used for half-precision 642 * calculations with the ARM "Standard FPSCR Value" 643 * 644 * Half-precision operations are governed by a separate 645 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 646 * status structure to control this. 647 * 648 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 649 * round-to-nearest and is used by any operations (generally 650 * Neon) which the architecture defines as controlled by the 651 * standard FPSCR value rather than the FPSCR. 652 * 653 * The "standard FPSCR but for fp16 ops" is needed because 654 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 655 * using a fixed value for it. 656 * 657 * To avoid having to transfer exception bits around, we simply 658 * say that the FPSCR cumulative exception flags are the logical 659 * OR of the flags in the four fp statuses. This relies on the 660 * only thing which needs to read the exception flags being 661 * an explicit FPSCR read. 662 */ 663 float_status fp_status; 664 float_status fp_status_f16; 665 float_status standard_fp_status; 666 float_status standard_fp_status_f16; 667 668 /* ZCR_EL[1-3] */ 669 uint64_t zcr_el[4]; 670 } vfp; 671 uint64_t exclusive_addr; 672 uint64_t exclusive_val; 673 uint64_t exclusive_high; 674 675 /* iwMMXt coprocessor state. */ 676 struct { 677 uint64_t regs[16]; 678 uint64_t val; 679 680 uint32_t cregs[16]; 681 } iwmmxt; 682 683 #ifdef TARGET_AARCH64 684 struct { 685 ARMPACKey apia; 686 ARMPACKey apib; 687 ARMPACKey apda; 688 ARMPACKey apdb; 689 ARMPACKey apga; 690 } keys; 691 692 uint64_t scxtnum_el[4]; 693 #endif 694 695 #if defined(CONFIG_USER_ONLY) 696 /* For usermode syscall translation. */ 697 int eabi; 698 #endif 699 700 struct CPUBreakpoint *cpu_breakpoint[16]; 701 struct CPUWatchpoint *cpu_watchpoint[16]; 702 703 /* Fields up to this point are cleared by a CPU reset */ 704 struct {} end_reset_fields; 705 706 /* Fields after this point are preserved across CPU reset. */ 707 708 /* Internal CPU feature flags. */ 709 uint64_t features; 710 711 /* PMSAv7 MPU */ 712 struct { 713 uint32_t *drbar; 714 uint32_t *drsr; 715 uint32_t *dracr; 716 uint32_t rnr[M_REG_NUM_BANKS]; 717 } pmsav7; 718 719 /* PMSAv8 MPU */ 720 struct { 721 /* The PMSAv8 implementation also shares some PMSAv7 config 722 * and state: 723 * pmsav7.rnr (region number register) 724 * pmsav7_dregion (number of configured regions) 725 */ 726 uint32_t *rbar[M_REG_NUM_BANKS]; 727 uint32_t *rlar[M_REG_NUM_BANKS]; 728 uint32_t mair0[M_REG_NUM_BANKS]; 729 uint32_t mair1[M_REG_NUM_BANKS]; 730 } pmsav8; 731 732 /* v8M SAU */ 733 struct { 734 uint32_t *rbar; 735 uint32_t *rlar; 736 uint32_t rnr; 737 uint32_t ctrl; 738 } sau; 739 740 void *nvic; 741 const struct arm_boot_info *boot_info; 742 /* Store GICv3CPUState to access from this struct */ 743 void *gicv3state; 744 745 #ifdef TARGET_TAGGED_ADDRESSES 746 /* Linux syscall tagged address support */ 747 bool tagged_addr_enable; 748 #endif 749 } CPUARMState; 750 751 static inline void set_feature(CPUARMState *env, int feature) 752 { 753 env->features |= 1ULL << feature; 754 } 755 756 static inline void unset_feature(CPUARMState *env, int feature) 757 { 758 env->features &= ~(1ULL << feature); 759 } 760 761 /** 762 * ARMELChangeHookFn: 763 * type of a function which can be registered via arm_register_el_change_hook() 764 * to get callbacks when the CPU changes its exception level or mode. 765 */ 766 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 767 typedef struct ARMELChangeHook ARMELChangeHook; 768 struct ARMELChangeHook { 769 ARMELChangeHookFn *hook; 770 void *opaque; 771 QLIST_ENTRY(ARMELChangeHook) node; 772 }; 773 774 /* These values map onto the return values for 775 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 776 typedef enum ARMPSCIState { 777 PSCI_ON = 0, 778 PSCI_OFF = 1, 779 PSCI_ON_PENDING = 2 780 } ARMPSCIState; 781 782 typedef struct ARMISARegisters ARMISARegisters; 783 784 /** 785 * ARMCPU: 786 * @env: #CPUARMState 787 * 788 * An ARM CPU core. 789 */ 790 struct ArchCPU { 791 /*< private >*/ 792 CPUState parent_obj; 793 /*< public >*/ 794 795 CPUNegativeOffsetState neg; 796 CPUARMState env; 797 798 /* Coprocessor information */ 799 GHashTable *cp_regs; 800 /* For marshalling (mostly coprocessor) register state between the 801 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 802 * we use these arrays. 803 */ 804 /* List of register indexes managed via these arrays; (full KVM style 805 * 64 bit indexes, not CPRegInfo 32 bit indexes) 806 */ 807 uint64_t *cpreg_indexes; 808 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 809 uint64_t *cpreg_values; 810 /* Length of the indexes, values, reset_values arrays */ 811 int32_t cpreg_array_len; 812 /* These are used only for migration: incoming data arrives in 813 * these fields and is sanity checked in post_load before copying 814 * to the working data structures above. 815 */ 816 uint64_t *cpreg_vmstate_indexes; 817 uint64_t *cpreg_vmstate_values; 818 int32_t cpreg_vmstate_array_len; 819 820 DynamicGDBXMLInfo dyn_sysreg_xml; 821 DynamicGDBXMLInfo dyn_svereg_xml; 822 823 /* Timers used by the generic (architected) timer */ 824 QEMUTimer *gt_timer[NUM_GTIMERS]; 825 /* 826 * Timer used by the PMU. Its state is restored after migration by 827 * pmu_op_finish() - it does not need other handling during migration 828 */ 829 QEMUTimer *pmu_timer; 830 /* GPIO outputs for generic timer */ 831 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 832 /* GPIO output for GICv3 maintenance interrupt signal */ 833 qemu_irq gicv3_maintenance_interrupt; 834 /* GPIO output for the PMU interrupt */ 835 qemu_irq pmu_interrupt; 836 837 /* MemoryRegion to use for secure physical accesses */ 838 MemoryRegion *secure_memory; 839 840 /* MemoryRegion to use for allocation tag accesses */ 841 MemoryRegion *tag_memory; 842 MemoryRegion *secure_tag_memory; 843 844 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 845 Object *idau; 846 847 /* 'compatible' string for this CPU for Linux device trees */ 848 const char *dtb_compatible; 849 850 /* PSCI version for this CPU 851 * Bits[31:16] = Major Version 852 * Bits[15:0] = Minor Version 853 */ 854 uint32_t psci_version; 855 856 /* Current power state, access guarded by BQL */ 857 ARMPSCIState power_state; 858 859 /* CPU has virtualization extension */ 860 bool has_el2; 861 /* CPU has security extension */ 862 bool has_el3; 863 /* CPU has PMU (Performance Monitor Unit) */ 864 bool has_pmu; 865 /* CPU has VFP */ 866 bool has_vfp; 867 /* CPU has Neon */ 868 bool has_neon; 869 /* CPU has M-profile DSP extension */ 870 bool has_dsp; 871 872 /* CPU has memory protection unit */ 873 bool has_mpu; 874 /* PMSAv7 MPU number of supported regions */ 875 uint32_t pmsav7_dregion; 876 /* v8M SAU number of supported regions */ 877 uint32_t sau_sregion; 878 879 /* PSCI conduit used to invoke PSCI methods 880 * 0 - disabled, 1 - smc, 2 - hvc 881 */ 882 uint32_t psci_conduit; 883 884 /* For v8M, initial value of the Secure VTOR */ 885 uint32_t init_svtor; 886 /* For v8M, initial value of the Non-secure VTOR */ 887 uint32_t init_nsvtor; 888 889 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 890 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 891 */ 892 uint32_t kvm_target; 893 894 /* KVM init features for this CPU */ 895 uint32_t kvm_init_features[7]; 896 897 /* KVM CPU state */ 898 899 /* KVM virtual time adjustment */ 900 bool kvm_adjvtime; 901 bool kvm_vtime_dirty; 902 uint64_t kvm_vtime; 903 904 /* KVM steal time */ 905 OnOffAuto kvm_steal_time; 906 907 /* Uniprocessor system with MP extensions */ 908 bool mp_is_up; 909 910 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 911 * and the probe failed (so we need to report the error in realize) 912 */ 913 bool host_cpu_probe_failed; 914 915 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 916 * register. 917 */ 918 int32_t core_count; 919 920 /* The instance init functions for implementation-specific subclasses 921 * set these fields to specify the implementation-dependent values of 922 * various constant registers and reset values of non-constant 923 * registers. 924 * Some of these might become QOM properties eventually. 925 * Field names match the official register names as defined in the 926 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 927 * is used for reset values of non-constant registers; no reset_ 928 * prefix means a constant register. 929 * Some of these registers are split out into a substructure that 930 * is shared with the translators to control the ISA. 931 * 932 * Note that if you add an ID register to the ARMISARegisters struct 933 * you need to also update the 32-bit and 64-bit versions of the 934 * kvm_arm_get_host_cpu_features() function to correctly populate the 935 * field by reading the value from the KVM vCPU. 936 */ 937 struct ARMISARegisters { 938 uint32_t id_isar0; 939 uint32_t id_isar1; 940 uint32_t id_isar2; 941 uint32_t id_isar3; 942 uint32_t id_isar4; 943 uint32_t id_isar5; 944 uint32_t id_isar6; 945 uint32_t id_mmfr0; 946 uint32_t id_mmfr1; 947 uint32_t id_mmfr2; 948 uint32_t id_mmfr3; 949 uint32_t id_mmfr4; 950 uint32_t id_pfr0; 951 uint32_t id_pfr1; 952 uint32_t id_pfr2; 953 uint32_t mvfr0; 954 uint32_t mvfr1; 955 uint32_t mvfr2; 956 uint32_t id_dfr0; 957 uint32_t dbgdidr; 958 uint64_t id_aa64isar0; 959 uint64_t id_aa64isar1; 960 uint64_t id_aa64pfr0; 961 uint64_t id_aa64pfr1; 962 uint64_t id_aa64mmfr0; 963 uint64_t id_aa64mmfr1; 964 uint64_t id_aa64mmfr2; 965 uint64_t id_aa64dfr0; 966 uint64_t id_aa64dfr1; 967 uint64_t id_aa64zfr0; 968 } isar; 969 uint64_t midr; 970 uint32_t revidr; 971 uint32_t reset_fpsid; 972 uint64_t ctr; 973 uint32_t reset_sctlr; 974 uint64_t pmceid0; 975 uint64_t pmceid1; 976 uint32_t id_afr0; 977 uint64_t id_aa64afr0; 978 uint64_t id_aa64afr1; 979 uint64_t clidr; 980 uint64_t mp_affinity; /* MP ID without feature bits */ 981 /* The elements of this array are the CCSIDR values for each cache, 982 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 983 */ 984 uint64_t ccsidr[16]; 985 uint64_t reset_cbar; 986 uint32_t reset_auxcr; 987 bool reset_hivecs; 988 989 /* 990 * Intermediate values used during property parsing. 991 * Once finalized, the values should be read from ID_AA64*. 992 */ 993 bool prop_pauth; 994 bool prop_pauth_impdef; 995 bool prop_lpa2; 996 997 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 998 uint32_t dcz_blocksize; 999 uint64_t rvbar_prop; /* Property/input signals. */ 1000 1001 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1002 int gic_num_lrs; /* number of list registers */ 1003 int gic_vpribits; /* number of virtual priority bits */ 1004 int gic_vprebits; /* number of virtual preemption bits */ 1005 int gic_pribits; /* number of physical priority bits */ 1006 1007 /* Whether the cfgend input is high (i.e. this CPU should reset into 1008 * big-endian mode). This setting isn't used directly: instead it modifies 1009 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1010 * architecture version. 1011 */ 1012 bool cfgend; 1013 1014 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1015 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1016 1017 int32_t node_id; /* NUMA node this CPU belongs to */ 1018 1019 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1020 uint8_t device_irq_level; 1021 1022 /* Used to set the maximum vector length the cpu will support. */ 1023 uint32_t sve_max_vq; 1024 1025 #ifdef CONFIG_USER_ONLY 1026 /* Used to set the default vector length at process start. */ 1027 uint32_t sve_default_vq; 1028 #endif 1029 1030 /* 1031 * In sve_vq_map each set bit is a supported vector length of 1032 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 1033 * length in quadwords. 1034 * 1035 * While processing properties during initialization, corresponding 1036 * sve_vq_init bits are set for bits in sve_vq_map that have been 1037 * set by properties. 1038 * 1039 * Bits set in sve_vq_supported represent valid vector lengths for 1040 * the CPU type. 1041 */ 1042 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); 1043 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); 1044 DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); 1045 1046 /* Generic timer counter frequency, in Hz */ 1047 uint64_t gt_cntfrq_hz; 1048 }; 1049 1050 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1051 1052 void arm_cpu_post_init(Object *obj); 1053 1054 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1055 1056 #ifndef CONFIG_USER_ONLY 1057 extern const VMStateDescription vmstate_arm_cpu; 1058 1059 void arm_cpu_do_interrupt(CPUState *cpu); 1060 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1061 #endif /* !CONFIG_USER_ONLY */ 1062 1063 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1064 MemTxAttrs *attrs); 1065 1066 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1067 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1068 1069 /* 1070 * Helpers to dynamically generates XML descriptions of the sysregs 1071 * and SVE registers. Returns the number of registers in each set. 1072 */ 1073 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1074 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1075 1076 /* Returns the dynamically generated XML for the gdb stub. 1077 * Returns a pointer to the XML contents for the specified XML file or NULL 1078 * if the XML name doesn't match the predefined one. 1079 */ 1080 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1081 1082 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1083 int cpuid, void *opaque); 1084 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1085 int cpuid, void *opaque); 1086 1087 #ifdef TARGET_AARCH64 1088 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1089 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1090 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1091 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1092 int new_el, bool el0_a64); 1093 void aarch64_add_sve_properties(Object *obj); 1094 void aarch64_add_pauth_properties(Object *obj); 1095 1096 /* 1097 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1098 * The byte at offset i from the start of the in-memory representation contains 1099 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1100 * lowest offsets are stored in the lowest memory addresses, then that nearly 1101 * matches QEMU's representation, which is to use an array of host-endian 1102 * uint64_t's, where the lower offsets are at the lower indices. To complete 1103 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1104 */ 1105 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1106 { 1107 #if HOST_BIG_ENDIAN 1108 int i; 1109 1110 for (i = 0; i < nr; ++i) { 1111 dst[i] = bswap64(src[i]); 1112 } 1113 1114 return dst; 1115 #else 1116 return src; 1117 #endif 1118 } 1119 1120 #else 1121 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1122 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1123 int n, bool a) 1124 { } 1125 static inline void aarch64_add_sve_properties(Object *obj) { } 1126 #endif 1127 1128 void aarch64_sync_32_to_64(CPUARMState *env); 1129 void aarch64_sync_64_to_32(CPUARMState *env); 1130 1131 int fp_exception_el(CPUARMState *env, int cur_el); 1132 int sve_exception_el(CPUARMState *env, int cur_el); 1133 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); 1134 1135 static inline bool is_a64(CPUARMState *env) 1136 { 1137 return env->aarch64; 1138 } 1139 1140 /** 1141 * pmu_op_start/finish 1142 * @env: CPUARMState 1143 * 1144 * Convert all PMU counters between their delta form (the typical mode when 1145 * they are enabled) and the guest-visible values. These two calls must 1146 * surround any action which might affect the counters. 1147 */ 1148 void pmu_op_start(CPUARMState *env); 1149 void pmu_op_finish(CPUARMState *env); 1150 1151 /* 1152 * Called when a PMU counter is due to overflow 1153 */ 1154 void arm_pmu_timer_cb(void *opaque); 1155 1156 /** 1157 * Functions to register as EL change hooks for PMU mode filtering 1158 */ 1159 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1160 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1161 1162 /* 1163 * pmu_init 1164 * @cpu: ARMCPU 1165 * 1166 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1167 * for the current configuration 1168 */ 1169 void pmu_init(ARMCPU *cpu); 1170 1171 /* SCTLR bit meanings. Several bits have been reused in newer 1172 * versions of the architecture; in that case we define constants 1173 * for both old and new bit meanings. Code which tests against those 1174 * bits should probably check or otherwise arrange that the CPU 1175 * is the architectural version it expects. 1176 */ 1177 #define SCTLR_M (1U << 0) 1178 #define SCTLR_A (1U << 1) 1179 #define SCTLR_C (1U << 2) 1180 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1181 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1182 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1183 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1184 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1185 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1186 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1187 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1188 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1189 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1190 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1191 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1192 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1193 #define SCTLR_SED (1U << 8) /* v8 onward */ 1194 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1195 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1196 #define SCTLR_F (1U << 10) /* up to v6 */ 1197 #define SCTLR_SW (1U << 10) /* v7 */ 1198 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1199 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1200 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1201 #define SCTLR_I (1U << 12) 1202 #define SCTLR_V (1U << 13) /* AArch32 only */ 1203 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1204 #define SCTLR_RR (1U << 14) /* up to v7 */ 1205 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1206 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1207 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1208 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1209 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1210 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1211 #define SCTLR_BR (1U << 17) /* PMSA only */ 1212 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1213 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1214 #define SCTLR_WXN (1U << 19) 1215 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1216 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1217 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1218 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1219 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1220 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1221 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1222 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1223 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1224 #define SCTLR_VE (1U << 24) /* up to v7 */ 1225 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1226 #define SCTLR_EE (1U << 25) 1227 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1228 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1229 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1230 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1231 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1232 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1233 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1234 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1235 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1236 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1237 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1238 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1239 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1240 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1241 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1242 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1243 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1244 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1245 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1246 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1247 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1248 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1249 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1250 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1251 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1252 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1253 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1254 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1255 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1256 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1257 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1258 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1259 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1260 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1261 1262 #define CPTR_TCPAC (1U << 31) 1263 #define CPTR_TTA (1U << 20) 1264 #define CPTR_TFP (1U << 10) 1265 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ 1266 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ 1267 1268 #define MDCR_EPMAD (1U << 21) 1269 #define MDCR_EDAD (1U << 20) 1270 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1271 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1272 #define MDCR_SDD (1U << 16) 1273 #define MDCR_SPD (3U << 14) 1274 #define MDCR_TDRA (1U << 11) 1275 #define MDCR_TDOSA (1U << 10) 1276 #define MDCR_TDA (1U << 9) 1277 #define MDCR_TDE (1U << 8) 1278 #define MDCR_HPME (1U << 7) 1279 #define MDCR_TPM (1U << 6) 1280 #define MDCR_TPMCR (1U << 5) 1281 #define MDCR_HPMN (0x1fU) 1282 1283 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1284 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1285 1286 #define CPSR_M (0x1fU) 1287 #define CPSR_T (1U << 5) 1288 #define CPSR_F (1U << 6) 1289 #define CPSR_I (1U << 7) 1290 #define CPSR_A (1U << 8) 1291 #define CPSR_E (1U << 9) 1292 #define CPSR_IT_2_7 (0xfc00U) 1293 #define CPSR_GE (0xfU << 16) 1294 #define CPSR_IL (1U << 20) 1295 #define CPSR_DIT (1U << 21) 1296 #define CPSR_PAN (1U << 22) 1297 #define CPSR_SSBS (1U << 23) 1298 #define CPSR_J (1U << 24) 1299 #define CPSR_IT_0_1 (3U << 25) 1300 #define CPSR_Q (1U << 27) 1301 #define CPSR_V (1U << 28) 1302 #define CPSR_C (1U << 29) 1303 #define CPSR_Z (1U << 30) 1304 #define CPSR_N (1U << 31) 1305 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1306 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1307 1308 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1309 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1310 | CPSR_NZCV) 1311 /* Bits writable in user mode. */ 1312 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1313 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1314 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1315 1316 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1317 #define XPSR_EXCP 0x1ffU 1318 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1319 #define XPSR_IT_2_7 CPSR_IT_2_7 1320 #define XPSR_GE CPSR_GE 1321 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1322 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1323 #define XPSR_IT_0_1 CPSR_IT_0_1 1324 #define XPSR_Q CPSR_Q 1325 #define XPSR_V CPSR_V 1326 #define XPSR_C CPSR_C 1327 #define XPSR_Z CPSR_Z 1328 #define XPSR_N CPSR_N 1329 #define XPSR_NZCV CPSR_NZCV 1330 #define XPSR_IT CPSR_IT 1331 1332 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1333 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1334 #define TTBCR_PD0 (1U << 4) 1335 #define TTBCR_PD1 (1U << 5) 1336 #define TTBCR_EPD0 (1U << 7) 1337 #define TTBCR_IRGN0 (3U << 8) 1338 #define TTBCR_ORGN0 (3U << 10) 1339 #define TTBCR_SH0 (3U << 12) 1340 #define TTBCR_T1SZ (3U << 16) 1341 #define TTBCR_A1 (1U << 22) 1342 #define TTBCR_EPD1 (1U << 23) 1343 #define TTBCR_IRGN1 (3U << 24) 1344 #define TTBCR_ORGN1 (3U << 26) 1345 #define TTBCR_SH1 (1U << 28) 1346 #define TTBCR_EAE (1U << 31) 1347 1348 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1349 * Only these are valid when in AArch64 mode; in 1350 * AArch32 mode SPSRs are basically CPSR-format. 1351 */ 1352 #define PSTATE_SP (1U) 1353 #define PSTATE_M (0xFU) 1354 #define PSTATE_nRW (1U << 4) 1355 #define PSTATE_F (1U << 6) 1356 #define PSTATE_I (1U << 7) 1357 #define PSTATE_A (1U << 8) 1358 #define PSTATE_D (1U << 9) 1359 #define PSTATE_BTYPE (3U << 10) 1360 #define PSTATE_SSBS (1U << 12) 1361 #define PSTATE_IL (1U << 20) 1362 #define PSTATE_SS (1U << 21) 1363 #define PSTATE_PAN (1U << 22) 1364 #define PSTATE_UAO (1U << 23) 1365 #define PSTATE_DIT (1U << 24) 1366 #define PSTATE_TCO (1U << 25) 1367 #define PSTATE_V (1U << 28) 1368 #define PSTATE_C (1U << 29) 1369 #define PSTATE_Z (1U << 30) 1370 #define PSTATE_N (1U << 31) 1371 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1372 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1373 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1374 /* Mode values for AArch64 */ 1375 #define PSTATE_MODE_EL3h 13 1376 #define PSTATE_MODE_EL3t 12 1377 #define PSTATE_MODE_EL2h 9 1378 #define PSTATE_MODE_EL2t 8 1379 #define PSTATE_MODE_EL1h 5 1380 #define PSTATE_MODE_EL1t 4 1381 #define PSTATE_MODE_EL0t 0 1382 1383 /* Write a new value to v7m.exception, thus transitioning into or out 1384 * of Handler mode; this may result in a change of active stack pointer. 1385 */ 1386 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1387 1388 /* Map EL and handler into a PSTATE_MODE. */ 1389 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1390 { 1391 return (el << 2) | handler; 1392 } 1393 1394 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1395 * interprocessing, so we don't attempt to sync with the cpsr state used by 1396 * the 32 bit decoder. 1397 */ 1398 static inline uint32_t pstate_read(CPUARMState *env) 1399 { 1400 int ZF; 1401 1402 ZF = (env->ZF == 0); 1403 return (env->NF & 0x80000000) | (ZF << 30) 1404 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1405 | env->pstate | env->daif | (env->btype << 10); 1406 } 1407 1408 static inline void pstate_write(CPUARMState *env, uint32_t val) 1409 { 1410 env->ZF = (~val) & PSTATE_Z; 1411 env->NF = val; 1412 env->CF = (val >> 29) & 1; 1413 env->VF = (val << 3) & 0x80000000; 1414 env->daif = val & PSTATE_DAIF; 1415 env->btype = (val >> 10) & 3; 1416 env->pstate = val & ~CACHED_PSTATE_BITS; 1417 } 1418 1419 /* Return the current CPSR value. */ 1420 uint32_t cpsr_read(CPUARMState *env); 1421 1422 typedef enum CPSRWriteType { 1423 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1424 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1425 CPSRWriteRaw = 2, 1426 /* trust values, no reg bank switch, no hflags rebuild */ 1427 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1428 } CPSRWriteType; 1429 1430 /* 1431 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1432 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1433 * correspond to TB flags bits cached in the hflags, unless @write_type 1434 * is CPSRWriteRaw. 1435 */ 1436 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1437 CPSRWriteType write_type); 1438 1439 /* Return the current xPSR value. */ 1440 static inline uint32_t xpsr_read(CPUARMState *env) 1441 { 1442 int ZF; 1443 ZF = (env->ZF == 0); 1444 return (env->NF & 0x80000000) | (ZF << 30) 1445 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1446 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1447 | ((env->condexec_bits & 0xfc) << 8) 1448 | (env->GE << 16) 1449 | env->v7m.exception; 1450 } 1451 1452 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1453 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1454 { 1455 if (mask & XPSR_NZCV) { 1456 env->ZF = (~val) & XPSR_Z; 1457 env->NF = val; 1458 env->CF = (val >> 29) & 1; 1459 env->VF = (val << 3) & 0x80000000; 1460 } 1461 if (mask & XPSR_Q) { 1462 env->QF = ((val & XPSR_Q) != 0); 1463 } 1464 if (mask & XPSR_GE) { 1465 env->GE = (val & XPSR_GE) >> 16; 1466 } 1467 #ifndef CONFIG_USER_ONLY 1468 if (mask & XPSR_T) { 1469 env->thumb = ((val & XPSR_T) != 0); 1470 } 1471 if (mask & XPSR_IT_0_1) { 1472 env->condexec_bits &= ~3; 1473 env->condexec_bits |= (val >> 25) & 3; 1474 } 1475 if (mask & XPSR_IT_2_7) { 1476 env->condexec_bits &= 3; 1477 env->condexec_bits |= (val >> 8) & 0xfc; 1478 } 1479 if (mask & XPSR_EXCP) { 1480 /* Note that this only happens on exception exit */ 1481 write_v7m_exception(env, val & XPSR_EXCP); 1482 } 1483 #endif 1484 } 1485 1486 #define HCR_VM (1ULL << 0) 1487 #define HCR_SWIO (1ULL << 1) 1488 #define HCR_PTW (1ULL << 2) 1489 #define HCR_FMO (1ULL << 3) 1490 #define HCR_IMO (1ULL << 4) 1491 #define HCR_AMO (1ULL << 5) 1492 #define HCR_VF (1ULL << 6) 1493 #define HCR_VI (1ULL << 7) 1494 #define HCR_VSE (1ULL << 8) 1495 #define HCR_FB (1ULL << 9) 1496 #define HCR_BSU_MASK (3ULL << 10) 1497 #define HCR_DC (1ULL << 12) 1498 #define HCR_TWI (1ULL << 13) 1499 #define HCR_TWE (1ULL << 14) 1500 #define HCR_TID0 (1ULL << 15) 1501 #define HCR_TID1 (1ULL << 16) 1502 #define HCR_TID2 (1ULL << 17) 1503 #define HCR_TID3 (1ULL << 18) 1504 #define HCR_TSC (1ULL << 19) 1505 #define HCR_TIDCP (1ULL << 20) 1506 #define HCR_TACR (1ULL << 21) 1507 #define HCR_TSW (1ULL << 22) 1508 #define HCR_TPCP (1ULL << 23) 1509 #define HCR_TPU (1ULL << 24) 1510 #define HCR_TTLB (1ULL << 25) 1511 #define HCR_TVM (1ULL << 26) 1512 #define HCR_TGE (1ULL << 27) 1513 #define HCR_TDZ (1ULL << 28) 1514 #define HCR_HCD (1ULL << 29) 1515 #define HCR_TRVM (1ULL << 30) 1516 #define HCR_RW (1ULL << 31) 1517 #define HCR_CD (1ULL << 32) 1518 #define HCR_ID (1ULL << 33) 1519 #define HCR_E2H (1ULL << 34) 1520 #define HCR_TLOR (1ULL << 35) 1521 #define HCR_TERR (1ULL << 36) 1522 #define HCR_TEA (1ULL << 37) 1523 #define HCR_MIOCNCE (1ULL << 38) 1524 /* RES0 bit 39 */ 1525 #define HCR_APK (1ULL << 40) 1526 #define HCR_API (1ULL << 41) 1527 #define HCR_NV (1ULL << 42) 1528 #define HCR_NV1 (1ULL << 43) 1529 #define HCR_AT (1ULL << 44) 1530 #define HCR_NV2 (1ULL << 45) 1531 #define HCR_FWB (1ULL << 46) 1532 #define HCR_FIEN (1ULL << 47) 1533 /* RES0 bit 48 */ 1534 #define HCR_TID4 (1ULL << 49) 1535 #define HCR_TICAB (1ULL << 50) 1536 #define HCR_AMVOFFEN (1ULL << 51) 1537 #define HCR_TOCU (1ULL << 52) 1538 #define HCR_ENSCXT (1ULL << 53) 1539 #define HCR_TTLBIS (1ULL << 54) 1540 #define HCR_TTLBOS (1ULL << 55) 1541 #define HCR_ATA (1ULL << 56) 1542 #define HCR_DCT (1ULL << 57) 1543 #define HCR_TID5 (1ULL << 58) 1544 #define HCR_TWEDEN (1ULL << 59) 1545 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1546 1547 #define HPFAR_NS (1ULL << 63) 1548 1549 #define SCR_NS (1U << 0) 1550 #define SCR_IRQ (1U << 1) 1551 #define SCR_FIQ (1U << 2) 1552 #define SCR_EA (1U << 3) 1553 #define SCR_FW (1U << 4) 1554 #define SCR_AW (1U << 5) 1555 #define SCR_NET (1U << 6) 1556 #define SCR_SMD (1U << 7) 1557 #define SCR_HCE (1U << 8) 1558 #define SCR_SIF (1U << 9) 1559 #define SCR_RW (1U << 10) 1560 #define SCR_ST (1U << 11) 1561 #define SCR_TWI (1U << 12) 1562 #define SCR_TWE (1U << 13) 1563 #define SCR_TLOR (1U << 14) 1564 #define SCR_TERR (1U << 15) 1565 #define SCR_APK (1U << 16) 1566 #define SCR_API (1U << 17) 1567 #define SCR_EEL2 (1U << 18) 1568 #define SCR_EASE (1U << 19) 1569 #define SCR_NMEA (1U << 20) 1570 #define SCR_FIEN (1U << 21) 1571 #define SCR_ENSCXT (1U << 25) 1572 #define SCR_ATA (1U << 26) 1573 #define SCR_FGTEN (1U << 27) 1574 #define SCR_ECVEN (1U << 28) 1575 #define SCR_TWEDEN (1U << 29) 1576 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1577 #define SCR_TME (1ULL << 34) 1578 #define SCR_AMVOFFEN (1ULL << 35) 1579 #define SCR_ENAS0 (1ULL << 36) 1580 #define SCR_ADEN (1ULL << 37) 1581 #define SCR_HXEN (1ULL << 38) 1582 #define SCR_TRNDR (1ULL << 40) 1583 #define SCR_ENTP2 (1ULL << 41) 1584 #define SCR_GPF (1ULL << 48) 1585 1586 #define HSTR_TTEE (1 << 16) 1587 #define HSTR_TJDBX (1 << 17) 1588 1589 /* Return the current FPSCR value. */ 1590 uint32_t vfp_get_fpscr(CPUARMState *env); 1591 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1592 1593 /* FPCR, Floating Point Control Register 1594 * FPSR, Floating Poiht Status Register 1595 * 1596 * For A64 the FPSCR is split into two logically distinct registers, 1597 * FPCR and FPSR. However since they still use non-overlapping bits 1598 * we store the underlying state in fpscr and just mask on read/write. 1599 */ 1600 #define FPSR_MASK 0xf800009f 1601 #define FPCR_MASK 0x07ff9f00 1602 1603 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1604 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1605 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1606 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1607 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1608 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1609 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1610 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1611 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1612 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1613 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1614 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1615 #define FPCR_V (1 << 28) /* FP overflow flag */ 1616 #define FPCR_C (1 << 29) /* FP carry flag */ 1617 #define FPCR_Z (1 << 30) /* FP zero flag */ 1618 #define FPCR_N (1 << 31) /* FP negative flag */ 1619 1620 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1621 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1622 #define FPCR_LTPSIZE_LENGTH 3 1623 1624 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1625 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1626 1627 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1628 { 1629 return vfp_get_fpscr(env) & FPSR_MASK; 1630 } 1631 1632 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1633 { 1634 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1635 vfp_set_fpscr(env, new_fpscr); 1636 } 1637 1638 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1639 { 1640 return vfp_get_fpscr(env) & FPCR_MASK; 1641 } 1642 1643 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1644 { 1645 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1646 vfp_set_fpscr(env, new_fpscr); 1647 } 1648 1649 enum arm_cpu_mode { 1650 ARM_CPU_MODE_USR = 0x10, 1651 ARM_CPU_MODE_FIQ = 0x11, 1652 ARM_CPU_MODE_IRQ = 0x12, 1653 ARM_CPU_MODE_SVC = 0x13, 1654 ARM_CPU_MODE_MON = 0x16, 1655 ARM_CPU_MODE_ABT = 0x17, 1656 ARM_CPU_MODE_HYP = 0x1a, 1657 ARM_CPU_MODE_UND = 0x1b, 1658 ARM_CPU_MODE_SYS = 0x1f 1659 }; 1660 1661 /* VFP system registers. */ 1662 #define ARM_VFP_FPSID 0 1663 #define ARM_VFP_FPSCR 1 1664 #define ARM_VFP_MVFR2 5 1665 #define ARM_VFP_MVFR1 6 1666 #define ARM_VFP_MVFR0 7 1667 #define ARM_VFP_FPEXC 8 1668 #define ARM_VFP_FPINST 9 1669 #define ARM_VFP_FPINST2 10 1670 /* These ones are M-profile only */ 1671 #define ARM_VFP_FPSCR_NZCVQC 2 1672 #define ARM_VFP_VPR 12 1673 #define ARM_VFP_P0 13 1674 #define ARM_VFP_FPCXT_NS 14 1675 #define ARM_VFP_FPCXT_S 15 1676 1677 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1678 #define QEMU_VFP_FPSCR_NZCV 0xffff 1679 1680 /* iwMMXt coprocessor control registers. */ 1681 #define ARM_IWMMXT_wCID 0 1682 #define ARM_IWMMXT_wCon 1 1683 #define ARM_IWMMXT_wCSSF 2 1684 #define ARM_IWMMXT_wCASF 3 1685 #define ARM_IWMMXT_wCGR0 8 1686 #define ARM_IWMMXT_wCGR1 9 1687 #define ARM_IWMMXT_wCGR2 10 1688 #define ARM_IWMMXT_wCGR3 11 1689 1690 /* V7M CCR bits */ 1691 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1692 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1693 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1694 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1695 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1696 FIELD(V7M_CCR, STKALIGN, 9, 1) 1697 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1698 FIELD(V7M_CCR, DC, 16, 1) 1699 FIELD(V7M_CCR, IC, 17, 1) 1700 FIELD(V7M_CCR, BP, 18, 1) 1701 FIELD(V7M_CCR, LOB, 19, 1) 1702 FIELD(V7M_CCR, TRD, 20, 1) 1703 1704 /* V7M SCR bits */ 1705 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1706 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1707 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1708 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1709 1710 /* V7M AIRCR bits */ 1711 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1712 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1713 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1714 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1715 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1716 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1717 FIELD(V7M_AIRCR, PRIS, 14, 1) 1718 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1719 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1720 1721 /* V7M CFSR bits for MMFSR */ 1722 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1723 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1724 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1725 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1726 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1727 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1728 1729 /* V7M CFSR bits for BFSR */ 1730 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1731 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1732 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1733 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1734 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1735 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1736 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1737 1738 /* V7M CFSR bits for UFSR */ 1739 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1740 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1741 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1742 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1743 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1744 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1745 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1746 1747 /* V7M CFSR bit masks covering all of the subregister bits */ 1748 FIELD(V7M_CFSR, MMFSR, 0, 8) 1749 FIELD(V7M_CFSR, BFSR, 8, 8) 1750 FIELD(V7M_CFSR, UFSR, 16, 16) 1751 1752 /* V7M HFSR bits */ 1753 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1754 FIELD(V7M_HFSR, FORCED, 30, 1) 1755 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1756 1757 /* V7M DFSR bits */ 1758 FIELD(V7M_DFSR, HALTED, 0, 1) 1759 FIELD(V7M_DFSR, BKPT, 1, 1) 1760 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1761 FIELD(V7M_DFSR, VCATCH, 3, 1) 1762 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1763 1764 /* V7M SFSR bits */ 1765 FIELD(V7M_SFSR, INVEP, 0, 1) 1766 FIELD(V7M_SFSR, INVIS, 1, 1) 1767 FIELD(V7M_SFSR, INVER, 2, 1) 1768 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1769 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1770 FIELD(V7M_SFSR, LSPERR, 5, 1) 1771 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1772 FIELD(V7M_SFSR, LSERR, 7, 1) 1773 1774 /* v7M MPU_CTRL bits */ 1775 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1776 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1777 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1778 1779 /* v7M CLIDR bits */ 1780 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1781 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1782 FIELD(V7M_CLIDR, LOC, 24, 3) 1783 FIELD(V7M_CLIDR, LOUU, 27, 3) 1784 FIELD(V7M_CLIDR, ICB, 30, 2) 1785 1786 FIELD(V7M_CSSELR, IND, 0, 1) 1787 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1788 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1789 * define a mask for this and check that it doesn't permit running off 1790 * the end of the array. 1791 */ 1792 FIELD(V7M_CSSELR, INDEX, 0, 4) 1793 1794 /* v7M FPCCR bits */ 1795 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1796 FIELD(V7M_FPCCR, USER, 1, 1) 1797 FIELD(V7M_FPCCR, S, 2, 1) 1798 FIELD(V7M_FPCCR, THREAD, 3, 1) 1799 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1800 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1801 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1802 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1803 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1804 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1805 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1806 FIELD(V7M_FPCCR, RES0, 11, 15) 1807 FIELD(V7M_FPCCR, TS, 26, 1) 1808 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1809 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1810 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1811 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1812 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1813 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1814 #define R_V7M_FPCCR_BANKED_MASK \ 1815 (R_V7M_FPCCR_LSPACT_MASK | \ 1816 R_V7M_FPCCR_USER_MASK | \ 1817 R_V7M_FPCCR_THREAD_MASK | \ 1818 R_V7M_FPCCR_MMRDY_MASK | \ 1819 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1820 R_V7M_FPCCR_UFRDY_MASK | \ 1821 R_V7M_FPCCR_ASPEN_MASK) 1822 1823 /* v7M VPR bits */ 1824 FIELD(V7M_VPR, P0, 0, 16) 1825 FIELD(V7M_VPR, MASK01, 16, 4) 1826 FIELD(V7M_VPR, MASK23, 20, 4) 1827 1828 /* 1829 * System register ID fields. 1830 */ 1831 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1832 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1833 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1834 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1835 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1836 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1837 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1838 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1839 FIELD(CLIDR_EL1, LOC, 24, 3) 1840 FIELD(CLIDR_EL1, LOUU, 27, 3) 1841 FIELD(CLIDR_EL1, ICB, 30, 3) 1842 1843 /* When FEAT_CCIDX is implemented */ 1844 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1845 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1846 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1847 1848 /* When FEAT_CCIDX is not implemented */ 1849 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1850 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1851 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1852 1853 FIELD(CTR_EL0, IMINLINE, 0, 4) 1854 FIELD(CTR_EL0, L1IP, 14, 2) 1855 FIELD(CTR_EL0, DMINLINE, 16, 4) 1856 FIELD(CTR_EL0, ERG, 20, 4) 1857 FIELD(CTR_EL0, CWG, 24, 4) 1858 FIELD(CTR_EL0, IDC, 28, 1) 1859 FIELD(CTR_EL0, DIC, 29, 1) 1860 FIELD(CTR_EL0, TMINLINE, 32, 6) 1861 1862 FIELD(MIDR_EL1, REVISION, 0, 4) 1863 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1864 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1865 FIELD(MIDR_EL1, VARIANT, 20, 4) 1866 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1867 1868 FIELD(ID_ISAR0, SWAP, 0, 4) 1869 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1870 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1871 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1872 FIELD(ID_ISAR0, COPROC, 16, 4) 1873 FIELD(ID_ISAR0, DEBUG, 20, 4) 1874 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1875 1876 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1877 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1878 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1879 FIELD(ID_ISAR1, EXTEND, 12, 4) 1880 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1881 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1882 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1883 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1884 1885 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1886 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1887 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1888 FIELD(ID_ISAR2, MULT, 12, 4) 1889 FIELD(ID_ISAR2, MULTS, 16, 4) 1890 FIELD(ID_ISAR2, MULTU, 20, 4) 1891 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1892 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1893 1894 FIELD(ID_ISAR3, SATURATE, 0, 4) 1895 FIELD(ID_ISAR3, SIMD, 4, 4) 1896 FIELD(ID_ISAR3, SVC, 8, 4) 1897 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1898 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1899 FIELD(ID_ISAR3, T32COPY, 20, 4) 1900 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1901 FIELD(ID_ISAR3, T32EE, 28, 4) 1902 1903 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1904 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1905 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1906 FIELD(ID_ISAR4, SMC, 12, 4) 1907 FIELD(ID_ISAR4, BARRIER, 16, 4) 1908 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1909 FIELD(ID_ISAR4, PSR_M, 24, 4) 1910 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1911 1912 FIELD(ID_ISAR5, SEVL, 0, 4) 1913 FIELD(ID_ISAR5, AES, 4, 4) 1914 FIELD(ID_ISAR5, SHA1, 8, 4) 1915 FIELD(ID_ISAR5, SHA2, 12, 4) 1916 FIELD(ID_ISAR5, CRC32, 16, 4) 1917 FIELD(ID_ISAR5, RDM, 24, 4) 1918 FIELD(ID_ISAR5, VCMA, 28, 4) 1919 1920 FIELD(ID_ISAR6, JSCVT, 0, 4) 1921 FIELD(ID_ISAR6, DP, 4, 4) 1922 FIELD(ID_ISAR6, FHM, 8, 4) 1923 FIELD(ID_ISAR6, SB, 12, 4) 1924 FIELD(ID_ISAR6, SPECRES, 16, 4) 1925 FIELD(ID_ISAR6, BF16, 20, 4) 1926 FIELD(ID_ISAR6, I8MM, 24, 4) 1927 1928 FIELD(ID_MMFR0, VMSA, 0, 4) 1929 FIELD(ID_MMFR0, PMSA, 4, 4) 1930 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1931 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1932 FIELD(ID_MMFR0, TCM, 16, 4) 1933 FIELD(ID_MMFR0, AUXREG, 20, 4) 1934 FIELD(ID_MMFR0, FCSE, 24, 4) 1935 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1936 1937 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1938 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1939 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1940 FIELD(ID_MMFR1, L1UNISW, 12, 4) 1941 FIELD(ID_MMFR1, L1HVD, 16, 4) 1942 FIELD(ID_MMFR1, L1UNI, 20, 4) 1943 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 1944 FIELD(ID_MMFR1, BPRED, 28, 4) 1945 1946 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 1947 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 1948 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 1949 FIELD(ID_MMFR2, HVDTLB, 12, 4) 1950 FIELD(ID_MMFR2, UNITLB, 16, 4) 1951 FIELD(ID_MMFR2, MEMBARR, 20, 4) 1952 FIELD(ID_MMFR2, WFISTALL, 24, 4) 1953 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 1954 1955 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 1956 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 1957 FIELD(ID_MMFR3, BPMAINT, 8, 4) 1958 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 1959 FIELD(ID_MMFR3, PAN, 16, 4) 1960 FIELD(ID_MMFR3, COHWALK, 20, 4) 1961 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 1962 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 1963 1964 FIELD(ID_MMFR4, SPECSEI, 0, 4) 1965 FIELD(ID_MMFR4, AC2, 4, 4) 1966 FIELD(ID_MMFR4, XNX, 8, 4) 1967 FIELD(ID_MMFR4, CNP, 12, 4) 1968 FIELD(ID_MMFR4, HPDS, 16, 4) 1969 FIELD(ID_MMFR4, LSM, 20, 4) 1970 FIELD(ID_MMFR4, CCIDX, 24, 4) 1971 FIELD(ID_MMFR4, EVT, 28, 4) 1972 1973 FIELD(ID_MMFR5, ETS, 0, 4) 1974 FIELD(ID_MMFR5, NTLBPA, 4, 4) 1975 1976 FIELD(ID_PFR0, STATE0, 0, 4) 1977 FIELD(ID_PFR0, STATE1, 4, 4) 1978 FIELD(ID_PFR0, STATE2, 8, 4) 1979 FIELD(ID_PFR0, STATE3, 12, 4) 1980 FIELD(ID_PFR0, CSV2, 16, 4) 1981 FIELD(ID_PFR0, AMU, 20, 4) 1982 FIELD(ID_PFR0, DIT, 24, 4) 1983 FIELD(ID_PFR0, RAS, 28, 4) 1984 1985 FIELD(ID_PFR1, PROGMOD, 0, 4) 1986 FIELD(ID_PFR1, SECURITY, 4, 4) 1987 FIELD(ID_PFR1, MPROGMOD, 8, 4) 1988 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 1989 FIELD(ID_PFR1, GENTIMER, 16, 4) 1990 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 1991 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 1992 FIELD(ID_PFR1, GIC, 28, 4) 1993 1994 FIELD(ID_PFR2, CSV3, 0, 4) 1995 FIELD(ID_PFR2, SSBS, 4, 4) 1996 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 1997 1998 FIELD(ID_AA64ISAR0, AES, 4, 4) 1999 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2000 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2001 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2002 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2003 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2004 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2005 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2006 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2007 FIELD(ID_AA64ISAR0, DP, 44, 4) 2008 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2009 FIELD(ID_AA64ISAR0, TS, 52, 4) 2010 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2011 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2012 2013 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2014 FIELD(ID_AA64ISAR1, APA, 4, 4) 2015 FIELD(ID_AA64ISAR1, API, 8, 4) 2016 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2017 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2018 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2019 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2020 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2021 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2022 FIELD(ID_AA64ISAR1, SB, 36, 4) 2023 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2024 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2025 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2026 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2027 FIELD(ID_AA64ISAR1, XS, 56, 4) 2028 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2029 2030 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2031 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2032 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2033 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2034 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2035 FIELD(ID_AA64ISAR2, BC, 20, 4) 2036 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2037 2038 FIELD(ID_AA64PFR0, EL0, 0, 4) 2039 FIELD(ID_AA64PFR0, EL1, 4, 4) 2040 FIELD(ID_AA64PFR0, EL2, 8, 4) 2041 FIELD(ID_AA64PFR0, EL3, 12, 4) 2042 FIELD(ID_AA64PFR0, FP, 16, 4) 2043 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2044 FIELD(ID_AA64PFR0, GIC, 24, 4) 2045 FIELD(ID_AA64PFR0, RAS, 28, 4) 2046 FIELD(ID_AA64PFR0, SVE, 32, 4) 2047 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2048 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2049 FIELD(ID_AA64PFR0, AMU, 44, 4) 2050 FIELD(ID_AA64PFR0, DIT, 48, 4) 2051 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2052 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2053 2054 FIELD(ID_AA64PFR1, BT, 0, 4) 2055 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2056 FIELD(ID_AA64PFR1, MTE, 8, 4) 2057 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2058 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2059 FIELD(ID_AA64PFR1, SME, 24, 4) 2060 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2061 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2062 FIELD(ID_AA64PFR1, NMI, 36, 4) 2063 2064 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2065 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2066 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2067 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2068 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2069 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2070 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2071 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2072 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2073 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2074 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2075 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2076 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2077 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2078 2079 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2080 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2081 FIELD(ID_AA64MMFR1, VH, 8, 4) 2082 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2083 FIELD(ID_AA64MMFR1, LO, 16, 4) 2084 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2085 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2086 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2087 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2088 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2089 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2090 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2091 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2092 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2093 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2094 2095 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2096 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2097 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2098 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2099 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2100 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2101 FIELD(ID_AA64MMFR2, NV, 24, 4) 2102 FIELD(ID_AA64MMFR2, ST, 28, 4) 2103 FIELD(ID_AA64MMFR2, AT, 32, 4) 2104 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2105 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2106 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2107 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2108 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2109 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2110 2111 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2112 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2113 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2114 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2115 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2116 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2117 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2118 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2119 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2120 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2121 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2122 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2123 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2124 2125 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2126 FIELD(ID_AA64ZFR0, AES, 4, 4) 2127 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2128 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2129 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2130 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2131 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2132 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2133 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2134 2135 FIELD(ID_DFR0, COPDBG, 0, 4) 2136 FIELD(ID_DFR0, COPSDBG, 4, 4) 2137 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2138 FIELD(ID_DFR0, COPTRC, 12, 4) 2139 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2140 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2141 FIELD(ID_DFR0, PERFMON, 24, 4) 2142 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2143 2144 FIELD(ID_DFR1, MTPMU, 0, 4) 2145 FIELD(ID_DFR1, HPMN0, 4, 4) 2146 2147 FIELD(DBGDIDR, SE_IMP, 12, 1) 2148 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2149 FIELD(DBGDIDR, VERSION, 16, 4) 2150 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2151 FIELD(DBGDIDR, BRPS, 24, 4) 2152 FIELD(DBGDIDR, WRPS, 28, 4) 2153 2154 FIELD(MVFR0, SIMDREG, 0, 4) 2155 FIELD(MVFR0, FPSP, 4, 4) 2156 FIELD(MVFR0, FPDP, 8, 4) 2157 FIELD(MVFR0, FPTRAP, 12, 4) 2158 FIELD(MVFR0, FPDIVIDE, 16, 4) 2159 FIELD(MVFR0, FPSQRT, 20, 4) 2160 FIELD(MVFR0, FPSHVEC, 24, 4) 2161 FIELD(MVFR0, FPROUND, 28, 4) 2162 2163 FIELD(MVFR1, FPFTZ, 0, 4) 2164 FIELD(MVFR1, FPDNAN, 4, 4) 2165 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2166 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2167 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2168 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2169 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2170 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2171 FIELD(MVFR1, FPHP, 24, 4) 2172 FIELD(MVFR1, SIMDFMAC, 28, 4) 2173 2174 FIELD(MVFR2, SIMDMISC, 0, 4) 2175 FIELD(MVFR2, FPMISC, 4, 4) 2176 2177 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2178 2179 /* If adding a feature bit which corresponds to a Linux ELF 2180 * HWCAP bit, remember to update the feature-bit-to-hwcap 2181 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2182 */ 2183 enum arm_features { 2184 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2185 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2186 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2187 ARM_FEATURE_V6, 2188 ARM_FEATURE_V6K, 2189 ARM_FEATURE_V7, 2190 ARM_FEATURE_THUMB2, 2191 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2192 ARM_FEATURE_NEON, 2193 ARM_FEATURE_M, /* Microcontroller profile. */ 2194 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2195 ARM_FEATURE_THUMB2EE, 2196 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2197 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2198 ARM_FEATURE_V4T, 2199 ARM_FEATURE_V5, 2200 ARM_FEATURE_STRONGARM, 2201 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2202 ARM_FEATURE_GENERIC_TIMER, 2203 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2204 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2205 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2206 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2207 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2208 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2209 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2210 ARM_FEATURE_V8, 2211 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2212 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2213 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2214 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2215 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2216 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2217 ARM_FEATURE_PMU, /* has PMU support */ 2218 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2219 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2220 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2221 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2222 }; 2223 2224 static inline int arm_feature(CPUARMState *env, int feature) 2225 { 2226 return (env->features & (1ULL << feature)) != 0; 2227 } 2228 2229 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2230 2231 #if !defined(CONFIG_USER_ONLY) 2232 /* Return true if exception levels below EL3 are in secure state, 2233 * or would be following an exception return to that level. 2234 * Unlike arm_is_secure() (which is always a question about the 2235 * _current_ state of the CPU) this doesn't care about the current 2236 * EL or mode. 2237 */ 2238 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2239 { 2240 if (arm_feature(env, ARM_FEATURE_EL3)) { 2241 return !(env->cp15.scr_el3 & SCR_NS); 2242 } else { 2243 /* If EL3 is not supported then the secure state is implementation 2244 * defined, in which case QEMU defaults to non-secure. 2245 */ 2246 return false; 2247 } 2248 } 2249 2250 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2251 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2252 { 2253 if (arm_feature(env, ARM_FEATURE_EL3)) { 2254 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2255 /* CPU currently in AArch64 state and EL3 */ 2256 return true; 2257 } else if (!is_a64(env) && 2258 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2259 /* CPU currently in AArch32 state and monitor mode */ 2260 return true; 2261 } 2262 } 2263 return false; 2264 } 2265 2266 /* Return true if the processor is in secure state */ 2267 static inline bool arm_is_secure(CPUARMState *env) 2268 { 2269 if (arm_is_el3_or_mon(env)) { 2270 return true; 2271 } 2272 return arm_is_secure_below_el3(env); 2273 } 2274 2275 /* 2276 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2277 * This corresponds to the pseudocode EL2Enabled() 2278 */ 2279 static inline bool arm_is_el2_enabled(CPUARMState *env) 2280 { 2281 if (arm_feature(env, ARM_FEATURE_EL2)) { 2282 if (arm_is_secure_below_el3(env)) { 2283 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2284 } 2285 return true; 2286 } 2287 return false; 2288 } 2289 2290 #else 2291 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2292 { 2293 return false; 2294 } 2295 2296 static inline bool arm_is_secure(CPUARMState *env) 2297 { 2298 return false; 2299 } 2300 2301 static inline bool arm_is_el2_enabled(CPUARMState *env) 2302 { 2303 return false; 2304 } 2305 #endif 2306 2307 /** 2308 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2309 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2310 * "for all purposes other than a direct read or write access of HCR_EL2." 2311 * Not included here is HCR_RW. 2312 */ 2313 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2314 2315 /* Return true if the specified exception level is running in AArch64 state. */ 2316 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2317 { 2318 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2319 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2320 */ 2321 assert(el >= 1 && el <= 3); 2322 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2323 2324 /* The highest exception level is always at the maximum supported 2325 * register width, and then lower levels have a register width controlled 2326 * by bits in the SCR or HCR registers. 2327 */ 2328 if (el == 3) { 2329 return aa64; 2330 } 2331 2332 if (arm_feature(env, ARM_FEATURE_EL3) && 2333 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2334 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2335 } 2336 2337 if (el == 2) { 2338 return aa64; 2339 } 2340 2341 if (arm_is_el2_enabled(env)) { 2342 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2343 } 2344 2345 return aa64; 2346 } 2347 2348 /* Function for determing whether guest cp register reads and writes should 2349 * access the secure or non-secure bank of a cp register. When EL3 is 2350 * operating in AArch32 state, the NS-bit determines whether the secure 2351 * instance of a cp register should be used. When EL3 is AArch64 (or if 2352 * it doesn't exist at all) then there is no register banking, and all 2353 * accesses are to the non-secure version. 2354 */ 2355 static inline bool access_secure_reg(CPUARMState *env) 2356 { 2357 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2358 !arm_el_is_aa64(env, 3) && 2359 !(env->cp15.scr_el3 & SCR_NS)); 2360 2361 return ret; 2362 } 2363 2364 /* Macros for accessing a specified CP register bank */ 2365 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2366 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2367 2368 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2369 do { \ 2370 if (_secure) { \ 2371 (_env)->cp15._regname##_s = (_val); \ 2372 } else { \ 2373 (_env)->cp15._regname##_ns = (_val); \ 2374 } \ 2375 } while (0) 2376 2377 /* Macros for automatically accessing a specific CP register bank depending on 2378 * the current secure state of the system. These macros are not intended for 2379 * supporting instruction translation reads/writes as these are dependent 2380 * solely on the SCR.NS bit and not the mode. 2381 */ 2382 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2383 A32_BANKED_REG_GET((_env), _regname, \ 2384 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2385 2386 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2387 A32_BANKED_REG_SET((_env), _regname, \ 2388 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2389 (_val)) 2390 2391 void arm_cpu_list(void); 2392 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2393 uint32_t cur_el, bool secure); 2394 2395 /* Interface between CPU and Interrupt controller. */ 2396 #ifndef CONFIG_USER_ONLY 2397 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2398 #else 2399 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2400 { 2401 return true; 2402 } 2403 #endif 2404 /** 2405 * armv7m_nvic_set_pending: mark the specified exception as pending 2406 * @opaque: the NVIC 2407 * @irq: the exception number to mark pending 2408 * @secure: false for non-banked exceptions or for the nonsecure 2409 * version of a banked exception, true for the secure version of a banked 2410 * exception. 2411 * 2412 * Marks the specified exception as pending. Note that we will assert() 2413 * if @secure is true and @irq does not specify one of the fixed set 2414 * of architecturally banked exceptions. 2415 */ 2416 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2417 /** 2418 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2419 * @opaque: the NVIC 2420 * @irq: the exception number to mark pending 2421 * @secure: false for non-banked exceptions or for the nonsecure 2422 * version of a banked exception, true for the secure version of a banked 2423 * exception. 2424 * 2425 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2426 * exceptions (exceptions generated in the course of trying to take 2427 * a different exception). 2428 */ 2429 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2430 /** 2431 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2432 * @opaque: the NVIC 2433 * @irq: the exception number to mark pending 2434 * @secure: false for non-banked exceptions or for the nonsecure 2435 * version of a banked exception, true for the secure version of a banked 2436 * exception. 2437 * 2438 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2439 * generated in the course of lazy stacking of FP registers. 2440 */ 2441 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2442 /** 2443 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2444 * exception, and whether it targets Secure state 2445 * @opaque: the NVIC 2446 * @pirq: set to pending exception number 2447 * @ptargets_secure: set to whether pending exception targets Secure 2448 * 2449 * This function writes the number of the highest priority pending 2450 * exception (the one which would be made active by 2451 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2452 * to true if the current highest priority pending exception should 2453 * be taken to Secure state, false for NS. 2454 */ 2455 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2456 bool *ptargets_secure); 2457 /** 2458 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2459 * @opaque: the NVIC 2460 * 2461 * Move the current highest priority pending exception from the pending 2462 * state to the active state, and update v7m.exception to indicate that 2463 * it is the exception currently being handled. 2464 */ 2465 void armv7m_nvic_acknowledge_irq(void *opaque); 2466 /** 2467 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2468 * @opaque: the NVIC 2469 * @irq: the exception number to complete 2470 * @secure: true if this exception was secure 2471 * 2472 * Returns: -1 if the irq was not active 2473 * 1 if completing this irq brought us back to base (no active irqs) 2474 * 0 if there is still an irq active after this one was completed 2475 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2476 */ 2477 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2478 /** 2479 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2480 * @opaque: the NVIC 2481 * @irq: the exception number to mark pending 2482 * @secure: false for non-banked exceptions or for the nonsecure 2483 * version of a banked exception, true for the secure version of a banked 2484 * exception. 2485 * 2486 * Return whether an exception is "ready", i.e. whether the exception is 2487 * enabled and is configured at a priority which would allow it to 2488 * interrupt the current execution priority. This controls whether the 2489 * RDY bit for it in the FPCCR is set. 2490 */ 2491 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2492 /** 2493 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2494 * @opaque: the NVIC 2495 * 2496 * Returns: the raw execution priority as defined by the v8M architecture. 2497 * This is the execution priority minus the effects of AIRCR.PRIS, 2498 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2499 * (v8M ARM ARM I_PKLD.) 2500 */ 2501 int armv7m_nvic_raw_execution_priority(void *opaque); 2502 /** 2503 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2504 * priority is negative for the specified security state. 2505 * @opaque: the NVIC 2506 * @secure: the security state to test 2507 * This corresponds to the pseudocode IsReqExecPriNeg(). 2508 */ 2509 #ifndef CONFIG_USER_ONLY 2510 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2511 #else 2512 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2513 { 2514 return false; 2515 } 2516 #endif 2517 2518 /* Interface for defining coprocessor registers. 2519 * Registers are defined in tables of arm_cp_reginfo structs 2520 * which are passed to define_arm_cp_regs(). 2521 */ 2522 2523 /* When looking up a coprocessor register we look for it 2524 * via an integer which encodes all of: 2525 * coprocessor number 2526 * Crn, Crm, opc1, opc2 fields 2527 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2528 * or via MRRC/MCRR?) 2529 * non-secure/secure bank (AArch32 only) 2530 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2531 * (In this case crn and opc2 should be zero.) 2532 * For AArch64, there is no 32/64 bit size distinction; 2533 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2534 * and 4 bit CRn and CRm. The encoding patterns are chosen 2535 * to be easy to convert to and from the KVM encodings, and also 2536 * so that the hashtable can contain both AArch32 and AArch64 2537 * registers (to allow for interprocessing where we might run 2538 * 32 bit code on a 64 bit core). 2539 */ 2540 /* This bit is private to our hashtable cpreg; in KVM register 2541 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2542 * in the upper bits of the 64 bit ID. 2543 */ 2544 #define CP_REG_AA64_SHIFT 28 2545 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2546 2547 /* To enable banking of coprocessor registers depending on ns-bit we 2548 * add a bit to distinguish between secure and non-secure cpregs in the 2549 * hashtable. 2550 */ 2551 #define CP_REG_NS_SHIFT 29 2552 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2553 2554 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2555 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2556 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2557 2558 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2559 (CP_REG_AA64_MASK | \ 2560 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2561 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2562 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2563 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2564 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2565 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2566 2567 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2568 * version used as a key for the coprocessor register hashtable 2569 */ 2570 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2571 { 2572 uint32_t cpregid = kvmid; 2573 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2574 cpregid |= CP_REG_AA64_MASK; 2575 } else { 2576 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2577 cpregid |= (1 << 15); 2578 } 2579 2580 /* KVM is always non-secure so add the NS flag on AArch32 register 2581 * entries. 2582 */ 2583 cpregid |= 1 << CP_REG_NS_SHIFT; 2584 } 2585 return cpregid; 2586 } 2587 2588 /* Convert a truncated 32 bit hashtable key into the full 2589 * 64 bit KVM register ID. 2590 */ 2591 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2592 { 2593 uint64_t kvmid; 2594 2595 if (cpregid & CP_REG_AA64_MASK) { 2596 kvmid = cpregid & ~CP_REG_AA64_MASK; 2597 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2598 } else { 2599 kvmid = cpregid & ~(1 << 15); 2600 if (cpregid & (1 << 15)) { 2601 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2602 } else { 2603 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2604 } 2605 } 2606 return kvmid; 2607 } 2608 2609 /* Return the highest implemented Exception Level */ 2610 static inline int arm_highest_el(CPUARMState *env) 2611 { 2612 if (arm_feature(env, ARM_FEATURE_EL3)) { 2613 return 3; 2614 } 2615 if (arm_feature(env, ARM_FEATURE_EL2)) { 2616 return 2; 2617 } 2618 return 1; 2619 } 2620 2621 /* Return true if a v7M CPU is in Handler mode */ 2622 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2623 { 2624 return env->v7m.exception != 0; 2625 } 2626 2627 /* Return the current Exception Level (as per ARMv8; note that this differs 2628 * from the ARMv7 Privilege Level). 2629 */ 2630 static inline int arm_current_el(CPUARMState *env) 2631 { 2632 if (arm_feature(env, ARM_FEATURE_M)) { 2633 return arm_v7m_is_handler_mode(env) || 2634 !(env->v7m.control[env->v7m.secure] & 1); 2635 } 2636 2637 if (is_a64(env)) { 2638 return extract32(env->pstate, 2, 2); 2639 } 2640 2641 switch (env->uncached_cpsr & 0x1f) { 2642 case ARM_CPU_MODE_USR: 2643 return 0; 2644 case ARM_CPU_MODE_HYP: 2645 return 2; 2646 case ARM_CPU_MODE_MON: 2647 return 3; 2648 default: 2649 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2650 /* If EL3 is 32-bit then all secure privileged modes run in 2651 * EL3 2652 */ 2653 return 3; 2654 } 2655 2656 return 1; 2657 } 2658 } 2659 2660 /** 2661 * write_list_to_cpustate 2662 * @cpu: ARMCPU 2663 * 2664 * For each register listed in the ARMCPU cpreg_indexes list, write 2665 * its value from the cpreg_values list into the ARMCPUState structure. 2666 * This updates TCG's working data structures from KVM data or 2667 * from incoming migration state. 2668 * 2669 * Returns: true if all register values were updated correctly, 2670 * false if some register was unknown or could not be written. 2671 * Note that we do not stop early on failure -- we will attempt 2672 * writing all registers in the list. 2673 */ 2674 bool write_list_to_cpustate(ARMCPU *cpu); 2675 2676 /** 2677 * write_cpustate_to_list: 2678 * @cpu: ARMCPU 2679 * @kvm_sync: true if this is for syncing back to KVM 2680 * 2681 * For each register listed in the ARMCPU cpreg_indexes list, write 2682 * its value from the ARMCPUState structure into the cpreg_values list. 2683 * This is used to copy info from TCG's working data structures into 2684 * KVM or for outbound migration. 2685 * 2686 * @kvm_sync is true if we are doing this in order to sync the 2687 * register state back to KVM. In this case we will only update 2688 * values in the list if the previous list->cpustate sync actually 2689 * successfully wrote the CPU state. Otherwise we will keep the value 2690 * that is in the list. 2691 * 2692 * Returns: true if all register values were read correctly, 2693 * false if some register was unknown or could not be read. 2694 * Note that we do not stop early on failure -- we will attempt 2695 * reading all registers in the list. 2696 */ 2697 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2698 2699 #define ARM_CPUID_TI915T 0x54029152 2700 #define ARM_CPUID_TI925T 0x54029252 2701 2702 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2703 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2704 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2705 2706 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2707 2708 #define cpu_list arm_cpu_list 2709 2710 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2711 * 2712 * If EL3 is 64-bit: 2713 * + NonSecure EL1 & 0 stage 1 2714 * + NonSecure EL1 & 0 stage 2 2715 * + NonSecure EL2 2716 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2717 * + Secure EL1 & 0 2718 * + Secure EL3 2719 * If EL3 is 32-bit: 2720 * + NonSecure PL1 & 0 stage 1 2721 * + NonSecure PL1 & 0 stage 2 2722 * + NonSecure PL2 2723 * + Secure PL0 2724 * + Secure PL1 2725 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2726 * 2727 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2728 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2729 * because they may differ in access permissions even if the VA->PA map is 2730 * the same 2731 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2732 * translation, which means that we have one mmu_idx that deals with two 2733 * concatenated translation regimes [this sort of combined s1+2 TLB is 2734 * architecturally permitted] 2735 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2736 * handling via the TLB. The only way to do a stage 1 translation without 2737 * the immediate stage 2 translation is via the ATS or AT system insns, 2738 * which can be slow-pathed and always do a page table walk. 2739 * The only use of stage 2 translations is either as part of an s1+2 2740 * lookup or when loading the descriptors during a stage 1 page table walk, 2741 * and in both those cases we don't use the TLB. 2742 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2743 * translation regimes, because they map reasonably well to each other 2744 * and they can't both be active at the same time. 2745 * 5. we want to be able to use the TLB for accesses done as part of a 2746 * stage1 page table walk, rather than having to walk the stage2 page 2747 * table over and over. 2748 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2749 * Never (PAN) bit within PSTATE. 2750 * 2751 * This gives us the following list of cases: 2752 * 2753 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2754 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2755 * NS EL1 EL1&0 stage 1+2 +PAN 2756 * NS EL0 EL2&0 2757 * NS EL2 EL2&0 2758 * NS EL2 EL2&0 +PAN 2759 * NS EL2 (aka NS PL2) 2760 * S EL0 EL1&0 (aka S PL0) 2761 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2762 * S EL1 EL1&0 +PAN 2763 * S EL3 (aka S PL1) 2764 * 2765 * for a total of 11 different mmu_idx. 2766 * 2767 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2768 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2769 * NS EL2 if we ever model a Cortex-R52). 2770 * 2771 * M profile CPUs are rather different as they do not have a true MMU. 2772 * They have the following different MMU indexes: 2773 * User 2774 * Privileged 2775 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2776 * Privileged, execution priority negative (ditto) 2777 * If the CPU supports the v8M Security Extension then there are also: 2778 * Secure User 2779 * Secure Privileged 2780 * Secure User, execution priority negative 2781 * Secure Privileged, execution priority negative 2782 * 2783 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2784 * are not quite the same -- different CPU types (most notably M profile 2785 * vs A/R profile) would like to use MMU indexes with different semantics, 2786 * but since we don't ever need to use all of those in a single CPU we 2787 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2788 * modes + total number of M profile MMU modes". The lower bits of 2789 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2790 * the same for any particular CPU. 2791 * Variables of type ARMMUIdx are always full values, and the core 2792 * index values are in variables of type 'int'. 2793 * 2794 * Our enumeration includes at the end some entries which are not "true" 2795 * mmu_idx values in that they don't have corresponding TLBs and are only 2796 * valid for doing slow path page table walks. 2797 * 2798 * The constant names here are patterned after the general style of the names 2799 * of the AT/ATS operations. 2800 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2801 * For M profile we arrange them to have a bit for priv, a bit for negpri 2802 * and a bit for secure. 2803 */ 2804 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2805 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2806 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2807 2808 /* Meanings of the bits for A profile mmu idx values */ 2809 #define ARM_MMU_IDX_A_NS 0x8 2810 2811 /* Meanings of the bits for M profile mmu idx values */ 2812 #define ARM_MMU_IDX_M_PRIV 0x1 2813 #define ARM_MMU_IDX_M_NEGPRI 0x2 2814 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2815 2816 #define ARM_MMU_IDX_TYPE_MASK \ 2817 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2818 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2819 2820 typedef enum ARMMMUIdx { 2821 /* 2822 * A-profile. 2823 */ 2824 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 2825 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 2826 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 2827 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 2828 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 2829 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 2830 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 2831 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 2832 2833 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 2834 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 2835 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 2836 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 2837 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 2838 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 2839 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 2840 2841 /* 2842 * These are not allocated TLBs and are used only for AT system 2843 * instructions or for the first stage of an S12 page table walk. 2844 */ 2845 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2846 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2847 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2848 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 2849 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 2850 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 2851 /* 2852 * Not allocated a TLB: used only for second stage of an S12 page 2853 * table walk, or for descriptor loads during first stage of an S1 2854 * page table walk. Note that if we ever want to have a TLB for this 2855 * then various TLB flush insns which currently are no-ops or flush 2856 * only stage 1 MMU indexes will need to change to flush stage 2. 2857 */ 2858 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 2859 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 2860 2861 /* 2862 * M-profile. 2863 */ 2864 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2865 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2866 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2867 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2868 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2869 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2870 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2871 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2872 } ARMMMUIdx; 2873 2874 /* 2875 * Bit macros for the core-mmu-index values for each index, 2876 * for use when calling tlb_flush_by_mmuidx() and friends. 2877 */ 2878 #define TO_CORE_BIT(NAME) \ 2879 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2880 2881 typedef enum ARMMMUIdxBit { 2882 TO_CORE_BIT(E10_0), 2883 TO_CORE_BIT(E20_0), 2884 TO_CORE_BIT(E10_1), 2885 TO_CORE_BIT(E10_1_PAN), 2886 TO_CORE_BIT(E2), 2887 TO_CORE_BIT(E20_2), 2888 TO_CORE_BIT(E20_2_PAN), 2889 TO_CORE_BIT(SE10_0), 2890 TO_CORE_BIT(SE20_0), 2891 TO_CORE_BIT(SE10_1), 2892 TO_CORE_BIT(SE20_2), 2893 TO_CORE_BIT(SE10_1_PAN), 2894 TO_CORE_BIT(SE20_2_PAN), 2895 TO_CORE_BIT(SE2), 2896 TO_CORE_BIT(SE3), 2897 2898 TO_CORE_BIT(MUser), 2899 TO_CORE_BIT(MPriv), 2900 TO_CORE_BIT(MUserNegPri), 2901 TO_CORE_BIT(MPrivNegPri), 2902 TO_CORE_BIT(MSUser), 2903 TO_CORE_BIT(MSPriv), 2904 TO_CORE_BIT(MSUserNegPri), 2905 TO_CORE_BIT(MSPrivNegPri), 2906 } ARMMMUIdxBit; 2907 2908 #undef TO_CORE_BIT 2909 2910 #define MMU_USER_IDX 0 2911 2912 /* Indexes used when registering address spaces with cpu_address_space_init */ 2913 typedef enum ARMASIdx { 2914 ARMASIdx_NS = 0, 2915 ARMASIdx_S = 1, 2916 ARMASIdx_TagNS = 2, 2917 ARMASIdx_TagS = 3, 2918 } ARMASIdx; 2919 2920 /* Return the Exception Level targeted by debug exceptions. */ 2921 static inline int arm_debug_target_el(CPUARMState *env) 2922 { 2923 bool secure = arm_is_secure(env); 2924 bool route_to_el2 = false; 2925 2926 if (arm_is_el2_enabled(env)) { 2927 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || 2928 env->cp15.mdcr_el2 & MDCR_TDE; 2929 } 2930 2931 if (route_to_el2) { 2932 return 2; 2933 } else if (arm_feature(env, ARM_FEATURE_EL3) && 2934 !arm_el_is_aa64(env, 3) && secure) { 2935 return 3; 2936 } else { 2937 return 1; 2938 } 2939 } 2940 2941 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2942 { 2943 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2944 * CSSELR is RAZ/WI. 2945 */ 2946 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2947 } 2948 2949 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ 2950 static inline bool aa64_generate_debug_exceptions(CPUARMState *env) 2951 { 2952 int cur_el = arm_current_el(env); 2953 int debug_el; 2954 2955 if (cur_el == 3) { 2956 return false; 2957 } 2958 2959 /* MDCR_EL3.SDD disables debug events from Secure state */ 2960 if (arm_is_secure_below_el3(env) 2961 && extract32(env->cp15.mdcr_el3, 16, 1)) { 2962 return false; 2963 } 2964 2965 /* 2966 * Same EL to same EL debug exceptions need MDSCR_KDE enabled 2967 * while not masking the (D)ebug bit in DAIF. 2968 */ 2969 debug_el = arm_debug_target_el(env); 2970 2971 if (cur_el == debug_el) { 2972 return extract32(env->cp15.mdscr_el1, 13, 1) 2973 && !(env->daif & PSTATE_D); 2974 } 2975 2976 /* Otherwise the debug target needs to be a higher EL */ 2977 return debug_el > cur_el; 2978 } 2979 2980 static inline bool aa32_generate_debug_exceptions(CPUARMState *env) 2981 { 2982 int el = arm_current_el(env); 2983 2984 if (el == 0 && arm_el_is_aa64(env, 1)) { 2985 return aa64_generate_debug_exceptions(env); 2986 } 2987 2988 if (arm_is_secure(env)) { 2989 int spd; 2990 2991 if (el == 0 && (env->cp15.sder & 1)) { 2992 /* SDER.SUIDEN means debug exceptions from Secure EL0 2993 * are always enabled. Otherwise they are controlled by 2994 * SDCR.SPD like those from other Secure ELs. 2995 */ 2996 return true; 2997 } 2998 2999 spd = extract32(env->cp15.mdcr_el3, 14, 2); 3000 switch (spd) { 3001 case 1: 3002 /* SPD == 0b01 is reserved, but behaves as 0b00. */ 3003 case 0: 3004 /* For 0b00 we return true if external secure invasive debug 3005 * is enabled. On real hardware this is controlled by external 3006 * signals to the core. QEMU always permits debug, and behaves 3007 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. 3008 */ 3009 return true; 3010 case 2: 3011 return false; 3012 case 3: 3013 return true; 3014 } 3015 } 3016 3017 return el != 2; 3018 } 3019 3020 /* Return true if debugging exceptions are currently enabled. 3021 * This corresponds to what in ARM ARM pseudocode would be 3022 * if UsingAArch32() then 3023 * return AArch32.GenerateDebugExceptions() 3024 * else 3025 * return AArch64.GenerateDebugExceptions() 3026 * We choose to push the if() down into this function for clarity, 3027 * since the pseudocode has it at all callsites except for the one in 3028 * CheckSoftwareStep(), where it is elided because both branches would 3029 * always return the same value. 3030 */ 3031 static inline bool arm_generate_debug_exceptions(CPUARMState *env) 3032 { 3033 if (env->aarch64) { 3034 return aa64_generate_debug_exceptions(env); 3035 } else { 3036 return aa32_generate_debug_exceptions(env); 3037 } 3038 } 3039 3040 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check 3041 * implicitly means this always returns false in pre-v8 CPUs.) 3042 */ 3043 static inline bool arm_singlestep_active(CPUARMState *env) 3044 { 3045 return extract32(env->cp15.mdscr_el1, 0, 1) 3046 && arm_el_is_aa64(env, arm_debug_target_el(env)) 3047 && arm_generate_debug_exceptions(env); 3048 } 3049 3050 static inline bool arm_sctlr_b(CPUARMState *env) 3051 { 3052 return 3053 /* We need not implement SCTLR.ITD in user-mode emulation, so 3054 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3055 * This lets people run BE32 binaries with "-cpu any". 3056 */ 3057 #ifndef CONFIG_USER_ONLY 3058 !arm_feature(env, ARM_FEATURE_V7) && 3059 #endif 3060 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3061 } 3062 3063 uint64_t arm_sctlr(CPUARMState *env, int el); 3064 3065 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3066 bool sctlr_b) 3067 { 3068 #ifdef CONFIG_USER_ONLY 3069 /* 3070 * In system mode, BE32 is modelled in line with the 3071 * architecture (as word-invariant big-endianness), where loads 3072 * and stores are done little endian but from addresses which 3073 * are adjusted by XORing with the appropriate constant. So the 3074 * endianness to use for the raw data access is not affected by 3075 * SCTLR.B. 3076 * In user mode, however, we model BE32 as byte-invariant 3077 * big-endianness (because user-only code cannot tell the 3078 * difference), and so we need to use a data access endianness 3079 * that depends on SCTLR.B. 3080 */ 3081 if (sctlr_b) { 3082 return true; 3083 } 3084 #endif 3085 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3086 return env->uncached_cpsr & CPSR_E; 3087 } 3088 3089 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3090 { 3091 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3092 } 3093 3094 /* Return true if the processor is in big-endian mode. */ 3095 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3096 { 3097 if (!is_a64(env)) { 3098 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3099 } else { 3100 int cur_el = arm_current_el(env); 3101 uint64_t sctlr = arm_sctlr(env, cur_el); 3102 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3103 } 3104 } 3105 3106 #include "exec/cpu-all.h" 3107 3108 /* 3109 * We have more than 32-bits worth of state per TB, so we split the data 3110 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3111 * We collect these two parts in CPUARMTBFlags where they are named 3112 * flags and flags2 respectively. 3113 * 3114 * The flags that are shared between all execution modes, TBFLAG_ANY, 3115 * are stored in flags. The flags that are specific to a given mode 3116 * are stores in flags2. Since cs_base is sized on the configured 3117 * address size, flags2 always has 64-bits for A64, and a minimum of 3118 * 32-bits for A32 and M32. 3119 * 3120 * The bits for 32-bit A-profile and M-profile partially overlap: 3121 * 3122 * 31 23 11 10 0 3123 * +-------------+----------+----------------+ 3124 * | | | TBFLAG_A32 | 3125 * | TBFLAG_AM32 | +-----+----------+ 3126 * | | |TBFLAG_M32| 3127 * +-------------+----------------+----------+ 3128 * 31 23 6 5 0 3129 * 3130 * Unless otherwise noted, these bits are cached in env->hflags. 3131 */ 3132 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3133 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3134 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3135 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3136 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3137 /* Target EL if we take a floating-point-disabled exception */ 3138 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3139 /* For A-profile only, target EL for debug exceptions. */ 3140 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) 3141 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3142 FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) 3143 FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) 3144 3145 /* 3146 * Bit usage when in AArch32 state, both A- and M-profile. 3147 */ 3148 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3149 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3150 3151 /* 3152 * Bit usage when in AArch32 state, for A-profile only. 3153 */ 3154 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3155 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3156 /* 3157 * We store the bottom two bits of the CPAR as TB flags and handle 3158 * checks on the other bits at runtime. This shares the same bits as 3159 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3160 * Not cached, because VECLEN+VECSTRIDE are not cached. 3161 */ 3162 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3163 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3164 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3165 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3166 /* 3167 * Indicates whether cp register reads and writes by guest code should access 3168 * the secure or nonsecure bank of banked registers; note that this is not 3169 * the same thing as the current security state of the processor! 3170 */ 3171 FIELD(TBFLAG_A32, NS, 10, 1) 3172 3173 /* 3174 * Bit usage when in AArch32 state, for M-profile only. 3175 */ 3176 /* Handler (ie not Thread) mode */ 3177 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3178 /* Whether we should generate stack-limit checks */ 3179 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3180 /* Set if FPCCR.LSPACT is set */ 3181 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3182 /* Set if we must create a new FP context */ 3183 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3184 /* Set if FPCCR.S does not match current security state */ 3185 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3186 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3187 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3188 3189 /* 3190 * Bit usage when in AArch64 state 3191 */ 3192 FIELD(TBFLAG_A64, TBII, 0, 2) 3193 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3194 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) 3195 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3196 FIELD(TBFLAG_A64, BT, 9, 1) 3197 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3198 FIELD(TBFLAG_A64, TBID, 12, 2) 3199 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3200 FIELD(TBFLAG_A64, ATA, 15, 1) 3201 FIELD(TBFLAG_A64, TCMA, 16, 2) 3202 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3203 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3204 3205 /* 3206 * Helpers for using the above. 3207 */ 3208 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3209 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3210 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3211 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3212 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3213 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3214 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3215 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3216 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3217 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3218 3219 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3220 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3221 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3222 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3223 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3224 3225 /** 3226 * cpu_mmu_index: 3227 * @env: The cpu environment 3228 * @ifetch: True for code access, false for data access. 3229 * 3230 * Return the core mmu index for the current translation regime. 3231 * This function is used by generic TCG code paths. 3232 */ 3233 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3234 { 3235 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3236 } 3237 3238 static inline bool bswap_code(bool sctlr_b) 3239 { 3240 #ifdef CONFIG_USER_ONLY 3241 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3242 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3243 * would also end up as a mixed-endian mode with BE code, LE data. 3244 */ 3245 return 3246 #if TARGET_BIG_ENDIAN 3247 1 ^ 3248 #endif 3249 sctlr_b; 3250 #else 3251 /* All code access in ARM is little endian, and there are no loaders 3252 * doing swaps that need to be reversed 3253 */ 3254 return 0; 3255 #endif 3256 } 3257 3258 #ifdef CONFIG_USER_ONLY 3259 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3260 { 3261 return 3262 #if TARGET_BIG_ENDIAN 3263 1 ^ 3264 #endif 3265 arm_cpu_data_is_big_endian(env); 3266 } 3267 #endif 3268 3269 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3270 target_ulong *cs_base, uint32_t *flags); 3271 3272 enum { 3273 QEMU_PSCI_CONDUIT_DISABLED = 0, 3274 QEMU_PSCI_CONDUIT_SMC = 1, 3275 QEMU_PSCI_CONDUIT_HVC = 2, 3276 }; 3277 3278 #ifndef CONFIG_USER_ONLY 3279 /* Return the address space index to use for a memory access */ 3280 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3281 { 3282 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3283 } 3284 3285 /* Return the AddressSpace to use for a memory access 3286 * (which depends on whether the access is S or NS, and whether 3287 * the board gave us a separate AddressSpace for S accesses). 3288 */ 3289 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3290 { 3291 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3292 } 3293 #endif 3294 3295 /** 3296 * arm_register_pre_el_change_hook: 3297 * Register a hook function which will be called immediately before this 3298 * CPU changes exception level or mode. The hook function will be 3299 * passed a pointer to the ARMCPU and the opaque data pointer passed 3300 * to this function when the hook was registered. 3301 * 3302 * Note that if a pre-change hook is called, any registered post-change hooks 3303 * are guaranteed to subsequently be called. 3304 */ 3305 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3306 void *opaque); 3307 /** 3308 * arm_register_el_change_hook: 3309 * Register a hook function which will be called immediately after this 3310 * CPU changes exception level or mode. The hook function will be 3311 * passed a pointer to the ARMCPU and the opaque data pointer passed 3312 * to this function when the hook was registered. 3313 * 3314 * Note that any registered hooks registered here are guaranteed to be called 3315 * if pre-change hooks have been. 3316 */ 3317 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3318 *opaque); 3319 3320 /** 3321 * arm_rebuild_hflags: 3322 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3323 */ 3324 void arm_rebuild_hflags(CPUARMState *env); 3325 3326 /** 3327 * aa32_vfp_dreg: 3328 * Return a pointer to the Dn register within env in 32-bit mode. 3329 */ 3330 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3331 { 3332 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3333 } 3334 3335 /** 3336 * aa32_vfp_qreg: 3337 * Return a pointer to the Qn register within env in 32-bit mode. 3338 */ 3339 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3340 { 3341 return &env->vfp.zregs[regno].d[0]; 3342 } 3343 3344 /** 3345 * aa64_vfp_qreg: 3346 * Return a pointer to the Qn register within env in 64-bit mode. 3347 */ 3348 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3349 { 3350 return &env->vfp.zregs[regno].d[0]; 3351 } 3352 3353 /* Shared between translate-sve.c and sve_helper.c. */ 3354 extern const uint64_t pred_esz_masks[4]; 3355 3356 /* Helper for the macros below, validating the argument type. */ 3357 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3358 { 3359 return x; 3360 } 3361 3362 /* 3363 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3364 * Using these should be a bit more self-documenting than using the 3365 * generic target bits directly. 3366 */ 3367 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3368 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3369 3370 /* 3371 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3372 */ 3373 #define PAGE_BTI PAGE_TARGET_1 3374 #define PAGE_MTE PAGE_TARGET_2 3375 3376 #ifdef TARGET_TAGGED_ADDRESSES 3377 /** 3378 * cpu_untagged_addr: 3379 * @cs: CPU context 3380 * @x: tagged address 3381 * 3382 * Remove any address tag from @x. This is explicitly related to the 3383 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3384 * 3385 * There should be a better place to put this, but we need this in 3386 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3387 */ 3388 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3389 { 3390 ARMCPU *cpu = ARM_CPU(cs); 3391 if (cpu->env.tagged_addr_enable) { 3392 /* 3393 * TBI is enabled for userspace but not kernelspace addresses. 3394 * Only clear the tag if bit 55 is clear. 3395 */ 3396 x &= sextract64(x, 0, 56); 3397 } 3398 return x; 3399 } 3400 #endif 3401 3402 /* 3403 * Naming convention for isar_feature functions: 3404 * Functions which test 32-bit ID registers should have _aa32_ in 3405 * their name. Functions which test 64-bit ID registers should have 3406 * _aa64_ in their name. These must only be used in code where we 3407 * know for certain that the CPU has AArch32 or AArch64 respectively 3408 * or where the correct answer for a CPU which doesn't implement that 3409 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3410 * system registers that are specific to that CPU state, for "should 3411 * we let this system register bit be set" tests where the 32-bit 3412 * flavour of the register doesn't have the bit, and so on). 3413 * Functions which simply ask "does this feature exist at all" have 3414 * _any_ in their name, and always return the logical OR of the _aa64_ 3415 * and the _aa32_ function. 3416 */ 3417 3418 /* 3419 * 32-bit feature tests via id registers. 3420 */ 3421 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3422 { 3423 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3424 } 3425 3426 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3427 { 3428 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3429 } 3430 3431 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3432 { 3433 /* (M-profile) low-overhead loops and branch future */ 3434 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3435 } 3436 3437 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3438 { 3439 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3440 } 3441 3442 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3443 { 3444 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3445 } 3446 3447 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3448 { 3449 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3450 } 3451 3452 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3453 { 3454 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3455 } 3456 3457 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3458 { 3459 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3460 } 3461 3462 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3463 { 3464 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3465 } 3466 3467 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3468 { 3469 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3470 } 3471 3472 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3473 { 3474 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3475 } 3476 3477 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3478 { 3479 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3480 } 3481 3482 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3483 { 3484 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3485 } 3486 3487 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3488 { 3489 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3490 } 3491 3492 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3493 { 3494 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3495 } 3496 3497 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3498 { 3499 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3500 } 3501 3502 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3503 { 3504 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3505 } 3506 3507 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3508 { 3509 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3510 } 3511 3512 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3513 { 3514 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3515 } 3516 3517 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3518 { 3519 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3520 } 3521 3522 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3523 { 3524 /* 3525 * Return true if M-profile state handling insns 3526 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3527 */ 3528 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3529 } 3530 3531 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3532 { 3533 /* Sadly this is encoded differently for A-profile and M-profile */ 3534 if (isar_feature_aa32_mprofile(id)) { 3535 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3536 } else { 3537 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3538 } 3539 } 3540 3541 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3542 { 3543 /* 3544 * Return true if MVE is supported (either integer or floating point). 3545 * We must check for M-profile as the MVFR1 field means something 3546 * else for A-profile. 3547 */ 3548 return isar_feature_aa32_mprofile(id) && 3549 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3550 } 3551 3552 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3553 { 3554 /* 3555 * Return true if MVE is supported (either integer or floating point). 3556 * We must check for M-profile as the MVFR1 field means something 3557 * else for A-profile. 3558 */ 3559 return isar_feature_aa32_mprofile(id) && 3560 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3561 } 3562 3563 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3564 { 3565 /* 3566 * Return true if either VFP or SIMD is implemented. 3567 * In this case, a minimum of VFP w/ D0-D15. 3568 */ 3569 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3570 } 3571 3572 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3573 { 3574 /* Return true if D16-D31 are implemented */ 3575 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3576 } 3577 3578 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3579 { 3580 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3581 } 3582 3583 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3584 { 3585 /* Return true if CPU supports single precision floating point, VFPv2 */ 3586 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3587 } 3588 3589 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3590 { 3591 /* Return true if CPU supports single precision floating point, VFPv3 */ 3592 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3593 } 3594 3595 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3596 { 3597 /* Return true if CPU supports double precision floating point, VFPv2 */ 3598 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3599 } 3600 3601 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3602 { 3603 /* Return true if CPU supports double precision floating point, VFPv3 */ 3604 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3605 } 3606 3607 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3608 { 3609 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3610 } 3611 3612 /* 3613 * We always set the FP and SIMD FP16 fields to indicate identical 3614 * levels of support (assuming SIMD is implemented at all), so 3615 * we only need one set of accessors. 3616 */ 3617 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3618 { 3619 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3620 } 3621 3622 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3623 { 3624 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3625 } 3626 3627 /* 3628 * Note that this ID register field covers both VFP and Neon FMAC, 3629 * so should usually be tested in combination with some other 3630 * check that confirms the presence of whichever of VFP or Neon is 3631 * relevant, to avoid accidentally enabling a Neon feature on 3632 * a VFP-no-Neon core or vice-versa. 3633 */ 3634 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3635 { 3636 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3637 } 3638 3639 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3640 { 3641 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3642 } 3643 3644 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3645 { 3646 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3647 } 3648 3649 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3650 { 3651 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3652 } 3653 3654 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3655 { 3656 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3657 } 3658 3659 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3660 { 3661 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3662 } 3663 3664 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3665 { 3666 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3667 } 3668 3669 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3670 { 3671 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3672 } 3673 3674 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3675 { 3676 /* 0xf means "non-standard IMPDEF PMU" */ 3677 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3678 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3679 } 3680 3681 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3682 { 3683 /* 0xf means "non-standard IMPDEF PMU" */ 3684 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3685 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3686 } 3687 3688 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3689 { 3690 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3691 } 3692 3693 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3694 { 3695 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3696 } 3697 3698 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3699 { 3700 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3701 } 3702 3703 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3704 { 3705 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3706 } 3707 3708 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3709 { 3710 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3711 } 3712 3713 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3714 { 3715 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3716 } 3717 3718 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3719 { 3720 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3721 } 3722 3723 /* 3724 * 64-bit feature tests via id registers. 3725 */ 3726 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3727 { 3728 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3729 } 3730 3731 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3732 { 3733 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3734 } 3735 3736 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3737 { 3738 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3739 } 3740 3741 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3742 { 3743 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3744 } 3745 3746 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3747 { 3748 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3749 } 3750 3751 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3752 { 3753 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3754 } 3755 3756 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3757 { 3758 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3759 } 3760 3761 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3762 { 3763 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3764 } 3765 3766 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3767 { 3768 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3769 } 3770 3771 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3772 { 3773 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3774 } 3775 3776 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3777 { 3778 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3779 } 3780 3781 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3782 { 3783 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3784 } 3785 3786 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3787 { 3788 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3789 } 3790 3791 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3792 { 3793 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3794 } 3795 3796 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3797 { 3798 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3799 } 3800 3801 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3802 { 3803 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3804 } 3805 3806 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3807 { 3808 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3809 } 3810 3811 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3812 { 3813 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3814 } 3815 3816 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3817 { 3818 /* 3819 * Return true if any form of pauth is enabled, as this 3820 * predicate controls migration of the 128-bit keys. 3821 */ 3822 return (id->id_aa64isar1 & 3823 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3824 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3825 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3826 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3827 } 3828 3829 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3830 { 3831 /* 3832 * Return true if pauth is enabled with the architected QARMA algorithm. 3833 * QEMU will always set APA+GPA to the same value. 3834 */ 3835 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3836 } 3837 3838 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3839 { 3840 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3841 } 3842 3843 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3844 { 3845 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3846 } 3847 3848 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3849 { 3850 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3851 } 3852 3853 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3854 { 3855 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3856 } 3857 3858 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3859 { 3860 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3861 } 3862 3863 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3864 { 3865 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3866 } 3867 3868 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3869 { 3870 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3871 } 3872 3873 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3874 { 3875 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3876 } 3877 3878 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3879 { 3880 /* We always set the AdvSIMD and FP fields identically. */ 3881 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3882 } 3883 3884 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3885 { 3886 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3887 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3888 } 3889 3890 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3891 { 3892 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3893 } 3894 3895 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3896 { 3897 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3898 } 3899 3900 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3901 { 3902 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3903 } 3904 3905 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3906 { 3907 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3908 } 3909 3910 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3911 { 3912 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3913 } 3914 3915 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3916 { 3917 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3918 } 3919 3920 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3921 { 3922 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3923 } 3924 3925 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3926 { 3927 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3928 } 3929 3930 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3931 { 3932 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3933 } 3934 3935 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3936 { 3937 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3938 } 3939 3940 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3941 { 3942 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3943 } 3944 3945 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 3946 { 3947 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 3948 } 3949 3950 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 3951 { 3952 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 3953 } 3954 3955 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3956 { 3957 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3958 } 3959 3960 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 3961 { 3962 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 3963 } 3964 3965 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 3966 { 3967 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 3968 } 3969 3970 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 3971 { 3972 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3973 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3974 } 3975 3976 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 3977 { 3978 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 3979 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3980 } 3981 3982 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 3983 { 3984 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 3985 } 3986 3987 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 3988 { 3989 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 3990 } 3991 3992 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 3993 { 3994 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 3995 } 3996 3997 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 3998 { 3999 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 4000 } 4001 4002 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 4003 { 4004 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 4005 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 4006 } 4007 4008 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 4009 { 4010 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 4011 } 4012 4013 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 4014 { 4015 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 4016 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 4017 } 4018 4019 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 4020 { 4021 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 4022 } 4023 4024 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4025 { 4026 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4027 } 4028 4029 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4030 { 4031 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4032 } 4033 4034 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4035 { 4036 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4037 } 4038 4039 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4040 { 4041 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4042 if (key >= 2) { 4043 return true; /* FEAT_CSV2_2 */ 4044 } 4045 if (key == 1) { 4046 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4047 return key >= 2; /* FEAT_CSV2_1p2 */ 4048 } 4049 return false; 4050 } 4051 4052 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4053 { 4054 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4055 } 4056 4057 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4058 { 4059 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4060 } 4061 4062 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4063 { 4064 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4065 } 4066 4067 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4068 { 4069 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4070 } 4071 4072 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4073 { 4074 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4075 } 4076 4077 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4078 { 4079 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4080 } 4081 4082 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4083 { 4084 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4085 } 4086 4087 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4088 { 4089 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4090 } 4091 4092 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4093 { 4094 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4095 } 4096 4097 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4098 { 4099 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4100 } 4101 4102 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4103 { 4104 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4105 } 4106 4107 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4108 { 4109 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4110 } 4111 4112 /* 4113 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4114 */ 4115 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4116 { 4117 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4118 } 4119 4120 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4121 { 4122 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4123 } 4124 4125 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4126 { 4127 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4128 } 4129 4130 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4131 { 4132 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4133 } 4134 4135 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4136 { 4137 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4138 } 4139 4140 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4141 { 4142 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4143 } 4144 4145 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4146 { 4147 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4148 } 4149 4150 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4151 { 4152 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4153 } 4154 4155 /* 4156 * Forward to the above feature tests given an ARMCPU pointer. 4157 */ 4158 #define cpu_isar_feature(name, cpu) \ 4159 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4160 4161 #endif 4162