1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/gdbstub.h" 29 #include "exec/page-protection.h" 30 #include "qapi/qapi-types-common.h" 31 #include "target/arm/multiprocessing.h" 32 #include "target/arm/gtimer.h" 33 34 #ifdef TARGET_AARCH64 35 #define KVM_HAVE_MCE_INJECTION 1 36 #endif 37 38 #define EXCP_UDEF 1 /* undefined instruction */ 39 #define EXCP_SWI 2 /* software interrupt */ 40 #define EXCP_PREFETCH_ABORT 3 41 #define EXCP_DATA_ABORT 4 42 #define EXCP_IRQ 5 43 #define EXCP_FIQ 6 44 #define EXCP_BKPT 7 45 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 46 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 47 #define EXCP_HVC 11 /* HyperVisor Call */ 48 #define EXCP_HYP_TRAP 12 49 #define EXCP_SMC 13 /* Secure Monitor Call */ 50 #define EXCP_VIRQ 14 51 #define EXCP_VFIQ 15 52 #define EXCP_SEMIHOST 16 /* semihosting call */ 53 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 54 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 55 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 56 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 57 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 58 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 59 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 60 #define EXCP_VSERR 24 61 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 62 #define EXCP_NMI 26 63 #define EXCP_VINMI 27 64 #define EXCP_VFNMI 28 65 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */ 66 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 67 68 #define ARMV7M_EXCP_RESET 1 69 #define ARMV7M_EXCP_NMI 2 70 #define ARMV7M_EXCP_HARD 3 71 #define ARMV7M_EXCP_MEM 4 72 #define ARMV7M_EXCP_BUS 5 73 #define ARMV7M_EXCP_USAGE 6 74 #define ARMV7M_EXCP_SECURE 7 75 #define ARMV7M_EXCP_SVC 11 76 #define ARMV7M_EXCP_DEBUG 12 77 #define ARMV7M_EXCP_PENDSV 14 78 #define ARMV7M_EXCP_SYSTICK 15 79 80 /* ARM-specific interrupt pending bits. */ 81 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 82 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 83 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 84 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 85 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 86 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 87 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 88 89 /* The usual mapping for an AArch64 system register to its AArch32 90 * counterpart is for the 32 bit world to have access to the lower 91 * half only (with writes leaving the upper half untouched). It's 92 * therefore useful to be able to pass TCG the offset of the least 93 * significant half of a uint64_t struct member. 94 */ 95 #if HOST_BIG_ENDIAN 96 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 97 #define offsetofhigh32(S, M) offsetof(S, M) 98 #else 99 #define offsetoflow32(S, M) offsetof(S, M) 100 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 101 #endif 102 103 /* ARM-specific extra insn start words: 104 * 1: Conditional execution bits 105 * 2: Partial exception syndrome for data aborts 106 */ 107 #define TARGET_INSN_START_EXTRA_WORDS 2 108 109 /* The 2nd extra word holding syndrome info for data aborts does not use 110 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 111 * help the sleb128 encoder do a better job. 112 * When restoring the CPU state, we shift it back up. 113 */ 114 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 115 #define ARM_INSN_START_WORD2_SHIFT 13 116 117 /* We currently assume float and double are IEEE single and double 118 precision respectively. 119 Doing runtime conversions is tricky because VFP registers may contain 120 integer values (eg. as the result of a FTOSI instruction). 121 s<2n> maps to the least significant half of d<n> 122 s<2n+1> maps to the most significant half of d<n> 123 */ 124 125 /** 126 * DynamicGDBFeatureInfo: 127 * @desc: Contains the feature descriptions. 128 * @data: A union with data specific to the set of registers 129 * @cpregs_keys: Array that contains the corresponding Key of 130 * a given cpreg with the same order of the cpreg 131 * in the XML description. 132 */ 133 typedef struct DynamicGDBFeatureInfo { 134 GDBFeature desc; 135 union { 136 struct { 137 uint32_t *keys; 138 } cpregs; 139 } data; 140 } DynamicGDBFeatureInfo; 141 142 /* CPU state for each instance of a generic timer (in cp15 c14) */ 143 typedef struct ARMGenericTimer { 144 uint64_t cval; /* Timer CompareValue register */ 145 uint64_t ctl; /* Timer Control register */ 146 } ARMGenericTimer; 147 148 /* Define a maximum sized vector register. 149 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 150 * For 64-bit, this is a 2048-bit SVE register. 151 * 152 * Note that the mapping between S, D, and Q views of the register bank 153 * differs between AArch64 and AArch32. 154 * In AArch32: 155 * Qn = regs[n].d[1]:regs[n].d[0] 156 * Dn = regs[n / 2].d[n & 1] 157 * Sn = regs[n / 4].d[n % 4 / 2], 158 * bits 31..0 for even n, and bits 63..32 for odd n 159 * (and regs[16] to regs[31] are inaccessible) 160 * In AArch64: 161 * Zn = regs[n].d[*] 162 * Qn = regs[n].d[1]:regs[n].d[0] 163 * Dn = regs[n].d[0] 164 * Sn = regs[n].d[0] bits 31..0 165 * Hn = regs[n].d[0] bits 15..0 166 * 167 * This corresponds to the architecturally defined mapping between 168 * the two execution states, and means we do not need to explicitly 169 * map these registers when changing states. 170 * 171 * Align the data for use with TCG host vector operations. 172 */ 173 174 #ifdef TARGET_AARCH64 175 # define ARM_MAX_VQ 16 176 #else 177 # define ARM_MAX_VQ 1 178 #endif 179 180 typedef struct ARMVectorReg { 181 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 182 } ARMVectorReg; 183 184 #ifdef TARGET_AARCH64 185 /* In AArch32 mode, predicate registers do not exist at all. */ 186 typedef struct ARMPredicateReg { 187 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 188 } ARMPredicateReg; 189 190 /* In AArch32 mode, PAC keys do not exist at all. */ 191 typedef struct ARMPACKey { 192 uint64_t lo, hi; 193 } ARMPACKey; 194 #endif 195 196 /* See the commentary above the TBFLAG field definitions. */ 197 typedef struct CPUARMTBFlags { 198 uint32_t flags; 199 target_ulong flags2; 200 } CPUARMTBFlags; 201 202 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 203 204 typedef struct NVICState NVICState; 205 206 /* 207 * Enum for indexing vfp.fp_status[]. 208 * 209 * FPST_A32: is the "normal" fp status for AArch32 insns 210 * FPST_A64: is the "normal" fp status for AArch64 insns 211 * FPST_A32_F16: used for AArch32 half-precision calculations 212 * FPST_A64_F16: used for AArch64 half-precision calculations 213 * FPST_STD: the ARM "Standard FPSCR Value" 214 * FPST_STD_F16: used for half-precision 215 * calculations with the ARM "Standard FPSCR Value" 216 * FPST_AH: used for the A64 insns which change behaviour 217 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 218 * and the reciprocal and square root estimate/step insns) 219 * FPST_AH_F16: used for the A64 insns which change behaviour 220 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 221 * and the reciprocal and square root estimate/step insns); 222 * for half-precision 223 * 224 * Half-precision operations are governed by a separate 225 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 226 * status structure to control this. 227 * 228 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 229 * round-to-nearest and is used by any operations (generally 230 * Neon) which the architecture defines as controlled by the 231 * standard FPSCR value rather than the FPSCR. 232 * 233 * The "standard FPSCR but for fp16 ops" is needed because 234 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 235 * using a fixed value for it. 236 * 237 * FPST_AH is needed because some insns have different 238 * behaviour when FPCR.AH == 1: they don't update cumulative 239 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and 240 * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, 241 * which means we need an FPST_AH_F16 as well. 242 * 243 * To avoid having to transfer exception bits around, we simply 244 * say that the FPSCR cumulative exception flags are the logical 245 * OR of the flags in the four fp statuses. This relies on the 246 * only thing which needs to read the exception flags being 247 * an explicit FPSCR read. 248 */ 249 typedef enum ARMFPStatusFlavour { 250 FPST_A32, 251 FPST_A64, 252 FPST_A32_F16, 253 FPST_A64_F16, 254 FPST_AH, 255 FPST_AH_F16, 256 FPST_STD, 257 FPST_STD_F16, 258 } ARMFPStatusFlavour; 259 #define FPST_COUNT 8 260 261 typedef struct CPUArchState { 262 /* Regs for current mode. */ 263 uint32_t regs[16]; 264 265 /* 32/64 switch only happens when taking and returning from 266 * exceptions so the overlap semantics are taken care of then 267 * instead of having a complicated union. 268 */ 269 /* Regs for A64 mode. */ 270 uint64_t xregs[32]; 271 uint64_t pc; 272 /* PSTATE isn't an architectural register for ARMv8. However, it is 273 * convenient for us to assemble the underlying state into a 32 bit format 274 * identical to the architectural format used for the SPSR. (This is also 275 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 276 * 'pstate' register are.) Of the PSTATE bits: 277 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 278 * semantics as for AArch32, as described in the comments on each field) 279 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 280 * DAIF (exception masks) are kept in env->daif 281 * BTYPE is kept in env->btype 282 * SM and ZA are kept in env->svcr 283 * all other bits are stored in their correct places in env->pstate 284 */ 285 uint32_t pstate; 286 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 287 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 288 289 /* Cached TBFLAGS state. See below for which bits are included. */ 290 CPUARMTBFlags hflags; 291 292 /* Frequently accessed CPSR bits are stored separately for efficiency. 293 This contains all the other bits. Use cpsr_{read,write} to access 294 the whole CPSR. */ 295 uint32_t uncached_cpsr; 296 uint32_t spsr; 297 298 /* Banked registers. */ 299 uint64_t banked_spsr[8]; 300 uint32_t banked_r13[8]; 301 uint32_t banked_r14[8]; 302 303 /* These hold r8-r12. */ 304 uint32_t usr_regs[5]; 305 uint32_t fiq_regs[5]; 306 307 /* cpsr flag cache for faster execution */ 308 uint32_t CF; /* 0 or 1 */ 309 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 310 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 311 uint32_t ZF; /* Z set if zero. */ 312 uint32_t QF; /* 0 or 1 */ 313 uint32_t GE; /* cpsr[19:16] */ 314 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 315 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 316 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 317 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 318 319 uint64_t elr_el[4]; /* AArch64 exception link regs */ 320 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 321 322 /* System control coprocessor (cp15) */ 323 struct { 324 uint32_t c0_cpuid; 325 union { /* Cache size selection */ 326 struct { 327 uint64_t _unused_csselr0; 328 uint64_t csselr_ns; 329 uint64_t _unused_csselr1; 330 uint64_t csselr_s; 331 }; 332 uint64_t csselr_el[4]; 333 }; 334 union { /* System control register. */ 335 struct { 336 uint64_t _unused_sctlr; 337 uint64_t sctlr_ns; 338 uint64_t hsctlr; 339 uint64_t sctlr_s; 340 }; 341 uint64_t sctlr_el[4]; 342 }; 343 uint64_t vsctlr; /* Virtualization System control register. */ 344 uint64_t cpacr_el1; /* Architectural feature access control register */ 345 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 346 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 347 uint64_t sder; /* Secure debug enable register. */ 348 uint32_t nsacr; /* Non-secure access control register. */ 349 union { /* MMU translation table base 0. */ 350 struct { 351 uint64_t _unused_ttbr0_0; 352 uint64_t ttbr0_ns; 353 uint64_t _unused_ttbr0_1; 354 uint64_t ttbr0_s; 355 }; 356 uint64_t ttbr0_el[4]; 357 }; 358 union { /* MMU translation table base 1. */ 359 struct { 360 uint64_t _unused_ttbr1_0; 361 uint64_t ttbr1_ns; 362 uint64_t _unused_ttbr1_1; 363 uint64_t ttbr1_s; 364 }; 365 uint64_t ttbr1_el[4]; 366 }; 367 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 368 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 369 /* MMU translation table base control. */ 370 uint64_t tcr_el[4]; 371 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 372 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 373 uint32_t c2_data; /* MPU data cacheable bits. */ 374 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 375 union { /* MMU domain access control register 376 * MPU write buffer control. 377 */ 378 struct { 379 uint64_t dacr_ns; 380 uint64_t dacr_s; 381 }; 382 struct { 383 uint64_t dacr32_el2; 384 }; 385 }; 386 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 387 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 388 uint64_t hcr_el2; /* Hypervisor configuration register */ 389 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 390 uint64_t scr_el3; /* Secure configuration register. */ 391 union { /* Fault status registers. */ 392 struct { 393 uint64_t ifsr_ns; 394 uint64_t ifsr_s; 395 }; 396 struct { 397 uint64_t ifsr32_el2; 398 }; 399 }; 400 union { 401 struct { 402 uint64_t _unused_dfsr; 403 uint64_t dfsr_ns; 404 uint64_t hsr; 405 uint64_t dfsr_s; 406 }; 407 uint64_t esr_el[4]; 408 }; 409 uint32_t c6_region[8]; /* MPU base/size registers. */ 410 union { /* Fault address registers. */ 411 struct { 412 uint64_t _unused_far0; 413 #if HOST_BIG_ENDIAN 414 uint32_t ifar_ns; 415 uint32_t dfar_ns; 416 uint32_t ifar_s; 417 uint32_t dfar_s; 418 #else 419 uint32_t dfar_ns; 420 uint32_t ifar_ns; 421 uint32_t dfar_s; 422 uint32_t ifar_s; 423 #endif 424 uint64_t _unused_far3; 425 }; 426 uint64_t far_el[4]; 427 }; 428 uint64_t hpfar_el2; 429 uint64_t hstr_el2; 430 union { /* Translation result. */ 431 struct { 432 uint64_t _unused_par_0; 433 uint64_t par_ns; 434 uint64_t _unused_par_1; 435 uint64_t par_s; 436 }; 437 uint64_t par_el[4]; 438 }; 439 440 uint32_t c9_insn; /* Cache lockdown registers. */ 441 uint32_t c9_data; 442 uint64_t c9_pmcr; /* performance monitor control register */ 443 uint64_t c9_pmcnten; /* perf monitor counter enables */ 444 uint64_t c9_pmovsr; /* perf monitor overflow status */ 445 uint64_t c9_pmuserenr; /* perf monitor user enable */ 446 uint64_t c9_pmselr; /* perf monitor counter selection register */ 447 uint64_t c9_pminten; /* perf monitor interrupt enables */ 448 union { /* Memory attribute redirection */ 449 struct { 450 #if HOST_BIG_ENDIAN 451 uint64_t _unused_mair_0; 452 uint32_t mair1_ns; 453 uint32_t mair0_ns; 454 uint64_t _unused_mair_1; 455 uint32_t mair1_s; 456 uint32_t mair0_s; 457 #else 458 uint64_t _unused_mair_0; 459 uint32_t mair0_ns; 460 uint32_t mair1_ns; 461 uint64_t _unused_mair_1; 462 uint32_t mair0_s; 463 uint32_t mair1_s; 464 #endif 465 }; 466 uint64_t mair_el[4]; 467 }; 468 union { /* vector base address register */ 469 struct { 470 uint64_t _unused_vbar; 471 uint64_t vbar_ns; 472 uint64_t hvbar; 473 uint64_t vbar_s; 474 }; 475 uint64_t vbar_el[4]; 476 }; 477 uint32_t mvbar; /* (monitor) vector base address register */ 478 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 479 struct { /* FCSE PID. */ 480 uint32_t fcseidr_ns; 481 uint32_t fcseidr_s; 482 }; 483 union { /* Context ID. */ 484 struct { 485 uint64_t _unused_contextidr_0; 486 uint64_t contextidr_ns; 487 uint64_t _unused_contextidr_1; 488 uint64_t contextidr_s; 489 }; 490 uint64_t contextidr_el[4]; 491 }; 492 union { /* User RW Thread register. */ 493 struct { 494 uint64_t tpidrurw_ns; 495 uint64_t tpidrprw_ns; 496 uint64_t htpidr; 497 uint64_t _tpidr_el3; 498 }; 499 uint64_t tpidr_el[4]; 500 }; 501 uint64_t tpidr2_el0; 502 /* The secure banks of these registers don't map anywhere */ 503 uint64_t tpidrurw_s; 504 uint64_t tpidrprw_s; 505 uint64_t tpidruro_s; 506 507 union { /* User RO Thread register. */ 508 uint64_t tpidruro_ns; 509 uint64_t tpidrro_el[1]; 510 }; 511 uint64_t c14_cntfrq; /* Counter Frequency register */ 512 uint64_t c14_cntkctl; /* Timer Control register */ 513 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 514 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 515 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 516 ARMGenericTimer c14_timer[NUM_GTIMERS]; 517 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 518 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 519 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 520 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 521 uint32_t c15_threadid; /* TI debugger thread-ID. */ 522 uint32_t c15_config_base_address; /* SCU base address. */ 523 uint32_t c15_diagnostic; /* diagnostic register */ 524 uint32_t c15_power_diagnostic; 525 uint32_t c15_power_control; /* power control */ 526 uint64_t dbgbvr[16]; /* breakpoint value registers */ 527 uint64_t dbgbcr[16]; /* breakpoint control registers */ 528 uint64_t dbgwvr[16]; /* watchpoint value registers */ 529 uint64_t dbgwcr[16]; /* watchpoint control registers */ 530 uint64_t dbgclaim; /* DBGCLAIM bits */ 531 uint64_t mdscr_el1; 532 uint64_t oslsr_el1; /* OS Lock Status */ 533 uint64_t osdlr_el1; /* OS DoubleLock status */ 534 uint64_t mdcr_el2; 535 uint64_t mdcr_el3; 536 /* Stores the architectural value of the counter *the last time it was 537 * updated* by pmccntr_op_start. Accesses should always be surrounded 538 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 539 * architecturally-correct value is being read/set. 540 */ 541 uint64_t c15_ccnt; 542 /* Stores the delta between the architectural value and the underlying 543 * cycle count during normal operation. It is used to update c15_ccnt 544 * to be the correct architectural value before accesses. During 545 * accesses, c15_ccnt_delta contains the underlying count being used 546 * for the access, after which it reverts to the delta value in 547 * pmccntr_op_finish. 548 */ 549 uint64_t c15_ccnt_delta; 550 uint64_t c14_pmevcntr[31]; 551 uint64_t c14_pmevcntr_delta[31]; 552 uint64_t c14_pmevtyper[31]; 553 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 554 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 555 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 556 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 557 uint64_t gcr_el1; 558 uint64_t rgsr_el1; 559 560 /* Minimal RAS registers */ 561 uint64_t disr_el1; 562 uint64_t vdisr_el2; 563 uint64_t vsesr_el2; 564 565 /* 566 * Fine-Grained Trap registers. We store these as arrays so the 567 * access checking code doesn't have to manually select 568 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 569 * FEAT_FGT2 will add more elements to these arrays. 570 */ 571 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 572 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 573 uint64_t fgt_exec[1]; /* HFGITR */ 574 575 /* RME registers */ 576 uint64_t gpccr_el3; 577 uint64_t gptbr_el3; 578 uint64_t mfar_el3; 579 580 /* NV2 register */ 581 uint64_t vncr_el2; 582 } cp15; 583 584 struct { 585 /* M profile has up to 4 stack pointers: 586 * a Main Stack Pointer and a Process Stack Pointer for each 587 * of the Secure and Non-Secure states. (If the CPU doesn't support 588 * the security extension then it has only two SPs.) 589 * In QEMU we always store the currently active SP in regs[13], 590 * and the non-active SP for the current security state in 591 * v7m.other_sp. The stack pointers for the inactive security state 592 * are stored in other_ss_msp and other_ss_psp. 593 * switch_v7m_security_state() is responsible for rearranging them 594 * when we change security state. 595 */ 596 uint32_t other_sp; 597 uint32_t other_ss_msp; 598 uint32_t other_ss_psp; 599 uint32_t vecbase[M_REG_NUM_BANKS]; 600 uint32_t basepri[M_REG_NUM_BANKS]; 601 uint32_t control[M_REG_NUM_BANKS]; 602 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 603 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 604 uint32_t hfsr; /* HardFault Status */ 605 uint32_t dfsr; /* Debug Fault Status Register */ 606 uint32_t sfsr; /* Secure Fault Status Register */ 607 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 608 uint32_t bfar; /* BusFault Address */ 609 uint32_t sfar; /* Secure Fault Address Register */ 610 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 611 int exception; 612 uint32_t primask[M_REG_NUM_BANKS]; 613 uint32_t faultmask[M_REG_NUM_BANKS]; 614 uint32_t aircr; /* only holds r/w state if security extn implemented */ 615 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 616 uint32_t csselr[M_REG_NUM_BANKS]; 617 uint32_t scr[M_REG_NUM_BANKS]; 618 uint32_t msplim[M_REG_NUM_BANKS]; 619 uint32_t psplim[M_REG_NUM_BANKS]; 620 uint32_t fpcar[M_REG_NUM_BANKS]; 621 uint32_t fpccr[M_REG_NUM_BANKS]; 622 uint32_t fpdscr[M_REG_NUM_BANKS]; 623 uint32_t cpacr[M_REG_NUM_BANKS]; 624 uint32_t nsacr; 625 uint32_t ltpsize; 626 uint32_t vpr; 627 } v7m; 628 629 /* Information associated with an exception about to be taken: 630 * code which raises an exception must set cs->exception_index and 631 * the relevant parts of this structure; the cpu_do_interrupt function 632 * will then set the guest-visible registers as part of the exception 633 * entry process. 634 */ 635 struct { 636 uint32_t syndrome; /* AArch64 format syndrome register */ 637 uint32_t fsr; /* AArch32 format fault status register info */ 638 uint64_t vaddress; /* virtual addr associated with exception, if any */ 639 uint32_t target_el; /* EL the exception should be targeted for */ 640 /* If we implement EL2 we will also need to store information 641 * about the intermediate physical address for stage 2 faults. 642 */ 643 } exception; 644 645 /* Information associated with an SError */ 646 struct { 647 uint8_t pending; 648 uint8_t has_esr; 649 uint64_t esr; 650 } serror; 651 652 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 653 654 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 655 uint32_t irq_line_state; 656 657 /* Thumb-2 EE state. */ 658 uint32_t teecr; 659 uint32_t teehbr; 660 661 /* VFP coprocessor state. */ 662 struct { 663 ARMVectorReg zregs[32]; 664 665 #ifdef TARGET_AARCH64 666 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 667 #define FFR_PRED_NUM 16 668 ARMPredicateReg pregs[17]; 669 /* Scratch space for aa64 sve predicate temporary. */ 670 ARMPredicateReg preg_tmp; 671 #endif 672 673 /* We store these fpcsr fields separately for convenience. */ 674 uint32_t qc[4] QEMU_ALIGNED(16); 675 int vec_len; 676 int vec_stride; 677 678 /* 679 * Floating point status and control registers. Some bits are 680 * stored separately in other fields or in the float_status below. 681 */ 682 uint64_t fpsr; 683 uint64_t fpcr; 684 685 uint32_t xregs[16]; 686 687 /* Scratch space for aa32 neon expansion. */ 688 uint32_t scratch[8]; 689 690 /* There are a number of distinct float control structures. */ 691 float_status fp_status[FPST_COUNT]; 692 693 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 694 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 695 } vfp; 696 697 uint64_t exclusive_addr; 698 uint64_t exclusive_val; 699 /* 700 * Contains the 'val' for the second 64-bit register of LDXP, which comes 701 * from the higher address, not the high part of a complete 128-bit value. 702 * In some ways it might be more convenient to record the exclusive value 703 * as the low and high halves of a 128 bit data value, but the current 704 * semantics of these fields are baked into the migration format. 705 */ 706 uint64_t exclusive_high; 707 708 /* iwMMXt coprocessor state. */ 709 struct { 710 uint64_t regs[16]; 711 uint64_t val; 712 713 uint32_t cregs[16]; 714 } iwmmxt; 715 716 #ifdef TARGET_AARCH64 717 struct { 718 ARMPACKey apia; 719 ARMPACKey apib; 720 ARMPACKey apda; 721 ARMPACKey apdb; 722 ARMPACKey apga; 723 } keys; 724 725 uint64_t scxtnum_el[4]; 726 727 /* 728 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 729 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 730 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 731 * When SVL is less than the architectural maximum, the accessible 732 * storage is restricted, such that if the SVL is X bytes the guest can 733 * see only the bottom X elements of zarray[], and only the least 734 * significant X bytes of each element of the array. (In other words, 735 * the observable part is always square.) 736 * 737 * The ZA storage can also be considered as a set of square tiles of 738 * elements of different sizes. The mapping from tiles to the ZA array 739 * is architecturally defined, such that for tiles of elements of esz 740 * bytes, the Nth row (or "horizontal slice") of tile T is in 741 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 742 * in the ZA storage, because its rows are striped through the ZA array. 743 * 744 * Because this is so large, keep this toward the end of the reset area, 745 * to keep the offsets into the rest of the structure smaller. 746 */ 747 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 748 #endif 749 750 struct CPUBreakpoint *cpu_breakpoint[16]; 751 struct CPUWatchpoint *cpu_watchpoint[16]; 752 753 /* Optional fault info across tlb lookup. */ 754 ARMMMUFaultInfo *tlb_fi; 755 756 /* Fields up to this point are cleared by a CPU reset */ 757 struct {} end_reset_fields; 758 759 /* Fields after this point are preserved across CPU reset. */ 760 761 /* Internal CPU feature flags. */ 762 uint64_t features; 763 764 /* PMSAv7 MPU */ 765 struct { 766 uint32_t *drbar; 767 uint32_t *drsr; 768 uint32_t *dracr; 769 uint32_t rnr[M_REG_NUM_BANKS]; 770 } pmsav7; 771 772 /* PMSAv8 MPU */ 773 struct { 774 /* The PMSAv8 implementation also shares some PMSAv7 config 775 * and state: 776 * pmsav7.rnr (region number register) 777 * pmsav7_dregion (number of configured regions) 778 */ 779 uint32_t *rbar[M_REG_NUM_BANKS]; 780 uint32_t *rlar[M_REG_NUM_BANKS]; 781 uint32_t *hprbar; 782 uint32_t *hprlar; 783 uint32_t mair0[M_REG_NUM_BANKS]; 784 uint32_t mair1[M_REG_NUM_BANKS]; 785 uint32_t hprselr; 786 } pmsav8; 787 788 /* v8M SAU */ 789 struct { 790 uint32_t *rbar; 791 uint32_t *rlar; 792 uint32_t rnr; 793 uint32_t ctrl; 794 } sau; 795 796 #if !defined(CONFIG_USER_ONLY) 797 NVICState *nvic; 798 const struct arm_boot_info *boot_info; 799 /* Store GICv3CPUState to access from this struct */ 800 void *gicv3state; 801 #else /* CONFIG_USER_ONLY */ 802 /* For usermode syscall translation. */ 803 bool eabi; 804 #endif /* CONFIG_USER_ONLY */ 805 806 #ifdef TARGET_TAGGED_ADDRESSES 807 /* Linux syscall tagged address support */ 808 bool tagged_addr_enable; 809 #endif 810 } CPUARMState; 811 812 static inline void set_feature(CPUARMState *env, int feature) 813 { 814 env->features |= 1ULL << feature; 815 } 816 817 static inline void unset_feature(CPUARMState *env, int feature) 818 { 819 env->features &= ~(1ULL << feature); 820 } 821 822 /** 823 * ARMELChangeHookFn: 824 * type of a function which can be registered via arm_register_el_change_hook() 825 * to get callbacks when the CPU changes its exception level or mode. 826 */ 827 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 828 typedef struct ARMELChangeHook ARMELChangeHook; 829 struct ARMELChangeHook { 830 ARMELChangeHookFn *hook; 831 void *opaque; 832 QLIST_ENTRY(ARMELChangeHook) node; 833 }; 834 835 /* These values map onto the return values for 836 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 837 typedef enum ARMPSCIState { 838 PSCI_ON = 0, 839 PSCI_OFF = 1, 840 PSCI_ON_PENDING = 2 841 } ARMPSCIState; 842 843 typedef struct ARMISARegisters ARMISARegisters; 844 845 /* 846 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 847 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 848 * 849 * While processing properties during initialization, corresponding init bits 850 * are set for bits in sve_vq_map that have been set by properties. 851 * 852 * Bits set in supported represent valid vector lengths for the CPU type. 853 */ 854 typedef struct { 855 uint32_t map, init, supported; 856 } ARMVQMap; 857 858 /** 859 * ARMCPU: 860 * @env: #CPUARMState 861 * 862 * An ARM CPU core. 863 */ 864 struct ArchCPU { 865 CPUState parent_obj; 866 867 CPUARMState env; 868 869 /* Coprocessor information */ 870 GHashTable *cp_regs; 871 /* For marshalling (mostly coprocessor) register state between the 872 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 873 * we use these arrays. 874 */ 875 /* List of register indexes managed via these arrays; (full KVM style 876 * 64 bit indexes, not CPRegInfo 32 bit indexes) 877 */ 878 uint64_t *cpreg_indexes; 879 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 880 uint64_t *cpreg_values; 881 /* Length of the indexes, values, reset_values arrays */ 882 int32_t cpreg_array_len; 883 /* These are used only for migration: incoming data arrives in 884 * these fields and is sanity checked in post_load before copying 885 * to the working data structures above. 886 */ 887 uint64_t *cpreg_vmstate_indexes; 888 uint64_t *cpreg_vmstate_values; 889 int32_t cpreg_vmstate_array_len; 890 891 DynamicGDBFeatureInfo dyn_sysreg_feature; 892 DynamicGDBFeatureInfo dyn_svereg_feature; 893 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 894 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 895 896 /* Timers used by the generic (architected) timer */ 897 QEMUTimer *gt_timer[NUM_GTIMERS]; 898 /* 899 * Timer used by the PMU. Its state is restored after migration by 900 * pmu_op_finish() - it does not need other handling during migration 901 */ 902 QEMUTimer *pmu_timer; 903 /* Timer used for WFxT timeouts */ 904 QEMUTimer *wfxt_timer; 905 906 /* GPIO outputs for generic timer */ 907 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 908 /* GPIO output for GICv3 maintenance interrupt signal */ 909 qemu_irq gicv3_maintenance_interrupt; 910 /* GPIO output for the PMU interrupt */ 911 qemu_irq pmu_interrupt; 912 913 /* MemoryRegion to use for secure physical accesses */ 914 MemoryRegion *secure_memory; 915 916 /* MemoryRegion to use for allocation tag accesses */ 917 MemoryRegion *tag_memory; 918 MemoryRegion *secure_tag_memory; 919 920 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 921 Object *idau; 922 923 /* 'compatible' string for this CPU for Linux device trees */ 924 const char *dtb_compatible; 925 926 /* PSCI version for this CPU 927 * Bits[31:16] = Major Version 928 * Bits[15:0] = Minor Version 929 */ 930 uint32_t psci_version; 931 932 /* Current power state, access guarded by BQL */ 933 ARMPSCIState power_state; 934 935 /* CPU has virtualization extension */ 936 bool has_el2; 937 /* CPU has security extension */ 938 bool has_el3; 939 /* CPU has PMU (Performance Monitor Unit) */ 940 bool has_pmu; 941 /* CPU has VFP */ 942 bool has_vfp; 943 /* CPU has 32 VFP registers */ 944 bool has_vfp_d32; 945 /* CPU has Neon */ 946 bool has_neon; 947 /* CPU has M-profile DSP extension */ 948 bool has_dsp; 949 950 /* CPU has memory protection unit */ 951 bool has_mpu; 952 /* CPU has MTE enabled in KVM mode */ 953 bool kvm_mte; 954 /* PMSAv7 MPU number of supported regions */ 955 uint32_t pmsav7_dregion; 956 /* PMSAv8 MPU number of supported hyp regions */ 957 uint32_t pmsav8r_hdregion; 958 /* v8M SAU number of supported regions */ 959 uint32_t sau_sregion; 960 961 /* PSCI conduit used to invoke PSCI methods 962 * 0 - disabled, 1 - smc, 2 - hvc 963 */ 964 uint32_t psci_conduit; 965 966 /* For v8M, initial value of the Secure VTOR */ 967 uint32_t init_svtor; 968 /* For v8M, initial value of the Non-secure VTOR */ 969 uint32_t init_nsvtor; 970 971 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 972 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 973 */ 974 uint32_t kvm_target; 975 976 #ifdef CONFIG_KVM 977 /* KVM init features for this CPU */ 978 uint32_t kvm_init_features[7]; 979 980 /* KVM CPU state */ 981 982 /* KVM virtual time adjustment */ 983 bool kvm_adjvtime; 984 bool kvm_vtime_dirty; 985 uint64_t kvm_vtime; 986 987 /* KVM steal time */ 988 OnOffAuto kvm_steal_time; 989 #endif /* CONFIG_KVM */ 990 991 /* Uniprocessor system with MP extensions */ 992 bool mp_is_up; 993 994 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 995 * and the probe failed (so we need to report the error in realize) 996 */ 997 bool host_cpu_probe_failed; 998 999 /* QOM property to indicate we should use the back-compat CNTFRQ default */ 1000 bool backcompat_cntfrq; 1001 1002 /* QOM property to indicate we should use the back-compat QARMA5 default */ 1003 bool backcompat_pauth_default_use_qarma5; 1004 1005 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 1006 * register. 1007 */ 1008 int32_t core_count; 1009 1010 /* The instance init functions for implementation-specific subclasses 1011 * set these fields to specify the implementation-dependent values of 1012 * various constant registers and reset values of non-constant 1013 * registers. 1014 * Some of these might become QOM properties eventually. 1015 * Field names match the official register names as defined in the 1016 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 1017 * is used for reset values of non-constant registers; no reset_ 1018 * prefix means a constant register. 1019 * Some of these registers are split out into a substructure that 1020 * is shared with the translators to control the ISA. 1021 * 1022 * Note that if you add an ID register to the ARMISARegisters struct 1023 * you need to also update the 32-bit and 64-bit versions of the 1024 * kvm_arm_get_host_cpu_features() function to correctly populate the 1025 * field by reading the value from the KVM vCPU. 1026 */ 1027 struct ARMISARegisters { 1028 uint32_t id_isar0; 1029 uint32_t id_isar1; 1030 uint32_t id_isar2; 1031 uint32_t id_isar3; 1032 uint32_t id_isar4; 1033 uint32_t id_isar5; 1034 uint32_t id_isar6; 1035 uint32_t id_mmfr0; 1036 uint32_t id_mmfr1; 1037 uint32_t id_mmfr2; 1038 uint32_t id_mmfr3; 1039 uint32_t id_mmfr4; 1040 uint32_t id_mmfr5; 1041 uint32_t id_pfr0; 1042 uint32_t id_pfr1; 1043 uint32_t id_pfr2; 1044 uint32_t mvfr0; 1045 uint32_t mvfr1; 1046 uint32_t mvfr2; 1047 uint32_t id_dfr0; 1048 uint32_t id_dfr1; 1049 uint32_t dbgdidr; 1050 uint32_t dbgdevid; 1051 uint32_t dbgdevid1; 1052 uint64_t id_aa64isar0; 1053 uint64_t id_aa64isar1; 1054 uint64_t id_aa64isar2; 1055 uint64_t id_aa64pfr0; 1056 uint64_t id_aa64pfr1; 1057 uint64_t id_aa64mmfr0; 1058 uint64_t id_aa64mmfr1; 1059 uint64_t id_aa64mmfr2; 1060 uint64_t id_aa64mmfr3; 1061 uint64_t id_aa64dfr0; 1062 uint64_t id_aa64dfr1; 1063 uint64_t id_aa64zfr0; 1064 uint64_t id_aa64smfr0; 1065 uint64_t reset_pmcr_el0; 1066 } isar; 1067 uint64_t midr; 1068 uint32_t revidr; 1069 uint32_t reset_fpsid; 1070 uint64_t ctr; 1071 uint32_t reset_sctlr; 1072 uint64_t pmceid0; 1073 uint64_t pmceid1; 1074 uint32_t id_afr0; 1075 uint64_t id_aa64afr0; 1076 uint64_t id_aa64afr1; 1077 uint64_t clidr; 1078 uint64_t mp_affinity; /* MP ID without feature bits */ 1079 /* The elements of this array are the CCSIDR values for each cache, 1080 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1081 */ 1082 uint64_t ccsidr[16]; 1083 uint64_t reset_cbar; 1084 uint32_t reset_auxcr; 1085 bool reset_hivecs; 1086 uint8_t reset_l0gptsz; 1087 1088 /* 1089 * Intermediate values used during property parsing. 1090 * Once finalized, the values should be read from ID_AA64*. 1091 */ 1092 bool prop_pauth; 1093 bool prop_pauth_impdef; 1094 bool prop_pauth_qarma3; 1095 bool prop_pauth_qarma5; 1096 bool prop_lpa2; 1097 1098 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1099 uint8_t dcz_blocksize; 1100 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1101 uint8_t gm_blocksize; 1102 1103 uint64_t rvbar_prop; /* Property/input signals. */ 1104 1105 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1106 int gic_num_lrs; /* number of list registers */ 1107 int gic_vpribits; /* number of virtual priority bits */ 1108 int gic_vprebits; /* number of virtual preemption bits */ 1109 int gic_pribits; /* number of physical priority bits */ 1110 1111 /* Whether the cfgend input is high (i.e. this CPU should reset into 1112 * big-endian mode). This setting isn't used directly: instead it modifies 1113 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1114 * architecture version. 1115 */ 1116 bool cfgend; 1117 1118 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1119 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1120 1121 int32_t node_id; /* NUMA node this CPU belongs to */ 1122 1123 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1124 uint8_t device_irq_level; 1125 1126 /* Used to set the maximum vector length the cpu will support. */ 1127 uint32_t sve_max_vq; 1128 1129 #ifdef CONFIG_USER_ONLY 1130 /* Used to set the default vector length at process start. */ 1131 uint32_t sve_default_vq; 1132 uint32_t sme_default_vq; 1133 #endif 1134 1135 ARMVQMap sve_vq; 1136 ARMVQMap sme_vq; 1137 1138 /* Generic timer counter frequency, in Hz */ 1139 uint64_t gt_cntfrq_hz; 1140 }; 1141 1142 typedef struct ARMCPUInfo { 1143 const char *name; 1144 const char *deprecation_note; 1145 void (*initfn)(Object *obj); 1146 void (*class_init)(ObjectClass *oc, void *data); 1147 } ARMCPUInfo; 1148 1149 /** 1150 * ARMCPUClass: 1151 * @parent_realize: The parent class' realize handler. 1152 * @parent_phases: The parent class' reset phase handlers. 1153 * 1154 * An ARM CPU model. 1155 */ 1156 struct ARMCPUClass { 1157 CPUClass parent_class; 1158 1159 const ARMCPUInfo *info; 1160 DeviceRealize parent_realize; 1161 ResettablePhases parent_phases; 1162 }; 1163 1164 struct AArch64CPUClass { 1165 ARMCPUClass parent_class; 1166 }; 1167 1168 /* Callback functions for the generic timer's timers. */ 1169 void arm_gt_ptimer_cb(void *opaque); 1170 void arm_gt_vtimer_cb(void *opaque); 1171 void arm_gt_htimer_cb(void *opaque); 1172 void arm_gt_stimer_cb(void *opaque); 1173 void arm_gt_hvtimer_cb(void *opaque); 1174 1175 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1176 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1177 1178 void arm_cpu_post_init(Object *obj); 1179 1180 #define ARM_AFF0_SHIFT 0 1181 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1182 #define ARM_AFF1_SHIFT 8 1183 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1184 #define ARM_AFF2_SHIFT 16 1185 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1186 #define ARM_AFF3_SHIFT 32 1187 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1188 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1189 1190 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1191 #define ARM64_AFFINITY_MASK \ 1192 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1193 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1194 1195 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1196 1197 #ifndef CONFIG_USER_ONLY 1198 extern const VMStateDescription vmstate_arm_cpu; 1199 1200 void arm_cpu_do_interrupt(CPUState *cpu); 1201 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1202 1203 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1204 MemTxAttrs *attrs); 1205 #endif /* !CONFIG_USER_ONLY */ 1206 1207 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1208 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1209 1210 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1211 int cpuid, DumpState *s); 1212 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1213 int cpuid, DumpState *s); 1214 1215 /** 1216 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1217 * @cpu: CPU (which must have been freshly reset) 1218 * @target_el: exception level to put the CPU into 1219 * @secure: whether to put the CPU in secure state 1220 * 1221 * When QEMU is directly running a guest kernel at a lower level than 1222 * EL3 it implicitly emulates some aspects of the guest firmware. 1223 * This includes that on reset we need to configure the parts of the 1224 * CPU corresponding to EL3 so that the real guest code can run at its 1225 * lower exception level. This function does that post-reset CPU setup, 1226 * for when we do direct boot of a guest kernel, and for when we 1227 * emulate PSCI and similar firmware interfaces starting a CPU at a 1228 * lower exception level. 1229 * 1230 * @target_el must be an EL implemented by the CPU between 1 and 3. 1231 * We do not support dropping into a Secure EL other than 3. 1232 * 1233 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1234 */ 1235 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1236 1237 #ifdef TARGET_AARCH64 1238 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1239 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1240 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1241 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1242 int new_el, bool el0_a64); 1243 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1244 1245 /* 1246 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1247 * The byte at offset i from the start of the in-memory representation contains 1248 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1249 * lowest offsets are stored in the lowest memory addresses, then that nearly 1250 * matches QEMU's representation, which is to use an array of host-endian 1251 * uint64_t's, where the lower offsets are at the lower indices. To complete 1252 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1253 */ 1254 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1255 { 1256 #if HOST_BIG_ENDIAN 1257 int i; 1258 1259 for (i = 0; i < nr; ++i) { 1260 dst[i] = bswap64(src[i]); 1261 } 1262 1263 return dst; 1264 #else 1265 return src; 1266 #endif 1267 } 1268 1269 #else 1270 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1271 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1272 int n, bool a) 1273 { } 1274 #endif 1275 1276 void aarch64_sync_32_to_64(CPUARMState *env); 1277 void aarch64_sync_64_to_32(CPUARMState *env); 1278 1279 int fp_exception_el(CPUARMState *env, int cur_el); 1280 int sve_exception_el(CPUARMState *env, int cur_el); 1281 int sme_exception_el(CPUARMState *env, int cur_el); 1282 1283 /** 1284 * sve_vqm1_for_el_sm: 1285 * @env: CPUARMState 1286 * @el: exception level 1287 * @sm: streaming mode 1288 * 1289 * Compute the current vector length for @el & @sm, in units of 1290 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1291 * If @sm, compute for SVL, otherwise NVL. 1292 */ 1293 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1294 1295 /* Likewise, but using @sm = PSTATE.SM. */ 1296 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1297 1298 static inline bool is_a64(CPUARMState *env) 1299 { 1300 return env->aarch64; 1301 } 1302 1303 /** 1304 * pmu_op_start/finish 1305 * @env: CPUARMState 1306 * 1307 * Convert all PMU counters between their delta form (the typical mode when 1308 * they are enabled) and the guest-visible values. These two calls must 1309 * surround any action which might affect the counters. 1310 */ 1311 void pmu_op_start(CPUARMState *env); 1312 void pmu_op_finish(CPUARMState *env); 1313 1314 /* 1315 * Called when a PMU counter is due to overflow 1316 */ 1317 void arm_pmu_timer_cb(void *opaque); 1318 1319 /** 1320 * Functions to register as EL change hooks for PMU mode filtering 1321 */ 1322 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1323 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1324 1325 /* 1326 * pmu_init 1327 * @cpu: ARMCPU 1328 * 1329 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1330 * for the current configuration 1331 */ 1332 void pmu_init(ARMCPU *cpu); 1333 1334 /* SCTLR bit meanings. Several bits have been reused in newer 1335 * versions of the architecture; in that case we define constants 1336 * for both old and new bit meanings. Code which tests against those 1337 * bits should probably check or otherwise arrange that the CPU 1338 * is the architectural version it expects. 1339 */ 1340 #define SCTLR_M (1U << 0) 1341 #define SCTLR_A (1U << 1) 1342 #define SCTLR_C (1U << 2) 1343 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1344 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1345 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1346 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1347 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1348 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1349 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1350 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1351 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1352 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1353 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1354 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1355 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1356 #define SCTLR_SED (1U << 8) /* v8 onward */ 1357 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1358 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1359 #define SCTLR_F (1U << 10) /* up to v6 */ 1360 #define SCTLR_SW (1U << 10) /* v7 */ 1361 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1362 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1363 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1364 #define SCTLR_I (1U << 12) 1365 #define SCTLR_V (1U << 13) /* AArch32 only */ 1366 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1367 #define SCTLR_RR (1U << 14) /* up to v7 */ 1368 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1369 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1370 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1371 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1372 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1373 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1374 #define SCTLR_BR (1U << 17) /* PMSA only */ 1375 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1376 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1377 #define SCTLR_WXN (1U << 19) 1378 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1379 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1380 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1381 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1382 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1383 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1384 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1385 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1386 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1387 #define SCTLR_VE (1U << 24) /* up to v7 */ 1388 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1389 #define SCTLR_EE (1U << 25) 1390 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1391 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1392 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1393 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1394 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1395 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1396 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1397 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1398 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1399 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1400 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1401 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1402 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */ 1403 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1404 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1405 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1406 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1407 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1408 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1409 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1410 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1411 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1412 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1413 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1414 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1415 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1416 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1417 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1418 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1419 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1420 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1421 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1422 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1423 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1424 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1425 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1426 1427 #define CPSR_M (0x1fU) 1428 #define CPSR_T (1U << 5) 1429 #define CPSR_F (1U << 6) 1430 #define CPSR_I (1U << 7) 1431 #define CPSR_A (1U << 8) 1432 #define CPSR_E (1U << 9) 1433 #define CPSR_IT_2_7 (0xfc00U) 1434 #define CPSR_GE (0xfU << 16) 1435 #define CPSR_IL (1U << 20) 1436 #define CPSR_DIT (1U << 21) 1437 #define CPSR_PAN (1U << 22) 1438 #define CPSR_SSBS (1U << 23) 1439 #define CPSR_J (1U << 24) 1440 #define CPSR_IT_0_1 (3U << 25) 1441 #define CPSR_Q (1U << 27) 1442 #define CPSR_V (1U << 28) 1443 #define CPSR_C (1U << 29) 1444 #define CPSR_Z (1U << 30) 1445 #define CPSR_N (1U << 31) 1446 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1447 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1448 #define ISR_FS (1U << 9) 1449 #define ISR_IS (1U << 10) 1450 1451 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1452 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1453 | CPSR_NZCV) 1454 /* Bits writable in user mode. */ 1455 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1456 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1457 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1458 1459 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1460 #define XPSR_EXCP 0x1ffU 1461 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1462 #define XPSR_IT_2_7 CPSR_IT_2_7 1463 #define XPSR_GE CPSR_GE 1464 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1465 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1466 #define XPSR_IT_0_1 CPSR_IT_0_1 1467 #define XPSR_Q CPSR_Q 1468 #define XPSR_V CPSR_V 1469 #define XPSR_C CPSR_C 1470 #define XPSR_Z CPSR_Z 1471 #define XPSR_N CPSR_N 1472 #define XPSR_NZCV CPSR_NZCV 1473 #define XPSR_IT CPSR_IT 1474 1475 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1476 * Only these are valid when in AArch64 mode; in 1477 * AArch32 mode SPSRs are basically CPSR-format. 1478 */ 1479 #define PSTATE_SP (1U) 1480 #define PSTATE_M (0xFU) 1481 #define PSTATE_nRW (1U << 4) 1482 #define PSTATE_F (1U << 6) 1483 #define PSTATE_I (1U << 7) 1484 #define PSTATE_A (1U << 8) 1485 #define PSTATE_D (1U << 9) 1486 #define PSTATE_BTYPE (3U << 10) 1487 #define PSTATE_SSBS (1U << 12) 1488 #define PSTATE_ALLINT (1U << 13) 1489 #define PSTATE_IL (1U << 20) 1490 #define PSTATE_SS (1U << 21) 1491 #define PSTATE_PAN (1U << 22) 1492 #define PSTATE_UAO (1U << 23) 1493 #define PSTATE_DIT (1U << 24) 1494 #define PSTATE_TCO (1U << 25) 1495 #define PSTATE_V (1U << 28) 1496 #define PSTATE_C (1U << 29) 1497 #define PSTATE_Z (1U << 30) 1498 #define PSTATE_N (1U << 31) 1499 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1500 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1501 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1502 /* Mode values for AArch64 */ 1503 #define PSTATE_MODE_EL3h 13 1504 #define PSTATE_MODE_EL3t 12 1505 #define PSTATE_MODE_EL2h 9 1506 #define PSTATE_MODE_EL2t 8 1507 #define PSTATE_MODE_EL1h 5 1508 #define PSTATE_MODE_EL1t 4 1509 #define PSTATE_MODE_EL0t 0 1510 1511 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1512 FIELD(SVCR, SM, 0, 1) 1513 FIELD(SVCR, ZA, 1, 1) 1514 1515 /* Fields for SMCR_ELx. */ 1516 FIELD(SMCR, LEN, 0, 4) 1517 FIELD(SMCR, FA64, 31, 1) 1518 1519 /* Write a new value to v7m.exception, thus transitioning into or out 1520 * of Handler mode; this may result in a change of active stack pointer. 1521 */ 1522 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1523 1524 /* Map EL and handler into a PSTATE_MODE. */ 1525 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1526 { 1527 return (el << 2) | handler; 1528 } 1529 1530 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1531 * interprocessing, so we don't attempt to sync with the cpsr state used by 1532 * the 32 bit decoder. 1533 */ 1534 static inline uint32_t pstate_read(CPUARMState *env) 1535 { 1536 int ZF; 1537 1538 ZF = (env->ZF == 0); 1539 return (env->NF & 0x80000000) | (ZF << 30) 1540 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1541 | env->pstate | env->daif | (env->btype << 10); 1542 } 1543 1544 static inline void pstate_write(CPUARMState *env, uint32_t val) 1545 { 1546 env->ZF = (~val) & PSTATE_Z; 1547 env->NF = val; 1548 env->CF = (val >> 29) & 1; 1549 env->VF = (val << 3) & 0x80000000; 1550 env->daif = val & PSTATE_DAIF; 1551 env->btype = (val >> 10) & 3; 1552 env->pstate = val & ~CACHED_PSTATE_BITS; 1553 } 1554 1555 /* Return the current CPSR value. */ 1556 uint32_t cpsr_read(CPUARMState *env); 1557 1558 typedef enum CPSRWriteType { 1559 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1560 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1561 CPSRWriteRaw = 2, 1562 /* trust values, no reg bank switch, no hflags rebuild */ 1563 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1564 } CPSRWriteType; 1565 1566 /* 1567 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1568 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1569 * correspond to TB flags bits cached in the hflags, unless @write_type 1570 * is CPSRWriteRaw. 1571 */ 1572 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1573 CPSRWriteType write_type); 1574 1575 /* Return the current xPSR value. */ 1576 static inline uint32_t xpsr_read(CPUARMState *env) 1577 { 1578 int ZF; 1579 ZF = (env->ZF == 0); 1580 return (env->NF & 0x80000000) | (ZF << 30) 1581 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1582 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1583 | ((env->condexec_bits & 0xfc) << 8) 1584 | (env->GE << 16) 1585 | env->v7m.exception; 1586 } 1587 1588 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1589 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1590 { 1591 if (mask & XPSR_NZCV) { 1592 env->ZF = (~val) & XPSR_Z; 1593 env->NF = val; 1594 env->CF = (val >> 29) & 1; 1595 env->VF = (val << 3) & 0x80000000; 1596 } 1597 if (mask & XPSR_Q) { 1598 env->QF = ((val & XPSR_Q) != 0); 1599 } 1600 if (mask & XPSR_GE) { 1601 env->GE = (val & XPSR_GE) >> 16; 1602 } 1603 #ifndef CONFIG_USER_ONLY 1604 if (mask & XPSR_T) { 1605 env->thumb = ((val & XPSR_T) != 0); 1606 } 1607 if (mask & XPSR_IT_0_1) { 1608 env->condexec_bits &= ~3; 1609 env->condexec_bits |= (val >> 25) & 3; 1610 } 1611 if (mask & XPSR_IT_2_7) { 1612 env->condexec_bits &= 3; 1613 env->condexec_bits |= (val >> 8) & 0xfc; 1614 } 1615 if (mask & XPSR_EXCP) { 1616 /* Note that this only happens on exception exit */ 1617 write_v7m_exception(env, val & XPSR_EXCP); 1618 } 1619 #endif 1620 } 1621 1622 #define HCR_VM (1ULL << 0) 1623 #define HCR_SWIO (1ULL << 1) 1624 #define HCR_PTW (1ULL << 2) 1625 #define HCR_FMO (1ULL << 3) 1626 #define HCR_IMO (1ULL << 4) 1627 #define HCR_AMO (1ULL << 5) 1628 #define HCR_VF (1ULL << 6) 1629 #define HCR_VI (1ULL << 7) 1630 #define HCR_VSE (1ULL << 8) 1631 #define HCR_FB (1ULL << 9) 1632 #define HCR_BSU_MASK (3ULL << 10) 1633 #define HCR_DC (1ULL << 12) 1634 #define HCR_TWI (1ULL << 13) 1635 #define HCR_TWE (1ULL << 14) 1636 #define HCR_TID0 (1ULL << 15) 1637 #define HCR_TID1 (1ULL << 16) 1638 #define HCR_TID2 (1ULL << 17) 1639 #define HCR_TID3 (1ULL << 18) 1640 #define HCR_TSC (1ULL << 19) 1641 #define HCR_TIDCP (1ULL << 20) 1642 #define HCR_TACR (1ULL << 21) 1643 #define HCR_TSW (1ULL << 22) 1644 #define HCR_TPCP (1ULL << 23) 1645 #define HCR_TPU (1ULL << 24) 1646 #define HCR_TTLB (1ULL << 25) 1647 #define HCR_TVM (1ULL << 26) 1648 #define HCR_TGE (1ULL << 27) 1649 #define HCR_TDZ (1ULL << 28) 1650 #define HCR_HCD (1ULL << 29) 1651 #define HCR_TRVM (1ULL << 30) 1652 #define HCR_RW (1ULL << 31) 1653 #define HCR_CD (1ULL << 32) 1654 #define HCR_ID (1ULL << 33) 1655 #define HCR_E2H (1ULL << 34) 1656 #define HCR_TLOR (1ULL << 35) 1657 #define HCR_TERR (1ULL << 36) 1658 #define HCR_TEA (1ULL << 37) 1659 #define HCR_MIOCNCE (1ULL << 38) 1660 #define HCR_TME (1ULL << 39) 1661 #define HCR_APK (1ULL << 40) 1662 #define HCR_API (1ULL << 41) 1663 #define HCR_NV (1ULL << 42) 1664 #define HCR_NV1 (1ULL << 43) 1665 #define HCR_AT (1ULL << 44) 1666 #define HCR_NV2 (1ULL << 45) 1667 #define HCR_FWB (1ULL << 46) 1668 #define HCR_FIEN (1ULL << 47) 1669 #define HCR_GPF (1ULL << 48) 1670 #define HCR_TID4 (1ULL << 49) 1671 #define HCR_TICAB (1ULL << 50) 1672 #define HCR_AMVOFFEN (1ULL << 51) 1673 #define HCR_TOCU (1ULL << 52) 1674 #define HCR_ENSCXT (1ULL << 53) 1675 #define HCR_TTLBIS (1ULL << 54) 1676 #define HCR_TTLBOS (1ULL << 55) 1677 #define HCR_ATA (1ULL << 56) 1678 #define HCR_DCT (1ULL << 57) 1679 #define HCR_TID5 (1ULL << 58) 1680 #define HCR_TWEDEN (1ULL << 59) 1681 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1682 1683 #define SCR_NS (1ULL << 0) 1684 #define SCR_IRQ (1ULL << 1) 1685 #define SCR_FIQ (1ULL << 2) 1686 #define SCR_EA (1ULL << 3) 1687 #define SCR_FW (1ULL << 4) 1688 #define SCR_AW (1ULL << 5) 1689 #define SCR_NET (1ULL << 6) 1690 #define SCR_SMD (1ULL << 7) 1691 #define SCR_HCE (1ULL << 8) 1692 #define SCR_SIF (1ULL << 9) 1693 #define SCR_RW (1ULL << 10) 1694 #define SCR_ST (1ULL << 11) 1695 #define SCR_TWI (1ULL << 12) 1696 #define SCR_TWE (1ULL << 13) 1697 #define SCR_TLOR (1ULL << 14) 1698 #define SCR_TERR (1ULL << 15) 1699 #define SCR_APK (1ULL << 16) 1700 #define SCR_API (1ULL << 17) 1701 #define SCR_EEL2 (1ULL << 18) 1702 #define SCR_EASE (1ULL << 19) 1703 #define SCR_NMEA (1ULL << 20) 1704 #define SCR_FIEN (1ULL << 21) 1705 #define SCR_ENSCXT (1ULL << 25) 1706 #define SCR_ATA (1ULL << 26) 1707 #define SCR_FGTEN (1ULL << 27) 1708 #define SCR_ECVEN (1ULL << 28) 1709 #define SCR_TWEDEN (1ULL << 29) 1710 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1711 #define SCR_TME (1ULL << 34) 1712 #define SCR_AMVOFFEN (1ULL << 35) 1713 #define SCR_ENAS0 (1ULL << 36) 1714 #define SCR_ADEN (1ULL << 37) 1715 #define SCR_HXEN (1ULL << 38) 1716 #define SCR_TRNDR (1ULL << 40) 1717 #define SCR_ENTP2 (1ULL << 41) 1718 #define SCR_GPF (1ULL << 48) 1719 #define SCR_NSE (1ULL << 62) 1720 1721 /* Return the current FPSCR value. */ 1722 uint32_t vfp_get_fpscr(CPUARMState *env); 1723 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1724 1725 /* 1726 * FPCR, Floating Point Control Register 1727 * FPSR, Floating Point Status Register 1728 * 1729 * For A64 floating point control and status bits are stored in 1730 * two logically distinct registers, FPCR and FPSR. We store these 1731 * in QEMU in vfp.fpcr and vfp.fpsr. 1732 * For A32 there was only one register, FPSCR. The bits are arranged 1733 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions, 1734 * so we can use appropriate masking to handle FPSCR reads and writes. 1735 * Note that the FPCR has some bits which are not visible in the 1736 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged. 1737 */ 1738 1739 /* FPCR bits */ 1740 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */ 1741 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */ 1742 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */ 1743 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1744 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1745 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1746 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1747 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1748 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */ 1749 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1750 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */ 1751 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1752 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */ 1753 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1754 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1755 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1756 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1757 1758 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1759 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1760 #define FPCR_LTPSIZE_LENGTH 3 1761 1762 /* Cumulative exception trap enable bits */ 1763 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE) 1764 1765 /* FPSR bits */ 1766 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */ 1767 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */ 1768 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */ 1769 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */ 1770 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */ 1771 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */ 1772 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */ 1773 #define FPSR_V (1 << 28) /* FP overflow flag */ 1774 #define FPSR_C (1 << 29) /* FP carry flag */ 1775 #define FPSR_Z (1 << 30) /* FP zero flag */ 1776 #define FPSR_N (1 << 31) /* FP negative flag */ 1777 1778 /* Cumulative exception status bits */ 1779 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC) 1780 1781 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V) 1782 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC) 1783 1784 /* A32 FPSCR bits which architecturally map to FPSR bits */ 1785 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK) 1786 /* A32 FPSCR bits which architecturally map to FPCR bits */ 1787 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \ 1788 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \ 1789 FPCR_FZ | FPCR_DN | FPCR_AHP) 1790 /* These masks don't overlap: each bit lives in only one place */ 1791 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK); 1792 1793 /** 1794 * vfp_get_fpsr: read the AArch64 FPSR 1795 * @env: CPU context 1796 * 1797 * Return the current AArch64 FPSR value 1798 */ 1799 uint32_t vfp_get_fpsr(CPUARMState *env); 1800 1801 /** 1802 * vfp_get_fpcr: read the AArch64 FPCR 1803 * @env: CPU context 1804 * 1805 * Return the current AArch64 FPCR value 1806 */ 1807 uint32_t vfp_get_fpcr(CPUARMState *env); 1808 1809 /** 1810 * vfp_set_fpsr: write the AArch64 FPSR 1811 * @env: CPU context 1812 * @value: new value 1813 */ 1814 void vfp_set_fpsr(CPUARMState *env, uint32_t value); 1815 1816 /** 1817 * vfp_set_fpcr: write the AArch64 FPCR 1818 * @env: CPU context 1819 * @value: new value 1820 */ 1821 void vfp_set_fpcr(CPUARMState *env, uint32_t value); 1822 1823 enum arm_cpu_mode { 1824 ARM_CPU_MODE_USR = 0x10, 1825 ARM_CPU_MODE_FIQ = 0x11, 1826 ARM_CPU_MODE_IRQ = 0x12, 1827 ARM_CPU_MODE_SVC = 0x13, 1828 ARM_CPU_MODE_MON = 0x16, 1829 ARM_CPU_MODE_ABT = 0x17, 1830 ARM_CPU_MODE_HYP = 0x1a, 1831 ARM_CPU_MODE_UND = 0x1b, 1832 ARM_CPU_MODE_SYS = 0x1f 1833 }; 1834 1835 /* VFP system registers. */ 1836 #define ARM_VFP_FPSID 0 1837 #define ARM_VFP_FPSCR 1 1838 #define ARM_VFP_MVFR2 5 1839 #define ARM_VFP_MVFR1 6 1840 #define ARM_VFP_MVFR0 7 1841 #define ARM_VFP_FPEXC 8 1842 #define ARM_VFP_FPINST 9 1843 #define ARM_VFP_FPINST2 10 1844 /* These ones are M-profile only */ 1845 #define ARM_VFP_FPSCR_NZCVQC 2 1846 #define ARM_VFP_VPR 12 1847 #define ARM_VFP_P0 13 1848 #define ARM_VFP_FPCXT_NS 14 1849 #define ARM_VFP_FPCXT_S 15 1850 1851 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1852 #define QEMU_VFP_FPSCR_NZCV 0xffff 1853 1854 /* iwMMXt coprocessor control registers. */ 1855 #define ARM_IWMMXT_wCID 0 1856 #define ARM_IWMMXT_wCon 1 1857 #define ARM_IWMMXT_wCSSF 2 1858 #define ARM_IWMMXT_wCASF 3 1859 #define ARM_IWMMXT_wCGR0 8 1860 #define ARM_IWMMXT_wCGR1 9 1861 #define ARM_IWMMXT_wCGR2 10 1862 #define ARM_IWMMXT_wCGR3 11 1863 1864 /* V7M CCR bits */ 1865 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1866 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1867 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1868 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1869 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1870 FIELD(V7M_CCR, STKALIGN, 9, 1) 1871 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1872 FIELD(V7M_CCR, DC, 16, 1) 1873 FIELD(V7M_CCR, IC, 17, 1) 1874 FIELD(V7M_CCR, BP, 18, 1) 1875 FIELD(V7M_CCR, LOB, 19, 1) 1876 FIELD(V7M_CCR, TRD, 20, 1) 1877 1878 /* V7M SCR bits */ 1879 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1880 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1881 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1882 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1883 1884 /* V7M AIRCR bits */ 1885 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1886 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1887 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1888 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1889 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1890 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1891 FIELD(V7M_AIRCR, PRIS, 14, 1) 1892 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1893 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1894 1895 /* V7M CFSR bits for MMFSR */ 1896 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1897 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1898 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1899 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1900 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1901 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1902 1903 /* V7M CFSR bits for BFSR */ 1904 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1905 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1906 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1907 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1908 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1909 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1910 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1911 1912 /* V7M CFSR bits for UFSR */ 1913 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1914 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1915 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1916 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1917 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1918 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1919 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1920 1921 /* V7M CFSR bit masks covering all of the subregister bits */ 1922 FIELD(V7M_CFSR, MMFSR, 0, 8) 1923 FIELD(V7M_CFSR, BFSR, 8, 8) 1924 FIELD(V7M_CFSR, UFSR, 16, 16) 1925 1926 /* V7M HFSR bits */ 1927 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1928 FIELD(V7M_HFSR, FORCED, 30, 1) 1929 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1930 1931 /* V7M DFSR bits */ 1932 FIELD(V7M_DFSR, HALTED, 0, 1) 1933 FIELD(V7M_DFSR, BKPT, 1, 1) 1934 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1935 FIELD(V7M_DFSR, VCATCH, 3, 1) 1936 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1937 1938 /* V7M SFSR bits */ 1939 FIELD(V7M_SFSR, INVEP, 0, 1) 1940 FIELD(V7M_SFSR, INVIS, 1, 1) 1941 FIELD(V7M_SFSR, INVER, 2, 1) 1942 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1943 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1944 FIELD(V7M_SFSR, LSPERR, 5, 1) 1945 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1946 FIELD(V7M_SFSR, LSERR, 7, 1) 1947 1948 /* v7M MPU_CTRL bits */ 1949 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1950 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1951 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1952 1953 /* v7M CLIDR bits */ 1954 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1955 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1956 FIELD(V7M_CLIDR, LOC, 24, 3) 1957 FIELD(V7M_CLIDR, LOUU, 27, 3) 1958 FIELD(V7M_CLIDR, ICB, 30, 2) 1959 1960 FIELD(V7M_CSSELR, IND, 0, 1) 1961 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1962 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1963 * define a mask for this and check that it doesn't permit running off 1964 * the end of the array. 1965 */ 1966 FIELD(V7M_CSSELR, INDEX, 0, 4) 1967 1968 /* v7M FPCCR bits */ 1969 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1970 FIELD(V7M_FPCCR, USER, 1, 1) 1971 FIELD(V7M_FPCCR, S, 2, 1) 1972 FIELD(V7M_FPCCR, THREAD, 3, 1) 1973 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1974 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1975 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1976 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1977 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1978 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1979 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1980 FIELD(V7M_FPCCR, RES0, 11, 15) 1981 FIELD(V7M_FPCCR, TS, 26, 1) 1982 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1983 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1984 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1985 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1986 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1987 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1988 #define R_V7M_FPCCR_BANKED_MASK \ 1989 (R_V7M_FPCCR_LSPACT_MASK | \ 1990 R_V7M_FPCCR_USER_MASK | \ 1991 R_V7M_FPCCR_THREAD_MASK | \ 1992 R_V7M_FPCCR_MMRDY_MASK | \ 1993 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1994 R_V7M_FPCCR_UFRDY_MASK | \ 1995 R_V7M_FPCCR_ASPEN_MASK) 1996 1997 /* v7M VPR bits */ 1998 FIELD(V7M_VPR, P0, 0, 16) 1999 FIELD(V7M_VPR, MASK01, 16, 4) 2000 FIELD(V7M_VPR, MASK23, 20, 4) 2001 2002 /* 2003 * System register ID fields. 2004 */ 2005 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2006 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2007 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2008 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2009 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2010 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2011 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2012 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2013 FIELD(CLIDR_EL1, LOC, 24, 3) 2014 FIELD(CLIDR_EL1, LOUU, 27, 3) 2015 FIELD(CLIDR_EL1, ICB, 30, 3) 2016 2017 /* When FEAT_CCIDX is implemented */ 2018 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2019 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2020 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2021 2022 /* When FEAT_CCIDX is not implemented */ 2023 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2024 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2025 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2026 2027 FIELD(CTR_EL0, IMINLINE, 0, 4) 2028 FIELD(CTR_EL0, L1IP, 14, 2) 2029 FIELD(CTR_EL0, DMINLINE, 16, 4) 2030 FIELD(CTR_EL0, ERG, 20, 4) 2031 FIELD(CTR_EL0, CWG, 24, 4) 2032 FIELD(CTR_EL0, IDC, 28, 1) 2033 FIELD(CTR_EL0, DIC, 29, 1) 2034 FIELD(CTR_EL0, TMINLINE, 32, 6) 2035 2036 FIELD(MIDR_EL1, REVISION, 0, 4) 2037 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2038 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2039 FIELD(MIDR_EL1, VARIANT, 20, 4) 2040 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2041 2042 FIELD(ID_ISAR0, SWAP, 0, 4) 2043 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2044 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2045 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2046 FIELD(ID_ISAR0, COPROC, 16, 4) 2047 FIELD(ID_ISAR0, DEBUG, 20, 4) 2048 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2049 2050 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2051 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2052 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2053 FIELD(ID_ISAR1, EXTEND, 12, 4) 2054 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2055 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2056 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2057 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2058 2059 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2060 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2061 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2062 FIELD(ID_ISAR2, MULT, 12, 4) 2063 FIELD(ID_ISAR2, MULTS, 16, 4) 2064 FIELD(ID_ISAR2, MULTU, 20, 4) 2065 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2066 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2067 2068 FIELD(ID_ISAR3, SATURATE, 0, 4) 2069 FIELD(ID_ISAR3, SIMD, 4, 4) 2070 FIELD(ID_ISAR3, SVC, 8, 4) 2071 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2072 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2073 FIELD(ID_ISAR3, T32COPY, 20, 4) 2074 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2075 FIELD(ID_ISAR3, T32EE, 28, 4) 2076 2077 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2078 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2079 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2080 FIELD(ID_ISAR4, SMC, 12, 4) 2081 FIELD(ID_ISAR4, BARRIER, 16, 4) 2082 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2083 FIELD(ID_ISAR4, PSR_M, 24, 4) 2084 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2085 2086 FIELD(ID_ISAR5, SEVL, 0, 4) 2087 FIELD(ID_ISAR5, AES, 4, 4) 2088 FIELD(ID_ISAR5, SHA1, 8, 4) 2089 FIELD(ID_ISAR5, SHA2, 12, 4) 2090 FIELD(ID_ISAR5, CRC32, 16, 4) 2091 FIELD(ID_ISAR5, RDM, 24, 4) 2092 FIELD(ID_ISAR5, VCMA, 28, 4) 2093 2094 FIELD(ID_ISAR6, JSCVT, 0, 4) 2095 FIELD(ID_ISAR6, DP, 4, 4) 2096 FIELD(ID_ISAR6, FHM, 8, 4) 2097 FIELD(ID_ISAR6, SB, 12, 4) 2098 FIELD(ID_ISAR6, SPECRES, 16, 4) 2099 FIELD(ID_ISAR6, BF16, 20, 4) 2100 FIELD(ID_ISAR6, I8MM, 24, 4) 2101 2102 FIELD(ID_MMFR0, VMSA, 0, 4) 2103 FIELD(ID_MMFR0, PMSA, 4, 4) 2104 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2105 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2106 FIELD(ID_MMFR0, TCM, 16, 4) 2107 FIELD(ID_MMFR0, AUXREG, 20, 4) 2108 FIELD(ID_MMFR0, FCSE, 24, 4) 2109 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2110 2111 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2112 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2113 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2114 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2115 FIELD(ID_MMFR1, L1HVD, 16, 4) 2116 FIELD(ID_MMFR1, L1UNI, 20, 4) 2117 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2118 FIELD(ID_MMFR1, BPRED, 28, 4) 2119 2120 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2121 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2122 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2123 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2124 FIELD(ID_MMFR2, UNITLB, 16, 4) 2125 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2126 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2127 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2128 2129 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2130 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2131 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2132 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2133 FIELD(ID_MMFR3, PAN, 16, 4) 2134 FIELD(ID_MMFR3, COHWALK, 20, 4) 2135 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2136 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2137 2138 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2139 FIELD(ID_MMFR4, AC2, 4, 4) 2140 FIELD(ID_MMFR4, XNX, 8, 4) 2141 FIELD(ID_MMFR4, CNP, 12, 4) 2142 FIELD(ID_MMFR4, HPDS, 16, 4) 2143 FIELD(ID_MMFR4, LSM, 20, 4) 2144 FIELD(ID_MMFR4, CCIDX, 24, 4) 2145 FIELD(ID_MMFR4, EVT, 28, 4) 2146 2147 FIELD(ID_MMFR5, ETS, 0, 4) 2148 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2149 2150 FIELD(ID_PFR0, STATE0, 0, 4) 2151 FIELD(ID_PFR0, STATE1, 4, 4) 2152 FIELD(ID_PFR0, STATE2, 8, 4) 2153 FIELD(ID_PFR0, STATE3, 12, 4) 2154 FIELD(ID_PFR0, CSV2, 16, 4) 2155 FIELD(ID_PFR0, AMU, 20, 4) 2156 FIELD(ID_PFR0, DIT, 24, 4) 2157 FIELD(ID_PFR0, RAS, 28, 4) 2158 2159 FIELD(ID_PFR1, PROGMOD, 0, 4) 2160 FIELD(ID_PFR1, SECURITY, 4, 4) 2161 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2162 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2163 FIELD(ID_PFR1, GENTIMER, 16, 4) 2164 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2165 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2166 FIELD(ID_PFR1, GIC, 28, 4) 2167 2168 FIELD(ID_PFR2, CSV3, 0, 4) 2169 FIELD(ID_PFR2, SSBS, 4, 4) 2170 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2171 2172 FIELD(ID_AA64ISAR0, AES, 4, 4) 2173 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2174 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2175 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2176 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2177 FIELD(ID_AA64ISAR0, TME, 24, 4) 2178 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2179 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2180 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2181 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2182 FIELD(ID_AA64ISAR0, DP, 44, 4) 2183 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2184 FIELD(ID_AA64ISAR0, TS, 52, 4) 2185 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2186 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2187 2188 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2189 FIELD(ID_AA64ISAR1, APA, 4, 4) 2190 FIELD(ID_AA64ISAR1, API, 8, 4) 2191 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2192 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2193 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2194 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2195 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2196 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2197 FIELD(ID_AA64ISAR1, SB, 36, 4) 2198 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2199 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2200 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2201 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2202 FIELD(ID_AA64ISAR1, XS, 56, 4) 2203 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2204 2205 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2206 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2207 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2208 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2209 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2210 FIELD(ID_AA64ISAR2, BC, 20, 4) 2211 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2212 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2213 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2214 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2215 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2216 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2217 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2218 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2219 2220 FIELD(ID_AA64PFR0, EL0, 0, 4) 2221 FIELD(ID_AA64PFR0, EL1, 4, 4) 2222 FIELD(ID_AA64PFR0, EL2, 8, 4) 2223 FIELD(ID_AA64PFR0, EL3, 12, 4) 2224 FIELD(ID_AA64PFR0, FP, 16, 4) 2225 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2226 FIELD(ID_AA64PFR0, GIC, 24, 4) 2227 FIELD(ID_AA64PFR0, RAS, 28, 4) 2228 FIELD(ID_AA64PFR0, SVE, 32, 4) 2229 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2230 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2231 FIELD(ID_AA64PFR0, AMU, 44, 4) 2232 FIELD(ID_AA64PFR0, DIT, 48, 4) 2233 FIELD(ID_AA64PFR0, RME, 52, 4) 2234 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2235 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2236 2237 FIELD(ID_AA64PFR1, BT, 0, 4) 2238 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2239 FIELD(ID_AA64PFR1, MTE, 8, 4) 2240 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2241 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2242 FIELD(ID_AA64PFR1, SME, 24, 4) 2243 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2244 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2245 FIELD(ID_AA64PFR1, NMI, 36, 4) 2246 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2247 FIELD(ID_AA64PFR1, GCS, 44, 4) 2248 FIELD(ID_AA64PFR1, THE, 48, 4) 2249 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2250 FIELD(ID_AA64PFR1, DF2, 56, 4) 2251 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2252 2253 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2254 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2255 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2256 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2257 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2258 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2259 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2260 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2261 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2262 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2263 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2264 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2265 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2266 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2267 2268 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2269 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2270 FIELD(ID_AA64MMFR1, VH, 8, 4) 2271 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2272 FIELD(ID_AA64MMFR1, LO, 16, 4) 2273 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2274 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2275 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2276 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2277 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2278 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2279 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2280 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2281 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2282 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2283 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2284 2285 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2286 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2287 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2288 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2289 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2290 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2291 FIELD(ID_AA64MMFR2, NV, 24, 4) 2292 FIELD(ID_AA64MMFR2, ST, 28, 4) 2293 FIELD(ID_AA64MMFR2, AT, 32, 4) 2294 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2295 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2296 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2297 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2298 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2299 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2300 2301 FIELD(ID_AA64MMFR3, TCRX, 0, 4) 2302 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) 2303 FIELD(ID_AA64MMFR3, S1PIE, 8, 4) 2304 FIELD(ID_AA64MMFR3, S2PIE, 12, 4) 2305 FIELD(ID_AA64MMFR3, S1POE, 16, 4) 2306 FIELD(ID_AA64MMFR3, S2POE, 20, 4) 2307 FIELD(ID_AA64MMFR3, AIE, 24, 4) 2308 FIELD(ID_AA64MMFR3, MEC, 28, 4) 2309 FIELD(ID_AA64MMFR3, D128, 32, 4) 2310 FIELD(ID_AA64MMFR3, D128_2, 36, 4) 2311 FIELD(ID_AA64MMFR3, SNERR, 40, 4) 2312 FIELD(ID_AA64MMFR3, ANERR, 44, 4) 2313 FIELD(ID_AA64MMFR3, SDERR, 52, 4) 2314 FIELD(ID_AA64MMFR3, ADERR, 56, 4) 2315 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) 2316 2317 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2318 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2319 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2320 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2321 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2322 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2323 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2324 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2325 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2326 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2327 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2328 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2329 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2330 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2331 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2332 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2333 2334 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2335 FIELD(ID_AA64ZFR0, AES, 4, 4) 2336 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2337 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2338 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2339 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2340 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2341 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2342 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2343 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2344 2345 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2346 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2347 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2348 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2349 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2350 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2351 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2352 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2353 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2354 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2355 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2356 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2357 2358 FIELD(ID_DFR0, COPDBG, 0, 4) 2359 FIELD(ID_DFR0, COPSDBG, 4, 4) 2360 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2361 FIELD(ID_DFR0, COPTRC, 12, 4) 2362 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2363 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2364 FIELD(ID_DFR0, PERFMON, 24, 4) 2365 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2366 2367 FIELD(ID_DFR1, MTPMU, 0, 4) 2368 FIELD(ID_DFR1, HPMN0, 4, 4) 2369 2370 FIELD(DBGDIDR, SE_IMP, 12, 1) 2371 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2372 FIELD(DBGDIDR, VERSION, 16, 4) 2373 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2374 FIELD(DBGDIDR, BRPS, 24, 4) 2375 FIELD(DBGDIDR, WRPS, 28, 4) 2376 2377 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2378 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2379 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2380 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2381 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2382 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2383 FIELD(DBGDEVID, AUXREGS, 24, 4) 2384 FIELD(DBGDEVID, CIDMASK, 28, 4) 2385 2386 FIELD(DBGDEVID1, PCSROFFSET, 0, 4) 2387 2388 FIELD(MVFR0, SIMDREG, 0, 4) 2389 FIELD(MVFR0, FPSP, 4, 4) 2390 FIELD(MVFR0, FPDP, 8, 4) 2391 FIELD(MVFR0, FPTRAP, 12, 4) 2392 FIELD(MVFR0, FPDIVIDE, 16, 4) 2393 FIELD(MVFR0, FPSQRT, 20, 4) 2394 FIELD(MVFR0, FPSHVEC, 24, 4) 2395 FIELD(MVFR0, FPROUND, 28, 4) 2396 2397 FIELD(MVFR1, FPFTZ, 0, 4) 2398 FIELD(MVFR1, FPDNAN, 4, 4) 2399 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2400 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2401 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2402 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2403 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2404 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2405 FIELD(MVFR1, FPHP, 24, 4) 2406 FIELD(MVFR1, SIMDFMAC, 28, 4) 2407 2408 FIELD(MVFR2, SIMDMISC, 0, 4) 2409 FIELD(MVFR2, FPMISC, 4, 4) 2410 2411 FIELD(GPCCR, PPS, 0, 3) 2412 FIELD(GPCCR, IRGN, 8, 2) 2413 FIELD(GPCCR, ORGN, 10, 2) 2414 FIELD(GPCCR, SH, 12, 2) 2415 FIELD(GPCCR, PGS, 14, 2) 2416 FIELD(GPCCR, GPC, 16, 1) 2417 FIELD(GPCCR, GPCP, 17, 1) 2418 FIELD(GPCCR, L0GPTSZ, 20, 4) 2419 2420 FIELD(MFAR, FPA, 12, 40) 2421 FIELD(MFAR, NSE, 62, 1) 2422 FIELD(MFAR, NS, 63, 1) 2423 2424 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2425 2426 /* If adding a feature bit which corresponds to a Linux ELF 2427 * HWCAP bit, remember to update the feature-bit-to-hwcap 2428 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2429 */ 2430 enum arm_features { 2431 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2432 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2433 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2434 ARM_FEATURE_V6, 2435 ARM_FEATURE_V6K, 2436 ARM_FEATURE_V7, 2437 ARM_FEATURE_THUMB2, 2438 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2439 ARM_FEATURE_NEON, 2440 ARM_FEATURE_M, /* Microcontroller profile. */ 2441 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2442 ARM_FEATURE_THUMB2EE, 2443 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2444 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2445 ARM_FEATURE_V4T, 2446 ARM_FEATURE_V5, 2447 ARM_FEATURE_STRONGARM, 2448 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2449 ARM_FEATURE_GENERIC_TIMER, 2450 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2451 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2452 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2453 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2454 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2455 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2456 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2457 ARM_FEATURE_V8, 2458 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2459 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2460 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2461 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2462 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2463 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2464 ARM_FEATURE_PMU, /* has PMU support */ 2465 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2466 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2467 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2468 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2469 /* 2470 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz 2471 * if the board doesn't set a value, instead of 1GHz. It is for backwards 2472 * compatibility and used only with CPU definitions that were already 2473 * in QEMU before we changed the default. It should not be set on any 2474 * CPU types added in future. 2475 */ 2476 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ 2477 }; 2478 2479 static inline int arm_feature(CPUARMState *env, int feature) 2480 { 2481 return (env->features & (1ULL << feature)) != 0; 2482 } 2483 2484 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2485 2486 /* 2487 * ARM v9 security states. 2488 * The ordering of the enumeration corresponds to the low 2 bits 2489 * of the GPI value, and (except for Root) the concat of NSE:NS. 2490 */ 2491 2492 typedef enum ARMSecuritySpace { 2493 ARMSS_Secure = 0, 2494 ARMSS_NonSecure = 1, 2495 ARMSS_Root = 2, 2496 ARMSS_Realm = 3, 2497 } ARMSecuritySpace; 2498 2499 /* Return true if @space is secure, in the pre-v9 sense. */ 2500 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2501 { 2502 return space == ARMSS_Secure || space == ARMSS_Root; 2503 } 2504 2505 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2506 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2507 { 2508 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2509 } 2510 2511 #if !defined(CONFIG_USER_ONLY) 2512 /** 2513 * arm_security_space_below_el3: 2514 * @env: cpu context 2515 * 2516 * Return the security space of exception levels below EL3, following 2517 * an exception return to those levels. Unlike arm_security_space, 2518 * this doesn't care about the current EL. 2519 */ 2520 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2521 2522 /** 2523 * arm_is_secure_below_el3: 2524 * @env: cpu context 2525 * 2526 * Return true if exception levels below EL3 are in secure state, 2527 * or would be following an exception return to those levels. 2528 */ 2529 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2530 { 2531 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2532 return ss == ARMSS_Secure; 2533 } 2534 2535 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2536 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2537 { 2538 assert(!arm_feature(env, ARM_FEATURE_M)); 2539 if (arm_feature(env, ARM_FEATURE_EL3)) { 2540 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2541 /* CPU currently in AArch64 state and EL3 */ 2542 return true; 2543 } else if (!is_a64(env) && 2544 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2545 /* CPU currently in AArch32 state and monitor mode */ 2546 return true; 2547 } 2548 } 2549 return false; 2550 } 2551 2552 /** 2553 * arm_security_space: 2554 * @env: cpu context 2555 * 2556 * Return the current security space of the cpu. 2557 */ 2558 ARMSecuritySpace arm_security_space(CPUARMState *env); 2559 2560 /** 2561 * arm_is_secure: 2562 * @env: cpu context 2563 * 2564 * Return true if the processor is in secure state. 2565 */ 2566 static inline bool arm_is_secure(CPUARMState *env) 2567 { 2568 return arm_space_is_secure(arm_security_space(env)); 2569 } 2570 2571 /* 2572 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2573 * This corresponds to the pseudocode EL2Enabled(). 2574 */ 2575 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2576 ARMSecuritySpace space) 2577 { 2578 assert(space != ARMSS_Root); 2579 return arm_feature(env, ARM_FEATURE_EL2) 2580 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2581 } 2582 2583 static inline bool arm_is_el2_enabled(CPUARMState *env) 2584 { 2585 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2586 } 2587 2588 #else 2589 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2590 { 2591 return ARMSS_NonSecure; 2592 } 2593 2594 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2595 { 2596 return false; 2597 } 2598 2599 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2600 { 2601 return false; 2602 } 2603 2604 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2605 { 2606 return ARMSS_NonSecure; 2607 } 2608 2609 static inline bool arm_is_secure(CPUARMState *env) 2610 { 2611 return false; 2612 } 2613 2614 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2615 ARMSecuritySpace space) 2616 { 2617 return false; 2618 } 2619 2620 static inline bool arm_is_el2_enabled(CPUARMState *env) 2621 { 2622 return false; 2623 } 2624 #endif 2625 2626 /** 2627 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2628 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2629 * "for all purposes other than a direct read or write access of HCR_EL2." 2630 * Not included here is HCR_RW. 2631 */ 2632 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2633 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2634 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2635 2636 /* Return true if the specified exception level is running in AArch64 state. */ 2637 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2638 { 2639 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2640 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2641 */ 2642 assert(el >= 1 && el <= 3); 2643 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2644 2645 /* The highest exception level is always at the maximum supported 2646 * register width, and then lower levels have a register width controlled 2647 * by bits in the SCR or HCR registers. 2648 */ 2649 if (el == 3) { 2650 return aa64; 2651 } 2652 2653 if (arm_feature(env, ARM_FEATURE_EL3) && 2654 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2655 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2656 } 2657 2658 if (el == 2) { 2659 return aa64; 2660 } 2661 2662 if (arm_is_el2_enabled(env)) { 2663 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2664 } 2665 2666 return aa64; 2667 } 2668 2669 /* Function for determining whether guest cp register reads and writes should 2670 * access the secure or non-secure bank of a cp register. When EL3 is 2671 * operating in AArch32 state, the NS-bit determines whether the secure 2672 * instance of a cp register should be used. When EL3 is AArch64 (or if 2673 * it doesn't exist at all) then there is no register banking, and all 2674 * accesses are to the non-secure version. 2675 */ 2676 static inline bool access_secure_reg(CPUARMState *env) 2677 { 2678 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2679 !arm_el_is_aa64(env, 3) && 2680 !(env->cp15.scr_el3 & SCR_NS)); 2681 2682 return ret; 2683 } 2684 2685 /* Macros for accessing a specified CP register bank */ 2686 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2687 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2688 2689 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2690 do { \ 2691 if (_secure) { \ 2692 (_env)->cp15._regname##_s = (_val); \ 2693 } else { \ 2694 (_env)->cp15._regname##_ns = (_val); \ 2695 } \ 2696 } while (0) 2697 2698 /* Macros for automatically accessing a specific CP register bank depending on 2699 * the current secure state of the system. These macros are not intended for 2700 * supporting instruction translation reads/writes as these are dependent 2701 * solely on the SCR.NS bit and not the mode. 2702 */ 2703 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2704 A32_BANKED_REG_GET((_env), _regname, \ 2705 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2706 2707 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2708 A32_BANKED_REG_SET((_env), _regname, \ 2709 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2710 (_val)) 2711 2712 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2713 uint32_t cur_el, bool secure); 2714 2715 /* Return the highest implemented Exception Level */ 2716 static inline int arm_highest_el(CPUARMState *env) 2717 { 2718 if (arm_feature(env, ARM_FEATURE_EL3)) { 2719 return 3; 2720 } 2721 if (arm_feature(env, ARM_FEATURE_EL2)) { 2722 return 2; 2723 } 2724 return 1; 2725 } 2726 2727 /* Return true if a v7M CPU is in Handler mode */ 2728 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2729 { 2730 return env->v7m.exception != 0; 2731 } 2732 2733 /* Return the current Exception Level (as per ARMv8; note that this differs 2734 * from the ARMv7 Privilege Level). 2735 */ 2736 static inline int arm_current_el(CPUARMState *env) 2737 { 2738 if (arm_feature(env, ARM_FEATURE_M)) { 2739 return arm_v7m_is_handler_mode(env) || 2740 !(env->v7m.control[env->v7m.secure] & 1); 2741 } 2742 2743 if (is_a64(env)) { 2744 return extract32(env->pstate, 2, 2); 2745 } 2746 2747 switch (env->uncached_cpsr & 0x1f) { 2748 case ARM_CPU_MODE_USR: 2749 return 0; 2750 case ARM_CPU_MODE_HYP: 2751 return 2; 2752 case ARM_CPU_MODE_MON: 2753 return 3; 2754 default: 2755 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2756 /* If EL3 is 32-bit then all secure privileged modes run in 2757 * EL3 2758 */ 2759 return 3; 2760 } 2761 2762 return 1; 2763 } 2764 } 2765 2766 /** 2767 * write_list_to_cpustate 2768 * @cpu: ARMCPU 2769 * 2770 * For each register listed in the ARMCPU cpreg_indexes list, write 2771 * its value from the cpreg_values list into the ARMCPUState structure. 2772 * This updates TCG's working data structures from KVM data or 2773 * from incoming migration state. 2774 * 2775 * Returns: true if all register values were updated correctly, 2776 * false if some register was unknown or could not be written. 2777 * Note that we do not stop early on failure -- we will attempt 2778 * writing all registers in the list. 2779 */ 2780 bool write_list_to_cpustate(ARMCPU *cpu); 2781 2782 /** 2783 * write_cpustate_to_list: 2784 * @cpu: ARMCPU 2785 * @kvm_sync: true if this is for syncing back to KVM 2786 * 2787 * For each register listed in the ARMCPU cpreg_indexes list, write 2788 * its value from the ARMCPUState structure into the cpreg_values list. 2789 * This is used to copy info from TCG's working data structures into 2790 * KVM or for outbound migration. 2791 * 2792 * @kvm_sync is true if we are doing this in order to sync the 2793 * register state back to KVM. In this case we will only update 2794 * values in the list if the previous list->cpustate sync actually 2795 * successfully wrote the CPU state. Otherwise we will keep the value 2796 * that is in the list. 2797 * 2798 * Returns: true if all register values were read correctly, 2799 * false if some register was unknown or could not be read. 2800 * Note that we do not stop early on failure -- we will attempt 2801 * reading all registers in the list. 2802 */ 2803 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2804 2805 #define ARM_CPUID_TI915T 0x54029152 2806 #define ARM_CPUID_TI925T 0x54029252 2807 2808 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2809 2810 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2811 2812 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2813 * 2814 * If EL3 is 64-bit: 2815 * + NonSecure EL1 & 0 stage 1 2816 * + NonSecure EL1 & 0 stage 2 2817 * + NonSecure EL2 2818 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2819 * + Secure EL1 & 0 stage 1 2820 * + Secure EL1 & 0 stage 2 (FEAT_SEL2) 2821 * + Secure EL2 (FEAT_SEL2) 2822 * + Secure EL2 & 0 (FEAT_SEL2) 2823 * + Realm EL1 & 0 stage 1 (FEAT_RME) 2824 * + Realm EL1 & 0 stage 2 (FEAT_RME) 2825 * + Realm EL2 (FEAT_RME) 2826 * + EL3 2827 * If EL3 is 32-bit: 2828 * + NonSecure PL1 & 0 stage 1 2829 * + NonSecure PL1 & 0 stage 2 2830 * + NonSecure PL2 2831 * + Secure PL1 & 0 2832 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2833 * 2834 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2835 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2836 * because they may differ in access permissions even if the VA->PA map is 2837 * the same 2838 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2839 * translation, which means that we have one mmu_idx that deals with two 2840 * concatenated translation regimes [this sort of combined s1+2 TLB is 2841 * architecturally permitted] 2842 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2843 * handling via the TLB. The only way to do a stage 1 translation without 2844 * the immediate stage 2 translation is via the ATS or AT system insns, 2845 * which can be slow-pathed and always do a page table walk. 2846 * The only use of stage 2 translations is either as part of an s1+2 2847 * lookup or when loading the descriptors during a stage 1 page table walk, 2848 * and in both those cases we don't use the TLB. 2849 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2850 * translation regimes, because they map reasonably well to each other 2851 * and they can't both be active at the same time. 2852 * 5. we want to be able to use the TLB for accesses done as part of a 2853 * stage1 page table walk, rather than having to walk the stage2 page 2854 * table over and over. 2855 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2856 * Never (PAN) bit within PSTATE. 2857 * 7. we fold together most secure and non-secure regimes for A-profile, 2858 * because there are no banked system registers for aarch64, so the 2859 * process of switching between secure and non-secure is 2860 * already heavyweight. 2861 * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, 2862 * because both are in use simultaneously for Secure EL2. 2863 * 2864 * This gives us the following list of cases: 2865 * 2866 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) 2867 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) 2868 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) 2869 * EL0 EL2&0 2870 * EL2 EL2&0 2871 * EL2 EL2&0 +PAN 2872 * EL2 (aka NS PL2) 2873 * EL3 (aka AArch32 S PL1 PL1&0) 2874 * AArch32 S PL0 PL1&0 (we call this EL30_0) 2875 * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) 2876 * Stage2 Secure 2877 * Stage2 NonSecure 2878 * plus one TLB per Physical address space: S, NS, Realm, Root 2879 * 2880 * for a total of 16 different mmu_idx. 2881 * 2882 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2883 * as A profile. They only need to distinguish EL0 and EL1 (and 2884 * EL2 for cores like the Cortex-R52). 2885 * 2886 * M profile CPUs are rather different as they do not have a true MMU. 2887 * They have the following different MMU indexes: 2888 * User 2889 * Privileged 2890 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2891 * Privileged, execution priority negative (ditto) 2892 * If the CPU supports the v8M Security Extension then there are also: 2893 * Secure User 2894 * Secure Privileged 2895 * Secure User, execution priority negative 2896 * Secure Privileged, execution priority negative 2897 * 2898 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2899 * are not quite the same -- different CPU types (most notably M profile 2900 * vs A/R profile) would like to use MMU indexes with different semantics, 2901 * but since we don't ever need to use all of those in a single CPU we 2902 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2903 * modes + total number of M profile MMU modes". The lower bits of 2904 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2905 * the same for any particular CPU. 2906 * Variables of type ARMMUIdx are always full values, and the core 2907 * index values are in variables of type 'int'. 2908 * 2909 * Our enumeration includes at the end some entries which are not "true" 2910 * mmu_idx values in that they don't have corresponding TLBs and are only 2911 * valid for doing slow path page table walks. 2912 * 2913 * The constant names here are patterned after the general style of the names 2914 * of the AT/ATS operations. 2915 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2916 * For M profile we arrange them to have a bit for priv, a bit for negpri 2917 * and a bit for secure. 2918 */ 2919 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2920 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2921 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2922 2923 /* Meanings of the bits for M profile mmu idx values */ 2924 #define ARM_MMU_IDX_M_PRIV 0x1 2925 #define ARM_MMU_IDX_M_NEGPRI 0x2 2926 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2927 2928 #define ARM_MMU_IDX_TYPE_MASK \ 2929 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2930 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2931 2932 typedef enum ARMMMUIdx { 2933 /* 2934 * A-profile. 2935 */ 2936 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2937 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2938 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2939 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2940 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2941 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2942 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2943 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2944 ARMMMUIdx_E30_0 = 8 | ARM_MMU_IDX_A, 2945 ARMMMUIdx_E30_3_PAN = 9 | ARM_MMU_IDX_A, 2946 2947 /* 2948 * Used for second stage of an S12 page table walk, or for descriptor 2949 * loads during first stage of an S1 page table walk. Note that both 2950 * are in use simultaneously for SecureEL2: the security state for 2951 * the S2 ptw is selected by the NS bit from the S1 ptw. 2952 */ 2953 ARMMMUIdx_Stage2_S = 10 | ARM_MMU_IDX_A, 2954 ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A, 2955 2956 /* TLBs with 1-1 mapping to the physical address spaces. */ 2957 ARMMMUIdx_Phys_S = 12 | ARM_MMU_IDX_A, 2958 ARMMMUIdx_Phys_NS = 13 | ARM_MMU_IDX_A, 2959 ARMMMUIdx_Phys_Root = 14 | ARM_MMU_IDX_A, 2960 ARMMMUIdx_Phys_Realm = 15 | ARM_MMU_IDX_A, 2961 2962 /* 2963 * These are not allocated TLBs and are used only for AT system 2964 * instructions or for the first stage of an S12 page table walk. 2965 */ 2966 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2967 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2968 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2969 2970 /* 2971 * M-profile. 2972 */ 2973 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2974 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2975 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2976 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2977 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2978 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2979 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2980 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2981 } ARMMMUIdx; 2982 2983 /* 2984 * Bit macros for the core-mmu-index values for each index, 2985 * for use when calling tlb_flush_by_mmuidx() and friends. 2986 */ 2987 #define TO_CORE_BIT(NAME) \ 2988 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2989 2990 typedef enum ARMMMUIdxBit { 2991 TO_CORE_BIT(E10_0), 2992 TO_CORE_BIT(E20_0), 2993 TO_CORE_BIT(E10_1), 2994 TO_CORE_BIT(E10_1_PAN), 2995 TO_CORE_BIT(E2), 2996 TO_CORE_BIT(E20_2), 2997 TO_CORE_BIT(E20_2_PAN), 2998 TO_CORE_BIT(E3), 2999 TO_CORE_BIT(E30_0), 3000 TO_CORE_BIT(E30_3_PAN), 3001 TO_CORE_BIT(Stage2), 3002 TO_CORE_BIT(Stage2_S), 3003 3004 TO_CORE_BIT(MUser), 3005 TO_CORE_BIT(MPriv), 3006 TO_CORE_BIT(MUserNegPri), 3007 TO_CORE_BIT(MPrivNegPri), 3008 TO_CORE_BIT(MSUser), 3009 TO_CORE_BIT(MSPriv), 3010 TO_CORE_BIT(MSUserNegPri), 3011 TO_CORE_BIT(MSPrivNegPri), 3012 } ARMMMUIdxBit; 3013 3014 #undef TO_CORE_BIT 3015 3016 #define MMU_USER_IDX 0 3017 3018 /* Indexes used when registering address spaces with cpu_address_space_init */ 3019 typedef enum ARMASIdx { 3020 ARMASIdx_NS = 0, 3021 ARMASIdx_S = 1, 3022 ARMASIdx_TagNS = 2, 3023 ARMASIdx_TagS = 3, 3024 } ARMASIdx; 3025 3026 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 3027 { 3028 /* Assert the relative order of the physical mmu indexes. */ 3029 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 3030 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 3031 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 3032 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 3033 3034 return ARMMMUIdx_Phys_S + space; 3035 } 3036 3037 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 3038 { 3039 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 3040 return idx - ARMMMUIdx_Phys_S; 3041 } 3042 3043 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3044 { 3045 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3046 * CSSELR is RAZ/WI. 3047 */ 3048 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3049 } 3050 3051 static inline bool arm_sctlr_b(CPUARMState *env) 3052 { 3053 return 3054 /* We need not implement SCTLR.ITD in user-mode emulation, so 3055 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3056 * This lets people run BE32 binaries with "-cpu any". 3057 */ 3058 #ifndef CONFIG_USER_ONLY 3059 !arm_feature(env, ARM_FEATURE_V7) && 3060 #endif 3061 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3062 } 3063 3064 uint64_t arm_sctlr(CPUARMState *env, int el); 3065 3066 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3067 bool sctlr_b) 3068 { 3069 #ifdef CONFIG_USER_ONLY 3070 /* 3071 * In system mode, BE32 is modelled in line with the 3072 * architecture (as word-invariant big-endianness), where loads 3073 * and stores are done little endian but from addresses which 3074 * are adjusted by XORing with the appropriate constant. So the 3075 * endianness to use for the raw data access is not affected by 3076 * SCTLR.B. 3077 * In user mode, however, we model BE32 as byte-invariant 3078 * big-endianness (because user-only code cannot tell the 3079 * difference), and so we need to use a data access endianness 3080 * that depends on SCTLR.B. 3081 */ 3082 if (sctlr_b) { 3083 return true; 3084 } 3085 #endif 3086 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3087 return env->uncached_cpsr & CPSR_E; 3088 } 3089 3090 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3091 { 3092 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3093 } 3094 3095 /* Return true if the processor is in big-endian mode. */ 3096 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3097 { 3098 if (!is_a64(env)) { 3099 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3100 } else { 3101 int cur_el = arm_current_el(env); 3102 uint64_t sctlr = arm_sctlr(env, cur_el); 3103 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3104 } 3105 } 3106 3107 #include "exec/cpu-all.h" 3108 3109 /* 3110 * We have more than 32-bits worth of state per TB, so we split the data 3111 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3112 * We collect these two parts in CPUARMTBFlags where they are named 3113 * flags and flags2 respectively. 3114 * 3115 * The flags that are shared between all execution modes, TBFLAG_ANY, 3116 * are stored in flags. The flags that are specific to a given mode 3117 * are stores in flags2. Since cs_base is sized on the configured 3118 * address size, flags2 always has 64-bits for A64, and a minimum of 3119 * 32-bits for A32 and M32. 3120 * 3121 * The bits for 32-bit A-profile and M-profile partially overlap: 3122 * 3123 * 31 23 11 10 0 3124 * +-------------+----------+----------------+ 3125 * | | | TBFLAG_A32 | 3126 * | TBFLAG_AM32 | +-----+----------+ 3127 * | | |TBFLAG_M32| 3128 * +-------------+----------------+----------+ 3129 * 31 23 6 5 0 3130 * 3131 * Unless otherwise noted, these bits are cached in env->hflags. 3132 */ 3133 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3134 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3135 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3136 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3137 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3138 /* Target EL if we take a floating-point-disabled exception */ 3139 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3140 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3141 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3142 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3143 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3144 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3145 3146 /* 3147 * Bit usage when in AArch32 state, both A- and M-profile. 3148 */ 3149 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3150 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3151 3152 /* 3153 * Bit usage when in AArch32 state, for A-profile only. 3154 */ 3155 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3156 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3157 /* 3158 * We store the bottom two bits of the CPAR as TB flags and handle 3159 * checks on the other bits at runtime. This shares the same bits as 3160 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3161 * Not cached, because VECLEN+VECSTRIDE are not cached. 3162 */ 3163 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3164 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3165 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3166 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3167 /* 3168 * Indicates whether cp register reads and writes by guest code should access 3169 * the secure or nonsecure bank of banked registers; note that this is not 3170 * the same thing as the current security state of the processor! 3171 */ 3172 FIELD(TBFLAG_A32, NS, 10, 1) 3173 /* 3174 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3175 * This requires an SME trap from AArch32 mode when using NEON. 3176 */ 3177 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3178 3179 /* 3180 * Bit usage when in AArch32 state, for M-profile only. 3181 */ 3182 /* Handler (ie not Thread) mode */ 3183 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3184 /* Whether we should generate stack-limit checks */ 3185 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3186 /* Set if FPCCR.LSPACT is set */ 3187 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3188 /* Set if we must create a new FP context */ 3189 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3190 /* Set if FPCCR.S does not match current security state */ 3191 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3192 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3193 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3194 /* Set if in secure mode */ 3195 FIELD(TBFLAG_M32, SECURE, 6, 1) 3196 3197 /* 3198 * Bit usage when in AArch64 state 3199 */ 3200 FIELD(TBFLAG_A64, TBII, 0, 2) 3201 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3202 /* The current vector length, either NVL or SVL. */ 3203 FIELD(TBFLAG_A64, VL, 4, 4) 3204 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3205 FIELD(TBFLAG_A64, BT, 9, 1) 3206 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3207 FIELD(TBFLAG_A64, TBID, 12, 2) 3208 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3209 FIELD(TBFLAG_A64, ATA, 15, 1) 3210 FIELD(TBFLAG_A64, TCMA, 16, 2) 3211 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3212 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3213 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3214 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3215 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3216 FIELD(TBFLAG_A64, SVL, 24, 4) 3217 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3218 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3219 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3220 FIELD(TBFLAG_A64, NAA, 30, 1) 3221 FIELD(TBFLAG_A64, ATA0, 31, 1) 3222 FIELD(TBFLAG_A64, NV, 32, 1) 3223 FIELD(TBFLAG_A64, NV1, 33, 1) 3224 FIELD(TBFLAG_A64, NV2, 34, 1) 3225 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3226 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3227 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3228 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3229 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ 3230 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */ 3231 3232 /* 3233 * Helpers for using the above. Note that only the A64 accessors use 3234 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3235 * word either is or might be 32 bits only. 3236 */ 3237 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3238 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3239 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3240 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3241 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3242 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3243 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3244 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3245 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3246 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3247 3248 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3249 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3250 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3251 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3252 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3253 3254 /** 3255 * sve_vq 3256 * @env: the cpu context 3257 * 3258 * Return the VL cached within env->hflags, in units of quadwords. 3259 */ 3260 static inline int sve_vq(CPUARMState *env) 3261 { 3262 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3263 } 3264 3265 /** 3266 * sme_vq 3267 * @env: the cpu context 3268 * 3269 * Return the SVL cached within env->hflags, in units of quadwords. 3270 */ 3271 static inline int sme_vq(CPUARMState *env) 3272 { 3273 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3274 } 3275 3276 static inline bool bswap_code(bool sctlr_b) 3277 { 3278 #ifdef CONFIG_USER_ONLY 3279 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3280 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3281 * would also end up as a mixed-endian mode with BE code, LE data. 3282 */ 3283 return TARGET_BIG_ENDIAN ^ sctlr_b; 3284 #else 3285 /* All code access in ARM is little endian, and there are no loaders 3286 * doing swaps that need to be reversed 3287 */ 3288 return 0; 3289 #endif 3290 } 3291 3292 #ifdef CONFIG_USER_ONLY 3293 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3294 { 3295 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3296 } 3297 #endif 3298 3299 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3300 uint64_t *cs_base, uint32_t *flags); 3301 3302 enum { 3303 QEMU_PSCI_CONDUIT_DISABLED = 0, 3304 QEMU_PSCI_CONDUIT_SMC = 1, 3305 QEMU_PSCI_CONDUIT_HVC = 2, 3306 }; 3307 3308 #ifndef CONFIG_USER_ONLY 3309 /* Return the address space index to use for a memory access */ 3310 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3311 { 3312 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3313 } 3314 3315 /* Return the AddressSpace to use for a memory access 3316 * (which depends on whether the access is S or NS, and whether 3317 * the board gave us a separate AddressSpace for S accesses). 3318 */ 3319 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3320 { 3321 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3322 } 3323 #endif 3324 3325 /** 3326 * arm_register_pre_el_change_hook: 3327 * Register a hook function which will be called immediately before this 3328 * CPU changes exception level or mode. The hook function will be 3329 * passed a pointer to the ARMCPU and the opaque data pointer passed 3330 * to this function when the hook was registered. 3331 * 3332 * Note that if a pre-change hook is called, any registered post-change hooks 3333 * are guaranteed to subsequently be called. 3334 */ 3335 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3336 void *opaque); 3337 /** 3338 * arm_register_el_change_hook: 3339 * Register a hook function which will be called immediately after this 3340 * CPU changes exception level or mode. The hook function will be 3341 * passed a pointer to the ARMCPU and the opaque data pointer passed 3342 * to this function when the hook was registered. 3343 * 3344 * Note that any registered hooks registered here are guaranteed to be called 3345 * if pre-change hooks have been. 3346 */ 3347 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3348 *opaque); 3349 3350 /** 3351 * arm_rebuild_hflags: 3352 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3353 */ 3354 void arm_rebuild_hflags(CPUARMState *env); 3355 3356 /** 3357 * aa32_vfp_dreg: 3358 * Return a pointer to the Dn register within env in 32-bit mode. 3359 */ 3360 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3361 { 3362 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3363 } 3364 3365 /** 3366 * aa32_vfp_qreg: 3367 * Return a pointer to the Qn register within env in 32-bit mode. 3368 */ 3369 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3370 { 3371 return &env->vfp.zregs[regno].d[0]; 3372 } 3373 3374 /** 3375 * aa64_vfp_qreg: 3376 * Return a pointer to the Qn register within env in 64-bit mode. 3377 */ 3378 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3379 { 3380 return &env->vfp.zregs[regno].d[0]; 3381 } 3382 3383 /* Shared between translate-sve.c and sve_helper.c. */ 3384 extern const uint64_t pred_esz_masks[5]; 3385 3386 /* 3387 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3388 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3389 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3390 */ 3391 #define PAGE_BTI PAGE_TARGET_1 3392 #define PAGE_MTE PAGE_TARGET_2 3393 #define PAGE_TARGET_STICKY PAGE_MTE 3394 3395 /* We associate one allocation tag per 16 bytes, the minimum. */ 3396 #define LOG2_TAG_GRANULE 4 3397 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3398 3399 #ifdef CONFIG_USER_ONLY 3400 3401 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3402 3403 #ifdef TARGET_TAGGED_ADDRESSES 3404 /** 3405 * cpu_untagged_addr: 3406 * @cs: CPU context 3407 * @x: tagged address 3408 * 3409 * Remove any address tag from @x. This is explicitly related to the 3410 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3411 * 3412 * There should be a better place to put this, but we need this in 3413 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3414 */ 3415 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3416 { 3417 CPUARMState *env = cpu_env(cs); 3418 if (env->tagged_addr_enable) { 3419 /* 3420 * TBI is enabled for userspace but not kernelspace addresses. 3421 * Only clear the tag if bit 55 is clear. 3422 */ 3423 x &= sextract64(x, 0, 56); 3424 } 3425 return x; 3426 } 3427 #endif /* TARGET_TAGGED_ADDRESSES */ 3428 #endif /* CONFIG_USER_ONLY */ 3429 3430 #endif 3431