1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/cpu-interrupt.h" 29 #include "exec/gdbstub.h" 30 #include "exec/page-protection.h" 31 #include "qapi/qapi-types-common.h" 32 #include "target/arm/multiprocessing.h" 33 #include "target/arm/gtimer.h" 34 35 #ifdef TARGET_AARCH64 36 #define KVM_HAVE_MCE_INJECTION 1 37 #endif 38 39 #define EXCP_UDEF 1 /* undefined instruction */ 40 #define EXCP_SWI 2 /* software interrupt */ 41 #define EXCP_PREFETCH_ABORT 3 42 #define EXCP_DATA_ABORT 4 43 #define EXCP_IRQ 5 44 #define EXCP_FIQ 6 45 #define EXCP_BKPT 7 46 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 47 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 48 #define EXCP_HVC 11 /* HyperVisor Call */ 49 #define EXCP_HYP_TRAP 12 50 #define EXCP_SMC 13 /* Secure Monitor Call */ 51 #define EXCP_VIRQ 14 52 #define EXCP_VFIQ 15 53 #define EXCP_SEMIHOST 16 /* semihosting call */ 54 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 55 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 56 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 57 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 58 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 59 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 60 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 61 #define EXCP_VSERR 24 62 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 63 #define EXCP_NMI 26 64 #define EXCP_VINMI 27 65 #define EXCP_VFNMI 28 66 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */ 67 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 68 69 #define ARMV7M_EXCP_RESET 1 70 #define ARMV7M_EXCP_NMI 2 71 #define ARMV7M_EXCP_HARD 3 72 #define ARMV7M_EXCP_MEM 4 73 #define ARMV7M_EXCP_BUS 5 74 #define ARMV7M_EXCP_USAGE 6 75 #define ARMV7M_EXCP_SECURE 7 76 #define ARMV7M_EXCP_SVC 11 77 #define ARMV7M_EXCP_DEBUG 12 78 #define ARMV7M_EXCP_PENDSV 14 79 #define ARMV7M_EXCP_SYSTICK 15 80 81 /* ARM-specific interrupt pending bits. */ 82 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 83 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 84 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 85 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 86 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 87 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 88 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 89 90 /* The usual mapping for an AArch64 system register to its AArch32 91 * counterpart is for the 32 bit world to have access to the lower 92 * half only (with writes leaving the upper half untouched). It's 93 * therefore useful to be able to pass TCG the offset of the least 94 * significant half of a uint64_t struct member. 95 */ 96 #if HOST_BIG_ENDIAN 97 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 98 #define offsetofhigh32(S, M) offsetof(S, M) 99 #else 100 #define offsetoflow32(S, M) offsetof(S, M) 101 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 102 #endif 103 104 /* ARM-specific extra insn start words: 105 * 1: Conditional execution bits 106 * 2: Partial exception syndrome for data aborts 107 */ 108 #define TARGET_INSN_START_EXTRA_WORDS 2 109 110 /* The 2nd extra word holding syndrome info for data aborts does not use 111 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 112 * help the sleb128 encoder do a better job. 113 * When restoring the CPU state, we shift it back up. 114 */ 115 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 116 #define ARM_INSN_START_WORD2_SHIFT 13 117 118 /* We currently assume float and double are IEEE single and double 119 precision respectively. 120 Doing runtime conversions is tricky because VFP registers may contain 121 integer values (eg. as the result of a FTOSI instruction). 122 s<2n> maps to the least significant half of d<n> 123 s<2n+1> maps to the most significant half of d<n> 124 */ 125 126 /** 127 * DynamicGDBFeatureInfo: 128 * @desc: Contains the feature descriptions. 129 * @data: A union with data specific to the set of registers 130 * @cpregs_keys: Array that contains the corresponding Key of 131 * a given cpreg with the same order of the cpreg 132 * in the XML description. 133 */ 134 typedef struct DynamicGDBFeatureInfo { 135 GDBFeature desc; 136 union { 137 struct { 138 uint32_t *keys; 139 } cpregs; 140 } data; 141 } DynamicGDBFeatureInfo; 142 143 /* CPU state for each instance of a generic timer (in cp15 c14) */ 144 typedef struct ARMGenericTimer { 145 uint64_t cval; /* Timer CompareValue register */ 146 uint64_t ctl; /* Timer Control register */ 147 } ARMGenericTimer; 148 149 /* Define a maximum sized vector register. 150 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 151 * For 64-bit, this is a 2048-bit SVE register. 152 * 153 * Note that the mapping between S, D, and Q views of the register bank 154 * differs between AArch64 and AArch32. 155 * In AArch32: 156 * Qn = regs[n].d[1]:regs[n].d[0] 157 * Dn = regs[n / 2].d[n & 1] 158 * Sn = regs[n / 4].d[n % 4 / 2], 159 * bits 31..0 for even n, and bits 63..32 for odd n 160 * (and regs[16] to regs[31] are inaccessible) 161 * In AArch64: 162 * Zn = regs[n].d[*] 163 * Qn = regs[n].d[1]:regs[n].d[0] 164 * Dn = regs[n].d[0] 165 * Sn = regs[n].d[0] bits 31..0 166 * Hn = regs[n].d[0] bits 15..0 167 * 168 * This corresponds to the architecturally defined mapping between 169 * the two execution states, and means we do not need to explicitly 170 * map these registers when changing states. 171 * 172 * Align the data for use with TCG host vector operations. 173 */ 174 175 #ifdef TARGET_AARCH64 176 # define ARM_MAX_VQ 16 177 #else 178 # define ARM_MAX_VQ 1 179 #endif 180 181 typedef struct ARMVectorReg { 182 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 183 } ARMVectorReg; 184 185 #ifdef TARGET_AARCH64 186 /* In AArch32 mode, predicate registers do not exist at all. */ 187 typedef struct ARMPredicateReg { 188 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 189 } ARMPredicateReg; 190 191 /* In AArch32 mode, PAC keys do not exist at all. */ 192 typedef struct ARMPACKey { 193 uint64_t lo, hi; 194 } ARMPACKey; 195 #endif 196 197 /* See the commentary above the TBFLAG field definitions. */ 198 typedef struct CPUARMTBFlags { 199 uint32_t flags; 200 target_ulong flags2; 201 } CPUARMTBFlags; 202 203 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 204 205 typedef struct NVICState NVICState; 206 207 /* 208 * Enum for indexing vfp.fp_status[]. 209 * 210 * FPST_A32: is the "normal" fp status for AArch32 insns 211 * FPST_A64: is the "normal" fp status for AArch64 insns 212 * FPST_A32_F16: used for AArch32 half-precision calculations 213 * FPST_A64_F16: used for AArch64 half-precision calculations 214 * FPST_STD: the ARM "Standard FPSCR Value" 215 * FPST_STD_F16: used for half-precision 216 * calculations with the ARM "Standard FPSCR Value" 217 * FPST_AH: used for the A64 insns which change behaviour 218 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 219 * and the reciprocal and square root estimate/step insns) 220 * FPST_AH_F16: used for the A64 insns which change behaviour 221 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 222 * and the reciprocal and square root estimate/step insns); 223 * for half-precision 224 * 225 * Half-precision operations are governed by a separate 226 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 227 * status structure to control this. 228 * 229 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 230 * round-to-nearest and is used by any operations (generally 231 * Neon) which the architecture defines as controlled by the 232 * standard FPSCR value rather than the FPSCR. 233 * 234 * The "standard FPSCR but for fp16 ops" is needed because 235 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 236 * using a fixed value for it. 237 * 238 * FPST_AH is needed because some insns have different 239 * behaviour when FPCR.AH == 1: they don't update cumulative 240 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and 241 * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, 242 * which means we need an FPST_AH_F16 as well. 243 * 244 * To avoid having to transfer exception bits around, we simply 245 * say that the FPSCR cumulative exception flags are the logical 246 * OR of the flags in the four fp statuses. This relies on the 247 * only thing which needs to read the exception flags being 248 * an explicit FPSCR read. 249 */ 250 typedef enum ARMFPStatusFlavour { 251 FPST_A32, 252 FPST_A64, 253 FPST_A32_F16, 254 FPST_A64_F16, 255 FPST_AH, 256 FPST_AH_F16, 257 FPST_STD, 258 FPST_STD_F16, 259 } ARMFPStatusFlavour; 260 #define FPST_COUNT 8 261 262 typedef struct CPUArchState { 263 /* Regs for current mode. */ 264 uint32_t regs[16]; 265 266 /* 32/64 switch only happens when taking and returning from 267 * exceptions so the overlap semantics are taken care of then 268 * instead of having a complicated union. 269 */ 270 /* Regs for A64 mode. */ 271 uint64_t xregs[32]; 272 uint64_t pc; 273 /* PSTATE isn't an architectural register for ARMv8. However, it is 274 * convenient for us to assemble the underlying state into a 32 bit format 275 * identical to the architectural format used for the SPSR. (This is also 276 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 277 * 'pstate' register are.) Of the PSTATE bits: 278 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 279 * semantics as for AArch32, as described in the comments on each field) 280 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 281 * DAIF (exception masks) are kept in env->daif 282 * BTYPE is kept in env->btype 283 * SM and ZA are kept in env->svcr 284 * all other bits are stored in their correct places in env->pstate 285 */ 286 uint32_t pstate; 287 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 288 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 289 290 /* Cached TBFLAGS state. See below for which bits are included. */ 291 CPUARMTBFlags hflags; 292 293 /* Frequently accessed CPSR bits are stored separately for efficiency. 294 This contains all the other bits. Use cpsr_{read,write} to access 295 the whole CPSR. */ 296 uint32_t uncached_cpsr; 297 uint32_t spsr; 298 299 /* Banked registers. */ 300 uint64_t banked_spsr[8]; 301 uint32_t banked_r13[8]; 302 uint32_t banked_r14[8]; 303 304 /* These hold r8-r12. */ 305 uint32_t usr_regs[5]; 306 uint32_t fiq_regs[5]; 307 308 /* cpsr flag cache for faster execution */ 309 uint32_t CF; /* 0 or 1 */ 310 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 311 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 312 uint32_t ZF; /* Z set if zero. */ 313 uint32_t QF; /* 0 or 1 */ 314 uint32_t GE; /* cpsr[19:16] */ 315 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 316 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 317 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 318 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 319 320 uint64_t elr_el[4]; /* AArch64 exception link regs */ 321 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 322 323 /* System control coprocessor (cp15) */ 324 struct { 325 uint32_t c0_cpuid; 326 union { /* Cache size selection */ 327 struct { 328 uint64_t _unused_csselr0; 329 uint64_t csselr_ns; 330 uint64_t _unused_csselr1; 331 uint64_t csselr_s; 332 }; 333 uint64_t csselr_el[4]; 334 }; 335 union { /* System control register. */ 336 struct { 337 uint64_t _unused_sctlr; 338 uint64_t sctlr_ns; 339 uint64_t hsctlr; 340 uint64_t sctlr_s; 341 }; 342 uint64_t sctlr_el[4]; 343 }; 344 uint64_t vsctlr; /* Virtualization System control register. */ 345 uint64_t cpacr_el1; /* Architectural feature access control register */ 346 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 347 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 348 uint64_t sder; /* Secure debug enable register. */ 349 uint32_t nsacr; /* Non-secure access control register. */ 350 union { /* MMU translation table base 0. */ 351 struct { 352 uint64_t _unused_ttbr0_0; 353 uint64_t ttbr0_ns; 354 uint64_t _unused_ttbr0_1; 355 uint64_t ttbr0_s; 356 }; 357 uint64_t ttbr0_el[4]; 358 }; 359 union { /* MMU translation table base 1. */ 360 struct { 361 uint64_t _unused_ttbr1_0; 362 uint64_t ttbr1_ns; 363 uint64_t _unused_ttbr1_1; 364 uint64_t ttbr1_s; 365 }; 366 uint64_t ttbr1_el[4]; 367 }; 368 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 369 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 370 /* MMU translation table base control. */ 371 uint64_t tcr_el[4]; 372 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 373 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 374 uint32_t c2_data; /* MPU data cacheable bits. */ 375 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 376 union { /* MMU domain access control register 377 * MPU write buffer control. 378 */ 379 struct { 380 uint64_t dacr_ns; 381 uint64_t dacr_s; 382 }; 383 struct { 384 uint64_t dacr32_el2; 385 }; 386 }; 387 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 388 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 389 uint64_t hcr_el2; /* Hypervisor configuration register */ 390 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 391 uint64_t scr_el3; /* Secure configuration register. */ 392 union { /* Fault status registers. */ 393 struct { 394 uint64_t ifsr_ns; 395 uint64_t ifsr_s; 396 }; 397 struct { 398 uint64_t ifsr32_el2; 399 }; 400 }; 401 union { 402 struct { 403 uint64_t _unused_dfsr; 404 uint64_t dfsr_ns; 405 uint64_t hsr; 406 uint64_t dfsr_s; 407 }; 408 uint64_t esr_el[4]; 409 }; 410 uint32_t c6_region[8]; /* MPU base/size registers. */ 411 union { /* Fault address registers. */ 412 struct { 413 uint64_t _unused_far0; 414 #if HOST_BIG_ENDIAN 415 uint32_t ifar_ns; 416 uint32_t dfar_ns; 417 uint32_t ifar_s; 418 uint32_t dfar_s; 419 #else 420 uint32_t dfar_ns; 421 uint32_t ifar_ns; 422 uint32_t dfar_s; 423 uint32_t ifar_s; 424 #endif 425 uint64_t _unused_far3; 426 }; 427 uint64_t far_el[4]; 428 }; 429 uint64_t hpfar_el2; 430 uint64_t hstr_el2; 431 union { /* Translation result. */ 432 struct { 433 uint64_t _unused_par_0; 434 uint64_t par_ns; 435 uint64_t _unused_par_1; 436 uint64_t par_s; 437 }; 438 uint64_t par_el[4]; 439 }; 440 441 uint32_t c9_insn; /* Cache lockdown registers. */ 442 uint32_t c9_data; 443 uint64_t c9_pmcr; /* performance monitor control register */ 444 uint64_t c9_pmcnten; /* perf monitor counter enables */ 445 uint64_t c9_pmovsr; /* perf monitor overflow status */ 446 uint64_t c9_pmuserenr; /* perf monitor user enable */ 447 uint64_t c9_pmselr; /* perf monitor counter selection register */ 448 uint64_t c9_pminten; /* perf monitor interrupt enables */ 449 union { /* Memory attribute redirection */ 450 struct { 451 #if HOST_BIG_ENDIAN 452 uint64_t _unused_mair_0; 453 uint32_t mair1_ns; 454 uint32_t mair0_ns; 455 uint64_t _unused_mair_1; 456 uint32_t mair1_s; 457 uint32_t mair0_s; 458 #else 459 uint64_t _unused_mair_0; 460 uint32_t mair0_ns; 461 uint32_t mair1_ns; 462 uint64_t _unused_mair_1; 463 uint32_t mair0_s; 464 uint32_t mair1_s; 465 #endif 466 }; 467 uint64_t mair_el[4]; 468 }; 469 union { /* vector base address register */ 470 struct { 471 uint64_t _unused_vbar; 472 uint64_t vbar_ns; 473 uint64_t hvbar; 474 uint64_t vbar_s; 475 }; 476 uint64_t vbar_el[4]; 477 }; 478 uint32_t mvbar; /* (monitor) vector base address register */ 479 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 480 struct { /* FCSE PID. */ 481 uint32_t fcseidr_ns; 482 uint32_t fcseidr_s; 483 }; 484 union { /* Context ID. */ 485 struct { 486 uint64_t _unused_contextidr_0; 487 uint64_t contextidr_ns; 488 uint64_t _unused_contextidr_1; 489 uint64_t contextidr_s; 490 }; 491 uint64_t contextidr_el[4]; 492 }; 493 union { /* User RW Thread register. */ 494 struct { 495 uint64_t tpidrurw_ns; 496 uint64_t tpidrprw_ns; 497 uint64_t htpidr; 498 uint64_t _tpidr_el3; 499 }; 500 uint64_t tpidr_el[4]; 501 }; 502 uint64_t tpidr2_el0; 503 /* The secure banks of these registers don't map anywhere */ 504 uint64_t tpidrurw_s; 505 uint64_t tpidrprw_s; 506 uint64_t tpidruro_s; 507 508 union { /* User RO Thread register. */ 509 uint64_t tpidruro_ns; 510 uint64_t tpidrro_el[1]; 511 }; 512 uint64_t c14_cntfrq; /* Counter Frequency register */ 513 uint64_t c14_cntkctl; /* Timer Control register */ 514 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 515 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 516 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 517 ARMGenericTimer c14_timer[NUM_GTIMERS]; 518 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 519 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 520 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 521 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 522 uint32_t c15_threadid; /* TI debugger thread-ID. */ 523 uint32_t c15_config_base_address; /* SCU base address. */ 524 uint32_t c15_diagnostic; /* diagnostic register */ 525 uint32_t c15_power_diagnostic; 526 uint32_t c15_power_control; /* power control */ 527 uint64_t dbgbvr[16]; /* breakpoint value registers */ 528 uint64_t dbgbcr[16]; /* breakpoint control registers */ 529 uint64_t dbgwvr[16]; /* watchpoint value registers */ 530 uint64_t dbgwcr[16]; /* watchpoint control registers */ 531 uint64_t dbgclaim; /* DBGCLAIM bits */ 532 uint64_t mdscr_el1; 533 uint64_t oslsr_el1; /* OS Lock Status */ 534 uint64_t osdlr_el1; /* OS DoubleLock status */ 535 uint64_t mdcr_el2; 536 uint64_t mdcr_el3; 537 /* Stores the architectural value of the counter *the last time it was 538 * updated* by pmccntr_op_start. Accesses should always be surrounded 539 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 540 * architecturally-correct value is being read/set. 541 */ 542 uint64_t c15_ccnt; 543 /* Stores the delta between the architectural value and the underlying 544 * cycle count during normal operation. It is used to update c15_ccnt 545 * to be the correct architectural value before accesses. During 546 * accesses, c15_ccnt_delta contains the underlying count being used 547 * for the access, after which it reverts to the delta value in 548 * pmccntr_op_finish. 549 */ 550 uint64_t c15_ccnt_delta; 551 uint64_t c14_pmevcntr[31]; 552 uint64_t c14_pmevcntr_delta[31]; 553 uint64_t c14_pmevtyper[31]; 554 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 555 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 556 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 557 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 558 uint64_t gcr_el1; 559 uint64_t rgsr_el1; 560 561 /* Minimal RAS registers */ 562 uint64_t disr_el1; 563 uint64_t vdisr_el2; 564 uint64_t vsesr_el2; 565 566 /* 567 * Fine-Grained Trap registers. We store these as arrays so the 568 * access checking code doesn't have to manually select 569 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 570 * FEAT_FGT2 will add more elements to these arrays. 571 */ 572 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 573 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 574 uint64_t fgt_exec[1]; /* HFGITR */ 575 576 /* RME registers */ 577 uint64_t gpccr_el3; 578 uint64_t gptbr_el3; 579 uint64_t mfar_el3; 580 581 /* NV2 register */ 582 uint64_t vncr_el2; 583 } cp15; 584 585 struct { 586 /* M profile has up to 4 stack pointers: 587 * a Main Stack Pointer and a Process Stack Pointer for each 588 * of the Secure and Non-Secure states. (If the CPU doesn't support 589 * the security extension then it has only two SPs.) 590 * In QEMU we always store the currently active SP in regs[13], 591 * and the non-active SP for the current security state in 592 * v7m.other_sp. The stack pointers for the inactive security state 593 * are stored in other_ss_msp and other_ss_psp. 594 * switch_v7m_security_state() is responsible for rearranging them 595 * when we change security state. 596 */ 597 uint32_t other_sp; 598 uint32_t other_ss_msp; 599 uint32_t other_ss_psp; 600 uint32_t vecbase[M_REG_NUM_BANKS]; 601 uint32_t basepri[M_REG_NUM_BANKS]; 602 uint32_t control[M_REG_NUM_BANKS]; 603 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 604 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 605 uint32_t hfsr; /* HardFault Status */ 606 uint32_t dfsr; /* Debug Fault Status Register */ 607 uint32_t sfsr; /* Secure Fault Status Register */ 608 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 609 uint32_t bfar; /* BusFault Address */ 610 uint32_t sfar; /* Secure Fault Address Register */ 611 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 612 int exception; 613 uint32_t primask[M_REG_NUM_BANKS]; 614 uint32_t faultmask[M_REG_NUM_BANKS]; 615 uint32_t aircr; /* only holds r/w state if security extn implemented */ 616 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 617 uint32_t csselr[M_REG_NUM_BANKS]; 618 uint32_t scr[M_REG_NUM_BANKS]; 619 uint32_t msplim[M_REG_NUM_BANKS]; 620 uint32_t psplim[M_REG_NUM_BANKS]; 621 uint32_t fpcar[M_REG_NUM_BANKS]; 622 uint32_t fpccr[M_REG_NUM_BANKS]; 623 uint32_t fpdscr[M_REG_NUM_BANKS]; 624 uint32_t cpacr[M_REG_NUM_BANKS]; 625 uint32_t nsacr; 626 uint32_t ltpsize; 627 uint32_t vpr; 628 } v7m; 629 630 /* Information associated with an exception about to be taken: 631 * code which raises an exception must set cs->exception_index and 632 * the relevant parts of this structure; the cpu_do_interrupt function 633 * will then set the guest-visible registers as part of the exception 634 * entry process. 635 */ 636 struct { 637 uint32_t syndrome; /* AArch64 format syndrome register */ 638 uint32_t fsr; /* AArch32 format fault status register info */ 639 uint64_t vaddress; /* virtual addr associated with exception, if any */ 640 uint32_t target_el; /* EL the exception should be targeted for */ 641 /* If we implement EL2 we will also need to store information 642 * about the intermediate physical address for stage 2 faults. 643 */ 644 } exception; 645 646 /* Information associated with an SError */ 647 struct { 648 uint8_t pending; 649 uint8_t has_esr; 650 uint64_t esr; 651 } serror; 652 653 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 654 655 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 656 uint32_t irq_line_state; 657 658 /* Thumb-2 EE state. */ 659 uint32_t teecr; 660 uint32_t teehbr; 661 662 /* VFP coprocessor state. */ 663 struct { 664 ARMVectorReg zregs[32]; 665 666 #ifdef TARGET_AARCH64 667 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 668 #define FFR_PRED_NUM 16 669 ARMPredicateReg pregs[17]; 670 /* Scratch space for aa64 sve predicate temporary. */ 671 ARMPredicateReg preg_tmp; 672 #endif 673 674 /* We store these fpcsr fields separately for convenience. */ 675 uint32_t qc[4] QEMU_ALIGNED(16); 676 int vec_len; 677 int vec_stride; 678 679 /* 680 * Floating point status and control registers. Some bits are 681 * stored separately in other fields or in the float_status below. 682 */ 683 uint64_t fpsr; 684 uint64_t fpcr; 685 686 uint32_t xregs[16]; 687 688 /* Scratch space for aa32 neon expansion. */ 689 uint32_t scratch[8]; 690 691 /* There are a number of distinct float control structures. */ 692 float_status fp_status[FPST_COUNT]; 693 694 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 695 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 696 } vfp; 697 698 uint64_t exclusive_addr; 699 uint64_t exclusive_val; 700 /* 701 * Contains the 'val' for the second 64-bit register of LDXP, which comes 702 * from the higher address, not the high part of a complete 128-bit value. 703 * In some ways it might be more convenient to record the exclusive value 704 * as the low and high halves of a 128 bit data value, but the current 705 * semantics of these fields are baked into the migration format. 706 */ 707 uint64_t exclusive_high; 708 709 /* iwMMXt coprocessor state. */ 710 struct { 711 uint64_t regs[16]; 712 uint64_t val; 713 714 uint32_t cregs[16]; 715 } iwmmxt; 716 717 #ifdef TARGET_AARCH64 718 struct { 719 ARMPACKey apia; 720 ARMPACKey apib; 721 ARMPACKey apda; 722 ARMPACKey apdb; 723 ARMPACKey apga; 724 } keys; 725 726 uint64_t scxtnum_el[4]; 727 728 /* 729 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 730 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 731 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 732 * When SVL is less than the architectural maximum, the accessible 733 * storage is restricted, such that if the SVL is X bytes the guest can 734 * see only the bottom X elements of zarray[], and only the least 735 * significant X bytes of each element of the array. (In other words, 736 * the observable part is always square.) 737 * 738 * The ZA storage can also be considered as a set of square tiles of 739 * elements of different sizes. The mapping from tiles to the ZA array 740 * is architecturally defined, such that for tiles of elements of esz 741 * bytes, the Nth row (or "horizontal slice") of tile T is in 742 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 743 * in the ZA storage, because its rows are striped through the ZA array. 744 * 745 * Because this is so large, keep this toward the end of the reset area, 746 * to keep the offsets into the rest of the structure smaller. 747 */ 748 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 749 #endif 750 751 struct CPUBreakpoint *cpu_breakpoint[16]; 752 struct CPUWatchpoint *cpu_watchpoint[16]; 753 754 /* Optional fault info across tlb lookup. */ 755 ARMMMUFaultInfo *tlb_fi; 756 757 /* Fields up to this point are cleared by a CPU reset */ 758 struct {} end_reset_fields; 759 760 /* Fields after this point are preserved across CPU reset. */ 761 762 /* Internal CPU feature flags. */ 763 uint64_t features; 764 765 /* PMSAv7 MPU */ 766 struct { 767 uint32_t *drbar; 768 uint32_t *drsr; 769 uint32_t *dracr; 770 uint32_t rnr[M_REG_NUM_BANKS]; 771 } pmsav7; 772 773 /* PMSAv8 MPU */ 774 struct { 775 /* The PMSAv8 implementation also shares some PMSAv7 config 776 * and state: 777 * pmsav7.rnr (region number register) 778 * pmsav7_dregion (number of configured regions) 779 */ 780 uint32_t *rbar[M_REG_NUM_BANKS]; 781 uint32_t *rlar[M_REG_NUM_BANKS]; 782 uint32_t *hprbar; 783 uint32_t *hprlar; 784 uint32_t mair0[M_REG_NUM_BANKS]; 785 uint32_t mair1[M_REG_NUM_BANKS]; 786 uint32_t hprselr; 787 } pmsav8; 788 789 /* v8M SAU */ 790 struct { 791 uint32_t *rbar; 792 uint32_t *rlar; 793 uint32_t rnr; 794 uint32_t ctrl; 795 } sau; 796 797 #if !defined(CONFIG_USER_ONLY) 798 NVICState *nvic; 799 const struct arm_boot_info *boot_info; 800 /* Store GICv3CPUState to access from this struct */ 801 void *gicv3state; 802 #else /* CONFIG_USER_ONLY */ 803 /* For usermode syscall translation. */ 804 bool eabi; 805 #endif /* CONFIG_USER_ONLY */ 806 807 #ifdef TARGET_TAGGED_ADDRESSES 808 /* Linux syscall tagged address support */ 809 bool tagged_addr_enable; 810 #endif 811 } CPUARMState; 812 813 static inline void set_feature(CPUARMState *env, int feature) 814 { 815 env->features |= 1ULL << feature; 816 } 817 818 static inline void unset_feature(CPUARMState *env, int feature) 819 { 820 env->features &= ~(1ULL << feature); 821 } 822 823 /** 824 * ARMELChangeHookFn: 825 * type of a function which can be registered via arm_register_el_change_hook() 826 * to get callbacks when the CPU changes its exception level or mode. 827 */ 828 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 829 typedef struct ARMELChangeHook ARMELChangeHook; 830 struct ARMELChangeHook { 831 ARMELChangeHookFn *hook; 832 void *opaque; 833 QLIST_ENTRY(ARMELChangeHook) node; 834 }; 835 836 /* These values map onto the return values for 837 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 838 typedef enum ARMPSCIState { 839 PSCI_ON = 0, 840 PSCI_OFF = 1, 841 PSCI_ON_PENDING = 2 842 } ARMPSCIState; 843 844 typedef struct ARMISARegisters ARMISARegisters; 845 846 /* 847 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 848 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 849 * 850 * While processing properties during initialization, corresponding init bits 851 * are set for bits in sve_vq_map that have been set by properties. 852 * 853 * Bits set in supported represent valid vector lengths for the CPU type. 854 */ 855 typedef struct { 856 uint32_t map, init, supported; 857 } ARMVQMap; 858 859 /** 860 * ARMCPU: 861 * @env: #CPUARMState 862 * 863 * An ARM CPU core. 864 */ 865 struct ArchCPU { 866 CPUState parent_obj; 867 868 CPUARMState env; 869 870 /* Coprocessor information */ 871 GHashTable *cp_regs; 872 /* For marshalling (mostly coprocessor) register state between the 873 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 874 * we use these arrays. 875 */ 876 /* List of register indexes managed via these arrays; (full KVM style 877 * 64 bit indexes, not CPRegInfo 32 bit indexes) 878 */ 879 uint64_t *cpreg_indexes; 880 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 881 uint64_t *cpreg_values; 882 /* Length of the indexes, values, reset_values arrays */ 883 int32_t cpreg_array_len; 884 /* These are used only for migration: incoming data arrives in 885 * these fields and is sanity checked in post_load before copying 886 * to the working data structures above. 887 */ 888 uint64_t *cpreg_vmstate_indexes; 889 uint64_t *cpreg_vmstate_values; 890 int32_t cpreg_vmstate_array_len; 891 892 DynamicGDBFeatureInfo dyn_sysreg_feature; 893 DynamicGDBFeatureInfo dyn_svereg_feature; 894 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 895 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 896 897 /* Timers used by the generic (architected) timer */ 898 QEMUTimer *gt_timer[NUM_GTIMERS]; 899 /* 900 * Timer used by the PMU. Its state is restored after migration by 901 * pmu_op_finish() - it does not need other handling during migration 902 */ 903 QEMUTimer *pmu_timer; 904 /* Timer used for WFxT timeouts */ 905 QEMUTimer *wfxt_timer; 906 907 /* GPIO outputs for generic timer */ 908 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 909 /* GPIO output for GICv3 maintenance interrupt signal */ 910 qemu_irq gicv3_maintenance_interrupt; 911 /* GPIO output for the PMU interrupt */ 912 qemu_irq pmu_interrupt; 913 914 /* MemoryRegion to use for secure physical accesses */ 915 MemoryRegion *secure_memory; 916 917 /* MemoryRegion to use for allocation tag accesses */ 918 MemoryRegion *tag_memory; 919 MemoryRegion *secure_tag_memory; 920 921 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 922 Object *idau; 923 924 /* 'compatible' string for this CPU for Linux device trees */ 925 const char *dtb_compatible; 926 927 /* PSCI version for this CPU 928 * Bits[31:16] = Major Version 929 * Bits[15:0] = Minor Version 930 */ 931 uint32_t psci_version; 932 933 /* Current power state, access guarded by BQL */ 934 ARMPSCIState power_state; 935 936 /* CPU has virtualization extension */ 937 bool has_el2; 938 /* CPU has security extension */ 939 bool has_el3; 940 /* CPU has PMU (Performance Monitor Unit) */ 941 bool has_pmu; 942 /* CPU has VFP */ 943 bool has_vfp; 944 /* CPU has 32 VFP registers */ 945 bool has_vfp_d32; 946 /* CPU has Neon */ 947 bool has_neon; 948 /* CPU has M-profile DSP extension */ 949 bool has_dsp; 950 951 /* CPU has memory protection unit */ 952 bool has_mpu; 953 /* CPU has MTE enabled in KVM mode */ 954 bool kvm_mte; 955 /* PMSAv7 MPU number of supported regions */ 956 uint32_t pmsav7_dregion; 957 /* PMSAv8 MPU number of supported hyp regions */ 958 uint32_t pmsav8r_hdregion; 959 /* v8M SAU number of supported regions */ 960 uint32_t sau_sregion; 961 962 /* PSCI conduit used to invoke PSCI methods 963 * 0 - disabled, 1 - smc, 2 - hvc 964 */ 965 uint32_t psci_conduit; 966 967 /* For v8M, initial value of the Secure VTOR */ 968 uint32_t init_svtor; 969 /* For v8M, initial value of the Non-secure VTOR */ 970 uint32_t init_nsvtor; 971 972 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 973 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 974 */ 975 uint32_t kvm_target; 976 977 #ifdef CONFIG_KVM 978 /* KVM init features for this CPU */ 979 uint32_t kvm_init_features[7]; 980 981 /* KVM CPU state */ 982 983 /* KVM virtual time adjustment */ 984 bool kvm_adjvtime; 985 bool kvm_vtime_dirty; 986 uint64_t kvm_vtime; 987 988 /* KVM steal time */ 989 OnOffAuto kvm_steal_time; 990 #endif /* CONFIG_KVM */ 991 992 /* Uniprocessor system with MP extensions */ 993 bool mp_is_up; 994 995 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 996 * and the probe failed (so we need to report the error in realize) 997 */ 998 bool host_cpu_probe_failed; 999 1000 /* QOM property to indicate we should use the back-compat CNTFRQ default */ 1001 bool backcompat_cntfrq; 1002 1003 /* QOM property to indicate we should use the back-compat QARMA5 default */ 1004 bool backcompat_pauth_default_use_qarma5; 1005 1006 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 1007 * register. 1008 */ 1009 int32_t core_count; 1010 1011 /* The instance init functions for implementation-specific subclasses 1012 * set these fields to specify the implementation-dependent values of 1013 * various constant registers and reset values of non-constant 1014 * registers. 1015 * Some of these might become QOM properties eventually. 1016 * Field names match the official register names as defined in the 1017 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 1018 * is used for reset values of non-constant registers; no reset_ 1019 * prefix means a constant register. 1020 * Some of these registers are split out into a substructure that 1021 * is shared with the translators to control the ISA. 1022 * 1023 * Note that if you add an ID register to the ARMISARegisters struct 1024 * you need to also update the 32-bit and 64-bit versions of the 1025 * kvm_arm_get_host_cpu_features() function to correctly populate the 1026 * field by reading the value from the KVM vCPU. 1027 */ 1028 struct ARMISARegisters { 1029 uint32_t id_isar0; 1030 uint32_t id_isar1; 1031 uint32_t id_isar2; 1032 uint32_t id_isar3; 1033 uint32_t id_isar4; 1034 uint32_t id_isar5; 1035 uint32_t id_isar6; 1036 uint32_t id_mmfr0; 1037 uint32_t id_mmfr1; 1038 uint32_t id_mmfr2; 1039 uint32_t id_mmfr3; 1040 uint32_t id_mmfr4; 1041 uint32_t id_mmfr5; 1042 uint32_t id_pfr0; 1043 uint32_t id_pfr1; 1044 uint32_t id_pfr2; 1045 uint32_t mvfr0; 1046 uint32_t mvfr1; 1047 uint32_t mvfr2; 1048 uint32_t id_dfr0; 1049 uint32_t id_dfr1; 1050 uint32_t dbgdidr; 1051 uint32_t dbgdevid; 1052 uint32_t dbgdevid1; 1053 uint64_t id_aa64isar0; 1054 uint64_t id_aa64isar1; 1055 uint64_t id_aa64isar2; 1056 uint64_t id_aa64pfr0; 1057 uint64_t id_aa64pfr1; 1058 uint64_t id_aa64mmfr0; 1059 uint64_t id_aa64mmfr1; 1060 uint64_t id_aa64mmfr2; 1061 uint64_t id_aa64mmfr3; 1062 uint64_t id_aa64dfr0; 1063 uint64_t id_aa64dfr1; 1064 uint64_t id_aa64zfr0; 1065 uint64_t id_aa64smfr0; 1066 uint64_t reset_pmcr_el0; 1067 } isar; 1068 uint64_t midr; 1069 uint32_t revidr; 1070 uint32_t reset_fpsid; 1071 uint64_t ctr; 1072 uint32_t reset_sctlr; 1073 uint64_t pmceid0; 1074 uint64_t pmceid1; 1075 uint32_t id_afr0; 1076 uint64_t id_aa64afr0; 1077 uint64_t id_aa64afr1; 1078 uint64_t clidr; 1079 uint64_t mp_affinity; /* MP ID without feature bits */ 1080 /* The elements of this array are the CCSIDR values for each cache, 1081 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1082 */ 1083 uint64_t ccsidr[16]; 1084 uint64_t reset_cbar; 1085 uint32_t reset_auxcr; 1086 bool reset_hivecs; 1087 uint8_t reset_l0gptsz; 1088 1089 /* 1090 * Intermediate values used during property parsing. 1091 * Once finalized, the values should be read from ID_AA64*. 1092 */ 1093 bool prop_pauth; 1094 bool prop_pauth_impdef; 1095 bool prop_pauth_qarma3; 1096 bool prop_pauth_qarma5; 1097 bool prop_lpa2; 1098 1099 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1100 uint8_t dcz_blocksize; 1101 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1102 uint8_t gm_blocksize; 1103 1104 uint64_t rvbar_prop; /* Property/input signals. */ 1105 1106 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1107 int gic_num_lrs; /* number of list registers */ 1108 int gic_vpribits; /* number of virtual priority bits */ 1109 int gic_vprebits; /* number of virtual preemption bits */ 1110 int gic_pribits; /* number of physical priority bits */ 1111 1112 /* Whether the cfgend input is high (i.e. this CPU should reset into 1113 * big-endian mode). This setting isn't used directly: instead it modifies 1114 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1115 * architecture version. 1116 */ 1117 bool cfgend; 1118 1119 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1120 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1121 1122 int32_t node_id; /* NUMA node this CPU belongs to */ 1123 1124 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1125 uint8_t device_irq_level; 1126 1127 /* Used to set the maximum vector length the cpu will support. */ 1128 uint32_t sve_max_vq; 1129 1130 #ifdef CONFIG_USER_ONLY 1131 /* Used to set the default vector length at process start. */ 1132 uint32_t sve_default_vq; 1133 uint32_t sme_default_vq; 1134 #endif 1135 1136 ARMVQMap sve_vq; 1137 ARMVQMap sme_vq; 1138 1139 /* Generic timer counter frequency, in Hz */ 1140 uint64_t gt_cntfrq_hz; 1141 }; 1142 1143 typedef struct ARMCPUInfo { 1144 const char *name; 1145 const char *deprecation_note; 1146 void (*initfn)(Object *obj); 1147 void (*class_init)(ObjectClass *oc, void *data); 1148 } ARMCPUInfo; 1149 1150 /** 1151 * ARMCPUClass: 1152 * @parent_realize: The parent class' realize handler. 1153 * @parent_phases: The parent class' reset phase handlers. 1154 * 1155 * An ARM CPU model. 1156 */ 1157 struct ARMCPUClass { 1158 CPUClass parent_class; 1159 1160 const ARMCPUInfo *info; 1161 DeviceRealize parent_realize; 1162 ResettablePhases parent_phases; 1163 }; 1164 1165 struct AArch64CPUClass { 1166 ARMCPUClass parent_class; 1167 }; 1168 1169 /* Callback functions for the generic timer's timers. */ 1170 void arm_gt_ptimer_cb(void *opaque); 1171 void arm_gt_vtimer_cb(void *opaque); 1172 void arm_gt_htimer_cb(void *opaque); 1173 void arm_gt_stimer_cb(void *opaque); 1174 void arm_gt_hvtimer_cb(void *opaque); 1175 void arm_gt_sel2timer_cb(void *opaque); 1176 void arm_gt_sel2vtimer_cb(void *opaque); 1177 1178 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1179 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1180 1181 void arm_cpu_post_init(Object *obj); 1182 1183 #define ARM_AFF0_SHIFT 0 1184 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1185 #define ARM_AFF1_SHIFT 8 1186 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1187 #define ARM_AFF2_SHIFT 16 1188 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1189 #define ARM_AFF3_SHIFT 32 1190 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1191 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1192 1193 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1194 #define ARM64_AFFINITY_MASK \ 1195 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1196 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1197 1198 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1199 1200 #ifndef CONFIG_USER_ONLY 1201 extern const VMStateDescription vmstate_arm_cpu; 1202 1203 void arm_cpu_do_interrupt(CPUState *cpu); 1204 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1205 1206 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1207 MemTxAttrs *attrs); 1208 #endif /* !CONFIG_USER_ONLY */ 1209 1210 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1211 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1212 1213 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1214 int cpuid, DumpState *s); 1215 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1216 int cpuid, DumpState *s); 1217 1218 /** 1219 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1220 * @cpu: CPU (which must have been freshly reset) 1221 * @target_el: exception level to put the CPU into 1222 * @secure: whether to put the CPU in secure state 1223 * 1224 * When QEMU is directly running a guest kernel at a lower level than 1225 * EL3 it implicitly emulates some aspects of the guest firmware. 1226 * This includes that on reset we need to configure the parts of the 1227 * CPU corresponding to EL3 so that the real guest code can run at its 1228 * lower exception level. This function does that post-reset CPU setup, 1229 * for when we do direct boot of a guest kernel, and for when we 1230 * emulate PSCI and similar firmware interfaces starting a CPU at a 1231 * lower exception level. 1232 * 1233 * @target_el must be an EL implemented by the CPU between 1 and 3. 1234 * We do not support dropping into a Secure EL other than 3. 1235 * 1236 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1237 */ 1238 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1239 1240 #ifdef TARGET_AARCH64 1241 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1242 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1243 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1244 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1245 int new_el, bool el0_a64); 1246 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1247 1248 /* 1249 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1250 * The byte at offset i from the start of the in-memory representation contains 1251 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1252 * lowest offsets are stored in the lowest memory addresses, then that nearly 1253 * matches QEMU's representation, which is to use an array of host-endian 1254 * uint64_t's, where the lower offsets are at the lower indices. To complete 1255 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1256 */ 1257 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1258 { 1259 #if HOST_BIG_ENDIAN 1260 int i; 1261 1262 for (i = 0; i < nr; ++i) { 1263 dst[i] = bswap64(src[i]); 1264 } 1265 1266 return dst; 1267 #else 1268 return src; 1269 #endif 1270 } 1271 1272 #else 1273 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1274 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1275 int n, bool a) 1276 { } 1277 #endif 1278 1279 void aarch64_sync_32_to_64(CPUARMState *env); 1280 void aarch64_sync_64_to_32(CPUARMState *env); 1281 1282 int fp_exception_el(CPUARMState *env, int cur_el); 1283 int sve_exception_el(CPUARMState *env, int cur_el); 1284 int sme_exception_el(CPUARMState *env, int cur_el); 1285 1286 /** 1287 * sve_vqm1_for_el_sm: 1288 * @env: CPUARMState 1289 * @el: exception level 1290 * @sm: streaming mode 1291 * 1292 * Compute the current vector length for @el & @sm, in units of 1293 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1294 * If @sm, compute for SVL, otherwise NVL. 1295 */ 1296 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1297 1298 /* Likewise, but using @sm = PSTATE.SM. */ 1299 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1300 1301 static inline bool is_a64(CPUARMState *env) 1302 { 1303 return env->aarch64; 1304 } 1305 1306 /** 1307 * pmu_op_start/finish 1308 * @env: CPUARMState 1309 * 1310 * Convert all PMU counters between their delta form (the typical mode when 1311 * they are enabled) and the guest-visible values. These two calls must 1312 * surround any action which might affect the counters. 1313 */ 1314 void pmu_op_start(CPUARMState *env); 1315 void pmu_op_finish(CPUARMState *env); 1316 1317 /* 1318 * Called when a PMU counter is due to overflow 1319 */ 1320 void arm_pmu_timer_cb(void *opaque); 1321 1322 /** 1323 * Functions to register as EL change hooks for PMU mode filtering 1324 */ 1325 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1326 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1327 1328 /* 1329 * pmu_init 1330 * @cpu: ARMCPU 1331 * 1332 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1333 * for the current configuration 1334 */ 1335 void pmu_init(ARMCPU *cpu); 1336 1337 /* SCTLR bit meanings. Several bits have been reused in newer 1338 * versions of the architecture; in that case we define constants 1339 * for both old and new bit meanings. Code which tests against those 1340 * bits should probably check or otherwise arrange that the CPU 1341 * is the architectural version it expects. 1342 */ 1343 #define SCTLR_M (1U << 0) 1344 #define SCTLR_A (1U << 1) 1345 #define SCTLR_C (1U << 2) 1346 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1347 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1348 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1349 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1350 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1351 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1352 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1353 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1354 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1355 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1356 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1357 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1358 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1359 #define SCTLR_SED (1U << 8) /* v8 onward */ 1360 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1361 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1362 #define SCTLR_F (1U << 10) /* up to v6 */ 1363 #define SCTLR_SW (1U << 10) /* v7 */ 1364 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1365 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1366 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1367 #define SCTLR_I (1U << 12) 1368 #define SCTLR_V (1U << 13) /* AArch32 only */ 1369 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1370 #define SCTLR_RR (1U << 14) /* up to v7 */ 1371 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1372 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1373 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1374 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1375 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1376 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1377 #define SCTLR_BR (1U << 17) /* PMSA only */ 1378 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1379 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1380 #define SCTLR_WXN (1U << 19) 1381 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1382 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1383 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1384 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1385 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1386 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1387 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1388 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1389 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1390 #define SCTLR_VE (1U << 24) /* up to v7 */ 1391 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1392 #define SCTLR_EE (1U << 25) 1393 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1394 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1395 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1396 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1397 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1398 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1399 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1400 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1401 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1402 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1403 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1404 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1405 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */ 1406 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1407 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1408 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1409 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1410 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1411 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1412 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1413 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1414 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1415 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1416 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1417 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1418 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1419 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1420 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1421 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1422 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1423 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1424 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1425 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1426 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1427 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1428 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1429 1430 #define CPSR_M (0x1fU) 1431 #define CPSR_T (1U << 5) 1432 #define CPSR_F (1U << 6) 1433 #define CPSR_I (1U << 7) 1434 #define CPSR_A (1U << 8) 1435 #define CPSR_E (1U << 9) 1436 #define CPSR_IT_2_7 (0xfc00U) 1437 #define CPSR_GE (0xfU << 16) 1438 #define CPSR_IL (1U << 20) 1439 #define CPSR_DIT (1U << 21) 1440 #define CPSR_PAN (1U << 22) 1441 #define CPSR_SSBS (1U << 23) 1442 #define CPSR_J (1U << 24) 1443 #define CPSR_IT_0_1 (3U << 25) 1444 #define CPSR_Q (1U << 27) 1445 #define CPSR_V (1U << 28) 1446 #define CPSR_C (1U << 29) 1447 #define CPSR_Z (1U << 30) 1448 #define CPSR_N (1U << 31) 1449 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1450 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1451 #define ISR_FS (1U << 9) 1452 #define ISR_IS (1U << 10) 1453 1454 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1455 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1456 | CPSR_NZCV) 1457 /* Bits writable in user mode. */ 1458 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1459 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1460 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1461 1462 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1463 #define XPSR_EXCP 0x1ffU 1464 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1465 #define XPSR_IT_2_7 CPSR_IT_2_7 1466 #define XPSR_GE CPSR_GE 1467 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1468 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1469 #define XPSR_IT_0_1 CPSR_IT_0_1 1470 #define XPSR_Q CPSR_Q 1471 #define XPSR_V CPSR_V 1472 #define XPSR_C CPSR_C 1473 #define XPSR_Z CPSR_Z 1474 #define XPSR_N CPSR_N 1475 #define XPSR_NZCV CPSR_NZCV 1476 #define XPSR_IT CPSR_IT 1477 1478 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1479 * Only these are valid when in AArch64 mode; in 1480 * AArch32 mode SPSRs are basically CPSR-format. 1481 */ 1482 #define PSTATE_SP (1U) 1483 #define PSTATE_M (0xFU) 1484 #define PSTATE_nRW (1U << 4) 1485 #define PSTATE_F (1U << 6) 1486 #define PSTATE_I (1U << 7) 1487 #define PSTATE_A (1U << 8) 1488 #define PSTATE_D (1U << 9) 1489 #define PSTATE_BTYPE (3U << 10) 1490 #define PSTATE_SSBS (1U << 12) 1491 #define PSTATE_ALLINT (1U << 13) 1492 #define PSTATE_IL (1U << 20) 1493 #define PSTATE_SS (1U << 21) 1494 #define PSTATE_PAN (1U << 22) 1495 #define PSTATE_UAO (1U << 23) 1496 #define PSTATE_DIT (1U << 24) 1497 #define PSTATE_TCO (1U << 25) 1498 #define PSTATE_V (1U << 28) 1499 #define PSTATE_C (1U << 29) 1500 #define PSTATE_Z (1U << 30) 1501 #define PSTATE_N (1U << 31) 1502 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1503 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1504 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1505 /* Mode values for AArch64 */ 1506 #define PSTATE_MODE_EL3h 13 1507 #define PSTATE_MODE_EL3t 12 1508 #define PSTATE_MODE_EL2h 9 1509 #define PSTATE_MODE_EL2t 8 1510 #define PSTATE_MODE_EL1h 5 1511 #define PSTATE_MODE_EL1t 4 1512 #define PSTATE_MODE_EL0t 0 1513 1514 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1515 FIELD(SVCR, SM, 0, 1) 1516 FIELD(SVCR, ZA, 1, 1) 1517 1518 /* Fields for SMCR_ELx. */ 1519 FIELD(SMCR, LEN, 0, 4) 1520 FIELD(SMCR, FA64, 31, 1) 1521 1522 /* Write a new value to v7m.exception, thus transitioning into or out 1523 * of Handler mode; this may result in a change of active stack pointer. 1524 */ 1525 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1526 1527 /* Map EL and handler into a PSTATE_MODE. */ 1528 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1529 { 1530 return (el << 2) | handler; 1531 } 1532 1533 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1534 * interprocessing, so we don't attempt to sync with the cpsr state used by 1535 * the 32 bit decoder. 1536 */ 1537 static inline uint32_t pstate_read(CPUARMState *env) 1538 { 1539 int ZF; 1540 1541 ZF = (env->ZF == 0); 1542 return (env->NF & 0x80000000) | (ZF << 30) 1543 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1544 | env->pstate | env->daif | (env->btype << 10); 1545 } 1546 1547 static inline void pstate_write(CPUARMState *env, uint32_t val) 1548 { 1549 env->ZF = (~val) & PSTATE_Z; 1550 env->NF = val; 1551 env->CF = (val >> 29) & 1; 1552 env->VF = (val << 3) & 0x80000000; 1553 env->daif = val & PSTATE_DAIF; 1554 env->btype = (val >> 10) & 3; 1555 env->pstate = val & ~CACHED_PSTATE_BITS; 1556 } 1557 1558 /* Return the current CPSR value. */ 1559 uint32_t cpsr_read(CPUARMState *env); 1560 1561 typedef enum CPSRWriteType { 1562 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1563 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1564 CPSRWriteRaw = 2, 1565 /* trust values, no reg bank switch, no hflags rebuild */ 1566 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1567 } CPSRWriteType; 1568 1569 /* 1570 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1571 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1572 * correspond to TB flags bits cached in the hflags, unless @write_type 1573 * is CPSRWriteRaw. 1574 */ 1575 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1576 CPSRWriteType write_type); 1577 1578 /* Return the current xPSR value. */ 1579 static inline uint32_t xpsr_read(CPUARMState *env) 1580 { 1581 int ZF; 1582 ZF = (env->ZF == 0); 1583 return (env->NF & 0x80000000) | (ZF << 30) 1584 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1585 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1586 | ((env->condexec_bits & 0xfc) << 8) 1587 | (env->GE << 16) 1588 | env->v7m.exception; 1589 } 1590 1591 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1592 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1593 { 1594 if (mask & XPSR_NZCV) { 1595 env->ZF = (~val) & XPSR_Z; 1596 env->NF = val; 1597 env->CF = (val >> 29) & 1; 1598 env->VF = (val << 3) & 0x80000000; 1599 } 1600 if (mask & XPSR_Q) { 1601 env->QF = ((val & XPSR_Q) != 0); 1602 } 1603 if (mask & XPSR_GE) { 1604 env->GE = (val & XPSR_GE) >> 16; 1605 } 1606 #ifndef CONFIG_USER_ONLY 1607 if (mask & XPSR_T) { 1608 env->thumb = ((val & XPSR_T) != 0); 1609 } 1610 if (mask & XPSR_IT_0_1) { 1611 env->condexec_bits &= ~3; 1612 env->condexec_bits |= (val >> 25) & 3; 1613 } 1614 if (mask & XPSR_IT_2_7) { 1615 env->condexec_bits &= 3; 1616 env->condexec_bits |= (val >> 8) & 0xfc; 1617 } 1618 if (mask & XPSR_EXCP) { 1619 /* Note that this only happens on exception exit */ 1620 write_v7m_exception(env, val & XPSR_EXCP); 1621 } 1622 #endif 1623 } 1624 1625 #define HCR_VM (1ULL << 0) 1626 #define HCR_SWIO (1ULL << 1) 1627 #define HCR_PTW (1ULL << 2) 1628 #define HCR_FMO (1ULL << 3) 1629 #define HCR_IMO (1ULL << 4) 1630 #define HCR_AMO (1ULL << 5) 1631 #define HCR_VF (1ULL << 6) 1632 #define HCR_VI (1ULL << 7) 1633 #define HCR_VSE (1ULL << 8) 1634 #define HCR_FB (1ULL << 9) 1635 #define HCR_BSU_MASK (3ULL << 10) 1636 #define HCR_DC (1ULL << 12) 1637 #define HCR_TWI (1ULL << 13) 1638 #define HCR_TWE (1ULL << 14) 1639 #define HCR_TID0 (1ULL << 15) 1640 #define HCR_TID1 (1ULL << 16) 1641 #define HCR_TID2 (1ULL << 17) 1642 #define HCR_TID3 (1ULL << 18) 1643 #define HCR_TSC (1ULL << 19) 1644 #define HCR_TIDCP (1ULL << 20) 1645 #define HCR_TACR (1ULL << 21) 1646 #define HCR_TSW (1ULL << 22) 1647 #define HCR_TPCP (1ULL << 23) 1648 #define HCR_TPU (1ULL << 24) 1649 #define HCR_TTLB (1ULL << 25) 1650 #define HCR_TVM (1ULL << 26) 1651 #define HCR_TGE (1ULL << 27) 1652 #define HCR_TDZ (1ULL << 28) 1653 #define HCR_HCD (1ULL << 29) 1654 #define HCR_TRVM (1ULL << 30) 1655 #define HCR_RW (1ULL << 31) 1656 #define HCR_CD (1ULL << 32) 1657 #define HCR_ID (1ULL << 33) 1658 #define HCR_E2H (1ULL << 34) 1659 #define HCR_TLOR (1ULL << 35) 1660 #define HCR_TERR (1ULL << 36) 1661 #define HCR_TEA (1ULL << 37) 1662 #define HCR_MIOCNCE (1ULL << 38) 1663 #define HCR_TME (1ULL << 39) 1664 #define HCR_APK (1ULL << 40) 1665 #define HCR_API (1ULL << 41) 1666 #define HCR_NV (1ULL << 42) 1667 #define HCR_NV1 (1ULL << 43) 1668 #define HCR_AT (1ULL << 44) 1669 #define HCR_NV2 (1ULL << 45) 1670 #define HCR_FWB (1ULL << 46) 1671 #define HCR_FIEN (1ULL << 47) 1672 #define HCR_GPF (1ULL << 48) 1673 #define HCR_TID4 (1ULL << 49) 1674 #define HCR_TICAB (1ULL << 50) 1675 #define HCR_AMVOFFEN (1ULL << 51) 1676 #define HCR_TOCU (1ULL << 52) 1677 #define HCR_ENSCXT (1ULL << 53) 1678 #define HCR_TTLBIS (1ULL << 54) 1679 #define HCR_TTLBOS (1ULL << 55) 1680 #define HCR_ATA (1ULL << 56) 1681 #define HCR_DCT (1ULL << 57) 1682 #define HCR_TID5 (1ULL << 58) 1683 #define HCR_TWEDEN (1ULL << 59) 1684 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1685 1686 #define SCR_NS (1ULL << 0) 1687 #define SCR_IRQ (1ULL << 1) 1688 #define SCR_FIQ (1ULL << 2) 1689 #define SCR_EA (1ULL << 3) 1690 #define SCR_FW (1ULL << 4) 1691 #define SCR_AW (1ULL << 5) 1692 #define SCR_NET (1ULL << 6) 1693 #define SCR_SMD (1ULL << 7) 1694 #define SCR_HCE (1ULL << 8) 1695 #define SCR_SIF (1ULL << 9) 1696 #define SCR_RW (1ULL << 10) 1697 #define SCR_ST (1ULL << 11) 1698 #define SCR_TWI (1ULL << 12) 1699 #define SCR_TWE (1ULL << 13) 1700 #define SCR_TLOR (1ULL << 14) 1701 #define SCR_TERR (1ULL << 15) 1702 #define SCR_APK (1ULL << 16) 1703 #define SCR_API (1ULL << 17) 1704 #define SCR_EEL2 (1ULL << 18) 1705 #define SCR_EASE (1ULL << 19) 1706 #define SCR_NMEA (1ULL << 20) 1707 #define SCR_FIEN (1ULL << 21) 1708 #define SCR_ENSCXT (1ULL << 25) 1709 #define SCR_ATA (1ULL << 26) 1710 #define SCR_FGTEN (1ULL << 27) 1711 #define SCR_ECVEN (1ULL << 28) 1712 #define SCR_TWEDEN (1ULL << 29) 1713 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1714 #define SCR_TME (1ULL << 34) 1715 #define SCR_AMVOFFEN (1ULL << 35) 1716 #define SCR_ENAS0 (1ULL << 36) 1717 #define SCR_ADEN (1ULL << 37) 1718 #define SCR_HXEN (1ULL << 38) 1719 #define SCR_TRNDR (1ULL << 40) 1720 #define SCR_ENTP2 (1ULL << 41) 1721 #define SCR_GPF (1ULL << 48) 1722 #define SCR_NSE (1ULL << 62) 1723 1724 /* Return the current FPSCR value. */ 1725 uint32_t vfp_get_fpscr(CPUARMState *env); 1726 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1727 1728 /* 1729 * FPCR, Floating Point Control Register 1730 * FPSR, Floating Point Status Register 1731 * 1732 * For A64 floating point control and status bits are stored in 1733 * two logically distinct registers, FPCR and FPSR. We store these 1734 * in QEMU in vfp.fpcr and vfp.fpsr. 1735 * For A32 there was only one register, FPSCR. The bits are arranged 1736 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions, 1737 * so we can use appropriate masking to handle FPSCR reads and writes. 1738 * Note that the FPCR has some bits which are not visible in the 1739 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged. 1740 */ 1741 1742 /* FPCR bits */ 1743 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */ 1744 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */ 1745 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */ 1746 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1747 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1748 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1749 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1750 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1751 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */ 1752 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1753 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */ 1754 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1755 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */ 1756 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1757 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1758 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1759 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1760 1761 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1762 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1763 #define FPCR_LTPSIZE_LENGTH 3 1764 1765 /* Cumulative exception trap enable bits */ 1766 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE) 1767 1768 /* FPSR bits */ 1769 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */ 1770 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */ 1771 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */ 1772 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */ 1773 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */ 1774 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */ 1775 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */ 1776 #define FPSR_V (1 << 28) /* FP overflow flag */ 1777 #define FPSR_C (1 << 29) /* FP carry flag */ 1778 #define FPSR_Z (1 << 30) /* FP zero flag */ 1779 #define FPSR_N (1 << 31) /* FP negative flag */ 1780 1781 /* Cumulative exception status bits */ 1782 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC) 1783 1784 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V) 1785 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC) 1786 1787 /* A32 FPSCR bits which architecturally map to FPSR bits */ 1788 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK) 1789 /* A32 FPSCR bits which architecturally map to FPCR bits */ 1790 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \ 1791 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \ 1792 FPCR_FZ | FPCR_DN | FPCR_AHP) 1793 /* These masks don't overlap: each bit lives in only one place */ 1794 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK); 1795 1796 /** 1797 * vfp_get_fpsr: read the AArch64 FPSR 1798 * @env: CPU context 1799 * 1800 * Return the current AArch64 FPSR value 1801 */ 1802 uint32_t vfp_get_fpsr(CPUARMState *env); 1803 1804 /** 1805 * vfp_get_fpcr: read the AArch64 FPCR 1806 * @env: CPU context 1807 * 1808 * Return the current AArch64 FPCR value 1809 */ 1810 uint32_t vfp_get_fpcr(CPUARMState *env); 1811 1812 /** 1813 * vfp_set_fpsr: write the AArch64 FPSR 1814 * @env: CPU context 1815 * @value: new value 1816 */ 1817 void vfp_set_fpsr(CPUARMState *env, uint32_t value); 1818 1819 /** 1820 * vfp_set_fpcr: write the AArch64 FPCR 1821 * @env: CPU context 1822 * @value: new value 1823 */ 1824 void vfp_set_fpcr(CPUARMState *env, uint32_t value); 1825 1826 enum arm_cpu_mode { 1827 ARM_CPU_MODE_USR = 0x10, 1828 ARM_CPU_MODE_FIQ = 0x11, 1829 ARM_CPU_MODE_IRQ = 0x12, 1830 ARM_CPU_MODE_SVC = 0x13, 1831 ARM_CPU_MODE_MON = 0x16, 1832 ARM_CPU_MODE_ABT = 0x17, 1833 ARM_CPU_MODE_HYP = 0x1a, 1834 ARM_CPU_MODE_UND = 0x1b, 1835 ARM_CPU_MODE_SYS = 0x1f 1836 }; 1837 1838 /* VFP system registers. */ 1839 #define ARM_VFP_FPSID 0 1840 #define ARM_VFP_FPSCR 1 1841 #define ARM_VFP_MVFR2 5 1842 #define ARM_VFP_MVFR1 6 1843 #define ARM_VFP_MVFR0 7 1844 #define ARM_VFP_FPEXC 8 1845 #define ARM_VFP_FPINST 9 1846 #define ARM_VFP_FPINST2 10 1847 /* These ones are M-profile only */ 1848 #define ARM_VFP_FPSCR_NZCVQC 2 1849 #define ARM_VFP_VPR 12 1850 #define ARM_VFP_P0 13 1851 #define ARM_VFP_FPCXT_NS 14 1852 #define ARM_VFP_FPCXT_S 15 1853 1854 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1855 #define QEMU_VFP_FPSCR_NZCV 0xffff 1856 1857 /* iwMMXt coprocessor control registers. */ 1858 #define ARM_IWMMXT_wCID 0 1859 #define ARM_IWMMXT_wCon 1 1860 #define ARM_IWMMXT_wCSSF 2 1861 #define ARM_IWMMXT_wCASF 3 1862 #define ARM_IWMMXT_wCGR0 8 1863 #define ARM_IWMMXT_wCGR1 9 1864 #define ARM_IWMMXT_wCGR2 10 1865 #define ARM_IWMMXT_wCGR3 11 1866 1867 /* V7M CCR bits */ 1868 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1869 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1870 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1871 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1872 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1873 FIELD(V7M_CCR, STKALIGN, 9, 1) 1874 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1875 FIELD(V7M_CCR, DC, 16, 1) 1876 FIELD(V7M_CCR, IC, 17, 1) 1877 FIELD(V7M_CCR, BP, 18, 1) 1878 FIELD(V7M_CCR, LOB, 19, 1) 1879 FIELD(V7M_CCR, TRD, 20, 1) 1880 1881 /* V7M SCR bits */ 1882 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1883 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1884 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1885 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1886 1887 /* V7M AIRCR bits */ 1888 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1889 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1890 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1891 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1892 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1893 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1894 FIELD(V7M_AIRCR, PRIS, 14, 1) 1895 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1896 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1897 1898 /* V7M CFSR bits for MMFSR */ 1899 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1900 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1901 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1902 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1903 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1904 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1905 1906 /* V7M CFSR bits for BFSR */ 1907 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1908 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1909 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1910 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1911 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1912 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1913 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1914 1915 /* V7M CFSR bits for UFSR */ 1916 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1917 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1918 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1919 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1920 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1921 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1922 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1923 1924 /* V7M CFSR bit masks covering all of the subregister bits */ 1925 FIELD(V7M_CFSR, MMFSR, 0, 8) 1926 FIELD(V7M_CFSR, BFSR, 8, 8) 1927 FIELD(V7M_CFSR, UFSR, 16, 16) 1928 1929 /* V7M HFSR bits */ 1930 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1931 FIELD(V7M_HFSR, FORCED, 30, 1) 1932 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1933 1934 /* V7M DFSR bits */ 1935 FIELD(V7M_DFSR, HALTED, 0, 1) 1936 FIELD(V7M_DFSR, BKPT, 1, 1) 1937 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1938 FIELD(V7M_DFSR, VCATCH, 3, 1) 1939 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1940 1941 /* V7M SFSR bits */ 1942 FIELD(V7M_SFSR, INVEP, 0, 1) 1943 FIELD(V7M_SFSR, INVIS, 1, 1) 1944 FIELD(V7M_SFSR, INVER, 2, 1) 1945 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1946 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1947 FIELD(V7M_SFSR, LSPERR, 5, 1) 1948 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1949 FIELD(V7M_SFSR, LSERR, 7, 1) 1950 1951 /* v7M MPU_CTRL bits */ 1952 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1953 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1954 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1955 1956 /* v7M CLIDR bits */ 1957 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1958 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1959 FIELD(V7M_CLIDR, LOC, 24, 3) 1960 FIELD(V7M_CLIDR, LOUU, 27, 3) 1961 FIELD(V7M_CLIDR, ICB, 30, 2) 1962 1963 FIELD(V7M_CSSELR, IND, 0, 1) 1964 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1965 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1966 * define a mask for this and check that it doesn't permit running off 1967 * the end of the array. 1968 */ 1969 FIELD(V7M_CSSELR, INDEX, 0, 4) 1970 1971 /* v7M FPCCR bits */ 1972 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1973 FIELD(V7M_FPCCR, USER, 1, 1) 1974 FIELD(V7M_FPCCR, S, 2, 1) 1975 FIELD(V7M_FPCCR, THREAD, 3, 1) 1976 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1977 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1978 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1979 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1980 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1981 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1982 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1983 FIELD(V7M_FPCCR, RES0, 11, 15) 1984 FIELD(V7M_FPCCR, TS, 26, 1) 1985 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1986 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1987 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1988 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1989 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1990 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1991 #define R_V7M_FPCCR_BANKED_MASK \ 1992 (R_V7M_FPCCR_LSPACT_MASK | \ 1993 R_V7M_FPCCR_USER_MASK | \ 1994 R_V7M_FPCCR_THREAD_MASK | \ 1995 R_V7M_FPCCR_MMRDY_MASK | \ 1996 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1997 R_V7M_FPCCR_UFRDY_MASK | \ 1998 R_V7M_FPCCR_ASPEN_MASK) 1999 2000 /* v7M VPR bits */ 2001 FIELD(V7M_VPR, P0, 0, 16) 2002 FIELD(V7M_VPR, MASK01, 16, 4) 2003 FIELD(V7M_VPR, MASK23, 20, 4) 2004 2005 /* 2006 * System register ID fields. 2007 */ 2008 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2009 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2010 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2011 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2012 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2013 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2014 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2015 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2016 FIELD(CLIDR_EL1, LOC, 24, 3) 2017 FIELD(CLIDR_EL1, LOUU, 27, 3) 2018 FIELD(CLIDR_EL1, ICB, 30, 3) 2019 2020 /* When FEAT_CCIDX is implemented */ 2021 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2022 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2023 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2024 2025 /* When FEAT_CCIDX is not implemented */ 2026 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2027 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2028 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2029 2030 FIELD(CTR_EL0, IMINLINE, 0, 4) 2031 FIELD(CTR_EL0, L1IP, 14, 2) 2032 FIELD(CTR_EL0, DMINLINE, 16, 4) 2033 FIELD(CTR_EL0, ERG, 20, 4) 2034 FIELD(CTR_EL0, CWG, 24, 4) 2035 FIELD(CTR_EL0, IDC, 28, 1) 2036 FIELD(CTR_EL0, DIC, 29, 1) 2037 FIELD(CTR_EL0, TMINLINE, 32, 6) 2038 2039 FIELD(MIDR_EL1, REVISION, 0, 4) 2040 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2041 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2042 FIELD(MIDR_EL1, VARIANT, 20, 4) 2043 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2044 2045 FIELD(ID_ISAR0, SWAP, 0, 4) 2046 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2047 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2048 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2049 FIELD(ID_ISAR0, COPROC, 16, 4) 2050 FIELD(ID_ISAR0, DEBUG, 20, 4) 2051 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2052 2053 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2054 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2055 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2056 FIELD(ID_ISAR1, EXTEND, 12, 4) 2057 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2058 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2059 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2060 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2061 2062 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2063 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2064 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2065 FIELD(ID_ISAR2, MULT, 12, 4) 2066 FIELD(ID_ISAR2, MULTS, 16, 4) 2067 FIELD(ID_ISAR2, MULTU, 20, 4) 2068 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2069 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2070 2071 FIELD(ID_ISAR3, SATURATE, 0, 4) 2072 FIELD(ID_ISAR3, SIMD, 4, 4) 2073 FIELD(ID_ISAR3, SVC, 8, 4) 2074 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2075 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2076 FIELD(ID_ISAR3, T32COPY, 20, 4) 2077 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2078 FIELD(ID_ISAR3, T32EE, 28, 4) 2079 2080 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2081 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2082 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2083 FIELD(ID_ISAR4, SMC, 12, 4) 2084 FIELD(ID_ISAR4, BARRIER, 16, 4) 2085 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2086 FIELD(ID_ISAR4, PSR_M, 24, 4) 2087 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2088 2089 FIELD(ID_ISAR5, SEVL, 0, 4) 2090 FIELD(ID_ISAR5, AES, 4, 4) 2091 FIELD(ID_ISAR5, SHA1, 8, 4) 2092 FIELD(ID_ISAR5, SHA2, 12, 4) 2093 FIELD(ID_ISAR5, CRC32, 16, 4) 2094 FIELD(ID_ISAR5, RDM, 24, 4) 2095 FIELD(ID_ISAR5, VCMA, 28, 4) 2096 2097 FIELD(ID_ISAR6, JSCVT, 0, 4) 2098 FIELD(ID_ISAR6, DP, 4, 4) 2099 FIELD(ID_ISAR6, FHM, 8, 4) 2100 FIELD(ID_ISAR6, SB, 12, 4) 2101 FIELD(ID_ISAR6, SPECRES, 16, 4) 2102 FIELD(ID_ISAR6, BF16, 20, 4) 2103 FIELD(ID_ISAR6, I8MM, 24, 4) 2104 2105 FIELD(ID_MMFR0, VMSA, 0, 4) 2106 FIELD(ID_MMFR0, PMSA, 4, 4) 2107 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2108 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2109 FIELD(ID_MMFR0, TCM, 16, 4) 2110 FIELD(ID_MMFR0, AUXREG, 20, 4) 2111 FIELD(ID_MMFR0, FCSE, 24, 4) 2112 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2113 2114 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2115 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2116 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2117 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2118 FIELD(ID_MMFR1, L1HVD, 16, 4) 2119 FIELD(ID_MMFR1, L1UNI, 20, 4) 2120 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2121 FIELD(ID_MMFR1, BPRED, 28, 4) 2122 2123 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2124 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2125 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2126 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2127 FIELD(ID_MMFR2, UNITLB, 16, 4) 2128 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2129 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2130 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2131 2132 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2133 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2134 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2135 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2136 FIELD(ID_MMFR3, PAN, 16, 4) 2137 FIELD(ID_MMFR3, COHWALK, 20, 4) 2138 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2139 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2140 2141 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2142 FIELD(ID_MMFR4, AC2, 4, 4) 2143 FIELD(ID_MMFR4, XNX, 8, 4) 2144 FIELD(ID_MMFR4, CNP, 12, 4) 2145 FIELD(ID_MMFR4, HPDS, 16, 4) 2146 FIELD(ID_MMFR4, LSM, 20, 4) 2147 FIELD(ID_MMFR4, CCIDX, 24, 4) 2148 FIELD(ID_MMFR4, EVT, 28, 4) 2149 2150 FIELD(ID_MMFR5, ETS, 0, 4) 2151 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2152 2153 FIELD(ID_PFR0, STATE0, 0, 4) 2154 FIELD(ID_PFR0, STATE1, 4, 4) 2155 FIELD(ID_PFR0, STATE2, 8, 4) 2156 FIELD(ID_PFR0, STATE3, 12, 4) 2157 FIELD(ID_PFR0, CSV2, 16, 4) 2158 FIELD(ID_PFR0, AMU, 20, 4) 2159 FIELD(ID_PFR0, DIT, 24, 4) 2160 FIELD(ID_PFR0, RAS, 28, 4) 2161 2162 FIELD(ID_PFR1, PROGMOD, 0, 4) 2163 FIELD(ID_PFR1, SECURITY, 4, 4) 2164 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2165 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2166 FIELD(ID_PFR1, GENTIMER, 16, 4) 2167 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2168 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2169 FIELD(ID_PFR1, GIC, 28, 4) 2170 2171 FIELD(ID_PFR2, CSV3, 0, 4) 2172 FIELD(ID_PFR2, SSBS, 4, 4) 2173 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2174 2175 FIELD(ID_AA64ISAR0, AES, 4, 4) 2176 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2177 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2178 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2179 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2180 FIELD(ID_AA64ISAR0, TME, 24, 4) 2181 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2182 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2183 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2184 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2185 FIELD(ID_AA64ISAR0, DP, 44, 4) 2186 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2187 FIELD(ID_AA64ISAR0, TS, 52, 4) 2188 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2189 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2190 2191 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2192 FIELD(ID_AA64ISAR1, APA, 4, 4) 2193 FIELD(ID_AA64ISAR1, API, 8, 4) 2194 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2195 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2196 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2197 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2198 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2199 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2200 FIELD(ID_AA64ISAR1, SB, 36, 4) 2201 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2202 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2203 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2204 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2205 FIELD(ID_AA64ISAR1, XS, 56, 4) 2206 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2207 2208 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2209 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2210 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2211 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2212 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2213 FIELD(ID_AA64ISAR2, BC, 20, 4) 2214 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2215 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2216 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2217 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2218 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2219 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2220 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2221 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2222 2223 FIELD(ID_AA64PFR0, EL0, 0, 4) 2224 FIELD(ID_AA64PFR0, EL1, 4, 4) 2225 FIELD(ID_AA64PFR0, EL2, 8, 4) 2226 FIELD(ID_AA64PFR0, EL3, 12, 4) 2227 FIELD(ID_AA64PFR0, FP, 16, 4) 2228 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2229 FIELD(ID_AA64PFR0, GIC, 24, 4) 2230 FIELD(ID_AA64PFR0, RAS, 28, 4) 2231 FIELD(ID_AA64PFR0, SVE, 32, 4) 2232 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2233 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2234 FIELD(ID_AA64PFR0, AMU, 44, 4) 2235 FIELD(ID_AA64PFR0, DIT, 48, 4) 2236 FIELD(ID_AA64PFR0, RME, 52, 4) 2237 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2238 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2239 2240 FIELD(ID_AA64PFR1, BT, 0, 4) 2241 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2242 FIELD(ID_AA64PFR1, MTE, 8, 4) 2243 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2244 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2245 FIELD(ID_AA64PFR1, SME, 24, 4) 2246 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2247 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2248 FIELD(ID_AA64PFR1, NMI, 36, 4) 2249 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2250 FIELD(ID_AA64PFR1, GCS, 44, 4) 2251 FIELD(ID_AA64PFR1, THE, 48, 4) 2252 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2253 FIELD(ID_AA64PFR1, DF2, 56, 4) 2254 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2255 2256 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2257 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2258 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2259 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2260 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2261 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2262 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2263 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2264 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2265 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2266 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2267 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2268 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2269 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2270 2271 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2272 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2273 FIELD(ID_AA64MMFR1, VH, 8, 4) 2274 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2275 FIELD(ID_AA64MMFR1, LO, 16, 4) 2276 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2277 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2278 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2279 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2280 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2281 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2282 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2283 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2284 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2285 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2286 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2287 2288 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2289 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2290 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2291 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2292 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2293 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2294 FIELD(ID_AA64MMFR2, NV, 24, 4) 2295 FIELD(ID_AA64MMFR2, ST, 28, 4) 2296 FIELD(ID_AA64MMFR2, AT, 32, 4) 2297 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2298 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2299 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2300 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2301 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2302 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2303 2304 FIELD(ID_AA64MMFR3, TCRX, 0, 4) 2305 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) 2306 FIELD(ID_AA64MMFR3, S1PIE, 8, 4) 2307 FIELD(ID_AA64MMFR3, S2PIE, 12, 4) 2308 FIELD(ID_AA64MMFR3, S1POE, 16, 4) 2309 FIELD(ID_AA64MMFR3, S2POE, 20, 4) 2310 FIELD(ID_AA64MMFR3, AIE, 24, 4) 2311 FIELD(ID_AA64MMFR3, MEC, 28, 4) 2312 FIELD(ID_AA64MMFR3, D128, 32, 4) 2313 FIELD(ID_AA64MMFR3, D128_2, 36, 4) 2314 FIELD(ID_AA64MMFR3, SNERR, 40, 4) 2315 FIELD(ID_AA64MMFR3, ANERR, 44, 4) 2316 FIELD(ID_AA64MMFR3, SDERR, 52, 4) 2317 FIELD(ID_AA64MMFR3, ADERR, 56, 4) 2318 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) 2319 2320 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2321 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2322 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2323 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2324 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2325 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2326 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2327 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2328 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2329 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2330 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2331 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2332 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2333 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2334 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2335 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2336 2337 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2338 FIELD(ID_AA64ZFR0, AES, 4, 4) 2339 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2340 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2341 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2342 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2343 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2344 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2345 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2346 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2347 2348 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2349 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2350 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2351 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2352 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2353 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2354 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2355 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2356 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2357 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2358 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2359 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2360 2361 FIELD(ID_DFR0, COPDBG, 0, 4) 2362 FIELD(ID_DFR0, COPSDBG, 4, 4) 2363 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2364 FIELD(ID_DFR0, COPTRC, 12, 4) 2365 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2366 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2367 FIELD(ID_DFR0, PERFMON, 24, 4) 2368 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2369 2370 FIELD(ID_DFR1, MTPMU, 0, 4) 2371 FIELD(ID_DFR1, HPMN0, 4, 4) 2372 2373 FIELD(DBGDIDR, SE_IMP, 12, 1) 2374 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2375 FIELD(DBGDIDR, VERSION, 16, 4) 2376 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2377 FIELD(DBGDIDR, BRPS, 24, 4) 2378 FIELD(DBGDIDR, WRPS, 28, 4) 2379 2380 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2381 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2382 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2383 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2384 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2385 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2386 FIELD(DBGDEVID, AUXREGS, 24, 4) 2387 FIELD(DBGDEVID, CIDMASK, 28, 4) 2388 2389 FIELD(DBGDEVID1, PCSROFFSET, 0, 4) 2390 2391 FIELD(MVFR0, SIMDREG, 0, 4) 2392 FIELD(MVFR0, FPSP, 4, 4) 2393 FIELD(MVFR0, FPDP, 8, 4) 2394 FIELD(MVFR0, FPTRAP, 12, 4) 2395 FIELD(MVFR0, FPDIVIDE, 16, 4) 2396 FIELD(MVFR0, FPSQRT, 20, 4) 2397 FIELD(MVFR0, FPSHVEC, 24, 4) 2398 FIELD(MVFR0, FPROUND, 28, 4) 2399 2400 FIELD(MVFR1, FPFTZ, 0, 4) 2401 FIELD(MVFR1, FPDNAN, 4, 4) 2402 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2403 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2404 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2405 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2406 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2407 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2408 FIELD(MVFR1, FPHP, 24, 4) 2409 FIELD(MVFR1, SIMDFMAC, 28, 4) 2410 2411 FIELD(MVFR2, SIMDMISC, 0, 4) 2412 FIELD(MVFR2, FPMISC, 4, 4) 2413 2414 FIELD(GPCCR, PPS, 0, 3) 2415 FIELD(GPCCR, IRGN, 8, 2) 2416 FIELD(GPCCR, ORGN, 10, 2) 2417 FIELD(GPCCR, SH, 12, 2) 2418 FIELD(GPCCR, PGS, 14, 2) 2419 FIELD(GPCCR, GPC, 16, 1) 2420 FIELD(GPCCR, GPCP, 17, 1) 2421 FIELD(GPCCR, L0GPTSZ, 20, 4) 2422 2423 FIELD(MFAR, FPA, 12, 40) 2424 FIELD(MFAR, NSE, 62, 1) 2425 FIELD(MFAR, NS, 63, 1) 2426 2427 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2428 2429 /* If adding a feature bit which corresponds to a Linux ELF 2430 * HWCAP bit, remember to update the feature-bit-to-hwcap 2431 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2432 */ 2433 enum arm_features { 2434 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2435 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2436 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2437 ARM_FEATURE_V6, 2438 ARM_FEATURE_V6K, 2439 ARM_FEATURE_V7, 2440 ARM_FEATURE_THUMB2, 2441 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2442 ARM_FEATURE_NEON, 2443 ARM_FEATURE_M, /* Microcontroller profile. */ 2444 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2445 ARM_FEATURE_THUMB2EE, 2446 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2447 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2448 ARM_FEATURE_V4T, 2449 ARM_FEATURE_V5, 2450 ARM_FEATURE_STRONGARM, 2451 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2452 ARM_FEATURE_GENERIC_TIMER, 2453 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2454 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2455 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2456 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2457 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2458 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2459 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2460 ARM_FEATURE_V8, 2461 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2462 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2463 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2464 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2465 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2466 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2467 ARM_FEATURE_PMU, /* has PMU support */ 2468 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2469 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2470 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2471 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2472 /* 2473 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz 2474 * if the board doesn't set a value, instead of 1GHz. It is for backwards 2475 * compatibility and used only with CPU definitions that were already 2476 * in QEMU before we changed the default. It should not be set on any 2477 * CPU types added in future. 2478 */ 2479 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ 2480 }; 2481 2482 static inline int arm_feature(CPUARMState *env, int feature) 2483 { 2484 return (env->features & (1ULL << feature)) != 0; 2485 } 2486 2487 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2488 2489 /* 2490 * ARM v9 security states. 2491 * The ordering of the enumeration corresponds to the low 2 bits 2492 * of the GPI value, and (except for Root) the concat of NSE:NS. 2493 */ 2494 2495 typedef enum ARMSecuritySpace { 2496 ARMSS_Secure = 0, 2497 ARMSS_NonSecure = 1, 2498 ARMSS_Root = 2, 2499 ARMSS_Realm = 3, 2500 } ARMSecuritySpace; 2501 2502 /* Return true if @space is secure, in the pre-v9 sense. */ 2503 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2504 { 2505 return space == ARMSS_Secure || space == ARMSS_Root; 2506 } 2507 2508 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2509 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2510 { 2511 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2512 } 2513 2514 #if !defined(CONFIG_USER_ONLY) 2515 /** 2516 * arm_security_space_below_el3: 2517 * @env: cpu context 2518 * 2519 * Return the security space of exception levels below EL3, following 2520 * an exception return to those levels. Unlike arm_security_space, 2521 * this doesn't care about the current EL. 2522 */ 2523 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2524 2525 /** 2526 * arm_is_secure_below_el3: 2527 * @env: cpu context 2528 * 2529 * Return true if exception levels below EL3 are in secure state, 2530 * or would be following an exception return to those levels. 2531 */ 2532 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2533 { 2534 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2535 return ss == ARMSS_Secure; 2536 } 2537 2538 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2539 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2540 { 2541 assert(!arm_feature(env, ARM_FEATURE_M)); 2542 if (arm_feature(env, ARM_FEATURE_EL3)) { 2543 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2544 /* CPU currently in AArch64 state and EL3 */ 2545 return true; 2546 } else if (!is_a64(env) && 2547 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2548 /* CPU currently in AArch32 state and monitor mode */ 2549 return true; 2550 } 2551 } 2552 return false; 2553 } 2554 2555 /** 2556 * arm_security_space: 2557 * @env: cpu context 2558 * 2559 * Return the current security space of the cpu. 2560 */ 2561 ARMSecuritySpace arm_security_space(CPUARMState *env); 2562 2563 /** 2564 * arm_is_secure: 2565 * @env: cpu context 2566 * 2567 * Return true if the processor is in secure state. 2568 */ 2569 static inline bool arm_is_secure(CPUARMState *env) 2570 { 2571 return arm_space_is_secure(arm_security_space(env)); 2572 } 2573 2574 /* 2575 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2576 * This corresponds to the pseudocode EL2Enabled(). 2577 */ 2578 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2579 ARMSecuritySpace space) 2580 { 2581 assert(space != ARMSS_Root); 2582 return arm_feature(env, ARM_FEATURE_EL2) 2583 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2584 } 2585 2586 static inline bool arm_is_el2_enabled(CPUARMState *env) 2587 { 2588 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2589 } 2590 2591 #else 2592 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2593 { 2594 return ARMSS_NonSecure; 2595 } 2596 2597 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2598 { 2599 return false; 2600 } 2601 2602 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2603 { 2604 return false; 2605 } 2606 2607 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2608 { 2609 return ARMSS_NonSecure; 2610 } 2611 2612 static inline bool arm_is_secure(CPUARMState *env) 2613 { 2614 return false; 2615 } 2616 2617 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2618 ARMSecuritySpace space) 2619 { 2620 return false; 2621 } 2622 2623 static inline bool arm_is_el2_enabled(CPUARMState *env) 2624 { 2625 return false; 2626 } 2627 #endif 2628 2629 /** 2630 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2631 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2632 * "for all purposes other than a direct read or write access of HCR_EL2." 2633 * Not included here is HCR_RW. 2634 */ 2635 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2636 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2637 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2638 2639 /* 2640 * Function for determining whether guest cp register reads and writes should 2641 * access the secure or non-secure bank of a cp register. When EL3 is 2642 * operating in AArch32 state, the NS-bit determines whether the secure 2643 * instance of a cp register should be used. When EL3 is AArch64 (or if 2644 * it doesn't exist at all) then there is no register banking, and all 2645 * accesses are to the non-secure version. 2646 */ 2647 bool access_secure_reg(CPUARMState *env); 2648 2649 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2650 uint32_t cur_el, bool secure); 2651 2652 /* Return the highest implemented Exception Level */ 2653 static inline int arm_highest_el(CPUARMState *env) 2654 { 2655 if (arm_feature(env, ARM_FEATURE_EL3)) { 2656 return 3; 2657 } 2658 if (arm_feature(env, ARM_FEATURE_EL2)) { 2659 return 2; 2660 } 2661 return 1; 2662 } 2663 2664 /* Return true if a v7M CPU is in Handler mode */ 2665 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2666 { 2667 return env->v7m.exception != 0; 2668 } 2669 2670 /** 2671 * write_list_to_cpustate 2672 * @cpu: ARMCPU 2673 * 2674 * For each register listed in the ARMCPU cpreg_indexes list, write 2675 * its value from the cpreg_values list into the ARMCPUState structure. 2676 * This updates TCG's working data structures from KVM data or 2677 * from incoming migration state. 2678 * 2679 * Returns: true if all register values were updated correctly, 2680 * false if some register was unknown or could not be written. 2681 * Note that we do not stop early on failure -- we will attempt 2682 * writing all registers in the list. 2683 */ 2684 bool write_list_to_cpustate(ARMCPU *cpu); 2685 2686 /** 2687 * write_cpustate_to_list: 2688 * @cpu: ARMCPU 2689 * @kvm_sync: true if this is for syncing back to KVM 2690 * 2691 * For each register listed in the ARMCPU cpreg_indexes list, write 2692 * its value from the ARMCPUState structure into the cpreg_values list. 2693 * This is used to copy info from TCG's working data structures into 2694 * KVM or for outbound migration. 2695 * 2696 * @kvm_sync is true if we are doing this in order to sync the 2697 * register state back to KVM. In this case we will only update 2698 * values in the list if the previous list->cpustate sync actually 2699 * successfully wrote the CPU state. Otherwise we will keep the value 2700 * that is in the list. 2701 * 2702 * Returns: true if all register values were read correctly, 2703 * false if some register was unknown or could not be read. 2704 * Note that we do not stop early on failure -- we will attempt 2705 * reading all registers in the list. 2706 */ 2707 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2708 2709 #define ARM_CPUID_TI915T 0x54029152 2710 #define ARM_CPUID_TI925T 0x54029252 2711 2712 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2713 2714 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2715 2716 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2717 * 2718 * If EL3 is 64-bit: 2719 * + NonSecure EL1 & 0 stage 1 2720 * + NonSecure EL1 & 0 stage 2 2721 * + NonSecure EL2 2722 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2723 * + Secure EL1 & 0 stage 1 2724 * + Secure EL1 & 0 stage 2 (FEAT_SEL2) 2725 * + Secure EL2 (FEAT_SEL2) 2726 * + Secure EL2 & 0 (FEAT_SEL2) 2727 * + Realm EL1 & 0 stage 1 (FEAT_RME) 2728 * + Realm EL1 & 0 stage 2 (FEAT_RME) 2729 * + Realm EL2 (FEAT_RME) 2730 * + EL3 2731 * If EL3 is 32-bit: 2732 * + NonSecure PL1 & 0 stage 1 2733 * + NonSecure PL1 & 0 stage 2 2734 * + NonSecure PL2 2735 * + Secure PL1 & 0 2736 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2737 * 2738 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2739 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2740 * because they may differ in access permissions even if the VA->PA map is 2741 * the same 2742 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2743 * translation, which means that we have one mmu_idx that deals with two 2744 * concatenated translation regimes [this sort of combined s1+2 TLB is 2745 * architecturally permitted] 2746 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2747 * handling via the TLB. The only way to do a stage 1 translation without 2748 * the immediate stage 2 translation is via the ATS or AT system insns, 2749 * which can be slow-pathed and always do a page table walk. 2750 * The only use of stage 2 translations is either as part of an s1+2 2751 * lookup or when loading the descriptors during a stage 1 page table walk, 2752 * and in both those cases we don't use the TLB. 2753 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2754 * translation regimes, because they map reasonably well to each other 2755 * and they can't both be active at the same time. 2756 * 5. we want to be able to use the TLB for accesses done as part of a 2757 * stage1 page table walk, rather than having to walk the stage2 page 2758 * table over and over. 2759 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2760 * Never (PAN) bit within PSTATE. 2761 * 7. we fold together most secure and non-secure regimes for A-profile, 2762 * because there are no banked system registers for aarch64, so the 2763 * process of switching between secure and non-secure is 2764 * already heavyweight. 2765 * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, 2766 * because both are in use simultaneously for Secure EL2. 2767 * 2768 * This gives us the following list of cases: 2769 * 2770 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) 2771 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) 2772 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) 2773 * EL0 EL2&0 2774 * EL2 EL2&0 2775 * EL2 EL2&0 +PAN 2776 * EL2 (aka NS PL2) 2777 * EL3 (aka AArch32 S PL1 PL1&0) 2778 * AArch32 S PL0 PL1&0 (we call this EL30_0) 2779 * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) 2780 * Stage2 Secure 2781 * Stage2 NonSecure 2782 * plus one TLB per Physical address space: S, NS, Realm, Root 2783 * 2784 * for a total of 16 different mmu_idx. 2785 * 2786 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2787 * as A profile. They only need to distinguish EL0 and EL1 (and 2788 * EL2 for cores like the Cortex-R52). 2789 * 2790 * M profile CPUs are rather different as they do not have a true MMU. 2791 * They have the following different MMU indexes: 2792 * User 2793 * Privileged 2794 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2795 * Privileged, execution priority negative (ditto) 2796 * If the CPU supports the v8M Security Extension then there are also: 2797 * Secure User 2798 * Secure Privileged 2799 * Secure User, execution priority negative 2800 * Secure Privileged, execution priority negative 2801 * 2802 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2803 * are not quite the same -- different CPU types (most notably M profile 2804 * vs A/R profile) would like to use MMU indexes with different semantics, 2805 * but since we don't ever need to use all of those in a single CPU we 2806 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2807 * modes + total number of M profile MMU modes". The lower bits of 2808 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2809 * the same for any particular CPU. 2810 * Variables of type ARMMUIdx are always full values, and the core 2811 * index values are in variables of type 'int'. 2812 * 2813 * Our enumeration includes at the end some entries which are not "true" 2814 * mmu_idx values in that they don't have corresponding TLBs and are only 2815 * valid for doing slow path page table walks. 2816 * 2817 * The constant names here are patterned after the general style of the names 2818 * of the AT/ATS operations. 2819 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2820 * For M profile we arrange them to have a bit for priv, a bit for negpri 2821 * and a bit for secure. 2822 */ 2823 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2824 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2825 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2826 2827 /* Meanings of the bits for M profile mmu idx values */ 2828 #define ARM_MMU_IDX_M_PRIV 0x1 2829 #define ARM_MMU_IDX_M_NEGPRI 0x2 2830 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2831 2832 #define ARM_MMU_IDX_TYPE_MASK \ 2833 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2834 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2835 2836 typedef enum ARMMMUIdx { 2837 /* 2838 * A-profile. 2839 */ 2840 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2841 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2842 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2843 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2844 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2845 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2846 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2847 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2848 ARMMMUIdx_E30_0 = 8 | ARM_MMU_IDX_A, 2849 ARMMMUIdx_E30_3_PAN = 9 | ARM_MMU_IDX_A, 2850 2851 /* 2852 * Used for second stage of an S12 page table walk, or for descriptor 2853 * loads during first stage of an S1 page table walk. Note that both 2854 * are in use simultaneously for SecureEL2: the security state for 2855 * the S2 ptw is selected by the NS bit from the S1 ptw. 2856 */ 2857 ARMMMUIdx_Stage2_S = 10 | ARM_MMU_IDX_A, 2858 ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A, 2859 2860 /* TLBs with 1-1 mapping to the physical address spaces. */ 2861 ARMMMUIdx_Phys_S = 12 | ARM_MMU_IDX_A, 2862 ARMMMUIdx_Phys_NS = 13 | ARM_MMU_IDX_A, 2863 ARMMMUIdx_Phys_Root = 14 | ARM_MMU_IDX_A, 2864 ARMMMUIdx_Phys_Realm = 15 | ARM_MMU_IDX_A, 2865 2866 /* 2867 * These are not allocated TLBs and are used only for AT system 2868 * instructions or for the first stage of an S12 page table walk. 2869 */ 2870 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2871 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2872 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2873 2874 /* 2875 * M-profile. 2876 */ 2877 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2878 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2879 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2880 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2881 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2882 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2883 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2884 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2885 } ARMMMUIdx; 2886 2887 /* 2888 * Bit macros for the core-mmu-index values for each index, 2889 * for use when calling tlb_flush_by_mmuidx() and friends. 2890 */ 2891 #define TO_CORE_BIT(NAME) \ 2892 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2893 2894 typedef enum ARMMMUIdxBit { 2895 TO_CORE_BIT(E10_0), 2896 TO_CORE_BIT(E20_0), 2897 TO_CORE_BIT(E10_1), 2898 TO_CORE_BIT(E10_1_PAN), 2899 TO_CORE_BIT(E2), 2900 TO_CORE_BIT(E20_2), 2901 TO_CORE_BIT(E20_2_PAN), 2902 TO_CORE_BIT(E3), 2903 TO_CORE_BIT(E30_0), 2904 TO_CORE_BIT(E30_3_PAN), 2905 TO_CORE_BIT(Stage2), 2906 TO_CORE_BIT(Stage2_S), 2907 2908 TO_CORE_BIT(MUser), 2909 TO_CORE_BIT(MPriv), 2910 TO_CORE_BIT(MUserNegPri), 2911 TO_CORE_BIT(MPrivNegPri), 2912 TO_CORE_BIT(MSUser), 2913 TO_CORE_BIT(MSPriv), 2914 TO_CORE_BIT(MSUserNegPri), 2915 TO_CORE_BIT(MSPrivNegPri), 2916 } ARMMMUIdxBit; 2917 2918 #undef TO_CORE_BIT 2919 2920 #define MMU_USER_IDX 0 2921 2922 /* Indexes used when registering address spaces with cpu_address_space_init */ 2923 typedef enum ARMASIdx { 2924 ARMASIdx_NS = 0, 2925 ARMASIdx_S = 1, 2926 ARMASIdx_TagNS = 2, 2927 ARMASIdx_TagS = 3, 2928 } ARMASIdx; 2929 2930 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2931 { 2932 /* Assert the relative order of the physical mmu indexes. */ 2933 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2934 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2935 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2936 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2937 2938 return ARMMMUIdx_Phys_S + space; 2939 } 2940 2941 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2942 { 2943 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2944 return idx - ARMMMUIdx_Phys_S; 2945 } 2946 2947 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2948 { 2949 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2950 * CSSELR is RAZ/WI. 2951 */ 2952 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2953 } 2954 2955 static inline bool arm_sctlr_b(CPUARMState *env) 2956 { 2957 return 2958 /* We need not implement SCTLR.ITD in user-mode emulation, so 2959 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2960 * This lets people run BE32 binaries with "-cpu any". 2961 */ 2962 #ifndef CONFIG_USER_ONLY 2963 !arm_feature(env, ARM_FEATURE_V7) && 2964 #endif 2965 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2966 } 2967 2968 uint64_t arm_sctlr(CPUARMState *env, int el); 2969 2970 #include "exec/cpu-all.h" 2971 2972 /* 2973 * We have more than 32-bits worth of state per TB, so we split the data 2974 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2975 * We collect these two parts in CPUARMTBFlags where they are named 2976 * flags and flags2 respectively. 2977 * 2978 * The flags that are shared between all execution modes, TBFLAG_ANY, 2979 * are stored in flags. The flags that are specific to a given mode 2980 * are stores in flags2. Since cs_base is sized on the configured 2981 * address size, flags2 always has 64-bits for A64, and a minimum of 2982 * 32-bits for A32 and M32. 2983 * 2984 * The bits for 32-bit A-profile and M-profile partially overlap: 2985 * 2986 * 31 23 11 10 0 2987 * +-------------+----------+----------------+ 2988 * | | | TBFLAG_A32 | 2989 * | TBFLAG_AM32 | +-----+----------+ 2990 * | | |TBFLAG_M32| 2991 * +-------------+----------------+----------+ 2992 * 31 23 6 5 0 2993 * 2994 * Unless otherwise noted, these bits are cached in env->hflags. 2995 */ 2996 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 2997 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 2998 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 2999 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3000 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3001 /* Target EL if we take a floating-point-disabled exception */ 3002 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3003 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3004 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3005 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3006 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3007 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3008 3009 /* 3010 * Bit usage when in AArch32 state, both A- and M-profile. 3011 */ 3012 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3013 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3014 3015 /* 3016 * Bit usage when in AArch32 state, for A-profile only. 3017 */ 3018 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3019 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3020 /* 3021 * We store the bottom two bits of the CPAR as TB flags and handle 3022 * checks on the other bits at runtime. This shares the same bits as 3023 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3024 * Not cached, because VECLEN+VECSTRIDE are not cached. 3025 */ 3026 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3027 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3028 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3029 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3030 /* 3031 * Indicates whether cp register reads and writes by guest code should access 3032 * the secure or nonsecure bank of banked registers; note that this is not 3033 * the same thing as the current security state of the processor! 3034 */ 3035 FIELD(TBFLAG_A32, NS, 10, 1) 3036 /* 3037 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3038 * This requires an SME trap from AArch32 mode when using NEON. 3039 */ 3040 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3041 3042 /* 3043 * Bit usage when in AArch32 state, for M-profile only. 3044 */ 3045 /* Handler (ie not Thread) mode */ 3046 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3047 /* Whether we should generate stack-limit checks */ 3048 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3049 /* Set if FPCCR.LSPACT is set */ 3050 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3051 /* Set if we must create a new FP context */ 3052 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3053 /* Set if FPCCR.S does not match current security state */ 3054 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3055 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3056 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3057 /* Set if in secure mode */ 3058 FIELD(TBFLAG_M32, SECURE, 6, 1) 3059 3060 /* 3061 * Bit usage when in AArch64 state 3062 */ 3063 FIELD(TBFLAG_A64, TBII, 0, 2) 3064 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3065 /* The current vector length, either NVL or SVL. */ 3066 FIELD(TBFLAG_A64, VL, 4, 4) 3067 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3068 FIELD(TBFLAG_A64, BT, 9, 1) 3069 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3070 FIELD(TBFLAG_A64, TBID, 12, 2) 3071 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3072 FIELD(TBFLAG_A64, ATA, 15, 1) 3073 FIELD(TBFLAG_A64, TCMA, 16, 2) 3074 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3075 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3076 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3077 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3078 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3079 FIELD(TBFLAG_A64, SVL, 24, 4) 3080 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3081 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3082 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3083 FIELD(TBFLAG_A64, NAA, 30, 1) 3084 FIELD(TBFLAG_A64, ATA0, 31, 1) 3085 FIELD(TBFLAG_A64, NV, 32, 1) 3086 FIELD(TBFLAG_A64, NV1, 33, 1) 3087 FIELD(TBFLAG_A64, NV2, 34, 1) 3088 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3089 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3090 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3091 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3092 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ 3093 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */ 3094 3095 /* 3096 * Helpers for using the above. Note that only the A64 accessors use 3097 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3098 * word either is or might be 32 bits only. 3099 */ 3100 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3101 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3102 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3103 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3104 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3105 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3106 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3107 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3108 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3109 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3110 3111 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3112 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3113 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3114 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3115 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3116 3117 /** 3118 * sve_vq 3119 * @env: the cpu context 3120 * 3121 * Return the VL cached within env->hflags, in units of quadwords. 3122 */ 3123 static inline int sve_vq(CPUARMState *env) 3124 { 3125 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3126 } 3127 3128 /** 3129 * sme_vq 3130 * @env: the cpu context 3131 * 3132 * Return the SVL cached within env->hflags, in units of quadwords. 3133 */ 3134 static inline int sme_vq(CPUARMState *env) 3135 { 3136 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3137 } 3138 3139 static inline bool bswap_code(bool sctlr_b) 3140 { 3141 #ifdef CONFIG_USER_ONLY 3142 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3143 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3144 * would also end up as a mixed-endian mode with BE code, LE data. 3145 */ 3146 return TARGET_BIG_ENDIAN ^ sctlr_b; 3147 #else 3148 /* All code access in ARM is little endian, and there are no loaders 3149 * doing swaps that need to be reversed 3150 */ 3151 return 0; 3152 #endif 3153 } 3154 3155 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3156 uint64_t *cs_base, uint32_t *flags); 3157 3158 enum { 3159 QEMU_PSCI_CONDUIT_DISABLED = 0, 3160 QEMU_PSCI_CONDUIT_SMC = 1, 3161 QEMU_PSCI_CONDUIT_HVC = 2, 3162 }; 3163 3164 #ifndef CONFIG_USER_ONLY 3165 /* Return the address space index to use for a memory access */ 3166 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3167 { 3168 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3169 } 3170 3171 /* Return the AddressSpace to use for a memory access 3172 * (which depends on whether the access is S or NS, and whether 3173 * the board gave us a separate AddressSpace for S accesses). 3174 */ 3175 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3176 { 3177 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3178 } 3179 #endif 3180 3181 /** 3182 * arm_register_pre_el_change_hook: 3183 * Register a hook function which will be called immediately before this 3184 * CPU changes exception level or mode. The hook function will be 3185 * passed a pointer to the ARMCPU and the opaque data pointer passed 3186 * to this function when the hook was registered. 3187 * 3188 * Note that if a pre-change hook is called, any registered post-change hooks 3189 * are guaranteed to subsequently be called. 3190 */ 3191 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3192 void *opaque); 3193 /** 3194 * arm_register_el_change_hook: 3195 * Register a hook function which will be called immediately after this 3196 * CPU changes exception level or mode. The hook function will be 3197 * passed a pointer to the ARMCPU and the opaque data pointer passed 3198 * to this function when the hook was registered. 3199 * 3200 * Note that any registered hooks registered here are guaranteed to be called 3201 * if pre-change hooks have been. 3202 */ 3203 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3204 *opaque); 3205 3206 /** 3207 * arm_rebuild_hflags: 3208 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3209 */ 3210 void arm_rebuild_hflags(CPUARMState *env); 3211 3212 /** 3213 * aa32_vfp_dreg: 3214 * Return a pointer to the Dn register within env in 32-bit mode. 3215 */ 3216 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3217 { 3218 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3219 } 3220 3221 /** 3222 * aa32_vfp_qreg: 3223 * Return a pointer to the Qn register within env in 32-bit mode. 3224 */ 3225 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3226 { 3227 return &env->vfp.zregs[regno].d[0]; 3228 } 3229 3230 /** 3231 * aa64_vfp_qreg: 3232 * Return a pointer to the Qn register within env in 64-bit mode. 3233 */ 3234 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3235 { 3236 return &env->vfp.zregs[regno].d[0]; 3237 } 3238 3239 /* Shared between translate-sve.c and sve_helper.c. */ 3240 extern const uint64_t pred_esz_masks[5]; 3241 3242 /* 3243 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3244 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3245 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3246 */ 3247 #define PAGE_BTI PAGE_TARGET_1 3248 #define PAGE_MTE PAGE_TARGET_2 3249 #define PAGE_TARGET_STICKY PAGE_MTE 3250 3251 /* We associate one allocation tag per 16 bytes, the minimum. */ 3252 #define LOG2_TAG_GRANULE 4 3253 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3254 3255 #ifdef CONFIG_USER_ONLY 3256 3257 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3258 3259 #ifdef TARGET_TAGGED_ADDRESSES 3260 /** 3261 * cpu_untagged_addr: 3262 * @cs: CPU context 3263 * @x: tagged address 3264 * 3265 * Remove any address tag from @x. This is explicitly related to the 3266 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3267 * 3268 * There should be a better place to put this, but we need this in 3269 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3270 */ 3271 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3272 { 3273 CPUARMState *env = cpu_env(cs); 3274 if (env->tagged_addr_enable) { 3275 /* 3276 * TBI is enabled for userspace but not kernelspace addresses. 3277 * Only clear the tag if bit 55 is clear. 3278 */ 3279 x &= sextract64(x, 0, 56); 3280 } 3281 return x; 3282 } 3283 #endif /* TARGET_TAGGED_ADDRESSES */ 3284 #endif /* CONFIG_USER_ONLY */ 3285 3286 #endif 3287