1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "exec/translation-block.h" 32 #include "accel/tcg/cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "cpu-features.h" 36 #include "exec/target_page.h" 37 #include "hw/qdev-properties.h" 38 #if !defined(CONFIG_USER_ONLY) 39 #include "hw/loader.h" 40 #include "hw/boards.h" 41 #ifdef CONFIG_TCG 42 #include "hw/intc/armv7m_nvic.h" 43 #endif /* CONFIG_TCG */ 44 #endif /* !CONFIG_USER_ONLY */ 45 #include "system/tcg.h" 46 #include "system/qtest.h" 47 #include "system/hw_accel.h" 48 #include "kvm_arm.h" 49 #include "disas/capstone.h" 50 #include "fpu/softfloat.h" 51 #include "cpregs.h" 52 #include "target/arm/cpu-qom.h" 53 #include "target/arm/gtimer.h" 54 55 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 56 { 57 ARMCPU *cpu = ARM_CPU(cs); 58 CPUARMState *env = &cpu->env; 59 60 if (is_a64(env)) { 61 env->pc = value; 62 env->thumb = false; 63 } else { 64 env->regs[15] = value & ~1; 65 env->thumb = value & 1; 66 } 67 } 68 69 static vaddr arm_cpu_get_pc(CPUState *cs) 70 { 71 ARMCPU *cpu = ARM_CPU(cs); 72 CPUARMState *env = &cpu->env; 73 74 if (is_a64(env)) { 75 return env->pc; 76 } else { 77 return env->regs[15]; 78 } 79 } 80 81 #ifdef CONFIG_TCG 82 void arm_cpu_synchronize_from_tb(CPUState *cs, 83 const TranslationBlock *tb) 84 { 85 /* The program counter is always up to date with CF_PCREL. */ 86 if (!(tb_cflags(tb) & CF_PCREL)) { 87 CPUARMState *env = cpu_env(cs); 88 /* 89 * It's OK to look at env for the current mode here, because it's 90 * never possible for an AArch64 TB to chain to an AArch32 TB. 91 */ 92 if (is_a64(env)) { 93 env->pc = tb->pc; 94 } else { 95 env->regs[15] = tb->pc; 96 } 97 } 98 } 99 100 void arm_restore_state_to_opc(CPUState *cs, 101 const TranslationBlock *tb, 102 const uint64_t *data) 103 { 104 CPUARMState *env = cpu_env(cs); 105 106 if (is_a64(env)) { 107 if (tb_cflags(tb) & CF_PCREL) { 108 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 109 } else { 110 env->pc = data[0]; 111 } 112 env->condexec_bits = 0; 113 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 114 } else { 115 if (tb_cflags(tb) & CF_PCREL) { 116 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 117 } else { 118 env->regs[15] = data[0]; 119 } 120 env->condexec_bits = data[1]; 121 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 122 } 123 } 124 125 int arm_cpu_mmu_index(CPUState *cs, bool ifetch) 126 { 127 return arm_env_mmu_index(cpu_env(cs)); 128 } 129 130 #endif /* CONFIG_TCG */ 131 132 #ifndef CONFIG_USER_ONLY 133 /* 134 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with 135 * IRQ without Superpriority. Moreover, if the GIC is configured so that 136 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see 137 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here 138 * unconditionally. 139 */ 140 static bool arm_cpu_has_work(CPUState *cs) 141 { 142 ARMCPU *cpu = ARM_CPU(cs); 143 144 return (cpu->power_state != PSCI_OFF) 145 && cs->interrupt_request & 146 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 147 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI 148 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 149 | CPU_INTERRUPT_EXITTB); 150 } 151 #endif /* !CONFIG_USER_ONLY */ 152 153 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 154 void *opaque) 155 { 156 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 157 158 entry->hook = hook; 159 entry->opaque = opaque; 160 161 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 162 } 163 164 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 165 void *opaque) 166 { 167 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 168 169 entry->hook = hook; 170 entry->opaque = opaque; 171 172 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 173 } 174 175 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 176 { 177 /* Reset a single ARMCPRegInfo register */ 178 ARMCPRegInfo *ri = value; 179 ARMCPU *cpu = opaque; 180 181 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 182 return; 183 } 184 185 if (ri->resetfn) { 186 ri->resetfn(&cpu->env, ri); 187 return; 188 } 189 190 /* A zero offset is never possible as it would be regs[0] 191 * so we use it to indicate that reset is being handled elsewhere. 192 * This is basically only used for fields in non-core coprocessors 193 * (like the pxa2xx ones). 194 */ 195 if (!ri->fieldoffset) { 196 return; 197 } 198 199 if (cpreg_field_is_64bit(ri)) { 200 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 201 } else { 202 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 203 } 204 } 205 206 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 207 { 208 /* Purely an assertion check: we've already done reset once, 209 * so now check that running the reset for the cpreg doesn't 210 * change its value. This traps bugs where two different cpregs 211 * both try to reset the same state field but to different values. 212 */ 213 ARMCPRegInfo *ri = value; 214 ARMCPU *cpu = opaque; 215 uint64_t oldvalue, newvalue; 216 217 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 218 return; 219 } 220 221 oldvalue = read_raw_cp_reg(&cpu->env, ri); 222 cp_reg_reset(key, value, opaque); 223 newvalue = read_raw_cp_reg(&cpu->env, ri); 224 assert(oldvalue == newvalue); 225 } 226 227 static void arm_cpu_reset_hold(Object *obj, ResetType type) 228 { 229 CPUState *cs = CPU(obj); 230 ARMCPU *cpu = ARM_CPU(cs); 231 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 232 CPUARMState *env = &cpu->env; 233 234 if (acc->parent_phases.hold) { 235 acc->parent_phases.hold(obj, type); 236 } 237 238 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 239 240 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 241 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 242 243 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 244 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 245 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 246 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 247 248 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; 249 250 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 251 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 252 } 253 254 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 255 /* 64 bit CPUs always start in 64 bit mode */ 256 env->aarch64 = true; 257 #if defined(CONFIG_USER_ONLY) 258 env->pstate = PSTATE_MODE_EL0t; 259 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 260 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 261 /* Enable all PAC keys. */ 262 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 263 SCTLR_EnDA | SCTLR_EnDB); 264 /* Trap on btype=3 for PACIxSP. */ 265 env->cp15.sctlr_el[1] |= SCTLR_BT0; 266 /* Trap on implementation defined registers. */ 267 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 268 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 269 } 270 /* and to the FP/Neon instructions */ 271 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 272 CPACR_EL1, FPEN, 3); 273 /* and to the SVE instructions, with default vector length */ 274 if (cpu_isar_feature(aa64_sve, cpu)) { 275 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 276 CPACR_EL1, ZEN, 3); 277 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 278 } 279 /* and for SME instructions, with default vector length, and TPIDR2 */ 280 if (cpu_isar_feature(aa64_sme, cpu)) { 281 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 282 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 283 CPACR_EL1, SMEN, 3); 284 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 285 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 286 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 287 SMCR, FA64, 1); 288 } 289 } 290 /* 291 * Enable 48-bit address space (TODO: take reserved_va into account). 292 * Enable TBI0 but not TBI1. 293 * Note that this must match useronly_clean_ptr. 294 */ 295 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 296 297 /* Enable MTE */ 298 if (cpu_isar_feature(aa64_mte, cpu)) { 299 /* Enable tag access, but leave TCF0 as No Effect (0). */ 300 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 301 /* 302 * Exclude all tags, so that tag 0 is always used. 303 * This corresponds to Linux current->thread.gcr_incl = 0. 304 * 305 * Set RRND, so that helper_irg() will generate a seed later. 306 * Here in cpu_reset(), the crypto subsystem has not yet been 307 * initialized. 308 */ 309 env->cp15.gcr_el1 = 0x1ffff; 310 } 311 /* 312 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 313 * This is not yet exposed from the Linux kernel in any way. 314 */ 315 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 316 /* Disable access to Debug Communication Channel (DCC). */ 317 env->cp15.mdscr_el1 |= 1 << 12; 318 /* Enable FEAT_MOPS */ 319 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; 320 #else 321 /* Reset into the highest available EL */ 322 if (arm_feature(env, ARM_FEATURE_EL3)) { 323 env->pstate = PSTATE_MODE_EL3h; 324 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 325 env->pstate = PSTATE_MODE_EL2h; 326 } else { 327 env->pstate = PSTATE_MODE_EL1h; 328 } 329 330 /* Sample rvbar at reset. */ 331 env->cp15.rvbar = cpu->rvbar_prop; 332 env->pc = env->cp15.rvbar; 333 #endif 334 } else { 335 #if defined(CONFIG_USER_ONLY) 336 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 337 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 338 CPACR, CP10, 3); 339 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 340 CPACR, CP11, 3); 341 #endif 342 if (arm_feature(env, ARM_FEATURE_V8)) { 343 env->cp15.rvbar = cpu->rvbar_prop; 344 env->regs[15] = cpu->rvbar_prop; 345 } 346 } 347 348 #if defined(CONFIG_USER_ONLY) 349 env->uncached_cpsr = ARM_CPU_MODE_USR; 350 /* For user mode we must enable access to coprocessors */ 351 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 352 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 353 env->cp15.c15_cpar = 3; 354 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 355 env->cp15.c15_cpar = 1; 356 } 357 #else 358 359 /* 360 * If the highest available EL is EL2, AArch32 will start in Hyp 361 * mode; otherwise it starts in SVC. Note that if we start in 362 * AArch64 then these values in the uncached_cpsr will be ignored. 363 */ 364 if (arm_feature(env, ARM_FEATURE_EL2) && 365 !arm_feature(env, ARM_FEATURE_EL3)) { 366 env->uncached_cpsr = ARM_CPU_MODE_HYP; 367 } else { 368 env->uncached_cpsr = ARM_CPU_MODE_SVC; 369 } 370 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 371 372 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 373 * executing as AArch32 then check if highvecs are enabled and 374 * adjust the PC accordingly. 375 */ 376 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 377 env->regs[15] = 0xFFFF0000; 378 } 379 380 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 381 #endif 382 383 if (arm_feature(env, ARM_FEATURE_M)) { 384 #ifndef CONFIG_USER_ONLY 385 uint32_t initial_msp; /* Loaded from 0x0 */ 386 uint32_t initial_pc; /* Loaded from 0x4 */ 387 uint8_t *rom; 388 uint32_t vecbase; 389 #endif 390 391 if (cpu_isar_feature(aa32_lob, cpu)) { 392 /* 393 * LTPSIZE is constant 4 if MVE not implemented, and resets 394 * to an UNKNOWN value if MVE is implemented. We choose to 395 * always reset to 4. 396 */ 397 env->v7m.ltpsize = 4; 398 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 399 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 400 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 401 } 402 403 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 404 env->v7m.secure = true; 405 } else { 406 /* This bit resets to 0 if security is supported, but 1 if 407 * it is not. The bit is not present in v7M, but we set it 408 * here so we can avoid having to make checks on it conditional 409 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 410 */ 411 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 412 /* 413 * Set NSACR to indicate "NS access permitted to everything"; 414 * this avoids having to have all the tests of it being 415 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 416 * v8.1M the guest-visible value of NSACR in a CPU without the 417 * Security Extension is 0xcff. 418 */ 419 env->v7m.nsacr = 0xcff; 420 } 421 422 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 423 * that it resets to 1, so QEMU always does that rather than making 424 * it dependent on CPU model. In v8M it is RES1. 425 */ 426 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 427 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 428 if (arm_feature(env, ARM_FEATURE_V8)) { 429 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 430 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 431 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 432 } 433 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 434 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 435 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 436 } 437 438 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 439 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 440 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 441 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 442 } 443 444 #ifndef CONFIG_USER_ONLY 445 /* Unlike A/R profile, M profile defines the reset LR value */ 446 env->regs[14] = 0xffffffff; 447 448 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 449 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 450 451 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 452 vecbase = env->v7m.vecbase[env->v7m.secure]; 453 rom = rom_ptr_for_as(cs->as, vecbase, 8); 454 if (rom) { 455 /* Address zero is covered by ROM which hasn't yet been 456 * copied into physical memory. 457 */ 458 initial_msp = ldl_p(rom); 459 initial_pc = ldl_p(rom + 4); 460 } else { 461 /* Address zero not covered by a ROM blob, or the ROM blob 462 * is in non-modifiable memory and this is a second reset after 463 * it got copied into memory. In the latter case, rom_ptr 464 * will return a NULL pointer and we should use ldl_phys instead. 465 */ 466 initial_msp = ldl_phys(cs->as, vecbase); 467 initial_pc = ldl_phys(cs->as, vecbase + 4); 468 } 469 470 qemu_log_mask(CPU_LOG_INT, 471 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 472 initial_msp, initial_pc); 473 474 env->regs[13] = initial_msp & 0xFFFFFFFC; 475 env->regs[15] = initial_pc & ~1; 476 env->thumb = initial_pc & 1; 477 #else 478 /* 479 * For user mode we run non-secure and with access to the FPU. 480 * The FPU context is active (ie does not need further setup) 481 * and is owned by non-secure. 482 */ 483 env->v7m.secure = false; 484 env->v7m.nsacr = 0xcff; 485 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 486 env->v7m.fpccr[M_REG_S] &= 487 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 488 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 489 #endif 490 } 491 492 /* M profile requires that reset clears the exclusive monitor; 493 * A profile does not, but clearing it makes more sense than having it 494 * set with an exclusive access on address zero. 495 */ 496 arm_clear_exclusive(env); 497 498 if (arm_feature(env, ARM_FEATURE_PMSA)) { 499 if (cpu->pmsav7_dregion > 0) { 500 if (arm_feature(env, ARM_FEATURE_V8)) { 501 memset(env->pmsav8.rbar[M_REG_NS], 0, 502 sizeof(*env->pmsav8.rbar[M_REG_NS]) 503 * cpu->pmsav7_dregion); 504 memset(env->pmsav8.rlar[M_REG_NS], 0, 505 sizeof(*env->pmsav8.rlar[M_REG_NS]) 506 * cpu->pmsav7_dregion); 507 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 508 memset(env->pmsav8.rbar[M_REG_S], 0, 509 sizeof(*env->pmsav8.rbar[M_REG_S]) 510 * cpu->pmsav7_dregion); 511 memset(env->pmsav8.rlar[M_REG_S], 0, 512 sizeof(*env->pmsav8.rlar[M_REG_S]) 513 * cpu->pmsav7_dregion); 514 } 515 } else if (arm_feature(env, ARM_FEATURE_V7)) { 516 memset(env->pmsav7.drbar, 0, 517 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 518 memset(env->pmsav7.drsr, 0, 519 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 520 memset(env->pmsav7.dracr, 0, 521 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 522 } 523 } 524 525 if (cpu->pmsav8r_hdregion > 0) { 526 memset(env->pmsav8.hprbar, 0, 527 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 528 memset(env->pmsav8.hprlar, 0, 529 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 530 } 531 532 env->pmsav7.rnr[M_REG_NS] = 0; 533 env->pmsav7.rnr[M_REG_S] = 0; 534 env->pmsav8.mair0[M_REG_NS] = 0; 535 env->pmsav8.mair0[M_REG_S] = 0; 536 env->pmsav8.mair1[M_REG_NS] = 0; 537 env->pmsav8.mair1[M_REG_S] = 0; 538 } 539 540 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 541 if (cpu->sau_sregion > 0) { 542 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 543 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 544 } 545 env->sau.rnr = 0; 546 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 547 * the Cortex-M33 does. 548 */ 549 env->sau.ctrl = 0; 550 } 551 552 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]); 553 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); 554 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); 555 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); 556 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); 557 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); 558 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); 559 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); 560 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); 561 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); 562 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); 563 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); 564 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]); 565 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); 566 567 #ifndef CONFIG_USER_ONLY 568 if (kvm_enabled()) { 569 kvm_arm_reset_vcpu(cpu); 570 } 571 #endif 572 573 if (tcg_enabled()) { 574 hw_breakpoint_update_all(cpu); 575 hw_watchpoint_update_all(cpu); 576 577 arm_rebuild_hflags(env); 578 } 579 } 580 581 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 582 { 583 ARMCPU *cpu = ARM_CPU(cpustate); 584 CPUARMState *env = &cpu->env; 585 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 586 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 587 588 /* 589 * Check we have the EL we're aiming for. If that is the 590 * highest implemented EL, then cpu_reset has already done 591 * all the work. 592 */ 593 switch (target_el) { 594 case 3: 595 assert(have_el3); 596 return; 597 case 2: 598 assert(have_el2); 599 if (!have_el3) { 600 return; 601 } 602 break; 603 case 1: 604 if (!have_el3 && !have_el2) { 605 return; 606 } 607 break; 608 default: 609 g_assert_not_reached(); 610 } 611 612 if (have_el3) { 613 /* 614 * Set the EL3 state so code can run at EL2. This should match 615 * the requirements set by Linux in its booting spec. 616 */ 617 if (env->aarch64) { 618 env->cp15.scr_el3 |= SCR_RW; 619 if (cpu_isar_feature(aa64_pauth, cpu)) { 620 env->cp15.scr_el3 |= SCR_API | SCR_APK; 621 } 622 if (cpu_isar_feature(aa64_mte, cpu)) { 623 env->cp15.scr_el3 |= SCR_ATA; 624 } 625 if (cpu_isar_feature(aa64_sve, cpu)) { 626 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 627 env->vfp.zcr_el[3] = 0xf; 628 } 629 if (cpu_isar_feature(aa64_sme, cpu)) { 630 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 631 env->cp15.scr_el3 |= SCR_ENTP2; 632 env->vfp.smcr_el[3] = 0xf; 633 } 634 if (cpu_isar_feature(aa64_hcx, cpu)) { 635 env->cp15.scr_el3 |= SCR_HXEN; 636 } 637 if (cpu_isar_feature(aa64_fgt, cpu)) { 638 env->cp15.scr_el3 |= SCR_FGTEN; 639 } 640 } 641 642 if (target_el == 2) { 643 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 644 env->cp15.scr_el3 |= SCR_HCE; 645 } 646 647 /* Put CPU into non-secure state */ 648 env->cp15.scr_el3 |= SCR_NS; 649 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 650 env->cp15.nsacr |= 3 << 10; 651 } 652 653 if (have_el2 && target_el < 2) { 654 /* Set EL2 state so code can run at EL1. */ 655 if (env->aarch64) { 656 env->cp15.hcr_el2 |= HCR_RW; 657 } 658 } 659 660 /* Set the CPU to the desired state */ 661 if (env->aarch64) { 662 env->pstate = aarch64_pstate_mode(target_el, true); 663 } else { 664 static const uint32_t mode_for_el[] = { 665 0, 666 ARM_CPU_MODE_SVC, 667 ARM_CPU_MODE_HYP, 668 ARM_CPU_MODE_SVC, 669 }; 670 671 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 672 } 673 } 674 675 676 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 677 678 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 679 unsigned int target_el, 680 unsigned int cur_el, bool secure, 681 uint64_t hcr_el2) 682 { 683 CPUARMState *env = cpu_env(cs); 684 bool pstate_unmasked; 685 bool unmasked = false; 686 bool allIntMask = false; 687 688 /* 689 * Don't take exceptions if they target a lower EL. 690 * This check should catch any exceptions that would not be taken 691 * but left pending. 692 */ 693 if (cur_el > target_el) { 694 return false; 695 } 696 697 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 698 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { 699 allIntMask = env->pstate & PSTATE_ALLINT || 700 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && 701 (env->pstate & PSTATE_SP)); 702 } 703 704 switch (excp_idx) { 705 case EXCP_NMI: 706 pstate_unmasked = !allIntMask; 707 break; 708 709 case EXCP_VINMI: 710 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 711 /* VINMIs are only taken when hypervized. */ 712 return false; 713 } 714 return !allIntMask; 715 case EXCP_VFNMI: 716 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 717 /* VFNMIs are only taken when hypervized. */ 718 return false; 719 } 720 return !allIntMask; 721 case EXCP_FIQ: 722 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask); 723 break; 724 725 case EXCP_IRQ: 726 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask); 727 break; 728 729 case EXCP_VFIQ: 730 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 731 /* VFIQs are only taken when hypervized. */ 732 return false; 733 } 734 return !(env->daif & PSTATE_F) && (!allIntMask); 735 case EXCP_VIRQ: 736 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 737 /* VIRQs are only taken when hypervized. */ 738 return false; 739 } 740 return !(env->daif & PSTATE_I) && (!allIntMask); 741 case EXCP_VSERR: 742 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 743 /* VIRQs are only taken when hypervized. */ 744 return false; 745 } 746 return !(env->daif & PSTATE_A); 747 default: 748 g_assert_not_reached(); 749 } 750 751 /* 752 * Use the target EL, current execution state and SCR/HCR settings to 753 * determine whether the corresponding CPSR bit is used to mask the 754 * interrupt. 755 */ 756 if ((target_el > cur_el) && (target_el != 1)) { 757 /* Exceptions targeting a higher EL may not be maskable */ 758 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 759 switch (target_el) { 760 case 2: 761 /* 762 * According to ARM DDI 0487H.a, an interrupt can be masked 763 * when HCR_E2H and HCR_TGE are both set regardless of the 764 * current Security state. Note that we need to revisit this 765 * part again once we need to support NMI. 766 */ 767 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 768 unmasked = true; 769 } 770 break; 771 case 3: 772 /* Interrupt cannot be masked when the target EL is 3 */ 773 unmasked = true; 774 break; 775 default: 776 g_assert_not_reached(); 777 } 778 } else { 779 /* 780 * The old 32-bit-only environment has a more complicated 781 * masking setup. HCR and SCR bits not only affect interrupt 782 * routing but also change the behaviour of masking. 783 */ 784 bool hcr, scr; 785 786 switch (excp_idx) { 787 case EXCP_FIQ: 788 /* 789 * If FIQs are routed to EL3 or EL2 then there are cases where 790 * we override the CPSR.F in determining if the exception is 791 * masked or not. If neither of these are set then we fall back 792 * to the CPSR.F setting otherwise we further assess the state 793 * below. 794 */ 795 hcr = hcr_el2 & HCR_FMO; 796 scr = (env->cp15.scr_el3 & SCR_FIQ); 797 798 /* 799 * When EL3 is 32-bit, the SCR.FW bit controls whether the 800 * CPSR.F bit masks FIQ interrupts when taken in non-secure 801 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 802 * when non-secure but only when FIQs are only routed to EL3. 803 */ 804 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 805 break; 806 case EXCP_IRQ: 807 /* 808 * When EL3 execution state is 32-bit, if HCR.IMO is set then 809 * we may override the CPSR.I masking when in non-secure state. 810 * The SCR.IRQ setting has already been taken into consideration 811 * when setting the target EL, so it does not have a further 812 * affect here. 813 */ 814 hcr = hcr_el2 & HCR_IMO; 815 scr = false; 816 break; 817 default: 818 g_assert_not_reached(); 819 } 820 821 if ((scr || hcr) && !secure) { 822 unmasked = true; 823 } 824 } 825 } 826 827 /* 828 * The PSTATE bits only mask the interrupt if we have not overridden the 829 * ability above. 830 */ 831 return unmasked || pstate_unmasked; 832 } 833 834 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 835 { 836 CPUARMState *env = cpu_env(cs); 837 uint32_t cur_el = arm_current_el(env); 838 bool secure = arm_is_secure(env); 839 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 840 uint32_t target_el; 841 uint32_t excp_idx; 842 843 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 844 845 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 846 (arm_sctlr(env, cur_el) & SCTLR_NMI)) { 847 if (interrupt_request & CPU_INTERRUPT_NMI) { 848 excp_idx = EXCP_NMI; 849 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 850 if (arm_excp_unmasked(cs, excp_idx, target_el, 851 cur_el, secure, hcr_el2)) { 852 goto found; 853 } 854 } 855 if (interrupt_request & CPU_INTERRUPT_VINMI) { 856 excp_idx = EXCP_VINMI; 857 target_el = 1; 858 if (arm_excp_unmasked(cs, excp_idx, target_el, 859 cur_el, secure, hcr_el2)) { 860 goto found; 861 } 862 } 863 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 864 excp_idx = EXCP_VFNMI; 865 target_el = 1; 866 if (arm_excp_unmasked(cs, excp_idx, target_el, 867 cur_el, secure, hcr_el2)) { 868 goto found; 869 } 870 } 871 } else { 872 /* 873 * NMI disabled: interrupts with superpriority are handled 874 * as if they didn't have it 875 */ 876 if (interrupt_request & CPU_INTERRUPT_NMI) { 877 interrupt_request |= CPU_INTERRUPT_HARD; 878 } 879 if (interrupt_request & CPU_INTERRUPT_VINMI) { 880 interrupt_request |= CPU_INTERRUPT_VIRQ; 881 } 882 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 883 interrupt_request |= CPU_INTERRUPT_VFIQ; 884 } 885 } 886 887 if (interrupt_request & CPU_INTERRUPT_FIQ) { 888 excp_idx = EXCP_FIQ; 889 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 890 if (arm_excp_unmasked(cs, excp_idx, target_el, 891 cur_el, secure, hcr_el2)) { 892 goto found; 893 } 894 } 895 if (interrupt_request & CPU_INTERRUPT_HARD) { 896 excp_idx = EXCP_IRQ; 897 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 898 if (arm_excp_unmasked(cs, excp_idx, target_el, 899 cur_el, secure, hcr_el2)) { 900 goto found; 901 } 902 } 903 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 904 excp_idx = EXCP_VIRQ; 905 target_el = 1; 906 if (arm_excp_unmasked(cs, excp_idx, target_el, 907 cur_el, secure, hcr_el2)) { 908 goto found; 909 } 910 } 911 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 912 excp_idx = EXCP_VFIQ; 913 target_el = 1; 914 if (arm_excp_unmasked(cs, excp_idx, target_el, 915 cur_el, secure, hcr_el2)) { 916 goto found; 917 } 918 } 919 if (interrupt_request & CPU_INTERRUPT_VSERR) { 920 excp_idx = EXCP_VSERR; 921 target_el = 1; 922 if (arm_excp_unmasked(cs, excp_idx, target_el, 923 cur_el, secure, hcr_el2)) { 924 /* Taking a virtual abort clears HCR_EL2.VSE */ 925 env->cp15.hcr_el2 &= ~HCR_VSE; 926 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 927 goto found; 928 } 929 } 930 return false; 931 932 found: 933 cs->exception_index = excp_idx; 934 env->exception.target_el = target_el; 935 cs->cc->tcg_ops->do_interrupt(cs); 936 return true; 937 } 938 939 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 940 941 void arm_cpu_update_virq(ARMCPU *cpu) 942 { 943 /* 944 * Update the interrupt level for VIRQ, which is the logical OR of 945 * the HCR_EL2.VI bit and the input line level from the GIC. 946 */ 947 CPUARMState *env = &cpu->env; 948 CPUState *cs = CPU(cpu); 949 950 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 951 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 952 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 953 954 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 955 if (new_state) { 956 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 957 } else { 958 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 959 } 960 } 961 } 962 963 void arm_cpu_update_vfiq(ARMCPU *cpu) 964 { 965 /* 966 * Update the interrupt level for VFIQ, which is the logical OR of 967 * the HCR_EL2.VF bit and the input line level from the GIC. 968 */ 969 CPUARMState *env = &cpu->env; 970 CPUState *cs = CPU(cpu); 971 972 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) && 973 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || 974 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 975 976 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 977 if (new_state) { 978 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 979 } else { 980 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 981 } 982 } 983 } 984 985 void arm_cpu_update_vinmi(ARMCPU *cpu) 986 { 987 /* 988 * Update the interrupt level for VINMI, which is the logical OR of 989 * the HCRX_EL2.VINMI bit and the input line level from the GIC. 990 */ 991 CPUARMState *env = &cpu->env; 992 CPUState *cs = CPU(cpu); 993 994 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 995 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 996 (env->irq_line_state & CPU_INTERRUPT_VINMI); 997 998 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) { 999 if (new_state) { 1000 cpu_interrupt(cs, CPU_INTERRUPT_VINMI); 1001 } else { 1002 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI); 1003 } 1004 } 1005 } 1006 1007 void arm_cpu_update_vfnmi(ARMCPU *cpu) 1008 { 1009 /* 1010 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit. 1011 */ 1012 CPUARMState *env = &cpu->env; 1013 CPUState *cs = CPU(cpu); 1014 1015 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) && 1016 (arm_hcrx_el2_eff(env) & HCRX_VFNMI); 1017 1018 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) { 1019 if (new_state) { 1020 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); 1021 } else { 1022 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI); 1023 } 1024 } 1025 } 1026 1027 void arm_cpu_update_vserr(ARMCPU *cpu) 1028 { 1029 /* 1030 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 1031 */ 1032 CPUARMState *env = &cpu->env; 1033 CPUState *cs = CPU(cpu); 1034 1035 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 1036 1037 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 1038 if (new_state) { 1039 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 1040 } else { 1041 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 1042 } 1043 } 1044 } 1045 1046 #ifndef CONFIG_USER_ONLY 1047 static void arm_cpu_set_irq(void *opaque, int irq, int level) 1048 { 1049 ARMCPU *cpu = opaque; 1050 CPUARMState *env = &cpu->env; 1051 CPUState *cs = CPU(cpu); 1052 static const int mask[] = { 1053 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 1054 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 1055 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 1056 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ, 1057 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI, 1058 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI, 1059 }; 1060 1061 if (!arm_feature(env, ARM_FEATURE_EL2) && 1062 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 1063 /* 1064 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 1065 * have EL2 support we don't care. (Unless the guest is doing something 1066 * silly this will only be calls saying "level is still 0".) 1067 */ 1068 return; 1069 } 1070 1071 if (level) { 1072 env->irq_line_state |= mask[irq]; 1073 } else { 1074 env->irq_line_state &= ~mask[irq]; 1075 } 1076 1077 switch (irq) { 1078 case ARM_CPU_VIRQ: 1079 arm_cpu_update_virq(cpu); 1080 break; 1081 case ARM_CPU_VFIQ: 1082 arm_cpu_update_vfiq(cpu); 1083 break; 1084 case ARM_CPU_VINMI: 1085 arm_cpu_update_vinmi(cpu); 1086 break; 1087 case ARM_CPU_IRQ: 1088 case ARM_CPU_FIQ: 1089 case ARM_CPU_NMI: 1090 if (level) { 1091 cpu_interrupt(cs, mask[irq]); 1092 } else { 1093 cpu_reset_interrupt(cs, mask[irq]); 1094 } 1095 break; 1096 default: 1097 g_assert_not_reached(); 1098 } 1099 } 1100 1101 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 1102 { 1103 #ifdef CONFIG_KVM 1104 ARMCPU *cpu = opaque; 1105 CPUARMState *env = &cpu->env; 1106 CPUState *cs = CPU(cpu); 1107 uint32_t linestate_bit; 1108 int irq_id; 1109 1110 switch (irq) { 1111 case ARM_CPU_IRQ: 1112 irq_id = KVM_ARM_IRQ_CPU_IRQ; 1113 linestate_bit = CPU_INTERRUPT_HARD; 1114 break; 1115 case ARM_CPU_FIQ: 1116 irq_id = KVM_ARM_IRQ_CPU_FIQ; 1117 linestate_bit = CPU_INTERRUPT_FIQ; 1118 break; 1119 default: 1120 g_assert_not_reached(); 1121 } 1122 1123 if (level) { 1124 env->irq_line_state |= linestate_bit; 1125 } else { 1126 env->irq_line_state &= ~linestate_bit; 1127 } 1128 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 1129 #endif 1130 } 1131 1132 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 1133 { 1134 ARMCPU *cpu = ARM_CPU(cs); 1135 CPUARMState *env = &cpu->env; 1136 1137 cpu_synchronize_state(cs); 1138 return arm_cpu_data_is_big_endian(env); 1139 } 1140 1141 #ifdef CONFIG_TCG 1142 bool arm_cpu_exec_halt(CPUState *cs) 1143 { 1144 bool leave_halt = cpu_has_work(cs); 1145 1146 if (leave_halt) { 1147 /* We're about to come out of WFI/WFE: disable the WFxT timer */ 1148 ARMCPU *cpu = ARM_CPU(cs); 1149 if (cpu->wfxt_timer) { 1150 timer_del(cpu->wfxt_timer); 1151 } 1152 } 1153 return leave_halt; 1154 } 1155 #endif 1156 1157 static void arm_wfxt_timer_cb(void *opaque) 1158 { 1159 ARMCPU *cpu = opaque; 1160 CPUState *cs = CPU(cpu); 1161 1162 /* 1163 * We expect the CPU to be halted; this will cause arm_cpu_is_work() 1164 * to return true (so we will come out of halt even with no other 1165 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt() 1166 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. 1167 */ 1168 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 1169 } 1170 #endif 1171 1172 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 1173 { 1174 ARMCPU *ac = ARM_CPU(cpu); 1175 CPUARMState *env = &ac->env; 1176 bool sctlr_b = arm_sctlr_b(env); 1177 1178 if (is_a64(env)) { 1179 info->cap_arch = CS_ARCH_ARM64; 1180 info->cap_insn_unit = 4; 1181 info->cap_insn_split = 4; 1182 } else { 1183 int cap_mode; 1184 if (env->thumb) { 1185 info->cap_insn_unit = 2; 1186 info->cap_insn_split = 4; 1187 cap_mode = CS_MODE_THUMB; 1188 } else { 1189 info->cap_insn_unit = 4; 1190 info->cap_insn_split = 4; 1191 cap_mode = CS_MODE_ARM; 1192 } 1193 if (arm_feature(env, ARM_FEATURE_V8)) { 1194 cap_mode |= CS_MODE_V8; 1195 } 1196 if (arm_feature(env, ARM_FEATURE_M)) { 1197 cap_mode |= CS_MODE_MCLASS; 1198 } 1199 info->cap_arch = CS_ARCH_ARM; 1200 info->cap_mode = cap_mode; 1201 } 1202 1203 info->endian = BFD_ENDIAN_LITTLE; 1204 if (bswap_code(sctlr_b)) { 1205 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 1206 } 1207 info->flags &= ~INSN_ARM_BE32; 1208 #ifndef CONFIG_USER_ONLY 1209 if (sctlr_b) { 1210 info->flags |= INSN_ARM_BE32; 1211 } 1212 #endif 1213 } 1214 1215 #ifdef TARGET_AARCH64 1216 1217 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1218 { 1219 ARMCPU *cpu = ARM_CPU(cs); 1220 CPUARMState *env = &cpu->env; 1221 uint32_t psr = pstate_read(env); 1222 int i, j; 1223 int el = arm_current_el(env); 1224 uint64_t hcr = arm_hcr_el2_eff(env); 1225 const char *ns_status; 1226 bool sve; 1227 1228 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 1229 for (i = 0; i < 32; i++) { 1230 if (i == 31) { 1231 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 1232 } else { 1233 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 1234 (i + 2) % 3 ? " " : "\n"); 1235 } 1236 } 1237 1238 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 1239 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1240 } else { 1241 ns_status = ""; 1242 } 1243 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 1244 psr, 1245 psr & PSTATE_N ? 'N' : '-', 1246 psr & PSTATE_Z ? 'Z' : '-', 1247 psr & PSTATE_C ? 'C' : '-', 1248 psr & PSTATE_V ? 'V' : '-', 1249 ns_status, 1250 el, 1251 psr & PSTATE_SP ? 'h' : 't'); 1252 1253 if (cpu_isar_feature(aa64_sme, cpu)) { 1254 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 1255 env->svcr, 1256 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 1257 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 1258 } 1259 if (cpu_isar_feature(aa64_bti, cpu)) { 1260 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1261 } 1262 qemu_fprintf(f, "%s%s%s", 1263 (hcr & HCR_NV) ? " NV" : "", 1264 (hcr & HCR_NV1) ? " NV1" : "", 1265 (hcr & HCR_NV2) ? " NV2" : ""); 1266 if (!(flags & CPU_DUMP_FPU)) { 1267 qemu_fprintf(f, "\n"); 1268 return; 1269 } 1270 if (fp_exception_el(env, el) != 0) { 1271 qemu_fprintf(f, " FPU disabled\n"); 1272 return; 1273 } 1274 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1275 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1276 1277 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1278 sve = sme_exception_el(env, el) == 0; 1279 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1280 sve = sve_exception_el(env, el) == 0; 1281 } else { 1282 sve = false; 1283 } 1284 1285 if (sve) { 1286 int zcr_len = sve_vqm1_for_el(env, el); 1287 1288 for (i = 0; i <= FFR_PRED_NUM; i++) { 1289 bool eol; 1290 if (i == FFR_PRED_NUM) { 1291 qemu_fprintf(f, "FFR="); 1292 /* It's last, so end the line. */ 1293 eol = true; 1294 } else { 1295 qemu_fprintf(f, "P%02d=", i); 1296 switch (zcr_len) { 1297 case 0: 1298 eol = i % 8 == 7; 1299 break; 1300 case 1: 1301 eol = i % 6 == 5; 1302 break; 1303 case 2: 1304 case 3: 1305 eol = i % 3 == 2; 1306 break; 1307 default: 1308 /* More than one quadword per predicate. */ 1309 eol = true; 1310 break; 1311 } 1312 } 1313 for (j = zcr_len / 4; j >= 0; j--) { 1314 int digits; 1315 if (j * 4 + 4 <= zcr_len + 1) { 1316 digits = 16; 1317 } else { 1318 digits = (zcr_len % 4 + 1) * 4; 1319 } 1320 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1321 env->vfp.pregs[i].p[j], 1322 j ? ":" : eol ? "\n" : " "); 1323 } 1324 } 1325 1326 if (zcr_len == 0) { 1327 /* 1328 * With vl=16, there are only 37 columns per register, 1329 * so output two registers per line. 1330 */ 1331 for (i = 0; i < 32; i++) { 1332 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1333 i, env->vfp.zregs[i].d[1], 1334 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1335 } 1336 } else { 1337 for (i = 0; i < 32; i++) { 1338 qemu_fprintf(f, "Z%02d=", i); 1339 for (j = zcr_len; j >= 0; j--) { 1340 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1341 env->vfp.zregs[i].d[j * 2 + 1], 1342 env->vfp.zregs[i].d[j * 2 + 0], 1343 j ? ":" : "\n"); 1344 } 1345 } 1346 } 1347 } else { 1348 for (i = 0; i < 32; i++) { 1349 uint64_t *q = aa64_vfp_qreg(env, i); 1350 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1351 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1352 } 1353 } 1354 1355 if (cpu_isar_feature(aa64_sme, cpu) && 1356 FIELD_EX64(env->svcr, SVCR, ZA) && 1357 sme_exception_el(env, el) == 0) { 1358 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1359 int svl = (zcr_len + 1) * 16; 1360 int svl_lg10 = svl < 100 ? 2 : 3; 1361 1362 for (i = 0; i < svl; i++) { 1363 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1364 for (j = zcr_len; j >= 0; --j) { 1365 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1366 env->zarray[i].d[2 * j + 1], 1367 env->zarray[i].d[2 * j], 1368 j ? ':' : '\n'); 1369 } 1370 } 1371 } 1372 } 1373 1374 #else 1375 1376 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1377 { 1378 g_assert_not_reached(); 1379 } 1380 1381 #endif 1382 1383 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1384 { 1385 ARMCPU *cpu = ARM_CPU(cs); 1386 CPUARMState *env = &cpu->env; 1387 int i; 1388 1389 if (is_a64(env)) { 1390 aarch64_cpu_dump_state(cs, f, flags); 1391 return; 1392 } 1393 1394 for (i = 0; i < 16; i++) { 1395 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1396 if ((i % 4) == 3) { 1397 qemu_fprintf(f, "\n"); 1398 } else { 1399 qemu_fprintf(f, " "); 1400 } 1401 } 1402 1403 if (arm_feature(env, ARM_FEATURE_M)) { 1404 uint32_t xpsr = xpsr_read(env); 1405 const char *mode; 1406 const char *ns_status = ""; 1407 1408 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1409 ns_status = env->v7m.secure ? "S " : "NS "; 1410 } 1411 1412 if (xpsr & XPSR_EXCP) { 1413 mode = "handler"; 1414 } else { 1415 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1416 mode = "unpriv-thread"; 1417 } else { 1418 mode = "priv-thread"; 1419 } 1420 } 1421 1422 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1423 xpsr, 1424 xpsr & XPSR_N ? 'N' : '-', 1425 xpsr & XPSR_Z ? 'Z' : '-', 1426 xpsr & XPSR_C ? 'C' : '-', 1427 xpsr & XPSR_V ? 'V' : '-', 1428 xpsr & XPSR_T ? 'T' : 'A', 1429 ns_status, 1430 mode); 1431 } else { 1432 uint32_t psr = cpsr_read(env); 1433 const char *ns_status = ""; 1434 1435 if (arm_feature(env, ARM_FEATURE_EL3) && 1436 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1437 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1438 } 1439 1440 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1441 psr, 1442 psr & CPSR_N ? 'N' : '-', 1443 psr & CPSR_Z ? 'Z' : '-', 1444 psr & CPSR_C ? 'C' : '-', 1445 psr & CPSR_V ? 'V' : '-', 1446 psr & CPSR_T ? 'T' : 'A', 1447 ns_status, 1448 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1449 } 1450 1451 if (flags & CPU_DUMP_FPU) { 1452 int numvfpregs = 0; 1453 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1454 numvfpregs = 32; 1455 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1456 numvfpregs = 16; 1457 } 1458 for (i = 0; i < numvfpregs; i++) { 1459 uint64_t v = *aa32_vfp_dreg(env, i); 1460 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1461 i * 2, (uint32_t)v, 1462 i * 2 + 1, (uint32_t)(v >> 32), 1463 i, v); 1464 } 1465 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1466 if (cpu_isar_feature(aa32_mve, cpu)) { 1467 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1468 } 1469 } 1470 } 1471 1472 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) 1473 { 1474 uint32_t Aff1 = idx / clustersz; 1475 uint32_t Aff0 = idx % clustersz; 1476 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1477 } 1478 1479 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) 1480 { 1481 return cpu->mp_affinity; 1482 } 1483 1484 static void arm_cpu_initfn(Object *obj) 1485 { 1486 ARMCPU *cpu = ARM_CPU(obj); 1487 1488 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1489 NULL, g_free); 1490 1491 QLIST_INIT(&cpu->pre_el_change_hooks); 1492 QLIST_INIT(&cpu->el_change_hooks); 1493 1494 #ifdef CONFIG_USER_ONLY 1495 # ifdef TARGET_AARCH64 1496 /* 1497 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1498 * These values were chosen to fit within the default signal frame. 1499 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1500 * and our corresponding cpu property. 1501 */ 1502 cpu->sve_default_vq = 4; 1503 cpu->sme_default_vq = 2; 1504 # endif 1505 #else 1506 /* Our inbound IRQ and FIQ lines */ 1507 if (kvm_enabled()) { 1508 /* 1509 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add 1510 * them to maintain the same interface as non-KVM CPUs. 1511 */ 1512 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); 1513 } else { 1514 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); 1515 } 1516 1517 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1518 ARRAY_SIZE(cpu->gt_timer_outputs)); 1519 1520 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1521 "gicv3-maintenance-interrupt", 1); 1522 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1523 "pmu-interrupt", 1); 1524 #endif 1525 1526 /* DTB consumers generally don't in fact care what the 'compatible' 1527 * string is, so always provide some string and trust that a hypothetical 1528 * picky DTB consumer will also provide a helpful error message. 1529 */ 1530 cpu->dtb_compatible = "qemu,unknown"; 1531 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1532 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1533 1534 if (tcg_enabled() || hvf_enabled()) { 1535 /* TCG and HVF implement PSCI 1.1 */ 1536 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1537 } 1538 } 1539 1540 /* 1541 * 0 means "unset, use the default value". That default might vary depending 1542 * on the CPU type, and is set in the realize fn. 1543 */ 1544 static const Property arm_cpu_gt_cntfrq_property = 1545 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); 1546 1547 static const Property arm_cpu_reset_cbar_property = 1548 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1549 1550 static const Property arm_cpu_reset_hivecs_property = 1551 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1552 1553 #ifndef CONFIG_USER_ONLY 1554 static const Property arm_cpu_has_el2_property = 1555 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1556 1557 static const Property arm_cpu_has_el3_property = 1558 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1559 #endif 1560 1561 static const Property arm_cpu_cfgend_property = 1562 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1563 1564 static const Property arm_cpu_has_vfp_property = 1565 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1566 1567 static const Property arm_cpu_has_vfp_d32_property = 1568 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1569 1570 static const Property arm_cpu_has_neon_property = 1571 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1572 1573 static const Property arm_cpu_has_dsp_property = 1574 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1575 1576 static const Property arm_cpu_has_mpu_property = 1577 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1578 1579 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1580 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1581 * the right value for that particular CPU type, and we don't want 1582 * to override that with an incorrect constant value. 1583 */ 1584 static const Property arm_cpu_pmsav7_dregion_property = 1585 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1586 pmsav7_dregion, 1587 qdev_prop_uint32, uint32_t); 1588 1589 static bool arm_get_pmu(Object *obj, Error **errp) 1590 { 1591 ARMCPU *cpu = ARM_CPU(obj); 1592 1593 return cpu->has_pmu; 1594 } 1595 1596 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1597 { 1598 ARMCPU *cpu = ARM_CPU(obj); 1599 1600 if (value) { 1601 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1602 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1603 return; 1604 } 1605 set_feature(&cpu->env, ARM_FEATURE_PMU); 1606 } else { 1607 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1608 } 1609 cpu->has_pmu = value; 1610 } 1611 1612 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1613 { 1614 /* 1615 * The exact approach to calculating guest ticks is: 1616 * 1617 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1618 * NANOSECONDS_PER_SECOND); 1619 * 1620 * We don't do that. Rather we intentionally use integer division 1621 * truncation below and in the caller for the conversion of host monotonic 1622 * time to guest ticks to provide the exact inverse for the semantics of 1623 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1624 * it loses precision when representing frequencies where 1625 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1626 * provide an exact inverse leads to scheduling timers with negative 1627 * periods, which in turn leads to sticky behaviour in the guest. 1628 * 1629 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1630 * cannot become zero. 1631 */ 1632 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1633 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1634 } 1635 1636 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1637 { 1638 CPUARMState *env = &cpu->env; 1639 bool no_aa32 = false; 1640 1641 /* 1642 * Some features automatically imply others: set the feature 1643 * bits explicitly for these cases. 1644 */ 1645 1646 if (arm_feature(env, ARM_FEATURE_M)) { 1647 set_feature(env, ARM_FEATURE_PMSA); 1648 } 1649 1650 if (arm_feature(env, ARM_FEATURE_V8)) { 1651 if (arm_feature(env, ARM_FEATURE_M)) { 1652 set_feature(env, ARM_FEATURE_V7); 1653 } else { 1654 set_feature(env, ARM_FEATURE_V7VE); 1655 } 1656 } 1657 1658 /* 1659 * There exist AArch64 cpus without AArch32 support. When KVM 1660 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1661 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1662 * As a general principle, we also do not make ID register 1663 * consistency checks anywhere unless using TCG, because only 1664 * for TCG would a consistency-check failure be a QEMU bug. 1665 */ 1666 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1667 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1668 } 1669 1670 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1671 /* 1672 * v7 Virtualization Extensions. In real hardware this implies 1673 * EL2 and also the presence of the Security Extensions. 1674 * For QEMU, for backwards-compatibility we implement some 1675 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1676 * include the various other features that V7VE implies. 1677 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1678 * Security Extensions is ARM_FEATURE_EL3. 1679 */ 1680 assert(!tcg_enabled() || no_aa32 || 1681 cpu_isar_feature(aa32_arm_div, cpu)); 1682 set_feature(env, ARM_FEATURE_LPAE); 1683 set_feature(env, ARM_FEATURE_V7); 1684 } 1685 if (arm_feature(env, ARM_FEATURE_V7)) { 1686 set_feature(env, ARM_FEATURE_VAPA); 1687 set_feature(env, ARM_FEATURE_THUMB2); 1688 set_feature(env, ARM_FEATURE_MPIDR); 1689 if (!arm_feature(env, ARM_FEATURE_M)) { 1690 set_feature(env, ARM_FEATURE_V6K); 1691 } else { 1692 set_feature(env, ARM_FEATURE_V6); 1693 } 1694 1695 /* 1696 * Always define VBAR for V7 CPUs even if it doesn't exist in 1697 * non-EL3 configs. This is needed by some legacy boards. 1698 */ 1699 set_feature(env, ARM_FEATURE_VBAR); 1700 } 1701 if (arm_feature(env, ARM_FEATURE_V6K)) { 1702 set_feature(env, ARM_FEATURE_V6); 1703 set_feature(env, ARM_FEATURE_MVFR); 1704 } 1705 if (arm_feature(env, ARM_FEATURE_V6)) { 1706 set_feature(env, ARM_FEATURE_V5); 1707 if (!arm_feature(env, ARM_FEATURE_M)) { 1708 assert(!tcg_enabled() || no_aa32 || 1709 cpu_isar_feature(aa32_jazelle, cpu)); 1710 set_feature(env, ARM_FEATURE_AUXCR); 1711 } 1712 } 1713 if (arm_feature(env, ARM_FEATURE_V5)) { 1714 set_feature(env, ARM_FEATURE_V4T); 1715 } 1716 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1717 set_feature(env, ARM_FEATURE_V7MP); 1718 } 1719 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1720 set_feature(env, ARM_FEATURE_CBAR); 1721 } 1722 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1723 !arm_feature(env, ARM_FEATURE_M)) { 1724 set_feature(env, ARM_FEATURE_THUMB_DSP); 1725 } 1726 } 1727 1728 void arm_cpu_post_init(Object *obj) 1729 { 1730 ARMCPU *cpu = ARM_CPU(obj); 1731 1732 /* 1733 * Some features imply others. Figure this out now, because we 1734 * are going to look at the feature bits in deciding which 1735 * properties to add. 1736 */ 1737 arm_cpu_propagate_feature_implications(cpu); 1738 1739 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1740 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1741 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1742 } 1743 1744 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1745 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1746 } 1747 1748 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1749 object_property_add_uint64_ptr(obj, "rvbar", 1750 &cpu->rvbar_prop, 1751 OBJ_PROP_FLAG_READWRITE); 1752 } 1753 1754 #ifndef CONFIG_USER_ONLY 1755 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1756 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1757 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1758 */ 1759 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1760 1761 object_property_add_link(obj, "secure-memory", 1762 TYPE_MEMORY_REGION, 1763 (Object **)&cpu->secure_memory, 1764 qdev_prop_allow_set_link_before_realize, 1765 OBJ_PROP_LINK_STRONG); 1766 } 1767 1768 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1769 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1770 } 1771 #endif 1772 1773 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1774 cpu->has_pmu = true; 1775 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1776 } 1777 1778 /* 1779 * Allow user to turn off VFP and Neon support, but only for TCG -- 1780 * KVM does not currently allow us to lie to the guest about its 1781 * ID/feature registers, so the guest always sees what the host has. 1782 */ 1783 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1784 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1785 cpu->has_vfp = true; 1786 cpu->has_vfp_d32 = true; 1787 if (tcg_enabled() || qtest_enabled()) { 1788 qdev_property_add_static(DEVICE(obj), 1789 &arm_cpu_has_vfp_property); 1790 } 1791 } 1792 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1793 cpu->has_vfp = true; 1794 if (tcg_enabled() || qtest_enabled()) { 1795 qdev_property_add_static(DEVICE(obj), 1796 &arm_cpu_has_vfp_property); 1797 } 1798 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1799 cpu->has_vfp_d32 = true; 1800 /* 1801 * The permitted values of the SIMDReg bits [3:0] on 1802 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1803 * make sure that has_vfp_d32 can not be set to false. 1804 */ 1805 if ((tcg_enabled() || qtest_enabled()) 1806 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1807 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1808 qdev_property_add_static(DEVICE(obj), 1809 &arm_cpu_has_vfp_d32_property); 1810 } 1811 } 1812 } 1813 1814 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1815 cpu->has_neon = true; 1816 if (!kvm_enabled()) { 1817 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1818 } 1819 } 1820 1821 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1822 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1823 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1824 } 1825 1826 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1827 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1828 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1829 qdev_property_add_static(DEVICE(obj), 1830 &arm_cpu_pmsav7_dregion_property); 1831 } 1832 } 1833 1834 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1835 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1836 qdev_prop_allow_set_link_before_realize, 1837 OBJ_PROP_LINK_STRONG); 1838 /* 1839 * M profile: initial value of the Secure VTOR. We can't just use 1840 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1841 * the property to be set after realize. 1842 */ 1843 object_property_add_uint32_ptr(obj, "init-svtor", 1844 &cpu->init_svtor, 1845 OBJ_PROP_FLAG_READWRITE); 1846 } 1847 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1848 /* 1849 * Initial value of the NS VTOR (for cores without the Security 1850 * extension, this is the only VTOR) 1851 */ 1852 object_property_add_uint32_ptr(obj, "init-nsvtor", 1853 &cpu->init_nsvtor, 1854 OBJ_PROP_FLAG_READWRITE); 1855 } 1856 1857 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1858 object_property_add_uint32_ptr(obj, "psci-conduit", 1859 &cpu->psci_conduit, 1860 OBJ_PROP_FLAG_READWRITE); 1861 1862 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1863 1864 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1865 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1866 } 1867 1868 if (kvm_enabled()) { 1869 kvm_arm_add_vcpu_properties(cpu); 1870 } 1871 1872 #ifndef CONFIG_USER_ONLY 1873 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1874 cpu_isar_feature(aa64_mte, cpu)) { 1875 object_property_add_link(obj, "tag-memory", 1876 TYPE_MEMORY_REGION, 1877 (Object **)&cpu->tag_memory, 1878 qdev_prop_allow_set_link_before_realize, 1879 OBJ_PROP_LINK_STRONG); 1880 1881 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1882 object_property_add_link(obj, "secure-tag-memory", 1883 TYPE_MEMORY_REGION, 1884 (Object **)&cpu->secure_tag_memory, 1885 qdev_prop_allow_set_link_before_realize, 1886 OBJ_PROP_LINK_STRONG); 1887 } 1888 } 1889 #endif 1890 } 1891 1892 static void arm_cpu_finalizefn(Object *obj) 1893 { 1894 ARMCPU *cpu = ARM_CPU(obj); 1895 ARMELChangeHook *hook, *next; 1896 1897 g_hash_table_destroy(cpu->cp_regs); 1898 1899 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1900 QLIST_REMOVE(hook, node); 1901 g_free(hook); 1902 } 1903 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1904 QLIST_REMOVE(hook, node); 1905 g_free(hook); 1906 } 1907 #ifndef CONFIG_USER_ONLY 1908 if (cpu->pmu_timer) { 1909 timer_free(cpu->pmu_timer); 1910 } 1911 if (cpu->wfxt_timer) { 1912 timer_free(cpu->wfxt_timer); 1913 } 1914 #endif 1915 } 1916 1917 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1918 { 1919 Error *local_err = NULL; 1920 1921 #ifdef TARGET_AARCH64 1922 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1923 arm_cpu_sve_finalize(cpu, &local_err); 1924 if (local_err != NULL) { 1925 error_propagate(errp, local_err); 1926 return; 1927 } 1928 1929 /* 1930 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless 1931 * FEAT_SME_FA64 is present). However our implementation currently 1932 * assumes it, so if the user asked for sve=off then turn off SME also. 1933 * (KVM doesn't currently support SME at all.) 1934 */ 1935 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) { 1936 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort); 1937 } 1938 1939 arm_cpu_sme_finalize(cpu, &local_err); 1940 if (local_err != NULL) { 1941 error_propagate(errp, local_err); 1942 return; 1943 } 1944 1945 arm_cpu_pauth_finalize(cpu, &local_err); 1946 if (local_err != NULL) { 1947 error_propagate(errp, local_err); 1948 return; 1949 } 1950 1951 arm_cpu_lpa2_finalize(cpu, &local_err); 1952 if (local_err != NULL) { 1953 error_propagate(errp, local_err); 1954 return; 1955 } 1956 } 1957 #endif 1958 1959 if (kvm_enabled()) { 1960 kvm_arm_steal_time_finalize(cpu, &local_err); 1961 if (local_err != NULL) { 1962 error_propagate(errp, local_err); 1963 return; 1964 } 1965 } 1966 } 1967 1968 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1969 { 1970 CPUState *cs = CPU(dev); 1971 ARMCPU *cpu = ARM_CPU(dev); 1972 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1973 CPUARMState *env = &cpu->env; 1974 Error *local_err = NULL; 1975 1976 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 1977 /* Use pc-relative instructions in system-mode */ 1978 tcg_cflags_set(cs, CF_PCREL); 1979 #endif 1980 1981 /* If we needed to query the host kernel for the CPU features 1982 * then it's possible that might have failed in the initfn, but 1983 * this is the first point where we can report it. 1984 */ 1985 if (cpu->host_cpu_probe_failed) { 1986 if (!kvm_enabled() && !hvf_enabled()) { 1987 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1988 } else { 1989 error_setg(errp, "Failed to retrieve host CPU features"); 1990 } 1991 return; 1992 } 1993 1994 if (!cpu->gt_cntfrq_hz) { 1995 /* 1996 * 0 means "the board didn't set a value, use the default". (We also 1997 * get here for the CONFIG_USER_ONLY case.) 1998 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before 1999 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, 2000 * which gives a 16ns tick period. 2001 * 2002 * We will use the back-compat value: 2003 * - for QEMU CPU types added before we standardized on 1GHz 2004 * - for versioned machine types with a version of 9.0 or earlier 2005 */ 2006 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || 2007 cpu->backcompat_cntfrq) { 2008 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; 2009 } else { 2010 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; 2011 } 2012 } 2013 2014 #ifndef CONFIG_USER_ONLY 2015 /* The NVIC and M-profile CPU are two halves of a single piece of 2016 * hardware; trying to use one without the other is a command line 2017 * error and will result in segfaults if not caught here. 2018 */ 2019 if (arm_feature(env, ARM_FEATURE_M)) { 2020 if (!env->nvic) { 2021 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 2022 return; 2023 } 2024 } else { 2025 if (env->nvic) { 2026 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 2027 return; 2028 } 2029 } 2030 2031 if (!tcg_enabled() && !qtest_enabled()) { 2032 /* 2033 * We assume that no accelerator except TCG (and the "not really an 2034 * accelerator" qtest) can handle these features, because Arm hardware 2035 * virtualization can't virtualize them. 2036 * 2037 * Catch all the cases which might cause us to create more than one 2038 * address space for the CPU (otherwise we will assert() later in 2039 * cpu_address_space_init()). 2040 */ 2041 if (arm_feature(env, ARM_FEATURE_M)) { 2042 error_setg(errp, 2043 "Cannot enable %s when using an M-profile guest CPU", 2044 current_accel_name()); 2045 return; 2046 } 2047 if (cpu->has_el3) { 2048 error_setg(errp, 2049 "Cannot enable %s when guest CPU has EL3 enabled", 2050 current_accel_name()); 2051 return; 2052 } 2053 if (cpu->tag_memory) { 2054 error_setg(errp, 2055 "Cannot enable %s when guest CPUs has MTE enabled", 2056 current_accel_name()); 2057 return; 2058 } 2059 } 2060 2061 { 2062 uint64_t scale = gt_cntfrq_period_ns(cpu); 2063 2064 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2065 arm_gt_ptimer_cb, cpu); 2066 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2067 arm_gt_vtimer_cb, cpu); 2068 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2069 arm_gt_htimer_cb, cpu); 2070 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2071 arm_gt_stimer_cb, cpu); 2072 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2073 arm_gt_hvtimer_cb, cpu); 2074 cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2075 arm_gt_sel2timer_cb, cpu); 2076 cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2077 arm_gt_sel2vtimer_cb, cpu); 2078 } 2079 #endif 2080 2081 cpu_exec_realizefn(cs, &local_err); 2082 if (local_err != NULL) { 2083 error_propagate(errp, local_err); 2084 return; 2085 } 2086 2087 arm_cpu_finalize_features(cpu, &local_err); 2088 if (local_err != NULL) { 2089 error_propagate(errp, local_err); 2090 return; 2091 } 2092 2093 #ifdef CONFIG_USER_ONLY 2094 /* 2095 * User mode relies on IC IVAU instructions to catch modification of 2096 * dual-mapped code. 2097 * 2098 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 2099 * IC IVAU even if the emulated processor does not normally require it. 2100 */ 2101 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 2102 #endif 2103 2104 if (arm_feature(env, ARM_FEATURE_AARCH64) && 2105 cpu->has_vfp != cpu->has_neon) { 2106 /* 2107 * This is an architectural requirement for AArch64; AArch32 is 2108 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 2109 */ 2110 error_setg(errp, 2111 "AArch64 CPUs must have both VFP and Neon or neither"); 2112 return; 2113 } 2114 2115 if (cpu->has_vfp_d32 != cpu->has_neon) { 2116 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 2117 return; 2118 } 2119 2120 if (!cpu->has_vfp_d32) { 2121 uint32_t u; 2122 2123 u = cpu->isar.mvfr0; 2124 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 2125 cpu->isar.mvfr0 = u; 2126 } 2127 2128 if (!cpu->has_vfp) { 2129 uint64_t t; 2130 uint32_t u; 2131 2132 t = cpu->isar.id_aa64isar1; 2133 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 2134 cpu->isar.id_aa64isar1 = t; 2135 2136 t = cpu->isar.id_aa64pfr0; 2137 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 2138 cpu->isar.id_aa64pfr0 = t; 2139 2140 u = cpu->isar.id_isar6; 2141 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 2142 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2143 cpu->isar.id_isar6 = u; 2144 2145 u = cpu->isar.mvfr0; 2146 u = FIELD_DP32(u, MVFR0, FPSP, 0); 2147 u = FIELD_DP32(u, MVFR0, FPDP, 0); 2148 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 2149 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 2150 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 2151 if (!arm_feature(env, ARM_FEATURE_M)) { 2152 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 2153 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 2154 } 2155 cpu->isar.mvfr0 = u; 2156 2157 u = cpu->isar.mvfr1; 2158 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 2159 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 2160 u = FIELD_DP32(u, MVFR1, FPHP, 0); 2161 if (arm_feature(env, ARM_FEATURE_M)) { 2162 u = FIELD_DP32(u, MVFR1, FP16, 0); 2163 } 2164 cpu->isar.mvfr1 = u; 2165 2166 u = cpu->isar.mvfr2; 2167 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 2168 cpu->isar.mvfr2 = u; 2169 } 2170 2171 if (!cpu->has_neon) { 2172 uint64_t t; 2173 uint32_t u; 2174 2175 unset_feature(env, ARM_FEATURE_NEON); 2176 2177 t = cpu->isar.id_aa64isar0; 2178 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 2179 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 2180 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 2181 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 2182 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 2183 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 2184 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 2185 cpu->isar.id_aa64isar0 = t; 2186 2187 t = cpu->isar.id_aa64isar1; 2188 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 2189 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 2190 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 2191 cpu->isar.id_aa64isar1 = t; 2192 2193 t = cpu->isar.id_aa64pfr0; 2194 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 2195 cpu->isar.id_aa64pfr0 = t; 2196 2197 u = cpu->isar.id_isar5; 2198 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 2199 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 2200 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 2201 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 2202 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 2203 cpu->isar.id_isar5 = u; 2204 2205 u = cpu->isar.id_isar6; 2206 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 2207 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 2208 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2209 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 2210 cpu->isar.id_isar6 = u; 2211 2212 if (!arm_feature(env, ARM_FEATURE_M)) { 2213 u = cpu->isar.mvfr1; 2214 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 2215 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 2216 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 2217 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 2218 cpu->isar.mvfr1 = u; 2219 2220 u = cpu->isar.mvfr2; 2221 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 2222 cpu->isar.mvfr2 = u; 2223 } 2224 } 2225 2226 if (!cpu->has_neon && !cpu->has_vfp) { 2227 uint64_t t; 2228 uint32_t u; 2229 2230 t = cpu->isar.id_aa64isar0; 2231 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 2232 cpu->isar.id_aa64isar0 = t; 2233 2234 t = cpu->isar.id_aa64isar1; 2235 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 2236 cpu->isar.id_aa64isar1 = t; 2237 2238 u = cpu->isar.mvfr0; 2239 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 2240 cpu->isar.mvfr0 = u; 2241 2242 /* Despite the name, this field covers both VFP and Neon */ 2243 u = cpu->isar.mvfr1; 2244 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 2245 cpu->isar.mvfr1 = u; 2246 } 2247 2248 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 2249 uint32_t u; 2250 2251 unset_feature(env, ARM_FEATURE_THUMB_DSP); 2252 2253 u = cpu->isar.id_isar1; 2254 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 2255 cpu->isar.id_isar1 = u; 2256 2257 u = cpu->isar.id_isar2; 2258 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 2259 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 2260 cpu->isar.id_isar2 = u; 2261 2262 u = cpu->isar.id_isar3; 2263 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 2264 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 2265 cpu->isar.id_isar3 = u; 2266 } 2267 2268 2269 /* 2270 * We rely on no XScale CPU having VFP so we can use the same bits in the 2271 * TB flags field for VECSTRIDE and XSCALE_CPAR. 2272 */ 2273 assert(arm_feature(env, ARM_FEATURE_AARCH64) || 2274 !cpu_isar_feature(aa32_vfp_simd, cpu) || 2275 !arm_feature(env, ARM_FEATURE_XSCALE)); 2276 2277 #ifndef CONFIG_USER_ONLY 2278 { 2279 int pagebits; 2280 if (arm_feature(env, ARM_FEATURE_V7) && 2281 !arm_feature(env, ARM_FEATURE_M) && 2282 !arm_feature(env, ARM_FEATURE_PMSA)) { 2283 /* 2284 * v7VMSA drops support for the old ARMv5 tiny pages, 2285 * so we can use 4K pages. 2286 */ 2287 pagebits = 12; 2288 } else { 2289 /* 2290 * For CPUs which might have tiny 1K pages, or which have an 2291 * MPU and might have small region sizes, stick with 1K pages. 2292 */ 2293 pagebits = 10; 2294 } 2295 if (!set_preferred_target_page_bits(pagebits)) { 2296 /* 2297 * This can only ever happen for hotplugging a CPU, or if 2298 * the board code incorrectly creates a CPU which it has 2299 * promised via minimum_page_size that it will not. 2300 */ 2301 error_setg(errp, "This CPU requires a smaller page size " 2302 "than the system is using"); 2303 return; 2304 } 2305 } 2306 #endif 2307 2308 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 2309 * We don't support setting cluster ID ([16..23]) (known as Aff2 2310 * in later ARM ARM versions), or any of the higher affinity level fields, 2311 * so these bits always RAZ. 2312 */ 2313 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2314 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, 2315 ARM_DEFAULT_CPUS_PER_CLUSTER); 2316 } 2317 2318 if (cpu->reset_hivecs) { 2319 cpu->reset_sctlr |= (1 << 13); 2320 } 2321 2322 if (cpu->cfgend) { 2323 if (arm_feature(env, ARM_FEATURE_V7)) { 2324 cpu->reset_sctlr |= SCTLR_EE; 2325 } else { 2326 cpu->reset_sctlr |= SCTLR_B; 2327 } 2328 } 2329 2330 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2331 /* If the has_el3 CPU property is disabled then we need to disable the 2332 * feature. 2333 */ 2334 unset_feature(env, ARM_FEATURE_EL3); 2335 2336 /* 2337 * Disable the security extension feature bits in the processor 2338 * feature registers as well. 2339 */ 2340 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 2341 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 2342 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2343 ID_AA64PFR0, EL3, 0); 2344 2345 /* Disable the realm management extension, which requires EL3. */ 2346 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2347 ID_AA64PFR0, RME, 0); 2348 } 2349 2350 if (!cpu->has_el2) { 2351 unset_feature(env, ARM_FEATURE_EL2); 2352 } 2353 2354 if (!cpu->has_pmu) { 2355 unset_feature(env, ARM_FEATURE_PMU); 2356 } 2357 if (arm_feature(env, ARM_FEATURE_PMU)) { 2358 pmu_init(cpu); 2359 2360 if (!kvm_enabled()) { 2361 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2362 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2363 } 2364 2365 #ifndef CONFIG_USER_ONLY 2366 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2367 cpu); 2368 #endif 2369 } else { 2370 cpu->isar.id_aa64dfr0 = 2371 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 2372 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 2373 cpu->pmceid0 = 0; 2374 cpu->pmceid1 = 0; 2375 } 2376 2377 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2378 /* 2379 * Disable the hypervisor feature bits in the processor feature 2380 * registers if we don't have EL2. 2381 */ 2382 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2383 ID_AA64PFR0, EL2, 0); 2384 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 2385 ID_PFR1, VIRTUALIZATION, 0); 2386 } 2387 2388 if (cpu_isar_feature(aa64_mte, cpu)) { 2389 /* 2390 * The architectural range of GM blocksize is 2-6, however qemu 2391 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2392 */ 2393 if (tcg_enabled()) { 2394 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2395 } 2396 2397 #ifndef CONFIG_USER_ONLY 2398 /* 2399 * If we run with TCG and do not have tag-memory provided by 2400 * the machine, then reduce MTE support to instructions enabled at EL0. 2401 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2402 */ 2403 if (tcg_enabled() && cpu->tag_memory == NULL) { 2404 cpu->isar.id_aa64pfr1 = 2405 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); 2406 } 2407 2408 /* 2409 * If MTE is supported by the host, however it should not be 2410 * enabled on the guest (i.e mte=off), clear guest's MTE bits." 2411 */ 2412 if (kvm_enabled() && !cpu->kvm_mte) { 2413 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 2414 } 2415 #endif 2416 } 2417 2418 #ifndef CONFIG_USER_ONLY 2419 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) { 2420 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2421 arm_wfxt_timer_cb, cpu); 2422 } 2423 #endif 2424 2425 if (tcg_enabled()) { 2426 /* 2427 * Don't report some architectural features in the ID registers 2428 * where TCG does not yet implement it (not even a minimal 2429 * stub version). This avoids guests falling over when they 2430 * try to access the non-existent system registers for them. 2431 */ 2432 /* FEAT_SPE (Statistical Profiling Extension) */ 2433 cpu->isar.id_aa64dfr0 = 2434 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2435 /* FEAT_TRBE (Trace Buffer Extension) */ 2436 cpu->isar.id_aa64dfr0 = 2437 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); 2438 /* FEAT_TRF (Self-hosted Trace Extension) */ 2439 cpu->isar.id_aa64dfr0 = 2440 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2441 cpu->isar.id_dfr0 = 2442 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2443 /* Trace Macrocell system register access */ 2444 cpu->isar.id_aa64dfr0 = 2445 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2446 cpu->isar.id_dfr0 = 2447 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2448 /* Memory mapped trace */ 2449 cpu->isar.id_dfr0 = 2450 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2451 /* FEAT_AMU (Activity Monitors Extension) */ 2452 cpu->isar.id_aa64pfr0 = 2453 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2454 cpu->isar.id_pfr0 = 2455 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2456 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2457 cpu->isar.id_aa64pfr0 = 2458 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2459 } 2460 2461 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2462 * to false or by setting pmsav7-dregion to 0. 2463 */ 2464 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2465 cpu->has_mpu = false; 2466 cpu->pmsav7_dregion = 0; 2467 cpu->pmsav8r_hdregion = 0; 2468 } 2469 2470 if (arm_feature(env, ARM_FEATURE_PMSA) && 2471 arm_feature(env, ARM_FEATURE_V7)) { 2472 uint32_t nr = cpu->pmsav7_dregion; 2473 2474 if (nr > 0xff) { 2475 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2476 return; 2477 } 2478 2479 if (nr) { 2480 if (arm_feature(env, ARM_FEATURE_V8)) { 2481 /* PMSAv8 */ 2482 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2483 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2484 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2485 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2486 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2487 } 2488 } else { 2489 env->pmsav7.drbar = g_new0(uint32_t, nr); 2490 env->pmsav7.drsr = g_new0(uint32_t, nr); 2491 env->pmsav7.dracr = g_new0(uint32_t, nr); 2492 } 2493 } 2494 2495 if (cpu->pmsav8r_hdregion > 0xff) { 2496 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2497 cpu->pmsav8r_hdregion); 2498 return; 2499 } 2500 2501 if (cpu->pmsav8r_hdregion) { 2502 env->pmsav8.hprbar = g_new0(uint32_t, 2503 cpu->pmsav8r_hdregion); 2504 env->pmsav8.hprlar = g_new0(uint32_t, 2505 cpu->pmsav8r_hdregion); 2506 } 2507 } 2508 2509 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2510 uint32_t nr = cpu->sau_sregion; 2511 2512 if (nr > 0xff) { 2513 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2514 return; 2515 } 2516 2517 if (nr) { 2518 env->sau.rbar = g_new0(uint32_t, nr); 2519 env->sau.rlar = g_new0(uint32_t, nr); 2520 } 2521 } 2522 2523 if (arm_feature(env, ARM_FEATURE_EL3)) { 2524 set_feature(env, ARM_FEATURE_VBAR); 2525 } 2526 2527 #ifndef CONFIG_USER_ONLY 2528 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2529 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2530 } 2531 #endif 2532 2533 register_cp_regs_for_features(cpu); 2534 arm_cpu_register_gdb_regs_for_features(cpu); 2535 arm_cpu_register_gdb_commands(cpu); 2536 2537 init_cpreg_list(cpu); 2538 2539 #ifndef CONFIG_USER_ONLY 2540 MachineState *ms = MACHINE(qdev_get_machine()); 2541 unsigned int smp_cpus = ms->smp.cpus; 2542 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2543 2544 /* 2545 * We must set cs->num_ases to the final value before 2546 * the first call to cpu_address_space_init. 2547 */ 2548 if (cpu->tag_memory != NULL) { 2549 cs->num_ases = 3 + has_secure; 2550 } else { 2551 cs->num_ases = 1 + has_secure; 2552 } 2553 2554 if (has_secure) { 2555 if (!cpu->secure_memory) { 2556 cpu->secure_memory = cs->memory; 2557 } 2558 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2559 cpu->secure_memory); 2560 } 2561 2562 if (cpu->tag_memory != NULL) { 2563 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2564 cpu->tag_memory); 2565 if (has_secure) { 2566 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2567 cpu->secure_tag_memory); 2568 } 2569 } 2570 2571 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2572 2573 /* No core_count specified, default to smp_cpus. */ 2574 if (cpu->core_count == -1) { 2575 cpu->core_count = smp_cpus; 2576 } 2577 #endif 2578 2579 if (tcg_enabled()) { 2580 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2581 2582 /* 2583 * We only support DCZ blocklen that fits on one page. 2584 * 2585 * Architectually this is always true. However TARGET_PAGE_SIZE 2586 * is variable and, for compatibility with -machine virt-2.7, 2587 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2588 * But even then, while the largest architectural DCZ blocklen 2589 * is 2KiB, no cpu actually uses such a large blocklen. 2590 */ 2591 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2592 2593 /* 2594 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2595 * both nibbles of each byte storing tag data may be written at once. 2596 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2597 */ 2598 if (cpu_isar_feature(aa64_mte, cpu)) { 2599 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2600 } 2601 } 2602 2603 qemu_init_vcpu(cs); 2604 cpu_reset(cs); 2605 2606 acc->parent_realize(dev, errp); 2607 } 2608 2609 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2610 { 2611 ObjectClass *oc; 2612 char *typename; 2613 char **cpuname; 2614 const char *cpunamestr; 2615 2616 cpuname = g_strsplit(cpu_model, ",", 1); 2617 cpunamestr = cpuname[0]; 2618 #ifdef CONFIG_USER_ONLY 2619 /* For backwards compatibility usermode emulation allows "-cpu any", 2620 * which has the same semantics as "-cpu max". 2621 */ 2622 if (!strcmp(cpunamestr, "any")) { 2623 cpunamestr = "max"; 2624 } 2625 #endif 2626 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2627 oc = object_class_by_name(typename); 2628 g_strfreev(cpuname); 2629 g_free(typename); 2630 2631 return oc; 2632 } 2633 2634 static const Property arm_cpu_properties[] = { 2635 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2636 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2637 mp_affinity, ARM64_AFFINITY_INVALID), 2638 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2639 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2640 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ 2641 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), 2642 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, 2643 backcompat_pauth_default_use_qarma5, false), 2644 }; 2645 2646 static const gchar *arm_gdb_arch_name(CPUState *cs) 2647 { 2648 ARMCPU *cpu = ARM_CPU(cs); 2649 CPUARMState *env = &cpu->env; 2650 2651 if (arm_gdbstub_is_aarch64(cpu)) { 2652 return "aarch64"; 2653 } 2654 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2655 return "iwmmxt"; 2656 } 2657 return "arm"; 2658 } 2659 2660 static const char *arm_gdb_get_core_xml_file(CPUState *cs) 2661 { 2662 ARMCPU *cpu = ARM_CPU(cs); 2663 CPUARMState *env = &cpu->env; 2664 2665 if (arm_gdbstub_is_aarch64(cpu)) { 2666 return "aarch64-core.xml"; 2667 } 2668 if (arm_feature(env, ARM_FEATURE_M)) { 2669 return "arm-m-profile.xml"; 2670 } 2671 return "arm-core.xml"; 2672 } 2673 2674 #ifdef CONFIG_USER_ONLY 2675 /** 2676 * aarch64_untagged_addr: 2677 * 2678 * Remove any address tag from @x. This is explicitly related to the 2679 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 2680 * 2681 * There should be a better place to put this, but we need this in 2682 * include/exec/cpu_ldst.h, and not some place linux-user specific. 2683 * 2684 * Note that arm-*-user will never set tagged_addr_enable. 2685 */ 2686 static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x) 2687 { 2688 CPUARMState *env = cpu_env(cs); 2689 if (env->tagged_addr_enable) { 2690 /* 2691 * TBI is enabled for userspace but not kernelspace addresses. 2692 * Only clear the tag if bit 55 is clear. 2693 */ 2694 x &= sextract64(x, 0, 56); 2695 } 2696 return x; 2697 } 2698 #else 2699 #include "hw/core/sysemu-cpu-ops.h" 2700 2701 static const struct SysemuCPUOps arm_sysemu_ops = { 2702 .has_work = arm_cpu_has_work, 2703 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2704 .asidx_from_attrs = arm_asidx_from_attrs, 2705 .write_elf32_note = arm_cpu_write_elf32_note, 2706 .write_elf64_note = arm_cpu_write_elf64_note, 2707 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2708 .legacy_vmsd = &vmstate_arm_cpu, 2709 }; 2710 #endif 2711 2712 #ifdef CONFIG_TCG 2713 static const TCGCPUOps arm_tcg_ops = { 2714 .mttcg_supported = true, 2715 /* ARM processors have a weak memory model */ 2716 .guest_default_memory_order = 0, 2717 2718 .initialize = arm_translate_init, 2719 .translate_code = arm_translate_code, 2720 .get_tb_cpu_state = arm_get_tb_cpu_state, 2721 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2722 .debug_excp_handler = arm_debug_excp_handler, 2723 .restore_state_to_opc = arm_restore_state_to_opc, 2724 .mmu_index = arm_cpu_mmu_index, 2725 2726 #ifdef CONFIG_USER_ONLY 2727 .record_sigsegv = arm_cpu_record_sigsegv, 2728 .record_sigbus = arm_cpu_record_sigbus, 2729 .untagged_addr = aarch64_untagged_addr, 2730 #else 2731 .tlb_fill_align = arm_cpu_tlb_fill_align, 2732 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2733 .cpu_exec_halt = arm_cpu_exec_halt, 2734 .cpu_exec_reset = cpu_reset, 2735 .do_interrupt = arm_cpu_do_interrupt, 2736 .do_transaction_failed = arm_cpu_do_transaction_failed, 2737 .do_unaligned_access = arm_cpu_do_unaligned_access, 2738 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2739 .debug_check_watchpoint = arm_debug_check_watchpoint, 2740 .debug_check_breakpoint = arm_debug_check_breakpoint, 2741 #endif /* !CONFIG_USER_ONLY */ 2742 }; 2743 #endif /* CONFIG_TCG */ 2744 2745 static void arm_cpu_class_init(ObjectClass *oc, const void *data) 2746 { 2747 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2748 CPUClass *cc = CPU_CLASS(acc); 2749 DeviceClass *dc = DEVICE_CLASS(oc); 2750 ResettableClass *rc = RESETTABLE_CLASS(oc); 2751 2752 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2753 &acc->parent_realize); 2754 2755 device_class_set_props(dc, arm_cpu_properties); 2756 2757 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2758 &acc->parent_phases); 2759 2760 cc->class_by_name = arm_cpu_class_by_name; 2761 cc->dump_state = arm_cpu_dump_state; 2762 cc->set_pc = arm_cpu_set_pc; 2763 cc->get_pc = arm_cpu_get_pc; 2764 cc->gdb_read_register = arm_cpu_gdb_read_register; 2765 cc->gdb_write_register = arm_cpu_gdb_write_register; 2766 #ifndef CONFIG_USER_ONLY 2767 cc->sysemu_ops = &arm_sysemu_ops; 2768 #endif 2769 cc->gdb_arch_name = arm_gdb_arch_name; 2770 cc->gdb_get_core_xml_file = arm_gdb_get_core_xml_file; 2771 cc->gdb_stop_before_watchpoint = true; 2772 cc->disas_set_info = arm_disas_set_info; 2773 2774 #ifdef CONFIG_TCG 2775 cc->tcg_ops = &arm_tcg_ops; 2776 #endif /* CONFIG_TCG */ 2777 } 2778 2779 static void arm_cpu_instance_init(Object *obj) 2780 { 2781 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2782 2783 acc->info->initfn(obj); 2784 arm_cpu_post_init(obj); 2785 } 2786 2787 static void cpu_register_class_init(ObjectClass *oc, const void *data) 2788 { 2789 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2790 CPUClass *cc = CPU_CLASS(acc); 2791 2792 acc->info = data; 2793 if (acc->info->deprecation_note) { 2794 cc->deprecation_note = acc->info->deprecation_note; 2795 } 2796 } 2797 2798 void arm_cpu_register(const ARMCPUInfo *info) 2799 { 2800 TypeInfo type_info = { 2801 .parent = TYPE_ARM_CPU, 2802 .instance_init = arm_cpu_instance_init, 2803 .class_init = info->class_init ?: cpu_register_class_init, 2804 .class_data = info, 2805 }; 2806 2807 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2808 type_register_static(&type_info); 2809 g_free((void *)type_info.name); 2810 } 2811 2812 static const TypeInfo arm_cpu_type_info = { 2813 .name = TYPE_ARM_CPU, 2814 .parent = TYPE_CPU, 2815 .instance_size = sizeof(ARMCPU), 2816 .instance_align = __alignof__(ARMCPU), 2817 .instance_init = arm_cpu_initfn, 2818 .instance_finalize = arm_cpu_finalizefn, 2819 .abstract = true, 2820 .class_size = sizeof(ARMCPUClass), 2821 .class_init = arm_cpu_class_init, 2822 }; 2823 2824 static void arm_cpu_register_types(void) 2825 { 2826 type_register_static(&arm_cpu_type_info); 2827 } 2828 2829 type_init(arm_cpu_register_types) 2830