1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "exec/translation-block.h" 32 #include "accel/tcg/cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "cpu-features.h" 36 #include "exec/exec-all.h" 37 #include "hw/qdev-properties.h" 38 #if !defined(CONFIG_USER_ONLY) 39 #include "hw/loader.h" 40 #include "hw/boards.h" 41 #ifdef CONFIG_TCG 42 #include "hw/intc/armv7m_nvic.h" 43 #endif /* CONFIG_TCG */ 44 #endif /* !CONFIG_USER_ONLY */ 45 #include "system/tcg.h" 46 #include "system/qtest.h" 47 #include "system/hw_accel.h" 48 #include "kvm_arm.h" 49 #include "disas/capstone.h" 50 #include "fpu/softfloat.h" 51 #include "cpregs.h" 52 #include "target/arm/cpu-qom.h" 53 #include "target/arm/gtimer.h" 54 55 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 56 { 57 ARMCPU *cpu = ARM_CPU(cs); 58 CPUARMState *env = &cpu->env; 59 60 if (is_a64(env)) { 61 env->pc = value; 62 env->thumb = false; 63 } else { 64 env->regs[15] = value & ~1; 65 env->thumb = value & 1; 66 } 67 } 68 69 static vaddr arm_cpu_get_pc(CPUState *cs) 70 { 71 ARMCPU *cpu = ARM_CPU(cs); 72 CPUARMState *env = &cpu->env; 73 74 if (is_a64(env)) { 75 return env->pc; 76 } else { 77 return env->regs[15]; 78 } 79 } 80 81 #ifdef CONFIG_TCG 82 void arm_cpu_synchronize_from_tb(CPUState *cs, 83 const TranslationBlock *tb) 84 { 85 /* The program counter is always up to date with CF_PCREL. */ 86 if (!(tb_cflags(tb) & CF_PCREL)) { 87 CPUARMState *env = cpu_env(cs); 88 /* 89 * It's OK to look at env for the current mode here, because it's 90 * never possible for an AArch64 TB to chain to an AArch32 TB. 91 */ 92 if (is_a64(env)) { 93 env->pc = tb->pc; 94 } else { 95 env->regs[15] = tb->pc; 96 } 97 } 98 } 99 100 void arm_restore_state_to_opc(CPUState *cs, 101 const TranslationBlock *tb, 102 const uint64_t *data) 103 { 104 CPUARMState *env = cpu_env(cs); 105 106 if (is_a64(env)) { 107 if (tb_cflags(tb) & CF_PCREL) { 108 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 109 } else { 110 env->pc = data[0]; 111 } 112 env->condexec_bits = 0; 113 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 114 } else { 115 if (tb_cflags(tb) & CF_PCREL) { 116 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 117 } else { 118 env->regs[15] = data[0]; 119 } 120 env->condexec_bits = data[1]; 121 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 122 } 123 } 124 #endif /* CONFIG_TCG */ 125 126 /* 127 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with 128 * IRQ without Superpriority. Moreover, if the GIC is configured so that 129 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see 130 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here 131 * unconditionally. 132 */ 133 static bool arm_cpu_has_work(CPUState *cs) 134 { 135 ARMCPU *cpu = ARM_CPU(cs); 136 137 return (cpu->power_state != PSCI_OFF) 138 && cs->interrupt_request & 139 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 140 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI 141 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 142 | CPU_INTERRUPT_EXITTB); 143 } 144 145 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) 146 { 147 return arm_env_mmu_index(cpu_env(cs)); 148 } 149 150 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 151 void *opaque) 152 { 153 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 154 155 entry->hook = hook; 156 entry->opaque = opaque; 157 158 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 159 } 160 161 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 162 void *opaque) 163 { 164 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 165 166 entry->hook = hook; 167 entry->opaque = opaque; 168 169 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 170 } 171 172 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 173 { 174 /* Reset a single ARMCPRegInfo register */ 175 ARMCPRegInfo *ri = value; 176 ARMCPU *cpu = opaque; 177 178 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 179 return; 180 } 181 182 if (ri->resetfn) { 183 ri->resetfn(&cpu->env, ri); 184 return; 185 } 186 187 /* A zero offset is never possible as it would be regs[0] 188 * so we use it to indicate that reset is being handled elsewhere. 189 * This is basically only used for fields in non-core coprocessors 190 * (like the pxa2xx ones). 191 */ 192 if (!ri->fieldoffset) { 193 return; 194 } 195 196 if (cpreg_field_is_64bit(ri)) { 197 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 198 } else { 199 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 200 } 201 } 202 203 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 204 { 205 /* Purely an assertion check: we've already done reset once, 206 * so now check that running the reset for the cpreg doesn't 207 * change its value. This traps bugs where two different cpregs 208 * both try to reset the same state field but to different values. 209 */ 210 ARMCPRegInfo *ri = value; 211 ARMCPU *cpu = opaque; 212 uint64_t oldvalue, newvalue; 213 214 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 215 return; 216 } 217 218 oldvalue = read_raw_cp_reg(&cpu->env, ri); 219 cp_reg_reset(key, value, opaque); 220 newvalue = read_raw_cp_reg(&cpu->env, ri); 221 assert(oldvalue == newvalue); 222 } 223 224 static void arm_cpu_reset_hold(Object *obj, ResetType type) 225 { 226 CPUState *cs = CPU(obj); 227 ARMCPU *cpu = ARM_CPU(cs); 228 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 229 CPUARMState *env = &cpu->env; 230 231 if (acc->parent_phases.hold) { 232 acc->parent_phases.hold(obj, type); 233 } 234 235 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 236 237 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 238 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 239 240 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 241 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 242 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 243 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 244 245 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; 246 247 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 248 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 249 } 250 251 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 252 /* 64 bit CPUs always start in 64 bit mode */ 253 env->aarch64 = true; 254 #if defined(CONFIG_USER_ONLY) 255 env->pstate = PSTATE_MODE_EL0t; 256 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 257 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 258 /* Enable all PAC keys. */ 259 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 260 SCTLR_EnDA | SCTLR_EnDB); 261 /* Trap on btype=3 for PACIxSP. */ 262 env->cp15.sctlr_el[1] |= SCTLR_BT0; 263 /* Trap on implementation defined registers. */ 264 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 265 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 266 } 267 /* and to the FP/Neon instructions */ 268 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 269 CPACR_EL1, FPEN, 3); 270 /* and to the SVE instructions, with default vector length */ 271 if (cpu_isar_feature(aa64_sve, cpu)) { 272 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 273 CPACR_EL1, ZEN, 3); 274 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 275 } 276 /* and for SME instructions, with default vector length, and TPIDR2 */ 277 if (cpu_isar_feature(aa64_sme, cpu)) { 278 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 279 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 280 CPACR_EL1, SMEN, 3); 281 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 282 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 283 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 284 SMCR, FA64, 1); 285 } 286 } 287 /* 288 * Enable 48-bit address space (TODO: take reserved_va into account). 289 * Enable TBI0 but not TBI1. 290 * Note that this must match useronly_clean_ptr. 291 */ 292 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 293 294 /* Enable MTE */ 295 if (cpu_isar_feature(aa64_mte, cpu)) { 296 /* Enable tag access, but leave TCF0 as No Effect (0). */ 297 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 298 /* 299 * Exclude all tags, so that tag 0 is always used. 300 * This corresponds to Linux current->thread.gcr_incl = 0. 301 * 302 * Set RRND, so that helper_irg() will generate a seed later. 303 * Here in cpu_reset(), the crypto subsystem has not yet been 304 * initialized. 305 */ 306 env->cp15.gcr_el1 = 0x1ffff; 307 } 308 /* 309 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 310 * This is not yet exposed from the Linux kernel in any way. 311 */ 312 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 313 /* Disable access to Debug Communication Channel (DCC). */ 314 env->cp15.mdscr_el1 |= 1 << 12; 315 /* Enable FEAT_MOPS */ 316 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; 317 #else 318 /* Reset into the highest available EL */ 319 if (arm_feature(env, ARM_FEATURE_EL3)) { 320 env->pstate = PSTATE_MODE_EL3h; 321 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 322 env->pstate = PSTATE_MODE_EL2h; 323 } else { 324 env->pstate = PSTATE_MODE_EL1h; 325 } 326 327 /* Sample rvbar at reset. */ 328 env->cp15.rvbar = cpu->rvbar_prop; 329 env->pc = env->cp15.rvbar; 330 #endif 331 } else { 332 #if defined(CONFIG_USER_ONLY) 333 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 334 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 335 CPACR, CP10, 3); 336 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 337 CPACR, CP11, 3); 338 #endif 339 if (arm_feature(env, ARM_FEATURE_V8)) { 340 env->cp15.rvbar = cpu->rvbar_prop; 341 env->regs[15] = cpu->rvbar_prop; 342 } 343 } 344 345 #if defined(CONFIG_USER_ONLY) 346 env->uncached_cpsr = ARM_CPU_MODE_USR; 347 /* For user mode we must enable access to coprocessors */ 348 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 349 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 350 env->cp15.c15_cpar = 3; 351 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 352 env->cp15.c15_cpar = 1; 353 } 354 #else 355 356 /* 357 * If the highest available EL is EL2, AArch32 will start in Hyp 358 * mode; otherwise it starts in SVC. Note that if we start in 359 * AArch64 then these values in the uncached_cpsr will be ignored. 360 */ 361 if (arm_feature(env, ARM_FEATURE_EL2) && 362 !arm_feature(env, ARM_FEATURE_EL3)) { 363 env->uncached_cpsr = ARM_CPU_MODE_HYP; 364 } else { 365 env->uncached_cpsr = ARM_CPU_MODE_SVC; 366 } 367 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 368 369 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 370 * executing as AArch32 then check if highvecs are enabled and 371 * adjust the PC accordingly. 372 */ 373 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 374 env->regs[15] = 0xFFFF0000; 375 } 376 377 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 378 #endif 379 380 if (arm_feature(env, ARM_FEATURE_M)) { 381 #ifndef CONFIG_USER_ONLY 382 uint32_t initial_msp; /* Loaded from 0x0 */ 383 uint32_t initial_pc; /* Loaded from 0x4 */ 384 uint8_t *rom; 385 uint32_t vecbase; 386 #endif 387 388 if (cpu_isar_feature(aa32_lob, cpu)) { 389 /* 390 * LTPSIZE is constant 4 if MVE not implemented, and resets 391 * to an UNKNOWN value if MVE is implemented. We choose to 392 * always reset to 4. 393 */ 394 env->v7m.ltpsize = 4; 395 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 396 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 397 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 398 } 399 400 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 401 env->v7m.secure = true; 402 } else { 403 /* This bit resets to 0 if security is supported, but 1 if 404 * it is not. The bit is not present in v7M, but we set it 405 * here so we can avoid having to make checks on it conditional 406 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 407 */ 408 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 409 /* 410 * Set NSACR to indicate "NS access permitted to everything"; 411 * this avoids having to have all the tests of it being 412 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 413 * v8.1M the guest-visible value of NSACR in a CPU without the 414 * Security Extension is 0xcff. 415 */ 416 env->v7m.nsacr = 0xcff; 417 } 418 419 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 420 * that it resets to 1, so QEMU always does that rather than making 421 * it dependent on CPU model. In v8M it is RES1. 422 */ 423 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 424 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 425 if (arm_feature(env, ARM_FEATURE_V8)) { 426 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 427 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 428 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 429 } 430 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 431 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 432 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 433 } 434 435 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 436 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 437 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 438 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 439 } 440 441 #ifndef CONFIG_USER_ONLY 442 /* Unlike A/R profile, M profile defines the reset LR value */ 443 env->regs[14] = 0xffffffff; 444 445 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 446 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 447 448 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 449 vecbase = env->v7m.vecbase[env->v7m.secure]; 450 rom = rom_ptr_for_as(cs->as, vecbase, 8); 451 if (rom) { 452 /* Address zero is covered by ROM which hasn't yet been 453 * copied into physical memory. 454 */ 455 initial_msp = ldl_p(rom); 456 initial_pc = ldl_p(rom + 4); 457 } else { 458 /* Address zero not covered by a ROM blob, or the ROM blob 459 * is in non-modifiable memory and this is a second reset after 460 * it got copied into memory. In the latter case, rom_ptr 461 * will return a NULL pointer and we should use ldl_phys instead. 462 */ 463 initial_msp = ldl_phys(cs->as, vecbase); 464 initial_pc = ldl_phys(cs->as, vecbase + 4); 465 } 466 467 qemu_log_mask(CPU_LOG_INT, 468 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 469 initial_msp, initial_pc); 470 471 env->regs[13] = initial_msp & 0xFFFFFFFC; 472 env->regs[15] = initial_pc & ~1; 473 env->thumb = initial_pc & 1; 474 #else 475 /* 476 * For user mode we run non-secure and with access to the FPU. 477 * The FPU context is active (ie does not need further setup) 478 * and is owned by non-secure. 479 */ 480 env->v7m.secure = false; 481 env->v7m.nsacr = 0xcff; 482 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 483 env->v7m.fpccr[M_REG_S] &= 484 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 485 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 486 #endif 487 } 488 489 /* M profile requires that reset clears the exclusive monitor; 490 * A profile does not, but clearing it makes more sense than having it 491 * set with an exclusive access on address zero. 492 */ 493 arm_clear_exclusive(env); 494 495 if (arm_feature(env, ARM_FEATURE_PMSA)) { 496 if (cpu->pmsav7_dregion > 0) { 497 if (arm_feature(env, ARM_FEATURE_V8)) { 498 memset(env->pmsav8.rbar[M_REG_NS], 0, 499 sizeof(*env->pmsav8.rbar[M_REG_NS]) 500 * cpu->pmsav7_dregion); 501 memset(env->pmsav8.rlar[M_REG_NS], 0, 502 sizeof(*env->pmsav8.rlar[M_REG_NS]) 503 * cpu->pmsav7_dregion); 504 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 505 memset(env->pmsav8.rbar[M_REG_S], 0, 506 sizeof(*env->pmsav8.rbar[M_REG_S]) 507 * cpu->pmsav7_dregion); 508 memset(env->pmsav8.rlar[M_REG_S], 0, 509 sizeof(*env->pmsav8.rlar[M_REG_S]) 510 * cpu->pmsav7_dregion); 511 } 512 } else if (arm_feature(env, ARM_FEATURE_V7)) { 513 memset(env->pmsav7.drbar, 0, 514 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 515 memset(env->pmsav7.drsr, 0, 516 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 517 memset(env->pmsav7.dracr, 0, 518 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 519 } 520 } 521 522 if (cpu->pmsav8r_hdregion > 0) { 523 memset(env->pmsav8.hprbar, 0, 524 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 525 memset(env->pmsav8.hprlar, 0, 526 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 527 } 528 529 env->pmsav7.rnr[M_REG_NS] = 0; 530 env->pmsav7.rnr[M_REG_S] = 0; 531 env->pmsav8.mair0[M_REG_NS] = 0; 532 env->pmsav8.mair0[M_REG_S] = 0; 533 env->pmsav8.mair1[M_REG_NS] = 0; 534 env->pmsav8.mair1[M_REG_S] = 0; 535 } 536 537 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 538 if (cpu->sau_sregion > 0) { 539 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 540 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 541 } 542 env->sau.rnr = 0; 543 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 544 * the Cortex-M33 does. 545 */ 546 env->sau.ctrl = 0; 547 } 548 549 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]); 550 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); 551 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); 552 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); 553 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); 554 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); 555 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); 556 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); 557 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); 558 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); 559 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); 560 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); 561 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]); 562 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); 563 564 #ifndef CONFIG_USER_ONLY 565 if (kvm_enabled()) { 566 kvm_arm_reset_vcpu(cpu); 567 } 568 #endif 569 570 if (tcg_enabled()) { 571 hw_breakpoint_update_all(cpu); 572 hw_watchpoint_update_all(cpu); 573 574 arm_rebuild_hflags(env); 575 } 576 } 577 578 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 579 { 580 ARMCPU *cpu = ARM_CPU(cpustate); 581 CPUARMState *env = &cpu->env; 582 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 583 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 584 585 /* 586 * Check we have the EL we're aiming for. If that is the 587 * highest implemented EL, then cpu_reset has already done 588 * all the work. 589 */ 590 switch (target_el) { 591 case 3: 592 assert(have_el3); 593 return; 594 case 2: 595 assert(have_el2); 596 if (!have_el3) { 597 return; 598 } 599 break; 600 case 1: 601 if (!have_el3 && !have_el2) { 602 return; 603 } 604 break; 605 default: 606 g_assert_not_reached(); 607 } 608 609 if (have_el3) { 610 /* 611 * Set the EL3 state so code can run at EL2. This should match 612 * the requirements set by Linux in its booting spec. 613 */ 614 if (env->aarch64) { 615 env->cp15.scr_el3 |= SCR_RW; 616 if (cpu_isar_feature(aa64_pauth, cpu)) { 617 env->cp15.scr_el3 |= SCR_API | SCR_APK; 618 } 619 if (cpu_isar_feature(aa64_mte, cpu)) { 620 env->cp15.scr_el3 |= SCR_ATA; 621 } 622 if (cpu_isar_feature(aa64_sve, cpu)) { 623 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 624 env->vfp.zcr_el[3] = 0xf; 625 } 626 if (cpu_isar_feature(aa64_sme, cpu)) { 627 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 628 env->cp15.scr_el3 |= SCR_ENTP2; 629 env->vfp.smcr_el[3] = 0xf; 630 } 631 if (cpu_isar_feature(aa64_hcx, cpu)) { 632 env->cp15.scr_el3 |= SCR_HXEN; 633 } 634 if (cpu_isar_feature(aa64_fgt, cpu)) { 635 env->cp15.scr_el3 |= SCR_FGTEN; 636 } 637 } 638 639 if (target_el == 2) { 640 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 641 env->cp15.scr_el3 |= SCR_HCE; 642 } 643 644 /* Put CPU into non-secure state */ 645 env->cp15.scr_el3 |= SCR_NS; 646 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 647 env->cp15.nsacr |= 3 << 10; 648 } 649 650 if (have_el2 && target_el < 2) { 651 /* Set EL2 state so code can run at EL1. */ 652 if (env->aarch64) { 653 env->cp15.hcr_el2 |= HCR_RW; 654 } 655 } 656 657 /* Set the CPU to the desired state */ 658 if (env->aarch64) { 659 env->pstate = aarch64_pstate_mode(target_el, true); 660 } else { 661 static const uint32_t mode_for_el[] = { 662 0, 663 ARM_CPU_MODE_SVC, 664 ARM_CPU_MODE_HYP, 665 ARM_CPU_MODE_SVC, 666 }; 667 668 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 669 } 670 } 671 672 673 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 674 675 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 676 unsigned int target_el, 677 unsigned int cur_el, bool secure, 678 uint64_t hcr_el2) 679 { 680 CPUARMState *env = cpu_env(cs); 681 bool pstate_unmasked; 682 bool unmasked = false; 683 bool allIntMask = false; 684 685 /* 686 * Don't take exceptions if they target a lower EL. 687 * This check should catch any exceptions that would not be taken 688 * but left pending. 689 */ 690 if (cur_el > target_el) { 691 return false; 692 } 693 694 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 695 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { 696 allIntMask = env->pstate & PSTATE_ALLINT || 697 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && 698 (env->pstate & PSTATE_SP)); 699 } 700 701 switch (excp_idx) { 702 case EXCP_NMI: 703 pstate_unmasked = !allIntMask; 704 break; 705 706 case EXCP_VINMI: 707 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 708 /* VINMIs are only taken when hypervized. */ 709 return false; 710 } 711 return !allIntMask; 712 case EXCP_VFNMI: 713 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 714 /* VFNMIs are only taken when hypervized. */ 715 return false; 716 } 717 return !allIntMask; 718 case EXCP_FIQ: 719 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask); 720 break; 721 722 case EXCP_IRQ: 723 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask); 724 break; 725 726 case EXCP_VFIQ: 727 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 728 /* VFIQs are only taken when hypervized. */ 729 return false; 730 } 731 return !(env->daif & PSTATE_F) && (!allIntMask); 732 case EXCP_VIRQ: 733 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 734 /* VIRQs are only taken when hypervized. */ 735 return false; 736 } 737 return !(env->daif & PSTATE_I) && (!allIntMask); 738 case EXCP_VSERR: 739 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 740 /* VIRQs are only taken when hypervized. */ 741 return false; 742 } 743 return !(env->daif & PSTATE_A); 744 default: 745 g_assert_not_reached(); 746 } 747 748 /* 749 * Use the target EL, current execution state and SCR/HCR settings to 750 * determine whether the corresponding CPSR bit is used to mask the 751 * interrupt. 752 */ 753 if ((target_el > cur_el) && (target_el != 1)) { 754 /* Exceptions targeting a higher EL may not be maskable */ 755 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 756 switch (target_el) { 757 case 2: 758 /* 759 * According to ARM DDI 0487H.a, an interrupt can be masked 760 * when HCR_E2H and HCR_TGE are both set regardless of the 761 * current Security state. Note that we need to revisit this 762 * part again once we need to support NMI. 763 */ 764 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 765 unmasked = true; 766 } 767 break; 768 case 3: 769 /* Interrupt cannot be masked when the target EL is 3 */ 770 unmasked = true; 771 break; 772 default: 773 g_assert_not_reached(); 774 } 775 } else { 776 /* 777 * The old 32-bit-only environment has a more complicated 778 * masking setup. HCR and SCR bits not only affect interrupt 779 * routing but also change the behaviour of masking. 780 */ 781 bool hcr, scr; 782 783 switch (excp_idx) { 784 case EXCP_FIQ: 785 /* 786 * If FIQs are routed to EL3 or EL2 then there are cases where 787 * we override the CPSR.F in determining if the exception is 788 * masked or not. If neither of these are set then we fall back 789 * to the CPSR.F setting otherwise we further assess the state 790 * below. 791 */ 792 hcr = hcr_el2 & HCR_FMO; 793 scr = (env->cp15.scr_el3 & SCR_FIQ); 794 795 /* 796 * When EL3 is 32-bit, the SCR.FW bit controls whether the 797 * CPSR.F bit masks FIQ interrupts when taken in non-secure 798 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 799 * when non-secure but only when FIQs are only routed to EL3. 800 */ 801 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 802 break; 803 case EXCP_IRQ: 804 /* 805 * When EL3 execution state is 32-bit, if HCR.IMO is set then 806 * we may override the CPSR.I masking when in non-secure state. 807 * The SCR.IRQ setting has already been taken into consideration 808 * when setting the target EL, so it does not have a further 809 * affect here. 810 */ 811 hcr = hcr_el2 & HCR_IMO; 812 scr = false; 813 break; 814 default: 815 g_assert_not_reached(); 816 } 817 818 if ((scr || hcr) && !secure) { 819 unmasked = true; 820 } 821 } 822 } 823 824 /* 825 * The PSTATE bits only mask the interrupt if we have not overridden the 826 * ability above. 827 */ 828 return unmasked || pstate_unmasked; 829 } 830 831 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 832 { 833 CPUClass *cc = CPU_GET_CLASS(cs); 834 CPUARMState *env = cpu_env(cs); 835 uint32_t cur_el = arm_current_el(env); 836 bool secure = arm_is_secure(env); 837 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 838 uint32_t target_el; 839 uint32_t excp_idx; 840 841 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 842 843 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 844 (arm_sctlr(env, cur_el) & SCTLR_NMI)) { 845 if (interrupt_request & CPU_INTERRUPT_NMI) { 846 excp_idx = EXCP_NMI; 847 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 848 if (arm_excp_unmasked(cs, excp_idx, target_el, 849 cur_el, secure, hcr_el2)) { 850 goto found; 851 } 852 } 853 if (interrupt_request & CPU_INTERRUPT_VINMI) { 854 excp_idx = EXCP_VINMI; 855 target_el = 1; 856 if (arm_excp_unmasked(cs, excp_idx, target_el, 857 cur_el, secure, hcr_el2)) { 858 goto found; 859 } 860 } 861 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 862 excp_idx = EXCP_VFNMI; 863 target_el = 1; 864 if (arm_excp_unmasked(cs, excp_idx, target_el, 865 cur_el, secure, hcr_el2)) { 866 goto found; 867 } 868 } 869 } else { 870 /* 871 * NMI disabled: interrupts with superpriority are handled 872 * as if they didn't have it 873 */ 874 if (interrupt_request & CPU_INTERRUPT_NMI) { 875 interrupt_request |= CPU_INTERRUPT_HARD; 876 } 877 if (interrupt_request & CPU_INTERRUPT_VINMI) { 878 interrupt_request |= CPU_INTERRUPT_VIRQ; 879 } 880 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 881 interrupt_request |= CPU_INTERRUPT_VFIQ; 882 } 883 } 884 885 if (interrupt_request & CPU_INTERRUPT_FIQ) { 886 excp_idx = EXCP_FIQ; 887 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 888 if (arm_excp_unmasked(cs, excp_idx, target_el, 889 cur_el, secure, hcr_el2)) { 890 goto found; 891 } 892 } 893 if (interrupt_request & CPU_INTERRUPT_HARD) { 894 excp_idx = EXCP_IRQ; 895 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 896 if (arm_excp_unmasked(cs, excp_idx, target_el, 897 cur_el, secure, hcr_el2)) { 898 goto found; 899 } 900 } 901 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 902 excp_idx = EXCP_VIRQ; 903 target_el = 1; 904 if (arm_excp_unmasked(cs, excp_idx, target_el, 905 cur_el, secure, hcr_el2)) { 906 goto found; 907 } 908 } 909 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 910 excp_idx = EXCP_VFIQ; 911 target_el = 1; 912 if (arm_excp_unmasked(cs, excp_idx, target_el, 913 cur_el, secure, hcr_el2)) { 914 goto found; 915 } 916 } 917 if (interrupt_request & CPU_INTERRUPT_VSERR) { 918 excp_idx = EXCP_VSERR; 919 target_el = 1; 920 if (arm_excp_unmasked(cs, excp_idx, target_el, 921 cur_el, secure, hcr_el2)) { 922 /* Taking a virtual abort clears HCR_EL2.VSE */ 923 env->cp15.hcr_el2 &= ~HCR_VSE; 924 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 925 goto found; 926 } 927 } 928 return false; 929 930 found: 931 cs->exception_index = excp_idx; 932 env->exception.target_el = target_el; 933 cc->tcg_ops->do_interrupt(cs); 934 return true; 935 } 936 937 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 938 939 void arm_cpu_update_virq(ARMCPU *cpu) 940 { 941 /* 942 * Update the interrupt level for VIRQ, which is the logical OR of 943 * the HCR_EL2.VI bit and the input line level from the GIC. 944 */ 945 CPUARMState *env = &cpu->env; 946 CPUState *cs = CPU(cpu); 947 948 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 949 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 950 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 951 952 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 953 if (new_state) { 954 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 955 } else { 956 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 957 } 958 } 959 } 960 961 void arm_cpu_update_vfiq(ARMCPU *cpu) 962 { 963 /* 964 * Update the interrupt level for VFIQ, which is the logical OR of 965 * the HCR_EL2.VF bit and the input line level from the GIC. 966 */ 967 CPUARMState *env = &cpu->env; 968 CPUState *cs = CPU(cpu); 969 970 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) && 971 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || 972 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 973 974 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 975 if (new_state) { 976 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 977 } else { 978 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 979 } 980 } 981 } 982 983 void arm_cpu_update_vinmi(ARMCPU *cpu) 984 { 985 /* 986 * Update the interrupt level for VINMI, which is the logical OR of 987 * the HCRX_EL2.VINMI bit and the input line level from the GIC. 988 */ 989 CPUARMState *env = &cpu->env; 990 CPUState *cs = CPU(cpu); 991 992 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 993 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 994 (env->irq_line_state & CPU_INTERRUPT_VINMI); 995 996 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) { 997 if (new_state) { 998 cpu_interrupt(cs, CPU_INTERRUPT_VINMI); 999 } else { 1000 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI); 1001 } 1002 } 1003 } 1004 1005 void arm_cpu_update_vfnmi(ARMCPU *cpu) 1006 { 1007 /* 1008 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit. 1009 */ 1010 CPUARMState *env = &cpu->env; 1011 CPUState *cs = CPU(cpu); 1012 1013 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) && 1014 (arm_hcrx_el2_eff(env) & HCRX_VFNMI); 1015 1016 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) { 1017 if (new_state) { 1018 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); 1019 } else { 1020 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI); 1021 } 1022 } 1023 } 1024 1025 void arm_cpu_update_vserr(ARMCPU *cpu) 1026 { 1027 /* 1028 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 1029 */ 1030 CPUARMState *env = &cpu->env; 1031 CPUState *cs = CPU(cpu); 1032 1033 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 1034 1035 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 1036 if (new_state) { 1037 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 1038 } else { 1039 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 1040 } 1041 } 1042 } 1043 1044 #ifndef CONFIG_USER_ONLY 1045 static void arm_cpu_set_irq(void *opaque, int irq, int level) 1046 { 1047 ARMCPU *cpu = opaque; 1048 CPUARMState *env = &cpu->env; 1049 CPUState *cs = CPU(cpu); 1050 static const int mask[] = { 1051 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 1052 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 1053 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 1054 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ, 1055 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI, 1056 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI, 1057 }; 1058 1059 if (!arm_feature(env, ARM_FEATURE_EL2) && 1060 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 1061 /* 1062 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 1063 * have EL2 support we don't care. (Unless the guest is doing something 1064 * silly this will only be calls saying "level is still 0".) 1065 */ 1066 return; 1067 } 1068 1069 if (level) { 1070 env->irq_line_state |= mask[irq]; 1071 } else { 1072 env->irq_line_state &= ~mask[irq]; 1073 } 1074 1075 switch (irq) { 1076 case ARM_CPU_VIRQ: 1077 arm_cpu_update_virq(cpu); 1078 break; 1079 case ARM_CPU_VFIQ: 1080 arm_cpu_update_vfiq(cpu); 1081 break; 1082 case ARM_CPU_VINMI: 1083 arm_cpu_update_vinmi(cpu); 1084 break; 1085 case ARM_CPU_IRQ: 1086 case ARM_CPU_FIQ: 1087 case ARM_CPU_NMI: 1088 if (level) { 1089 cpu_interrupt(cs, mask[irq]); 1090 } else { 1091 cpu_reset_interrupt(cs, mask[irq]); 1092 } 1093 break; 1094 default: 1095 g_assert_not_reached(); 1096 } 1097 } 1098 1099 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 1100 { 1101 #ifdef CONFIG_KVM 1102 ARMCPU *cpu = opaque; 1103 CPUARMState *env = &cpu->env; 1104 CPUState *cs = CPU(cpu); 1105 uint32_t linestate_bit; 1106 int irq_id; 1107 1108 switch (irq) { 1109 case ARM_CPU_IRQ: 1110 irq_id = KVM_ARM_IRQ_CPU_IRQ; 1111 linestate_bit = CPU_INTERRUPT_HARD; 1112 break; 1113 case ARM_CPU_FIQ: 1114 irq_id = KVM_ARM_IRQ_CPU_FIQ; 1115 linestate_bit = CPU_INTERRUPT_FIQ; 1116 break; 1117 default: 1118 g_assert_not_reached(); 1119 } 1120 1121 if (level) { 1122 env->irq_line_state |= linestate_bit; 1123 } else { 1124 env->irq_line_state &= ~linestate_bit; 1125 } 1126 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 1127 #endif 1128 } 1129 1130 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 1131 { 1132 ARMCPU *cpu = ARM_CPU(cs); 1133 CPUARMState *env = &cpu->env; 1134 1135 cpu_synchronize_state(cs); 1136 return arm_cpu_data_is_big_endian(env); 1137 } 1138 1139 #ifdef CONFIG_TCG 1140 bool arm_cpu_exec_halt(CPUState *cs) 1141 { 1142 bool leave_halt = cpu_has_work(cs); 1143 1144 if (leave_halt) { 1145 /* We're about to come out of WFI/WFE: disable the WFxT timer */ 1146 ARMCPU *cpu = ARM_CPU(cs); 1147 if (cpu->wfxt_timer) { 1148 timer_del(cpu->wfxt_timer); 1149 } 1150 } 1151 return leave_halt; 1152 } 1153 #endif 1154 1155 static void arm_wfxt_timer_cb(void *opaque) 1156 { 1157 ARMCPU *cpu = opaque; 1158 CPUState *cs = CPU(cpu); 1159 1160 /* 1161 * We expect the CPU to be halted; this will cause arm_cpu_is_work() 1162 * to return true (so we will come out of halt even with no other 1163 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt() 1164 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. 1165 */ 1166 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 1167 } 1168 #endif 1169 1170 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 1171 { 1172 ARMCPU *ac = ARM_CPU(cpu); 1173 CPUARMState *env = &ac->env; 1174 bool sctlr_b = arm_sctlr_b(env); 1175 1176 if (is_a64(env)) { 1177 info->cap_arch = CS_ARCH_ARM64; 1178 info->cap_insn_unit = 4; 1179 info->cap_insn_split = 4; 1180 } else { 1181 int cap_mode; 1182 if (env->thumb) { 1183 info->cap_insn_unit = 2; 1184 info->cap_insn_split = 4; 1185 cap_mode = CS_MODE_THUMB; 1186 } else { 1187 info->cap_insn_unit = 4; 1188 info->cap_insn_split = 4; 1189 cap_mode = CS_MODE_ARM; 1190 } 1191 if (arm_feature(env, ARM_FEATURE_V8)) { 1192 cap_mode |= CS_MODE_V8; 1193 } 1194 if (arm_feature(env, ARM_FEATURE_M)) { 1195 cap_mode |= CS_MODE_MCLASS; 1196 } 1197 info->cap_arch = CS_ARCH_ARM; 1198 info->cap_mode = cap_mode; 1199 } 1200 1201 info->endian = BFD_ENDIAN_LITTLE; 1202 if (bswap_code(sctlr_b)) { 1203 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 1204 } 1205 info->flags &= ~INSN_ARM_BE32; 1206 #ifndef CONFIG_USER_ONLY 1207 if (sctlr_b) { 1208 info->flags |= INSN_ARM_BE32; 1209 } 1210 #endif 1211 } 1212 1213 #ifdef TARGET_AARCH64 1214 1215 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1216 { 1217 ARMCPU *cpu = ARM_CPU(cs); 1218 CPUARMState *env = &cpu->env; 1219 uint32_t psr = pstate_read(env); 1220 int i, j; 1221 int el = arm_current_el(env); 1222 uint64_t hcr = arm_hcr_el2_eff(env); 1223 const char *ns_status; 1224 bool sve; 1225 1226 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 1227 for (i = 0; i < 32; i++) { 1228 if (i == 31) { 1229 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 1230 } else { 1231 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 1232 (i + 2) % 3 ? " " : "\n"); 1233 } 1234 } 1235 1236 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 1237 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1238 } else { 1239 ns_status = ""; 1240 } 1241 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 1242 psr, 1243 psr & PSTATE_N ? 'N' : '-', 1244 psr & PSTATE_Z ? 'Z' : '-', 1245 psr & PSTATE_C ? 'C' : '-', 1246 psr & PSTATE_V ? 'V' : '-', 1247 ns_status, 1248 el, 1249 psr & PSTATE_SP ? 'h' : 't'); 1250 1251 if (cpu_isar_feature(aa64_sme, cpu)) { 1252 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 1253 env->svcr, 1254 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 1255 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 1256 } 1257 if (cpu_isar_feature(aa64_bti, cpu)) { 1258 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1259 } 1260 qemu_fprintf(f, "%s%s%s", 1261 (hcr & HCR_NV) ? " NV" : "", 1262 (hcr & HCR_NV1) ? " NV1" : "", 1263 (hcr & HCR_NV2) ? " NV2" : ""); 1264 if (!(flags & CPU_DUMP_FPU)) { 1265 qemu_fprintf(f, "\n"); 1266 return; 1267 } 1268 if (fp_exception_el(env, el) != 0) { 1269 qemu_fprintf(f, " FPU disabled\n"); 1270 return; 1271 } 1272 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1273 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1274 1275 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1276 sve = sme_exception_el(env, el) == 0; 1277 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1278 sve = sve_exception_el(env, el) == 0; 1279 } else { 1280 sve = false; 1281 } 1282 1283 if (sve) { 1284 int zcr_len = sve_vqm1_for_el(env, el); 1285 1286 for (i = 0; i <= FFR_PRED_NUM; i++) { 1287 bool eol; 1288 if (i == FFR_PRED_NUM) { 1289 qemu_fprintf(f, "FFR="); 1290 /* It's last, so end the line. */ 1291 eol = true; 1292 } else { 1293 qemu_fprintf(f, "P%02d=", i); 1294 switch (zcr_len) { 1295 case 0: 1296 eol = i % 8 == 7; 1297 break; 1298 case 1: 1299 eol = i % 6 == 5; 1300 break; 1301 case 2: 1302 case 3: 1303 eol = i % 3 == 2; 1304 break; 1305 default: 1306 /* More than one quadword per predicate. */ 1307 eol = true; 1308 break; 1309 } 1310 } 1311 for (j = zcr_len / 4; j >= 0; j--) { 1312 int digits; 1313 if (j * 4 + 4 <= zcr_len + 1) { 1314 digits = 16; 1315 } else { 1316 digits = (zcr_len % 4 + 1) * 4; 1317 } 1318 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1319 env->vfp.pregs[i].p[j], 1320 j ? ":" : eol ? "\n" : " "); 1321 } 1322 } 1323 1324 if (zcr_len == 0) { 1325 /* 1326 * With vl=16, there are only 37 columns per register, 1327 * so output two registers per line. 1328 */ 1329 for (i = 0; i < 32; i++) { 1330 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1331 i, env->vfp.zregs[i].d[1], 1332 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1333 } 1334 } else { 1335 for (i = 0; i < 32; i++) { 1336 qemu_fprintf(f, "Z%02d=", i); 1337 for (j = zcr_len; j >= 0; j--) { 1338 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1339 env->vfp.zregs[i].d[j * 2 + 1], 1340 env->vfp.zregs[i].d[j * 2 + 0], 1341 j ? ":" : "\n"); 1342 } 1343 } 1344 } 1345 } else { 1346 for (i = 0; i < 32; i++) { 1347 uint64_t *q = aa64_vfp_qreg(env, i); 1348 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1349 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1350 } 1351 } 1352 1353 if (cpu_isar_feature(aa64_sme, cpu) && 1354 FIELD_EX64(env->svcr, SVCR, ZA) && 1355 sme_exception_el(env, el) == 0) { 1356 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1357 int svl = (zcr_len + 1) * 16; 1358 int svl_lg10 = svl < 100 ? 2 : 3; 1359 1360 for (i = 0; i < svl; i++) { 1361 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1362 for (j = zcr_len; j >= 0; --j) { 1363 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1364 env->zarray[i].d[2 * j + 1], 1365 env->zarray[i].d[2 * j], 1366 j ? ':' : '\n'); 1367 } 1368 } 1369 } 1370 } 1371 1372 #else 1373 1374 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1375 { 1376 g_assert_not_reached(); 1377 } 1378 1379 #endif 1380 1381 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1382 { 1383 ARMCPU *cpu = ARM_CPU(cs); 1384 CPUARMState *env = &cpu->env; 1385 int i; 1386 1387 if (is_a64(env)) { 1388 aarch64_cpu_dump_state(cs, f, flags); 1389 return; 1390 } 1391 1392 for (i = 0; i < 16; i++) { 1393 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1394 if ((i % 4) == 3) { 1395 qemu_fprintf(f, "\n"); 1396 } else { 1397 qemu_fprintf(f, " "); 1398 } 1399 } 1400 1401 if (arm_feature(env, ARM_FEATURE_M)) { 1402 uint32_t xpsr = xpsr_read(env); 1403 const char *mode; 1404 const char *ns_status = ""; 1405 1406 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1407 ns_status = env->v7m.secure ? "S " : "NS "; 1408 } 1409 1410 if (xpsr & XPSR_EXCP) { 1411 mode = "handler"; 1412 } else { 1413 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1414 mode = "unpriv-thread"; 1415 } else { 1416 mode = "priv-thread"; 1417 } 1418 } 1419 1420 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1421 xpsr, 1422 xpsr & XPSR_N ? 'N' : '-', 1423 xpsr & XPSR_Z ? 'Z' : '-', 1424 xpsr & XPSR_C ? 'C' : '-', 1425 xpsr & XPSR_V ? 'V' : '-', 1426 xpsr & XPSR_T ? 'T' : 'A', 1427 ns_status, 1428 mode); 1429 } else { 1430 uint32_t psr = cpsr_read(env); 1431 const char *ns_status = ""; 1432 1433 if (arm_feature(env, ARM_FEATURE_EL3) && 1434 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1435 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1436 } 1437 1438 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1439 psr, 1440 psr & CPSR_N ? 'N' : '-', 1441 psr & CPSR_Z ? 'Z' : '-', 1442 psr & CPSR_C ? 'C' : '-', 1443 psr & CPSR_V ? 'V' : '-', 1444 psr & CPSR_T ? 'T' : 'A', 1445 ns_status, 1446 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1447 } 1448 1449 if (flags & CPU_DUMP_FPU) { 1450 int numvfpregs = 0; 1451 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1452 numvfpregs = 32; 1453 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1454 numvfpregs = 16; 1455 } 1456 for (i = 0; i < numvfpregs; i++) { 1457 uint64_t v = *aa32_vfp_dreg(env, i); 1458 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1459 i * 2, (uint32_t)v, 1460 i * 2 + 1, (uint32_t)(v >> 32), 1461 i, v); 1462 } 1463 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1464 if (cpu_isar_feature(aa32_mve, cpu)) { 1465 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1466 } 1467 } 1468 } 1469 1470 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) 1471 { 1472 uint32_t Aff1 = idx / clustersz; 1473 uint32_t Aff0 = idx % clustersz; 1474 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1475 } 1476 1477 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) 1478 { 1479 return cpu->mp_affinity; 1480 } 1481 1482 static void arm_cpu_initfn(Object *obj) 1483 { 1484 ARMCPU *cpu = ARM_CPU(obj); 1485 1486 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1487 NULL, g_free); 1488 1489 QLIST_INIT(&cpu->pre_el_change_hooks); 1490 QLIST_INIT(&cpu->el_change_hooks); 1491 1492 #ifdef CONFIG_USER_ONLY 1493 # ifdef TARGET_AARCH64 1494 /* 1495 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1496 * These values were chosen to fit within the default signal frame. 1497 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1498 * and our corresponding cpu property. 1499 */ 1500 cpu->sve_default_vq = 4; 1501 cpu->sme_default_vq = 2; 1502 # endif 1503 #else 1504 /* Our inbound IRQ and FIQ lines */ 1505 if (kvm_enabled()) { 1506 /* 1507 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add 1508 * them to maintain the same interface as non-KVM CPUs. 1509 */ 1510 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); 1511 } else { 1512 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); 1513 } 1514 1515 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1516 ARRAY_SIZE(cpu->gt_timer_outputs)); 1517 1518 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1519 "gicv3-maintenance-interrupt", 1); 1520 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1521 "pmu-interrupt", 1); 1522 #endif 1523 1524 /* DTB consumers generally don't in fact care what the 'compatible' 1525 * string is, so always provide some string and trust that a hypothetical 1526 * picky DTB consumer will also provide a helpful error message. 1527 */ 1528 cpu->dtb_compatible = "qemu,unknown"; 1529 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1530 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1531 1532 if (tcg_enabled() || hvf_enabled()) { 1533 /* TCG and HVF implement PSCI 1.1 */ 1534 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1535 } 1536 } 1537 1538 /* 1539 * 0 means "unset, use the default value". That default might vary depending 1540 * on the CPU type, and is set in the realize fn. 1541 */ 1542 static const Property arm_cpu_gt_cntfrq_property = 1543 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); 1544 1545 static const Property arm_cpu_reset_cbar_property = 1546 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1547 1548 static const Property arm_cpu_reset_hivecs_property = 1549 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1550 1551 #ifndef CONFIG_USER_ONLY 1552 static const Property arm_cpu_has_el2_property = 1553 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1554 1555 static const Property arm_cpu_has_el3_property = 1556 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1557 #endif 1558 1559 static const Property arm_cpu_cfgend_property = 1560 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1561 1562 static const Property arm_cpu_has_vfp_property = 1563 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1564 1565 static const Property arm_cpu_has_vfp_d32_property = 1566 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1567 1568 static const Property arm_cpu_has_neon_property = 1569 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1570 1571 static const Property arm_cpu_has_dsp_property = 1572 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1573 1574 static const Property arm_cpu_has_mpu_property = 1575 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1576 1577 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1578 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1579 * the right value for that particular CPU type, and we don't want 1580 * to override that with an incorrect constant value. 1581 */ 1582 static const Property arm_cpu_pmsav7_dregion_property = 1583 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1584 pmsav7_dregion, 1585 qdev_prop_uint32, uint32_t); 1586 1587 static bool arm_get_pmu(Object *obj, Error **errp) 1588 { 1589 ARMCPU *cpu = ARM_CPU(obj); 1590 1591 return cpu->has_pmu; 1592 } 1593 1594 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1595 { 1596 ARMCPU *cpu = ARM_CPU(obj); 1597 1598 if (value) { 1599 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1600 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1601 return; 1602 } 1603 set_feature(&cpu->env, ARM_FEATURE_PMU); 1604 } else { 1605 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1606 } 1607 cpu->has_pmu = value; 1608 } 1609 1610 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1611 { 1612 /* 1613 * The exact approach to calculating guest ticks is: 1614 * 1615 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1616 * NANOSECONDS_PER_SECOND); 1617 * 1618 * We don't do that. Rather we intentionally use integer division 1619 * truncation below and in the caller for the conversion of host monotonic 1620 * time to guest ticks to provide the exact inverse for the semantics of 1621 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1622 * it loses precision when representing frequencies where 1623 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1624 * provide an exact inverse leads to scheduling timers with negative 1625 * periods, which in turn leads to sticky behaviour in the guest. 1626 * 1627 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1628 * cannot become zero. 1629 */ 1630 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1631 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1632 } 1633 1634 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1635 { 1636 CPUARMState *env = &cpu->env; 1637 bool no_aa32 = false; 1638 1639 /* 1640 * Some features automatically imply others: set the feature 1641 * bits explicitly for these cases. 1642 */ 1643 1644 if (arm_feature(env, ARM_FEATURE_M)) { 1645 set_feature(env, ARM_FEATURE_PMSA); 1646 } 1647 1648 if (arm_feature(env, ARM_FEATURE_V8)) { 1649 if (arm_feature(env, ARM_FEATURE_M)) { 1650 set_feature(env, ARM_FEATURE_V7); 1651 } else { 1652 set_feature(env, ARM_FEATURE_V7VE); 1653 } 1654 } 1655 1656 /* 1657 * There exist AArch64 cpus without AArch32 support. When KVM 1658 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1659 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1660 * As a general principle, we also do not make ID register 1661 * consistency checks anywhere unless using TCG, because only 1662 * for TCG would a consistency-check failure be a QEMU bug. 1663 */ 1664 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1665 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1666 } 1667 1668 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1669 /* 1670 * v7 Virtualization Extensions. In real hardware this implies 1671 * EL2 and also the presence of the Security Extensions. 1672 * For QEMU, for backwards-compatibility we implement some 1673 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1674 * include the various other features that V7VE implies. 1675 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1676 * Security Extensions is ARM_FEATURE_EL3. 1677 */ 1678 assert(!tcg_enabled() || no_aa32 || 1679 cpu_isar_feature(aa32_arm_div, cpu)); 1680 set_feature(env, ARM_FEATURE_LPAE); 1681 set_feature(env, ARM_FEATURE_V7); 1682 } 1683 if (arm_feature(env, ARM_FEATURE_V7)) { 1684 set_feature(env, ARM_FEATURE_VAPA); 1685 set_feature(env, ARM_FEATURE_THUMB2); 1686 set_feature(env, ARM_FEATURE_MPIDR); 1687 if (!arm_feature(env, ARM_FEATURE_M)) { 1688 set_feature(env, ARM_FEATURE_V6K); 1689 } else { 1690 set_feature(env, ARM_FEATURE_V6); 1691 } 1692 1693 /* 1694 * Always define VBAR for V7 CPUs even if it doesn't exist in 1695 * non-EL3 configs. This is needed by some legacy boards. 1696 */ 1697 set_feature(env, ARM_FEATURE_VBAR); 1698 } 1699 if (arm_feature(env, ARM_FEATURE_V6K)) { 1700 set_feature(env, ARM_FEATURE_V6); 1701 set_feature(env, ARM_FEATURE_MVFR); 1702 } 1703 if (arm_feature(env, ARM_FEATURE_V6)) { 1704 set_feature(env, ARM_FEATURE_V5); 1705 if (!arm_feature(env, ARM_FEATURE_M)) { 1706 assert(!tcg_enabled() || no_aa32 || 1707 cpu_isar_feature(aa32_jazelle, cpu)); 1708 set_feature(env, ARM_FEATURE_AUXCR); 1709 } 1710 } 1711 if (arm_feature(env, ARM_FEATURE_V5)) { 1712 set_feature(env, ARM_FEATURE_V4T); 1713 } 1714 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1715 set_feature(env, ARM_FEATURE_V7MP); 1716 } 1717 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1718 set_feature(env, ARM_FEATURE_CBAR); 1719 } 1720 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1721 !arm_feature(env, ARM_FEATURE_M)) { 1722 set_feature(env, ARM_FEATURE_THUMB_DSP); 1723 } 1724 } 1725 1726 void arm_cpu_post_init(Object *obj) 1727 { 1728 ARMCPU *cpu = ARM_CPU(obj); 1729 1730 /* 1731 * Some features imply others. Figure this out now, because we 1732 * are going to look at the feature bits in deciding which 1733 * properties to add. 1734 */ 1735 arm_cpu_propagate_feature_implications(cpu); 1736 1737 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1738 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1739 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1740 } 1741 1742 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1743 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1744 } 1745 1746 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1747 object_property_add_uint64_ptr(obj, "rvbar", 1748 &cpu->rvbar_prop, 1749 OBJ_PROP_FLAG_READWRITE); 1750 } 1751 1752 #ifndef CONFIG_USER_ONLY 1753 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1754 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1755 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1756 */ 1757 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1758 1759 object_property_add_link(obj, "secure-memory", 1760 TYPE_MEMORY_REGION, 1761 (Object **)&cpu->secure_memory, 1762 qdev_prop_allow_set_link_before_realize, 1763 OBJ_PROP_LINK_STRONG); 1764 } 1765 1766 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1767 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1768 } 1769 #endif 1770 1771 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1772 cpu->has_pmu = true; 1773 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1774 } 1775 1776 /* 1777 * Allow user to turn off VFP and Neon support, but only for TCG -- 1778 * KVM does not currently allow us to lie to the guest about its 1779 * ID/feature registers, so the guest always sees what the host has. 1780 */ 1781 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1782 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1783 cpu->has_vfp = true; 1784 cpu->has_vfp_d32 = true; 1785 if (tcg_enabled() || qtest_enabled()) { 1786 qdev_property_add_static(DEVICE(obj), 1787 &arm_cpu_has_vfp_property); 1788 } 1789 } 1790 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1791 cpu->has_vfp = true; 1792 if (tcg_enabled() || qtest_enabled()) { 1793 qdev_property_add_static(DEVICE(obj), 1794 &arm_cpu_has_vfp_property); 1795 } 1796 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1797 cpu->has_vfp_d32 = true; 1798 /* 1799 * The permitted values of the SIMDReg bits [3:0] on 1800 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1801 * make sure that has_vfp_d32 can not be set to false. 1802 */ 1803 if ((tcg_enabled() || qtest_enabled()) 1804 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1805 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1806 qdev_property_add_static(DEVICE(obj), 1807 &arm_cpu_has_vfp_d32_property); 1808 } 1809 } 1810 } 1811 1812 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1813 cpu->has_neon = true; 1814 if (!kvm_enabled()) { 1815 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1816 } 1817 } 1818 1819 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1820 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1821 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1822 } 1823 1824 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1825 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1826 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1827 qdev_property_add_static(DEVICE(obj), 1828 &arm_cpu_pmsav7_dregion_property); 1829 } 1830 } 1831 1832 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1833 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1834 qdev_prop_allow_set_link_before_realize, 1835 OBJ_PROP_LINK_STRONG); 1836 /* 1837 * M profile: initial value of the Secure VTOR. We can't just use 1838 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1839 * the property to be set after realize. 1840 */ 1841 object_property_add_uint32_ptr(obj, "init-svtor", 1842 &cpu->init_svtor, 1843 OBJ_PROP_FLAG_READWRITE); 1844 } 1845 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1846 /* 1847 * Initial value of the NS VTOR (for cores without the Security 1848 * extension, this is the only VTOR) 1849 */ 1850 object_property_add_uint32_ptr(obj, "init-nsvtor", 1851 &cpu->init_nsvtor, 1852 OBJ_PROP_FLAG_READWRITE); 1853 } 1854 1855 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1856 object_property_add_uint32_ptr(obj, "psci-conduit", 1857 &cpu->psci_conduit, 1858 OBJ_PROP_FLAG_READWRITE); 1859 1860 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1861 1862 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1863 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1864 } 1865 1866 if (kvm_enabled()) { 1867 kvm_arm_add_vcpu_properties(cpu); 1868 } 1869 1870 #ifndef CONFIG_USER_ONLY 1871 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1872 cpu_isar_feature(aa64_mte, cpu)) { 1873 object_property_add_link(obj, "tag-memory", 1874 TYPE_MEMORY_REGION, 1875 (Object **)&cpu->tag_memory, 1876 qdev_prop_allow_set_link_before_realize, 1877 OBJ_PROP_LINK_STRONG); 1878 1879 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1880 object_property_add_link(obj, "secure-tag-memory", 1881 TYPE_MEMORY_REGION, 1882 (Object **)&cpu->secure_tag_memory, 1883 qdev_prop_allow_set_link_before_realize, 1884 OBJ_PROP_LINK_STRONG); 1885 } 1886 } 1887 #endif 1888 } 1889 1890 static void arm_cpu_finalizefn(Object *obj) 1891 { 1892 ARMCPU *cpu = ARM_CPU(obj); 1893 ARMELChangeHook *hook, *next; 1894 1895 g_hash_table_destroy(cpu->cp_regs); 1896 1897 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1898 QLIST_REMOVE(hook, node); 1899 g_free(hook); 1900 } 1901 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1902 QLIST_REMOVE(hook, node); 1903 g_free(hook); 1904 } 1905 #ifndef CONFIG_USER_ONLY 1906 if (cpu->pmu_timer) { 1907 timer_free(cpu->pmu_timer); 1908 } 1909 if (cpu->wfxt_timer) { 1910 timer_free(cpu->wfxt_timer); 1911 } 1912 #endif 1913 } 1914 1915 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1916 { 1917 Error *local_err = NULL; 1918 1919 #ifdef TARGET_AARCH64 1920 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1921 arm_cpu_sve_finalize(cpu, &local_err); 1922 if (local_err != NULL) { 1923 error_propagate(errp, local_err); 1924 return; 1925 } 1926 1927 /* 1928 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless 1929 * FEAT_SME_FA64 is present). However our implementation currently 1930 * assumes it, so if the user asked for sve=off then turn off SME also. 1931 * (KVM doesn't currently support SME at all.) 1932 */ 1933 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) { 1934 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort); 1935 } 1936 1937 arm_cpu_sme_finalize(cpu, &local_err); 1938 if (local_err != NULL) { 1939 error_propagate(errp, local_err); 1940 return; 1941 } 1942 1943 arm_cpu_pauth_finalize(cpu, &local_err); 1944 if (local_err != NULL) { 1945 error_propagate(errp, local_err); 1946 return; 1947 } 1948 1949 arm_cpu_lpa2_finalize(cpu, &local_err); 1950 if (local_err != NULL) { 1951 error_propagate(errp, local_err); 1952 return; 1953 } 1954 } 1955 #endif 1956 1957 if (kvm_enabled()) { 1958 kvm_arm_steal_time_finalize(cpu, &local_err); 1959 if (local_err != NULL) { 1960 error_propagate(errp, local_err); 1961 return; 1962 } 1963 } 1964 } 1965 1966 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1967 { 1968 CPUState *cs = CPU(dev); 1969 ARMCPU *cpu = ARM_CPU(dev); 1970 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1971 CPUARMState *env = &cpu->env; 1972 Error *local_err = NULL; 1973 1974 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 1975 /* Use pc-relative instructions in system-mode */ 1976 tcg_cflags_set(cs, CF_PCREL); 1977 #endif 1978 1979 /* If we needed to query the host kernel for the CPU features 1980 * then it's possible that might have failed in the initfn, but 1981 * this is the first point where we can report it. 1982 */ 1983 if (cpu->host_cpu_probe_failed) { 1984 if (!kvm_enabled() && !hvf_enabled()) { 1985 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1986 } else { 1987 error_setg(errp, "Failed to retrieve host CPU features"); 1988 } 1989 return; 1990 } 1991 1992 if (!cpu->gt_cntfrq_hz) { 1993 /* 1994 * 0 means "the board didn't set a value, use the default". (We also 1995 * get here for the CONFIG_USER_ONLY case.) 1996 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before 1997 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, 1998 * which gives a 16ns tick period. 1999 * 2000 * We will use the back-compat value: 2001 * - for QEMU CPU types added before we standardized on 1GHz 2002 * - for versioned machine types with a version of 9.0 or earlier 2003 */ 2004 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || 2005 cpu->backcompat_cntfrq) { 2006 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; 2007 } else { 2008 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; 2009 } 2010 } 2011 2012 #ifndef CONFIG_USER_ONLY 2013 /* The NVIC and M-profile CPU are two halves of a single piece of 2014 * hardware; trying to use one without the other is a command line 2015 * error and will result in segfaults if not caught here. 2016 */ 2017 if (arm_feature(env, ARM_FEATURE_M)) { 2018 if (!env->nvic) { 2019 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 2020 return; 2021 } 2022 } else { 2023 if (env->nvic) { 2024 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 2025 return; 2026 } 2027 } 2028 2029 if (!tcg_enabled() && !qtest_enabled()) { 2030 /* 2031 * We assume that no accelerator except TCG (and the "not really an 2032 * accelerator" qtest) can handle these features, because Arm hardware 2033 * virtualization can't virtualize them. 2034 * 2035 * Catch all the cases which might cause us to create more than one 2036 * address space for the CPU (otherwise we will assert() later in 2037 * cpu_address_space_init()). 2038 */ 2039 if (arm_feature(env, ARM_FEATURE_M)) { 2040 error_setg(errp, 2041 "Cannot enable %s when using an M-profile guest CPU", 2042 current_accel_name()); 2043 return; 2044 } 2045 if (cpu->has_el3) { 2046 error_setg(errp, 2047 "Cannot enable %s when guest CPU has EL3 enabled", 2048 current_accel_name()); 2049 return; 2050 } 2051 if (cpu->tag_memory) { 2052 error_setg(errp, 2053 "Cannot enable %s when guest CPUs has MTE enabled", 2054 current_accel_name()); 2055 return; 2056 } 2057 } 2058 2059 { 2060 uint64_t scale = gt_cntfrq_period_ns(cpu); 2061 2062 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2063 arm_gt_ptimer_cb, cpu); 2064 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2065 arm_gt_vtimer_cb, cpu); 2066 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2067 arm_gt_htimer_cb, cpu); 2068 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2069 arm_gt_stimer_cb, cpu); 2070 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2071 arm_gt_hvtimer_cb, cpu); 2072 } 2073 #endif 2074 2075 cpu_exec_realizefn(cs, &local_err); 2076 if (local_err != NULL) { 2077 error_propagate(errp, local_err); 2078 return; 2079 } 2080 2081 arm_cpu_finalize_features(cpu, &local_err); 2082 if (local_err != NULL) { 2083 error_propagate(errp, local_err); 2084 return; 2085 } 2086 2087 #ifdef CONFIG_USER_ONLY 2088 /* 2089 * User mode relies on IC IVAU instructions to catch modification of 2090 * dual-mapped code. 2091 * 2092 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 2093 * IC IVAU even if the emulated processor does not normally require it. 2094 */ 2095 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 2096 #endif 2097 2098 if (arm_feature(env, ARM_FEATURE_AARCH64) && 2099 cpu->has_vfp != cpu->has_neon) { 2100 /* 2101 * This is an architectural requirement for AArch64; AArch32 is 2102 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 2103 */ 2104 error_setg(errp, 2105 "AArch64 CPUs must have both VFP and Neon or neither"); 2106 return; 2107 } 2108 2109 if (cpu->has_vfp_d32 != cpu->has_neon) { 2110 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 2111 return; 2112 } 2113 2114 if (!cpu->has_vfp_d32) { 2115 uint32_t u; 2116 2117 u = cpu->isar.mvfr0; 2118 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 2119 cpu->isar.mvfr0 = u; 2120 } 2121 2122 if (!cpu->has_vfp) { 2123 uint64_t t; 2124 uint32_t u; 2125 2126 t = cpu->isar.id_aa64isar1; 2127 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 2128 cpu->isar.id_aa64isar1 = t; 2129 2130 t = cpu->isar.id_aa64pfr0; 2131 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 2132 cpu->isar.id_aa64pfr0 = t; 2133 2134 u = cpu->isar.id_isar6; 2135 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 2136 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2137 cpu->isar.id_isar6 = u; 2138 2139 u = cpu->isar.mvfr0; 2140 u = FIELD_DP32(u, MVFR0, FPSP, 0); 2141 u = FIELD_DP32(u, MVFR0, FPDP, 0); 2142 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 2143 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 2144 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 2145 if (!arm_feature(env, ARM_FEATURE_M)) { 2146 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 2147 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 2148 } 2149 cpu->isar.mvfr0 = u; 2150 2151 u = cpu->isar.mvfr1; 2152 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 2153 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 2154 u = FIELD_DP32(u, MVFR1, FPHP, 0); 2155 if (arm_feature(env, ARM_FEATURE_M)) { 2156 u = FIELD_DP32(u, MVFR1, FP16, 0); 2157 } 2158 cpu->isar.mvfr1 = u; 2159 2160 u = cpu->isar.mvfr2; 2161 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 2162 cpu->isar.mvfr2 = u; 2163 } 2164 2165 if (!cpu->has_neon) { 2166 uint64_t t; 2167 uint32_t u; 2168 2169 unset_feature(env, ARM_FEATURE_NEON); 2170 2171 t = cpu->isar.id_aa64isar0; 2172 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 2173 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 2174 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 2175 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 2176 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 2177 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 2178 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 2179 cpu->isar.id_aa64isar0 = t; 2180 2181 t = cpu->isar.id_aa64isar1; 2182 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 2183 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 2184 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 2185 cpu->isar.id_aa64isar1 = t; 2186 2187 t = cpu->isar.id_aa64pfr0; 2188 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 2189 cpu->isar.id_aa64pfr0 = t; 2190 2191 u = cpu->isar.id_isar5; 2192 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 2193 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 2194 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 2195 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 2196 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 2197 cpu->isar.id_isar5 = u; 2198 2199 u = cpu->isar.id_isar6; 2200 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 2201 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 2202 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2203 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 2204 cpu->isar.id_isar6 = u; 2205 2206 if (!arm_feature(env, ARM_FEATURE_M)) { 2207 u = cpu->isar.mvfr1; 2208 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 2209 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 2210 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 2211 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 2212 cpu->isar.mvfr1 = u; 2213 2214 u = cpu->isar.mvfr2; 2215 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 2216 cpu->isar.mvfr2 = u; 2217 } 2218 } 2219 2220 if (!cpu->has_neon && !cpu->has_vfp) { 2221 uint64_t t; 2222 uint32_t u; 2223 2224 t = cpu->isar.id_aa64isar0; 2225 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 2226 cpu->isar.id_aa64isar0 = t; 2227 2228 t = cpu->isar.id_aa64isar1; 2229 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 2230 cpu->isar.id_aa64isar1 = t; 2231 2232 u = cpu->isar.mvfr0; 2233 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 2234 cpu->isar.mvfr0 = u; 2235 2236 /* Despite the name, this field covers both VFP and Neon */ 2237 u = cpu->isar.mvfr1; 2238 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 2239 cpu->isar.mvfr1 = u; 2240 } 2241 2242 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 2243 uint32_t u; 2244 2245 unset_feature(env, ARM_FEATURE_THUMB_DSP); 2246 2247 u = cpu->isar.id_isar1; 2248 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 2249 cpu->isar.id_isar1 = u; 2250 2251 u = cpu->isar.id_isar2; 2252 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 2253 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 2254 cpu->isar.id_isar2 = u; 2255 2256 u = cpu->isar.id_isar3; 2257 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 2258 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 2259 cpu->isar.id_isar3 = u; 2260 } 2261 2262 2263 /* 2264 * We rely on no XScale CPU having VFP so we can use the same bits in the 2265 * TB flags field for VECSTRIDE and XSCALE_CPAR. 2266 */ 2267 assert(arm_feature(env, ARM_FEATURE_AARCH64) || 2268 !cpu_isar_feature(aa32_vfp_simd, cpu) || 2269 !arm_feature(env, ARM_FEATURE_XSCALE)); 2270 2271 #ifndef CONFIG_USER_ONLY 2272 { 2273 int pagebits; 2274 if (arm_feature(env, ARM_FEATURE_V7) && 2275 !arm_feature(env, ARM_FEATURE_M) && 2276 !arm_feature(env, ARM_FEATURE_PMSA)) { 2277 /* 2278 * v7VMSA drops support for the old ARMv5 tiny pages, 2279 * so we can use 4K pages. 2280 */ 2281 pagebits = 12; 2282 } else { 2283 /* 2284 * For CPUs which might have tiny 1K pages, or which have an 2285 * MPU and might have small region sizes, stick with 1K pages. 2286 */ 2287 pagebits = 10; 2288 } 2289 if (!set_preferred_target_page_bits(pagebits)) { 2290 /* 2291 * This can only ever happen for hotplugging a CPU, or if 2292 * the board code incorrectly creates a CPU which it has 2293 * promised via minimum_page_size that it will not. 2294 */ 2295 error_setg(errp, "This CPU requires a smaller page size " 2296 "than the system is using"); 2297 return; 2298 } 2299 } 2300 #endif 2301 2302 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 2303 * We don't support setting cluster ID ([16..23]) (known as Aff2 2304 * in later ARM ARM versions), or any of the higher affinity level fields, 2305 * so these bits always RAZ. 2306 */ 2307 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2308 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, 2309 ARM_DEFAULT_CPUS_PER_CLUSTER); 2310 } 2311 2312 if (cpu->reset_hivecs) { 2313 cpu->reset_sctlr |= (1 << 13); 2314 } 2315 2316 if (cpu->cfgend) { 2317 if (arm_feature(env, ARM_FEATURE_V7)) { 2318 cpu->reset_sctlr |= SCTLR_EE; 2319 } else { 2320 cpu->reset_sctlr |= SCTLR_B; 2321 } 2322 } 2323 2324 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2325 /* If the has_el3 CPU property is disabled then we need to disable the 2326 * feature. 2327 */ 2328 unset_feature(env, ARM_FEATURE_EL3); 2329 2330 /* 2331 * Disable the security extension feature bits in the processor 2332 * feature registers as well. 2333 */ 2334 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 2335 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 2336 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2337 ID_AA64PFR0, EL3, 0); 2338 2339 /* Disable the realm management extension, which requires EL3. */ 2340 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2341 ID_AA64PFR0, RME, 0); 2342 } 2343 2344 if (!cpu->has_el2) { 2345 unset_feature(env, ARM_FEATURE_EL2); 2346 } 2347 2348 if (!cpu->has_pmu) { 2349 unset_feature(env, ARM_FEATURE_PMU); 2350 } 2351 if (arm_feature(env, ARM_FEATURE_PMU)) { 2352 pmu_init(cpu); 2353 2354 if (!kvm_enabled()) { 2355 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2356 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2357 } 2358 2359 #ifndef CONFIG_USER_ONLY 2360 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2361 cpu); 2362 #endif 2363 } else { 2364 cpu->isar.id_aa64dfr0 = 2365 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 2366 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 2367 cpu->pmceid0 = 0; 2368 cpu->pmceid1 = 0; 2369 } 2370 2371 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2372 /* 2373 * Disable the hypervisor feature bits in the processor feature 2374 * registers if we don't have EL2. 2375 */ 2376 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2377 ID_AA64PFR0, EL2, 0); 2378 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 2379 ID_PFR1, VIRTUALIZATION, 0); 2380 } 2381 2382 if (cpu_isar_feature(aa64_mte, cpu)) { 2383 /* 2384 * The architectural range of GM blocksize is 2-6, however qemu 2385 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2386 */ 2387 if (tcg_enabled()) { 2388 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2389 } 2390 2391 #ifndef CONFIG_USER_ONLY 2392 /* 2393 * If we run with TCG and do not have tag-memory provided by 2394 * the machine, then reduce MTE support to instructions enabled at EL0. 2395 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2396 */ 2397 if (tcg_enabled() && cpu->tag_memory == NULL) { 2398 cpu->isar.id_aa64pfr1 = 2399 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); 2400 } 2401 2402 /* 2403 * If MTE is supported by the host, however it should not be 2404 * enabled on the guest (i.e mte=off), clear guest's MTE bits." 2405 */ 2406 if (kvm_enabled() && !cpu->kvm_mte) { 2407 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 2408 } 2409 #endif 2410 } 2411 2412 #ifndef CONFIG_USER_ONLY 2413 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) { 2414 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2415 arm_wfxt_timer_cb, cpu); 2416 } 2417 #endif 2418 2419 if (tcg_enabled()) { 2420 /* 2421 * Don't report some architectural features in the ID registers 2422 * where TCG does not yet implement it (not even a minimal 2423 * stub version). This avoids guests falling over when they 2424 * try to access the non-existent system registers for them. 2425 */ 2426 /* FEAT_SPE (Statistical Profiling Extension) */ 2427 cpu->isar.id_aa64dfr0 = 2428 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2429 /* FEAT_TRBE (Trace Buffer Extension) */ 2430 cpu->isar.id_aa64dfr0 = 2431 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); 2432 /* FEAT_TRF (Self-hosted Trace Extension) */ 2433 cpu->isar.id_aa64dfr0 = 2434 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2435 cpu->isar.id_dfr0 = 2436 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2437 /* Trace Macrocell system register access */ 2438 cpu->isar.id_aa64dfr0 = 2439 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2440 cpu->isar.id_dfr0 = 2441 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2442 /* Memory mapped trace */ 2443 cpu->isar.id_dfr0 = 2444 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2445 /* FEAT_AMU (Activity Monitors Extension) */ 2446 cpu->isar.id_aa64pfr0 = 2447 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2448 cpu->isar.id_pfr0 = 2449 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2450 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2451 cpu->isar.id_aa64pfr0 = 2452 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2453 } 2454 2455 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2456 * to false or by setting pmsav7-dregion to 0. 2457 */ 2458 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2459 cpu->has_mpu = false; 2460 cpu->pmsav7_dregion = 0; 2461 cpu->pmsav8r_hdregion = 0; 2462 } 2463 2464 if (arm_feature(env, ARM_FEATURE_PMSA) && 2465 arm_feature(env, ARM_FEATURE_V7)) { 2466 uint32_t nr = cpu->pmsav7_dregion; 2467 2468 if (nr > 0xff) { 2469 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2470 return; 2471 } 2472 2473 if (nr) { 2474 if (arm_feature(env, ARM_FEATURE_V8)) { 2475 /* PMSAv8 */ 2476 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2477 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2478 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2479 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2480 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2481 } 2482 } else { 2483 env->pmsav7.drbar = g_new0(uint32_t, nr); 2484 env->pmsav7.drsr = g_new0(uint32_t, nr); 2485 env->pmsav7.dracr = g_new0(uint32_t, nr); 2486 } 2487 } 2488 2489 if (cpu->pmsav8r_hdregion > 0xff) { 2490 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2491 cpu->pmsav8r_hdregion); 2492 return; 2493 } 2494 2495 if (cpu->pmsav8r_hdregion) { 2496 env->pmsav8.hprbar = g_new0(uint32_t, 2497 cpu->pmsav8r_hdregion); 2498 env->pmsav8.hprlar = g_new0(uint32_t, 2499 cpu->pmsav8r_hdregion); 2500 } 2501 } 2502 2503 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2504 uint32_t nr = cpu->sau_sregion; 2505 2506 if (nr > 0xff) { 2507 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2508 return; 2509 } 2510 2511 if (nr) { 2512 env->sau.rbar = g_new0(uint32_t, nr); 2513 env->sau.rlar = g_new0(uint32_t, nr); 2514 } 2515 } 2516 2517 if (arm_feature(env, ARM_FEATURE_EL3)) { 2518 set_feature(env, ARM_FEATURE_VBAR); 2519 } 2520 2521 #ifndef CONFIG_USER_ONLY 2522 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2523 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2524 } 2525 #endif 2526 2527 register_cp_regs_for_features(cpu); 2528 arm_cpu_register_gdb_regs_for_features(cpu); 2529 arm_cpu_register_gdb_commands(cpu); 2530 2531 init_cpreg_list(cpu); 2532 2533 #ifndef CONFIG_USER_ONLY 2534 MachineState *ms = MACHINE(qdev_get_machine()); 2535 unsigned int smp_cpus = ms->smp.cpus; 2536 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2537 2538 /* 2539 * We must set cs->num_ases to the final value before 2540 * the first call to cpu_address_space_init. 2541 */ 2542 if (cpu->tag_memory != NULL) { 2543 cs->num_ases = 3 + has_secure; 2544 } else { 2545 cs->num_ases = 1 + has_secure; 2546 } 2547 2548 if (has_secure) { 2549 if (!cpu->secure_memory) { 2550 cpu->secure_memory = cs->memory; 2551 } 2552 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2553 cpu->secure_memory); 2554 } 2555 2556 if (cpu->tag_memory != NULL) { 2557 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2558 cpu->tag_memory); 2559 if (has_secure) { 2560 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2561 cpu->secure_tag_memory); 2562 } 2563 } 2564 2565 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2566 2567 /* No core_count specified, default to smp_cpus. */ 2568 if (cpu->core_count == -1) { 2569 cpu->core_count = smp_cpus; 2570 } 2571 #endif 2572 2573 if (tcg_enabled()) { 2574 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2575 2576 /* 2577 * We only support DCZ blocklen that fits on one page. 2578 * 2579 * Architectually this is always true. However TARGET_PAGE_SIZE 2580 * is variable and, for compatibility with -machine virt-2.7, 2581 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2582 * But even then, while the largest architectural DCZ blocklen 2583 * is 2KiB, no cpu actually uses such a large blocklen. 2584 */ 2585 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2586 2587 /* 2588 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2589 * both nibbles of each byte storing tag data may be written at once. 2590 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2591 */ 2592 if (cpu_isar_feature(aa64_mte, cpu)) { 2593 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2594 } 2595 } 2596 2597 qemu_init_vcpu(cs); 2598 cpu_reset(cs); 2599 2600 acc->parent_realize(dev, errp); 2601 } 2602 2603 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2604 { 2605 ObjectClass *oc; 2606 char *typename; 2607 char **cpuname; 2608 const char *cpunamestr; 2609 2610 cpuname = g_strsplit(cpu_model, ",", 1); 2611 cpunamestr = cpuname[0]; 2612 #ifdef CONFIG_USER_ONLY 2613 /* For backwards compatibility usermode emulation allows "-cpu any", 2614 * which has the same semantics as "-cpu max". 2615 */ 2616 if (!strcmp(cpunamestr, "any")) { 2617 cpunamestr = "max"; 2618 } 2619 #endif 2620 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2621 oc = object_class_by_name(typename); 2622 g_strfreev(cpuname); 2623 g_free(typename); 2624 2625 return oc; 2626 } 2627 2628 static const Property arm_cpu_properties[] = { 2629 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2630 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2631 mp_affinity, ARM64_AFFINITY_INVALID), 2632 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2633 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2634 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ 2635 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), 2636 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, 2637 backcompat_pauth_default_use_qarma5, false), 2638 }; 2639 2640 static const gchar *arm_gdb_arch_name(CPUState *cs) 2641 { 2642 ARMCPU *cpu = ARM_CPU(cs); 2643 CPUARMState *env = &cpu->env; 2644 2645 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2646 return "iwmmxt"; 2647 } 2648 return "arm"; 2649 } 2650 2651 #ifndef CONFIG_USER_ONLY 2652 #include "hw/core/sysemu-cpu-ops.h" 2653 2654 static const struct SysemuCPUOps arm_sysemu_ops = { 2655 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2656 .asidx_from_attrs = arm_asidx_from_attrs, 2657 .write_elf32_note = arm_cpu_write_elf32_note, 2658 .write_elf64_note = arm_cpu_write_elf64_note, 2659 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2660 .legacy_vmsd = &vmstate_arm_cpu, 2661 }; 2662 #endif 2663 2664 #ifdef CONFIG_TCG 2665 static const TCGCPUOps arm_tcg_ops = { 2666 .initialize = arm_translate_init, 2667 .translate_code = arm_translate_code, 2668 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2669 .debug_excp_handler = arm_debug_excp_handler, 2670 .restore_state_to_opc = arm_restore_state_to_opc, 2671 2672 #ifdef CONFIG_USER_ONLY 2673 .record_sigsegv = arm_cpu_record_sigsegv, 2674 .record_sigbus = arm_cpu_record_sigbus, 2675 #else 2676 .tlb_fill_align = arm_cpu_tlb_fill_align, 2677 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2678 .cpu_exec_halt = arm_cpu_exec_halt, 2679 .do_interrupt = arm_cpu_do_interrupt, 2680 .do_transaction_failed = arm_cpu_do_transaction_failed, 2681 .do_unaligned_access = arm_cpu_do_unaligned_access, 2682 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2683 .debug_check_watchpoint = arm_debug_check_watchpoint, 2684 .debug_check_breakpoint = arm_debug_check_breakpoint, 2685 #endif /* !CONFIG_USER_ONLY */ 2686 }; 2687 #endif /* CONFIG_TCG */ 2688 2689 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2690 { 2691 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2692 CPUClass *cc = CPU_CLASS(acc); 2693 DeviceClass *dc = DEVICE_CLASS(oc); 2694 ResettableClass *rc = RESETTABLE_CLASS(oc); 2695 2696 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2697 &acc->parent_realize); 2698 2699 device_class_set_props(dc, arm_cpu_properties); 2700 2701 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2702 &acc->parent_phases); 2703 2704 cc->class_by_name = arm_cpu_class_by_name; 2705 cc->has_work = arm_cpu_has_work; 2706 cc->mmu_index = arm_cpu_mmu_index; 2707 cc->dump_state = arm_cpu_dump_state; 2708 cc->set_pc = arm_cpu_set_pc; 2709 cc->get_pc = arm_cpu_get_pc; 2710 cc->gdb_read_register = arm_cpu_gdb_read_register; 2711 cc->gdb_write_register = arm_cpu_gdb_write_register; 2712 #ifndef CONFIG_USER_ONLY 2713 cc->sysemu_ops = &arm_sysemu_ops; 2714 #endif 2715 cc->gdb_arch_name = arm_gdb_arch_name; 2716 cc->gdb_stop_before_watchpoint = true; 2717 cc->disas_set_info = arm_disas_set_info; 2718 2719 #ifdef CONFIG_TCG 2720 cc->tcg_ops = &arm_tcg_ops; 2721 #endif /* CONFIG_TCG */ 2722 } 2723 2724 static void arm_cpu_instance_init(Object *obj) 2725 { 2726 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2727 2728 acc->info->initfn(obj); 2729 arm_cpu_post_init(obj); 2730 } 2731 2732 static void cpu_register_class_init(ObjectClass *oc, void *data) 2733 { 2734 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2735 CPUClass *cc = CPU_CLASS(acc); 2736 2737 acc->info = data; 2738 cc->gdb_core_xml_file = "arm-core.xml"; 2739 if (acc->info->deprecation_note) { 2740 cc->deprecation_note = acc->info->deprecation_note; 2741 } 2742 } 2743 2744 void arm_cpu_register(const ARMCPUInfo *info) 2745 { 2746 TypeInfo type_info = { 2747 .parent = TYPE_ARM_CPU, 2748 .instance_init = arm_cpu_instance_init, 2749 .class_init = info->class_init ?: cpu_register_class_init, 2750 .class_data = (void *)info, 2751 }; 2752 2753 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2754 type_register_static(&type_info); 2755 g_free((void *)type_info.name); 2756 } 2757 2758 static const TypeInfo arm_cpu_type_info = { 2759 .name = TYPE_ARM_CPU, 2760 .parent = TYPE_CPU, 2761 .instance_size = sizeof(ARMCPU), 2762 .instance_align = __alignof__(ARMCPU), 2763 .instance_init = arm_cpu_initfn, 2764 .instance_finalize = arm_cpu_finalizefn, 2765 .abstract = true, 2766 .class_size = sizeof(ARMCPUClass), 2767 .class_init = arm_cpu_class_init, 2768 }; 2769 2770 static void arm_cpu_register_types(void) 2771 { 2772 type_register_static(&arm_cpu_type_info); 2773 } 2774 2775 type_init(arm_cpu_register_types) 2776