1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "exec/translation-block.h" 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "cpu-features.h" 36 #include "exec/exec-all.h" 37 #include "hw/qdev-properties.h" 38 #if !defined(CONFIG_USER_ONLY) 39 #include "hw/loader.h" 40 #include "hw/boards.h" 41 #ifdef CONFIG_TCG 42 #include "hw/intc/armv7m_nvic.h" 43 #endif /* CONFIG_TCG */ 44 #endif /* !CONFIG_USER_ONLY */ 45 #include "system/tcg.h" 46 #include "system/qtest.h" 47 #include "system/hw_accel.h" 48 #include "kvm_arm.h" 49 #include "disas/capstone.h" 50 #include "fpu/softfloat.h" 51 #include "cpregs.h" 52 #include "target/arm/cpu-qom.h" 53 #include "target/arm/gtimer.h" 54 55 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 56 { 57 ARMCPU *cpu = ARM_CPU(cs); 58 CPUARMState *env = &cpu->env; 59 60 if (is_a64(env)) { 61 env->pc = value; 62 env->thumb = false; 63 } else { 64 env->regs[15] = value & ~1; 65 env->thumb = value & 1; 66 } 67 } 68 69 static vaddr arm_cpu_get_pc(CPUState *cs) 70 { 71 ARMCPU *cpu = ARM_CPU(cs); 72 CPUARMState *env = &cpu->env; 73 74 if (is_a64(env)) { 75 return env->pc; 76 } else { 77 return env->regs[15]; 78 } 79 } 80 81 #ifdef CONFIG_TCG 82 void arm_cpu_synchronize_from_tb(CPUState *cs, 83 const TranslationBlock *tb) 84 { 85 /* The program counter is always up to date with CF_PCREL. */ 86 if (!(tb_cflags(tb) & CF_PCREL)) { 87 CPUARMState *env = cpu_env(cs); 88 /* 89 * It's OK to look at env for the current mode here, because it's 90 * never possible for an AArch64 TB to chain to an AArch32 TB. 91 */ 92 if (is_a64(env)) { 93 env->pc = tb->pc; 94 } else { 95 env->regs[15] = tb->pc; 96 } 97 } 98 } 99 100 void arm_restore_state_to_opc(CPUState *cs, 101 const TranslationBlock *tb, 102 const uint64_t *data) 103 { 104 CPUARMState *env = cpu_env(cs); 105 106 if (is_a64(env)) { 107 if (tb_cflags(tb) & CF_PCREL) { 108 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 109 } else { 110 env->pc = data[0]; 111 } 112 env->condexec_bits = 0; 113 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 114 } else { 115 if (tb_cflags(tb) & CF_PCREL) { 116 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 117 } else { 118 env->regs[15] = data[0]; 119 } 120 env->condexec_bits = data[1]; 121 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 122 } 123 } 124 #endif /* CONFIG_TCG */ 125 126 /* 127 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with 128 * IRQ without Superpriority. Moreover, if the GIC is configured so that 129 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see 130 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here 131 * unconditionally. 132 */ 133 static bool arm_cpu_has_work(CPUState *cs) 134 { 135 ARMCPU *cpu = ARM_CPU(cs); 136 137 return (cpu->power_state != PSCI_OFF) 138 && cs->interrupt_request & 139 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 140 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI 141 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 142 | CPU_INTERRUPT_EXITTB); 143 } 144 145 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) 146 { 147 return arm_env_mmu_index(cpu_env(cs)); 148 } 149 150 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 151 void *opaque) 152 { 153 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 154 155 entry->hook = hook; 156 entry->opaque = opaque; 157 158 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 159 } 160 161 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 162 void *opaque) 163 { 164 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 165 166 entry->hook = hook; 167 entry->opaque = opaque; 168 169 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 170 } 171 172 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 173 { 174 /* Reset a single ARMCPRegInfo register */ 175 ARMCPRegInfo *ri = value; 176 ARMCPU *cpu = opaque; 177 178 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 179 return; 180 } 181 182 if (ri->resetfn) { 183 ri->resetfn(&cpu->env, ri); 184 return; 185 } 186 187 /* A zero offset is never possible as it would be regs[0] 188 * so we use it to indicate that reset is being handled elsewhere. 189 * This is basically only used for fields in non-core coprocessors 190 * (like the pxa2xx ones). 191 */ 192 if (!ri->fieldoffset) { 193 return; 194 } 195 196 if (cpreg_field_is_64bit(ri)) { 197 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 198 } else { 199 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 200 } 201 } 202 203 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 204 { 205 /* Purely an assertion check: we've already done reset once, 206 * so now check that running the reset for the cpreg doesn't 207 * change its value. This traps bugs where two different cpregs 208 * both try to reset the same state field but to different values. 209 */ 210 ARMCPRegInfo *ri = value; 211 ARMCPU *cpu = opaque; 212 uint64_t oldvalue, newvalue; 213 214 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 215 return; 216 } 217 218 oldvalue = read_raw_cp_reg(&cpu->env, ri); 219 cp_reg_reset(key, value, opaque); 220 newvalue = read_raw_cp_reg(&cpu->env, ri); 221 assert(oldvalue == newvalue); 222 } 223 224 static void arm_cpu_reset_hold(Object *obj, ResetType type) 225 { 226 CPUState *cs = CPU(obj); 227 ARMCPU *cpu = ARM_CPU(cs); 228 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 229 CPUARMState *env = &cpu->env; 230 231 if (acc->parent_phases.hold) { 232 acc->parent_phases.hold(obj, type); 233 } 234 235 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 236 237 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 238 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 239 240 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 241 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 242 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 243 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 244 245 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; 246 247 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 248 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 249 } 250 251 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 252 /* 64 bit CPUs always start in 64 bit mode */ 253 env->aarch64 = true; 254 #if defined(CONFIG_USER_ONLY) 255 env->pstate = PSTATE_MODE_EL0t; 256 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 257 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 258 /* Enable all PAC keys. */ 259 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 260 SCTLR_EnDA | SCTLR_EnDB); 261 /* Trap on btype=3 for PACIxSP. */ 262 env->cp15.sctlr_el[1] |= SCTLR_BT0; 263 /* Trap on implementation defined registers. */ 264 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 265 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 266 } 267 /* and to the FP/Neon instructions */ 268 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 269 CPACR_EL1, FPEN, 3); 270 /* and to the SVE instructions, with default vector length */ 271 if (cpu_isar_feature(aa64_sve, cpu)) { 272 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 273 CPACR_EL1, ZEN, 3); 274 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 275 } 276 /* and for SME instructions, with default vector length, and TPIDR2 */ 277 if (cpu_isar_feature(aa64_sme, cpu)) { 278 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 279 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 280 CPACR_EL1, SMEN, 3); 281 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 282 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 283 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 284 SMCR, FA64, 1); 285 } 286 } 287 /* 288 * Enable 48-bit address space (TODO: take reserved_va into account). 289 * Enable TBI0 but not TBI1. 290 * Note that this must match useronly_clean_ptr. 291 */ 292 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 293 294 /* Enable MTE */ 295 if (cpu_isar_feature(aa64_mte, cpu)) { 296 /* Enable tag access, but leave TCF0 as No Effect (0). */ 297 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 298 /* 299 * Exclude all tags, so that tag 0 is always used. 300 * This corresponds to Linux current->thread.gcr_incl = 0. 301 * 302 * Set RRND, so that helper_irg() will generate a seed later. 303 * Here in cpu_reset(), the crypto subsystem has not yet been 304 * initialized. 305 */ 306 env->cp15.gcr_el1 = 0x1ffff; 307 } 308 /* 309 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 310 * This is not yet exposed from the Linux kernel in any way. 311 */ 312 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 313 /* Disable access to Debug Communication Channel (DCC). */ 314 env->cp15.mdscr_el1 |= 1 << 12; 315 /* Enable FEAT_MOPS */ 316 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; 317 #else 318 /* Reset into the highest available EL */ 319 if (arm_feature(env, ARM_FEATURE_EL3)) { 320 env->pstate = PSTATE_MODE_EL3h; 321 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 322 env->pstate = PSTATE_MODE_EL2h; 323 } else { 324 env->pstate = PSTATE_MODE_EL1h; 325 } 326 327 /* Sample rvbar at reset. */ 328 env->cp15.rvbar = cpu->rvbar_prop; 329 env->pc = env->cp15.rvbar; 330 #endif 331 } else { 332 #if defined(CONFIG_USER_ONLY) 333 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 334 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 335 CPACR, CP10, 3); 336 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 337 CPACR, CP11, 3); 338 #endif 339 if (arm_feature(env, ARM_FEATURE_V8)) { 340 env->cp15.rvbar = cpu->rvbar_prop; 341 env->regs[15] = cpu->rvbar_prop; 342 } 343 } 344 345 #if defined(CONFIG_USER_ONLY) 346 env->uncached_cpsr = ARM_CPU_MODE_USR; 347 /* For user mode we must enable access to coprocessors */ 348 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 349 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 350 env->cp15.c15_cpar = 3; 351 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 352 env->cp15.c15_cpar = 1; 353 } 354 #else 355 356 /* 357 * If the highest available EL is EL2, AArch32 will start in Hyp 358 * mode; otherwise it starts in SVC. Note that if we start in 359 * AArch64 then these values in the uncached_cpsr will be ignored. 360 */ 361 if (arm_feature(env, ARM_FEATURE_EL2) && 362 !arm_feature(env, ARM_FEATURE_EL3)) { 363 env->uncached_cpsr = ARM_CPU_MODE_HYP; 364 } else { 365 env->uncached_cpsr = ARM_CPU_MODE_SVC; 366 } 367 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 368 369 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 370 * executing as AArch32 then check if highvecs are enabled and 371 * adjust the PC accordingly. 372 */ 373 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 374 env->regs[15] = 0xFFFF0000; 375 } 376 377 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 378 #endif 379 380 if (arm_feature(env, ARM_FEATURE_M)) { 381 #ifndef CONFIG_USER_ONLY 382 uint32_t initial_msp; /* Loaded from 0x0 */ 383 uint32_t initial_pc; /* Loaded from 0x4 */ 384 uint8_t *rom; 385 uint32_t vecbase; 386 #endif 387 388 if (cpu_isar_feature(aa32_lob, cpu)) { 389 /* 390 * LTPSIZE is constant 4 if MVE not implemented, and resets 391 * to an UNKNOWN value if MVE is implemented. We choose to 392 * always reset to 4. 393 */ 394 env->v7m.ltpsize = 4; 395 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 396 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 397 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 398 } 399 400 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 401 env->v7m.secure = true; 402 } else { 403 /* This bit resets to 0 if security is supported, but 1 if 404 * it is not. The bit is not present in v7M, but we set it 405 * here so we can avoid having to make checks on it conditional 406 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 407 */ 408 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 409 /* 410 * Set NSACR to indicate "NS access permitted to everything"; 411 * this avoids having to have all the tests of it being 412 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 413 * v8.1M the guest-visible value of NSACR in a CPU without the 414 * Security Extension is 0xcff. 415 */ 416 env->v7m.nsacr = 0xcff; 417 } 418 419 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 420 * that it resets to 1, so QEMU always does that rather than making 421 * it dependent on CPU model. In v8M it is RES1. 422 */ 423 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 424 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 425 if (arm_feature(env, ARM_FEATURE_V8)) { 426 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 427 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 428 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 429 } 430 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 431 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 432 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 433 } 434 435 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 436 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 437 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 438 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 439 } 440 441 #ifndef CONFIG_USER_ONLY 442 /* Unlike A/R profile, M profile defines the reset LR value */ 443 env->regs[14] = 0xffffffff; 444 445 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 446 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 447 448 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 449 vecbase = env->v7m.vecbase[env->v7m.secure]; 450 rom = rom_ptr_for_as(cs->as, vecbase, 8); 451 if (rom) { 452 /* Address zero is covered by ROM which hasn't yet been 453 * copied into physical memory. 454 */ 455 initial_msp = ldl_p(rom); 456 initial_pc = ldl_p(rom + 4); 457 } else { 458 /* Address zero not covered by a ROM blob, or the ROM blob 459 * is in non-modifiable memory and this is a second reset after 460 * it got copied into memory. In the latter case, rom_ptr 461 * will return a NULL pointer and we should use ldl_phys instead. 462 */ 463 initial_msp = ldl_phys(cs->as, vecbase); 464 initial_pc = ldl_phys(cs->as, vecbase + 4); 465 } 466 467 qemu_log_mask(CPU_LOG_INT, 468 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 469 initial_msp, initial_pc); 470 471 env->regs[13] = initial_msp & 0xFFFFFFFC; 472 env->regs[15] = initial_pc & ~1; 473 env->thumb = initial_pc & 1; 474 #else 475 /* 476 * For user mode we run non-secure and with access to the FPU. 477 * The FPU context is active (ie does not need further setup) 478 * and is owned by non-secure. 479 */ 480 env->v7m.secure = false; 481 env->v7m.nsacr = 0xcff; 482 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 483 env->v7m.fpccr[M_REG_S] &= 484 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 485 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 486 #endif 487 } 488 489 /* M profile requires that reset clears the exclusive monitor; 490 * A profile does not, but clearing it makes more sense than having it 491 * set with an exclusive access on address zero. 492 */ 493 arm_clear_exclusive(env); 494 495 if (arm_feature(env, ARM_FEATURE_PMSA)) { 496 if (cpu->pmsav7_dregion > 0) { 497 if (arm_feature(env, ARM_FEATURE_V8)) { 498 memset(env->pmsav8.rbar[M_REG_NS], 0, 499 sizeof(*env->pmsav8.rbar[M_REG_NS]) 500 * cpu->pmsav7_dregion); 501 memset(env->pmsav8.rlar[M_REG_NS], 0, 502 sizeof(*env->pmsav8.rlar[M_REG_NS]) 503 * cpu->pmsav7_dregion); 504 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 505 memset(env->pmsav8.rbar[M_REG_S], 0, 506 sizeof(*env->pmsav8.rbar[M_REG_S]) 507 * cpu->pmsav7_dregion); 508 memset(env->pmsav8.rlar[M_REG_S], 0, 509 sizeof(*env->pmsav8.rlar[M_REG_S]) 510 * cpu->pmsav7_dregion); 511 } 512 } else if (arm_feature(env, ARM_FEATURE_V7)) { 513 memset(env->pmsav7.drbar, 0, 514 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 515 memset(env->pmsav7.drsr, 0, 516 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 517 memset(env->pmsav7.dracr, 0, 518 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 519 } 520 } 521 522 if (cpu->pmsav8r_hdregion > 0) { 523 memset(env->pmsav8.hprbar, 0, 524 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 525 memset(env->pmsav8.hprlar, 0, 526 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 527 } 528 529 env->pmsav7.rnr[M_REG_NS] = 0; 530 env->pmsav7.rnr[M_REG_S] = 0; 531 env->pmsav8.mair0[M_REG_NS] = 0; 532 env->pmsav8.mair0[M_REG_S] = 0; 533 env->pmsav8.mair1[M_REG_NS] = 0; 534 env->pmsav8.mair1[M_REG_S] = 0; 535 } 536 537 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 538 if (cpu->sau_sregion > 0) { 539 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 540 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 541 } 542 env->sau.rnr = 0; 543 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 544 * the Cortex-M33 does. 545 */ 546 env->sau.ctrl = 0; 547 } 548 549 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]); 550 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); 551 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); 552 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); 553 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); 554 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); 555 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); 556 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); 557 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); 558 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); 559 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); 560 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); 561 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]); 562 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); 563 564 #ifndef CONFIG_USER_ONLY 565 if (kvm_enabled()) { 566 kvm_arm_reset_vcpu(cpu); 567 } 568 #endif 569 570 if (tcg_enabled()) { 571 hw_breakpoint_update_all(cpu); 572 hw_watchpoint_update_all(cpu); 573 574 arm_rebuild_hflags(env); 575 } 576 } 577 578 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 579 { 580 ARMCPU *cpu = ARM_CPU(cpustate); 581 CPUARMState *env = &cpu->env; 582 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 583 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 584 585 /* 586 * Check we have the EL we're aiming for. If that is the 587 * highest implemented EL, then cpu_reset has already done 588 * all the work. 589 */ 590 switch (target_el) { 591 case 3: 592 assert(have_el3); 593 return; 594 case 2: 595 assert(have_el2); 596 if (!have_el3) { 597 return; 598 } 599 break; 600 case 1: 601 if (!have_el3 && !have_el2) { 602 return; 603 } 604 break; 605 default: 606 g_assert_not_reached(); 607 } 608 609 if (have_el3) { 610 /* 611 * Set the EL3 state so code can run at EL2. This should match 612 * the requirements set by Linux in its booting spec. 613 */ 614 if (env->aarch64) { 615 env->cp15.scr_el3 |= SCR_RW; 616 if (cpu_isar_feature(aa64_pauth, cpu)) { 617 env->cp15.scr_el3 |= SCR_API | SCR_APK; 618 } 619 if (cpu_isar_feature(aa64_mte, cpu)) { 620 env->cp15.scr_el3 |= SCR_ATA; 621 } 622 if (cpu_isar_feature(aa64_sve, cpu)) { 623 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 624 env->vfp.zcr_el[3] = 0xf; 625 } 626 if (cpu_isar_feature(aa64_sme, cpu)) { 627 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 628 env->cp15.scr_el3 |= SCR_ENTP2; 629 env->vfp.smcr_el[3] = 0xf; 630 } 631 if (cpu_isar_feature(aa64_hcx, cpu)) { 632 env->cp15.scr_el3 |= SCR_HXEN; 633 } 634 if (cpu_isar_feature(aa64_fgt, cpu)) { 635 env->cp15.scr_el3 |= SCR_FGTEN; 636 } 637 } 638 639 if (target_el == 2) { 640 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 641 env->cp15.scr_el3 |= SCR_HCE; 642 } 643 644 /* Put CPU into non-secure state */ 645 env->cp15.scr_el3 |= SCR_NS; 646 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 647 env->cp15.nsacr |= 3 << 10; 648 } 649 650 if (have_el2 && target_el < 2) { 651 /* Set EL2 state so code can run at EL1. */ 652 if (env->aarch64) { 653 env->cp15.hcr_el2 |= HCR_RW; 654 } 655 } 656 657 /* Set the CPU to the desired state */ 658 if (env->aarch64) { 659 env->pstate = aarch64_pstate_mode(target_el, true); 660 } else { 661 static const uint32_t mode_for_el[] = { 662 0, 663 ARM_CPU_MODE_SVC, 664 ARM_CPU_MODE_HYP, 665 ARM_CPU_MODE_SVC, 666 }; 667 668 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 669 } 670 } 671 672 673 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 674 675 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 676 unsigned int target_el, 677 unsigned int cur_el, bool secure, 678 uint64_t hcr_el2) 679 { 680 CPUARMState *env = cpu_env(cs); 681 bool pstate_unmasked; 682 bool unmasked = false; 683 bool allIntMask = false; 684 685 /* 686 * Don't take exceptions if they target a lower EL. 687 * This check should catch any exceptions that would not be taken 688 * but left pending. 689 */ 690 if (cur_el > target_el) { 691 return false; 692 } 693 694 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 695 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { 696 allIntMask = env->pstate & PSTATE_ALLINT || 697 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && 698 (env->pstate & PSTATE_SP)); 699 } 700 701 switch (excp_idx) { 702 case EXCP_NMI: 703 pstate_unmasked = !allIntMask; 704 break; 705 706 case EXCP_VINMI: 707 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 708 /* VINMIs are only taken when hypervized. */ 709 return false; 710 } 711 return !allIntMask; 712 case EXCP_VFNMI: 713 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 714 /* VFNMIs are only taken when hypervized. */ 715 return false; 716 } 717 return !allIntMask; 718 case EXCP_FIQ: 719 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask); 720 break; 721 722 case EXCP_IRQ: 723 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask); 724 break; 725 726 case EXCP_VFIQ: 727 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 728 /* VFIQs are only taken when hypervized. */ 729 return false; 730 } 731 return !(env->daif & PSTATE_F) && (!allIntMask); 732 case EXCP_VIRQ: 733 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 734 /* VIRQs are only taken when hypervized. */ 735 return false; 736 } 737 return !(env->daif & PSTATE_I) && (!allIntMask); 738 case EXCP_VSERR: 739 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 740 /* VIRQs are only taken when hypervized. */ 741 return false; 742 } 743 return !(env->daif & PSTATE_A); 744 default: 745 g_assert_not_reached(); 746 } 747 748 /* 749 * Use the target EL, current execution state and SCR/HCR settings to 750 * determine whether the corresponding CPSR bit is used to mask the 751 * interrupt. 752 */ 753 if ((target_el > cur_el) && (target_el != 1)) { 754 /* Exceptions targeting a higher EL may not be maskable */ 755 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 756 switch (target_el) { 757 case 2: 758 /* 759 * According to ARM DDI 0487H.a, an interrupt can be masked 760 * when HCR_E2H and HCR_TGE are both set regardless of the 761 * current Security state. Note that we need to revisit this 762 * part again once we need to support NMI. 763 */ 764 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 765 unmasked = true; 766 } 767 break; 768 case 3: 769 /* Interrupt cannot be masked when the target EL is 3 */ 770 unmasked = true; 771 break; 772 default: 773 g_assert_not_reached(); 774 } 775 } else { 776 /* 777 * The old 32-bit-only environment has a more complicated 778 * masking setup. HCR and SCR bits not only affect interrupt 779 * routing but also change the behaviour of masking. 780 */ 781 bool hcr, scr; 782 783 switch (excp_idx) { 784 case EXCP_FIQ: 785 /* 786 * If FIQs are routed to EL3 or EL2 then there are cases where 787 * we override the CPSR.F in determining if the exception is 788 * masked or not. If neither of these are set then we fall back 789 * to the CPSR.F setting otherwise we further assess the state 790 * below. 791 */ 792 hcr = hcr_el2 & HCR_FMO; 793 scr = (env->cp15.scr_el3 & SCR_FIQ); 794 795 /* 796 * When EL3 is 32-bit, the SCR.FW bit controls whether the 797 * CPSR.F bit masks FIQ interrupts when taken in non-secure 798 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 799 * when non-secure but only when FIQs are only routed to EL3. 800 */ 801 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 802 break; 803 case EXCP_IRQ: 804 /* 805 * When EL3 execution state is 32-bit, if HCR.IMO is set then 806 * we may override the CPSR.I masking when in non-secure state. 807 * The SCR.IRQ setting has already been taken into consideration 808 * when setting the target EL, so it does not have a further 809 * affect here. 810 */ 811 hcr = hcr_el2 & HCR_IMO; 812 scr = false; 813 break; 814 default: 815 g_assert_not_reached(); 816 } 817 818 if ((scr || hcr) && !secure) { 819 unmasked = true; 820 } 821 } 822 } 823 824 /* 825 * The PSTATE bits only mask the interrupt if we have not overridden the 826 * ability above. 827 */ 828 return unmasked || pstate_unmasked; 829 } 830 831 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 832 { 833 CPUClass *cc = CPU_GET_CLASS(cs); 834 CPUARMState *env = cpu_env(cs); 835 uint32_t cur_el = arm_current_el(env); 836 bool secure = arm_is_secure(env); 837 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 838 uint32_t target_el; 839 uint32_t excp_idx; 840 841 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 842 843 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 844 (arm_sctlr(env, cur_el) & SCTLR_NMI)) { 845 if (interrupt_request & CPU_INTERRUPT_NMI) { 846 excp_idx = EXCP_NMI; 847 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 848 if (arm_excp_unmasked(cs, excp_idx, target_el, 849 cur_el, secure, hcr_el2)) { 850 goto found; 851 } 852 } 853 if (interrupt_request & CPU_INTERRUPT_VINMI) { 854 excp_idx = EXCP_VINMI; 855 target_el = 1; 856 if (arm_excp_unmasked(cs, excp_idx, target_el, 857 cur_el, secure, hcr_el2)) { 858 goto found; 859 } 860 } 861 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 862 excp_idx = EXCP_VFNMI; 863 target_el = 1; 864 if (arm_excp_unmasked(cs, excp_idx, target_el, 865 cur_el, secure, hcr_el2)) { 866 goto found; 867 } 868 } 869 } else { 870 /* 871 * NMI disabled: interrupts with superpriority are handled 872 * as if they didn't have it 873 */ 874 if (interrupt_request & CPU_INTERRUPT_NMI) { 875 interrupt_request |= CPU_INTERRUPT_HARD; 876 } 877 if (interrupt_request & CPU_INTERRUPT_VINMI) { 878 interrupt_request |= CPU_INTERRUPT_VIRQ; 879 } 880 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 881 interrupt_request |= CPU_INTERRUPT_VFIQ; 882 } 883 } 884 885 if (interrupt_request & CPU_INTERRUPT_FIQ) { 886 excp_idx = EXCP_FIQ; 887 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 888 if (arm_excp_unmasked(cs, excp_idx, target_el, 889 cur_el, secure, hcr_el2)) { 890 goto found; 891 } 892 } 893 if (interrupt_request & CPU_INTERRUPT_HARD) { 894 excp_idx = EXCP_IRQ; 895 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 896 if (arm_excp_unmasked(cs, excp_idx, target_el, 897 cur_el, secure, hcr_el2)) { 898 goto found; 899 } 900 } 901 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 902 excp_idx = EXCP_VIRQ; 903 target_el = 1; 904 if (arm_excp_unmasked(cs, excp_idx, target_el, 905 cur_el, secure, hcr_el2)) { 906 goto found; 907 } 908 } 909 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 910 excp_idx = EXCP_VFIQ; 911 target_el = 1; 912 if (arm_excp_unmasked(cs, excp_idx, target_el, 913 cur_el, secure, hcr_el2)) { 914 goto found; 915 } 916 } 917 if (interrupt_request & CPU_INTERRUPT_VSERR) { 918 excp_idx = EXCP_VSERR; 919 target_el = 1; 920 if (arm_excp_unmasked(cs, excp_idx, target_el, 921 cur_el, secure, hcr_el2)) { 922 /* Taking a virtual abort clears HCR_EL2.VSE */ 923 env->cp15.hcr_el2 &= ~HCR_VSE; 924 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 925 goto found; 926 } 927 } 928 return false; 929 930 found: 931 cs->exception_index = excp_idx; 932 env->exception.target_el = target_el; 933 cc->tcg_ops->do_interrupt(cs); 934 return true; 935 } 936 937 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 938 939 void arm_cpu_update_virq(ARMCPU *cpu) 940 { 941 /* 942 * Update the interrupt level for VIRQ, which is the logical OR of 943 * the HCR_EL2.VI bit and the input line level from the GIC. 944 */ 945 CPUARMState *env = &cpu->env; 946 CPUState *cs = CPU(cpu); 947 948 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 949 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 950 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 951 952 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 953 if (new_state) { 954 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 955 } else { 956 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 957 } 958 } 959 } 960 961 void arm_cpu_update_vfiq(ARMCPU *cpu) 962 { 963 /* 964 * Update the interrupt level for VFIQ, which is the logical OR of 965 * the HCR_EL2.VF bit and the input line level from the GIC. 966 */ 967 CPUARMState *env = &cpu->env; 968 CPUState *cs = CPU(cpu); 969 970 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) && 971 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || 972 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 973 974 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 975 if (new_state) { 976 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 977 } else { 978 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 979 } 980 } 981 } 982 983 void arm_cpu_update_vinmi(ARMCPU *cpu) 984 { 985 /* 986 * Update the interrupt level for VINMI, which is the logical OR of 987 * the HCRX_EL2.VINMI bit and the input line level from the GIC. 988 */ 989 CPUARMState *env = &cpu->env; 990 CPUState *cs = CPU(cpu); 991 992 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 993 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 994 (env->irq_line_state & CPU_INTERRUPT_VINMI); 995 996 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) { 997 if (new_state) { 998 cpu_interrupt(cs, CPU_INTERRUPT_VINMI); 999 } else { 1000 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI); 1001 } 1002 } 1003 } 1004 1005 void arm_cpu_update_vfnmi(ARMCPU *cpu) 1006 { 1007 /* 1008 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit. 1009 */ 1010 CPUARMState *env = &cpu->env; 1011 CPUState *cs = CPU(cpu); 1012 1013 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) && 1014 (arm_hcrx_el2_eff(env) & HCRX_VFNMI); 1015 1016 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) { 1017 if (new_state) { 1018 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); 1019 } else { 1020 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI); 1021 } 1022 } 1023 } 1024 1025 void arm_cpu_update_vserr(ARMCPU *cpu) 1026 { 1027 /* 1028 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 1029 */ 1030 CPUARMState *env = &cpu->env; 1031 CPUState *cs = CPU(cpu); 1032 1033 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 1034 1035 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 1036 if (new_state) { 1037 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 1038 } else { 1039 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 1040 } 1041 } 1042 } 1043 1044 #ifndef CONFIG_USER_ONLY 1045 static void arm_cpu_set_irq(void *opaque, int irq, int level) 1046 { 1047 ARMCPU *cpu = opaque; 1048 CPUARMState *env = &cpu->env; 1049 CPUState *cs = CPU(cpu); 1050 static const int mask[] = { 1051 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 1052 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 1053 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 1054 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ, 1055 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI, 1056 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI, 1057 }; 1058 1059 if (!arm_feature(env, ARM_FEATURE_EL2) && 1060 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 1061 /* 1062 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 1063 * have EL2 support we don't care. (Unless the guest is doing something 1064 * silly this will only be calls saying "level is still 0".) 1065 */ 1066 return; 1067 } 1068 1069 if (level) { 1070 env->irq_line_state |= mask[irq]; 1071 } else { 1072 env->irq_line_state &= ~mask[irq]; 1073 } 1074 1075 switch (irq) { 1076 case ARM_CPU_VIRQ: 1077 arm_cpu_update_virq(cpu); 1078 break; 1079 case ARM_CPU_VFIQ: 1080 arm_cpu_update_vfiq(cpu); 1081 break; 1082 case ARM_CPU_VINMI: 1083 arm_cpu_update_vinmi(cpu); 1084 break; 1085 case ARM_CPU_IRQ: 1086 case ARM_CPU_FIQ: 1087 case ARM_CPU_NMI: 1088 if (level) { 1089 cpu_interrupt(cs, mask[irq]); 1090 } else { 1091 cpu_reset_interrupt(cs, mask[irq]); 1092 } 1093 break; 1094 default: 1095 g_assert_not_reached(); 1096 } 1097 } 1098 1099 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 1100 { 1101 #ifdef CONFIG_KVM 1102 ARMCPU *cpu = opaque; 1103 CPUARMState *env = &cpu->env; 1104 CPUState *cs = CPU(cpu); 1105 uint32_t linestate_bit; 1106 int irq_id; 1107 1108 switch (irq) { 1109 case ARM_CPU_IRQ: 1110 irq_id = KVM_ARM_IRQ_CPU_IRQ; 1111 linestate_bit = CPU_INTERRUPT_HARD; 1112 break; 1113 case ARM_CPU_FIQ: 1114 irq_id = KVM_ARM_IRQ_CPU_FIQ; 1115 linestate_bit = CPU_INTERRUPT_FIQ; 1116 break; 1117 default: 1118 g_assert_not_reached(); 1119 } 1120 1121 if (level) { 1122 env->irq_line_state |= linestate_bit; 1123 } else { 1124 env->irq_line_state &= ~linestate_bit; 1125 } 1126 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 1127 #endif 1128 } 1129 1130 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 1131 { 1132 ARMCPU *cpu = ARM_CPU(cs); 1133 CPUARMState *env = &cpu->env; 1134 1135 cpu_synchronize_state(cs); 1136 return arm_cpu_data_is_big_endian(env); 1137 } 1138 1139 #ifdef CONFIG_TCG 1140 bool arm_cpu_exec_halt(CPUState *cs) 1141 { 1142 bool leave_halt = cpu_has_work(cs); 1143 1144 if (leave_halt) { 1145 /* We're about to come out of WFI/WFE: disable the WFxT timer */ 1146 ARMCPU *cpu = ARM_CPU(cs); 1147 if (cpu->wfxt_timer) { 1148 timer_del(cpu->wfxt_timer); 1149 } 1150 } 1151 return leave_halt; 1152 } 1153 #endif 1154 1155 static void arm_wfxt_timer_cb(void *opaque) 1156 { 1157 ARMCPU *cpu = opaque; 1158 CPUState *cs = CPU(cpu); 1159 1160 /* 1161 * We expect the CPU to be halted; this will cause arm_cpu_is_work() 1162 * to return true (so we will come out of halt even with no other 1163 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt() 1164 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. 1165 */ 1166 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 1167 } 1168 #endif 1169 1170 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 1171 { 1172 ARMCPU *ac = ARM_CPU(cpu); 1173 CPUARMState *env = &ac->env; 1174 bool sctlr_b; 1175 1176 if (is_a64(env)) { 1177 info->cap_arch = CS_ARCH_ARM64; 1178 info->cap_insn_unit = 4; 1179 info->cap_insn_split = 4; 1180 } else { 1181 int cap_mode; 1182 if (env->thumb) { 1183 info->cap_insn_unit = 2; 1184 info->cap_insn_split = 4; 1185 cap_mode = CS_MODE_THUMB; 1186 } else { 1187 info->cap_insn_unit = 4; 1188 info->cap_insn_split = 4; 1189 cap_mode = CS_MODE_ARM; 1190 } 1191 if (arm_feature(env, ARM_FEATURE_V8)) { 1192 cap_mode |= CS_MODE_V8; 1193 } 1194 if (arm_feature(env, ARM_FEATURE_M)) { 1195 cap_mode |= CS_MODE_MCLASS; 1196 } 1197 info->cap_arch = CS_ARCH_ARM; 1198 info->cap_mode = cap_mode; 1199 } 1200 1201 sctlr_b = arm_sctlr_b(env); 1202 if (bswap_code(sctlr_b)) { 1203 #if TARGET_BIG_ENDIAN 1204 info->endian = BFD_ENDIAN_LITTLE; 1205 #else 1206 info->endian = BFD_ENDIAN_BIG; 1207 #endif 1208 } 1209 info->flags &= ~INSN_ARM_BE32; 1210 #ifndef CONFIG_USER_ONLY 1211 if (sctlr_b) { 1212 info->flags |= INSN_ARM_BE32; 1213 } 1214 #endif 1215 } 1216 1217 #ifdef TARGET_AARCH64 1218 1219 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1220 { 1221 ARMCPU *cpu = ARM_CPU(cs); 1222 CPUARMState *env = &cpu->env; 1223 uint32_t psr = pstate_read(env); 1224 int i, j; 1225 int el = arm_current_el(env); 1226 uint64_t hcr = arm_hcr_el2_eff(env); 1227 const char *ns_status; 1228 bool sve; 1229 1230 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 1231 for (i = 0; i < 32; i++) { 1232 if (i == 31) { 1233 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 1234 } else { 1235 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 1236 (i + 2) % 3 ? " " : "\n"); 1237 } 1238 } 1239 1240 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 1241 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1242 } else { 1243 ns_status = ""; 1244 } 1245 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 1246 psr, 1247 psr & PSTATE_N ? 'N' : '-', 1248 psr & PSTATE_Z ? 'Z' : '-', 1249 psr & PSTATE_C ? 'C' : '-', 1250 psr & PSTATE_V ? 'V' : '-', 1251 ns_status, 1252 el, 1253 psr & PSTATE_SP ? 'h' : 't'); 1254 1255 if (cpu_isar_feature(aa64_sme, cpu)) { 1256 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 1257 env->svcr, 1258 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 1259 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 1260 } 1261 if (cpu_isar_feature(aa64_bti, cpu)) { 1262 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1263 } 1264 qemu_fprintf(f, "%s%s%s", 1265 (hcr & HCR_NV) ? " NV" : "", 1266 (hcr & HCR_NV1) ? " NV1" : "", 1267 (hcr & HCR_NV2) ? " NV2" : ""); 1268 if (!(flags & CPU_DUMP_FPU)) { 1269 qemu_fprintf(f, "\n"); 1270 return; 1271 } 1272 if (fp_exception_el(env, el) != 0) { 1273 qemu_fprintf(f, " FPU disabled\n"); 1274 return; 1275 } 1276 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1277 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1278 1279 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1280 sve = sme_exception_el(env, el) == 0; 1281 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1282 sve = sve_exception_el(env, el) == 0; 1283 } else { 1284 sve = false; 1285 } 1286 1287 if (sve) { 1288 int zcr_len = sve_vqm1_for_el(env, el); 1289 1290 for (i = 0; i <= FFR_PRED_NUM; i++) { 1291 bool eol; 1292 if (i == FFR_PRED_NUM) { 1293 qemu_fprintf(f, "FFR="); 1294 /* It's last, so end the line. */ 1295 eol = true; 1296 } else { 1297 qemu_fprintf(f, "P%02d=", i); 1298 switch (zcr_len) { 1299 case 0: 1300 eol = i % 8 == 7; 1301 break; 1302 case 1: 1303 eol = i % 6 == 5; 1304 break; 1305 case 2: 1306 case 3: 1307 eol = i % 3 == 2; 1308 break; 1309 default: 1310 /* More than one quadword per predicate. */ 1311 eol = true; 1312 break; 1313 } 1314 } 1315 for (j = zcr_len / 4; j >= 0; j--) { 1316 int digits; 1317 if (j * 4 + 4 <= zcr_len + 1) { 1318 digits = 16; 1319 } else { 1320 digits = (zcr_len % 4 + 1) * 4; 1321 } 1322 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1323 env->vfp.pregs[i].p[j], 1324 j ? ":" : eol ? "\n" : " "); 1325 } 1326 } 1327 1328 if (zcr_len == 0) { 1329 /* 1330 * With vl=16, there are only 37 columns per register, 1331 * so output two registers per line. 1332 */ 1333 for (i = 0; i < 32; i++) { 1334 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1335 i, env->vfp.zregs[i].d[1], 1336 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1337 } 1338 } else { 1339 for (i = 0; i < 32; i++) { 1340 qemu_fprintf(f, "Z%02d=", i); 1341 for (j = zcr_len; j >= 0; j--) { 1342 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1343 env->vfp.zregs[i].d[j * 2 + 1], 1344 env->vfp.zregs[i].d[j * 2 + 0], 1345 j ? ":" : "\n"); 1346 } 1347 } 1348 } 1349 } else { 1350 for (i = 0; i < 32; i++) { 1351 uint64_t *q = aa64_vfp_qreg(env, i); 1352 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1353 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1354 } 1355 } 1356 1357 if (cpu_isar_feature(aa64_sme, cpu) && 1358 FIELD_EX64(env->svcr, SVCR, ZA) && 1359 sme_exception_el(env, el) == 0) { 1360 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1361 int svl = (zcr_len + 1) * 16; 1362 int svl_lg10 = svl < 100 ? 2 : 3; 1363 1364 for (i = 0; i < svl; i++) { 1365 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1366 for (j = zcr_len; j >= 0; --j) { 1367 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1368 env->zarray[i].d[2 * j + 1], 1369 env->zarray[i].d[2 * j], 1370 j ? ':' : '\n'); 1371 } 1372 } 1373 } 1374 } 1375 1376 #else 1377 1378 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1379 { 1380 g_assert_not_reached(); 1381 } 1382 1383 #endif 1384 1385 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1386 { 1387 ARMCPU *cpu = ARM_CPU(cs); 1388 CPUARMState *env = &cpu->env; 1389 int i; 1390 1391 if (is_a64(env)) { 1392 aarch64_cpu_dump_state(cs, f, flags); 1393 return; 1394 } 1395 1396 for (i = 0; i < 16; i++) { 1397 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1398 if ((i % 4) == 3) { 1399 qemu_fprintf(f, "\n"); 1400 } else { 1401 qemu_fprintf(f, " "); 1402 } 1403 } 1404 1405 if (arm_feature(env, ARM_FEATURE_M)) { 1406 uint32_t xpsr = xpsr_read(env); 1407 const char *mode; 1408 const char *ns_status = ""; 1409 1410 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1411 ns_status = env->v7m.secure ? "S " : "NS "; 1412 } 1413 1414 if (xpsr & XPSR_EXCP) { 1415 mode = "handler"; 1416 } else { 1417 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1418 mode = "unpriv-thread"; 1419 } else { 1420 mode = "priv-thread"; 1421 } 1422 } 1423 1424 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1425 xpsr, 1426 xpsr & XPSR_N ? 'N' : '-', 1427 xpsr & XPSR_Z ? 'Z' : '-', 1428 xpsr & XPSR_C ? 'C' : '-', 1429 xpsr & XPSR_V ? 'V' : '-', 1430 xpsr & XPSR_T ? 'T' : 'A', 1431 ns_status, 1432 mode); 1433 } else { 1434 uint32_t psr = cpsr_read(env); 1435 const char *ns_status = ""; 1436 1437 if (arm_feature(env, ARM_FEATURE_EL3) && 1438 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1439 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1440 } 1441 1442 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1443 psr, 1444 psr & CPSR_N ? 'N' : '-', 1445 psr & CPSR_Z ? 'Z' : '-', 1446 psr & CPSR_C ? 'C' : '-', 1447 psr & CPSR_V ? 'V' : '-', 1448 psr & CPSR_T ? 'T' : 'A', 1449 ns_status, 1450 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1451 } 1452 1453 if (flags & CPU_DUMP_FPU) { 1454 int numvfpregs = 0; 1455 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1456 numvfpregs = 32; 1457 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1458 numvfpregs = 16; 1459 } 1460 for (i = 0; i < numvfpregs; i++) { 1461 uint64_t v = *aa32_vfp_dreg(env, i); 1462 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1463 i * 2, (uint32_t)v, 1464 i * 2 + 1, (uint32_t)(v >> 32), 1465 i, v); 1466 } 1467 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1468 if (cpu_isar_feature(aa32_mve, cpu)) { 1469 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1470 } 1471 } 1472 } 1473 1474 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) 1475 { 1476 uint32_t Aff1 = idx / clustersz; 1477 uint32_t Aff0 = idx % clustersz; 1478 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1479 } 1480 1481 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) 1482 { 1483 return cpu->mp_affinity; 1484 } 1485 1486 static void arm_cpu_initfn(Object *obj) 1487 { 1488 ARMCPU *cpu = ARM_CPU(obj); 1489 1490 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1491 NULL, g_free); 1492 1493 QLIST_INIT(&cpu->pre_el_change_hooks); 1494 QLIST_INIT(&cpu->el_change_hooks); 1495 1496 #ifdef CONFIG_USER_ONLY 1497 # ifdef TARGET_AARCH64 1498 /* 1499 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1500 * These values were chosen to fit within the default signal frame. 1501 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1502 * and our corresponding cpu property. 1503 */ 1504 cpu->sve_default_vq = 4; 1505 cpu->sme_default_vq = 2; 1506 # endif 1507 #else 1508 /* Our inbound IRQ and FIQ lines */ 1509 if (kvm_enabled()) { 1510 /* 1511 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add 1512 * them to maintain the same interface as non-KVM CPUs. 1513 */ 1514 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); 1515 } else { 1516 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); 1517 } 1518 1519 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1520 ARRAY_SIZE(cpu->gt_timer_outputs)); 1521 1522 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1523 "gicv3-maintenance-interrupt", 1); 1524 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1525 "pmu-interrupt", 1); 1526 #endif 1527 1528 /* DTB consumers generally don't in fact care what the 'compatible' 1529 * string is, so always provide some string and trust that a hypothetical 1530 * picky DTB consumer will also provide a helpful error message. 1531 */ 1532 cpu->dtb_compatible = "qemu,unknown"; 1533 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1534 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1535 1536 if (tcg_enabled() || hvf_enabled()) { 1537 /* TCG and HVF implement PSCI 1.1 */ 1538 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1539 } 1540 } 1541 1542 /* 1543 * 0 means "unset, use the default value". That default might vary depending 1544 * on the CPU type, and is set in the realize fn. 1545 */ 1546 static const Property arm_cpu_gt_cntfrq_property = 1547 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); 1548 1549 static const Property arm_cpu_reset_cbar_property = 1550 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1551 1552 static const Property arm_cpu_reset_hivecs_property = 1553 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1554 1555 #ifndef CONFIG_USER_ONLY 1556 static const Property arm_cpu_has_el2_property = 1557 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1558 1559 static const Property arm_cpu_has_el3_property = 1560 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1561 #endif 1562 1563 static const Property arm_cpu_cfgend_property = 1564 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1565 1566 static const Property arm_cpu_has_vfp_property = 1567 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1568 1569 static const Property arm_cpu_has_vfp_d32_property = 1570 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1571 1572 static const Property arm_cpu_has_neon_property = 1573 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1574 1575 static const Property arm_cpu_has_dsp_property = 1576 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1577 1578 static const Property arm_cpu_has_mpu_property = 1579 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1580 1581 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1582 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1583 * the right value for that particular CPU type, and we don't want 1584 * to override that with an incorrect constant value. 1585 */ 1586 static const Property arm_cpu_pmsav7_dregion_property = 1587 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1588 pmsav7_dregion, 1589 qdev_prop_uint32, uint32_t); 1590 1591 static bool arm_get_pmu(Object *obj, Error **errp) 1592 { 1593 ARMCPU *cpu = ARM_CPU(obj); 1594 1595 return cpu->has_pmu; 1596 } 1597 1598 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1599 { 1600 ARMCPU *cpu = ARM_CPU(obj); 1601 1602 if (value) { 1603 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1604 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1605 return; 1606 } 1607 set_feature(&cpu->env, ARM_FEATURE_PMU); 1608 } else { 1609 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1610 } 1611 cpu->has_pmu = value; 1612 } 1613 1614 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1615 { 1616 /* 1617 * The exact approach to calculating guest ticks is: 1618 * 1619 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1620 * NANOSECONDS_PER_SECOND); 1621 * 1622 * We don't do that. Rather we intentionally use integer division 1623 * truncation below and in the caller for the conversion of host monotonic 1624 * time to guest ticks to provide the exact inverse for the semantics of 1625 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1626 * it loses precision when representing frequencies where 1627 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1628 * provide an exact inverse leads to scheduling timers with negative 1629 * periods, which in turn leads to sticky behaviour in the guest. 1630 * 1631 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1632 * cannot become zero. 1633 */ 1634 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1635 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1636 } 1637 1638 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1639 { 1640 CPUARMState *env = &cpu->env; 1641 bool no_aa32 = false; 1642 1643 /* 1644 * Some features automatically imply others: set the feature 1645 * bits explicitly for these cases. 1646 */ 1647 1648 if (arm_feature(env, ARM_FEATURE_M)) { 1649 set_feature(env, ARM_FEATURE_PMSA); 1650 } 1651 1652 if (arm_feature(env, ARM_FEATURE_V8)) { 1653 if (arm_feature(env, ARM_FEATURE_M)) { 1654 set_feature(env, ARM_FEATURE_V7); 1655 } else { 1656 set_feature(env, ARM_FEATURE_V7VE); 1657 } 1658 } 1659 1660 /* 1661 * There exist AArch64 cpus without AArch32 support. When KVM 1662 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1663 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1664 * As a general principle, we also do not make ID register 1665 * consistency checks anywhere unless using TCG, because only 1666 * for TCG would a consistency-check failure be a QEMU bug. 1667 */ 1668 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1669 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1670 } 1671 1672 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1673 /* 1674 * v7 Virtualization Extensions. In real hardware this implies 1675 * EL2 and also the presence of the Security Extensions. 1676 * For QEMU, for backwards-compatibility we implement some 1677 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1678 * include the various other features that V7VE implies. 1679 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1680 * Security Extensions is ARM_FEATURE_EL3. 1681 */ 1682 assert(!tcg_enabled() || no_aa32 || 1683 cpu_isar_feature(aa32_arm_div, cpu)); 1684 set_feature(env, ARM_FEATURE_LPAE); 1685 set_feature(env, ARM_FEATURE_V7); 1686 } 1687 if (arm_feature(env, ARM_FEATURE_V7)) { 1688 set_feature(env, ARM_FEATURE_VAPA); 1689 set_feature(env, ARM_FEATURE_THUMB2); 1690 set_feature(env, ARM_FEATURE_MPIDR); 1691 if (!arm_feature(env, ARM_FEATURE_M)) { 1692 set_feature(env, ARM_FEATURE_V6K); 1693 } else { 1694 set_feature(env, ARM_FEATURE_V6); 1695 } 1696 1697 /* 1698 * Always define VBAR for V7 CPUs even if it doesn't exist in 1699 * non-EL3 configs. This is needed by some legacy boards. 1700 */ 1701 set_feature(env, ARM_FEATURE_VBAR); 1702 } 1703 if (arm_feature(env, ARM_FEATURE_V6K)) { 1704 set_feature(env, ARM_FEATURE_V6); 1705 set_feature(env, ARM_FEATURE_MVFR); 1706 } 1707 if (arm_feature(env, ARM_FEATURE_V6)) { 1708 set_feature(env, ARM_FEATURE_V5); 1709 if (!arm_feature(env, ARM_FEATURE_M)) { 1710 assert(!tcg_enabled() || no_aa32 || 1711 cpu_isar_feature(aa32_jazelle, cpu)); 1712 set_feature(env, ARM_FEATURE_AUXCR); 1713 } 1714 } 1715 if (arm_feature(env, ARM_FEATURE_V5)) { 1716 set_feature(env, ARM_FEATURE_V4T); 1717 } 1718 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1719 set_feature(env, ARM_FEATURE_V7MP); 1720 } 1721 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1722 set_feature(env, ARM_FEATURE_CBAR); 1723 } 1724 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1725 !arm_feature(env, ARM_FEATURE_M)) { 1726 set_feature(env, ARM_FEATURE_THUMB_DSP); 1727 } 1728 } 1729 1730 void arm_cpu_post_init(Object *obj) 1731 { 1732 ARMCPU *cpu = ARM_CPU(obj); 1733 1734 /* 1735 * Some features imply others. Figure this out now, because we 1736 * are going to look at the feature bits in deciding which 1737 * properties to add. 1738 */ 1739 arm_cpu_propagate_feature_implications(cpu); 1740 1741 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1742 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1743 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1744 } 1745 1746 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1747 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1748 } 1749 1750 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1751 object_property_add_uint64_ptr(obj, "rvbar", 1752 &cpu->rvbar_prop, 1753 OBJ_PROP_FLAG_READWRITE); 1754 } 1755 1756 #ifndef CONFIG_USER_ONLY 1757 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1758 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1759 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1760 */ 1761 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1762 1763 object_property_add_link(obj, "secure-memory", 1764 TYPE_MEMORY_REGION, 1765 (Object **)&cpu->secure_memory, 1766 qdev_prop_allow_set_link_before_realize, 1767 OBJ_PROP_LINK_STRONG); 1768 } 1769 1770 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1771 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1772 } 1773 #endif 1774 1775 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1776 cpu->has_pmu = true; 1777 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1778 } 1779 1780 /* 1781 * Allow user to turn off VFP and Neon support, but only for TCG -- 1782 * KVM does not currently allow us to lie to the guest about its 1783 * ID/feature registers, so the guest always sees what the host has. 1784 */ 1785 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1786 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1787 cpu->has_vfp = true; 1788 cpu->has_vfp_d32 = true; 1789 if (tcg_enabled() || qtest_enabled()) { 1790 qdev_property_add_static(DEVICE(obj), 1791 &arm_cpu_has_vfp_property); 1792 } 1793 } 1794 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1795 cpu->has_vfp = true; 1796 if (tcg_enabled() || qtest_enabled()) { 1797 qdev_property_add_static(DEVICE(obj), 1798 &arm_cpu_has_vfp_property); 1799 } 1800 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1801 cpu->has_vfp_d32 = true; 1802 /* 1803 * The permitted values of the SIMDReg bits [3:0] on 1804 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1805 * make sure that has_vfp_d32 can not be set to false. 1806 */ 1807 if ((tcg_enabled() || qtest_enabled()) 1808 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1809 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1810 qdev_property_add_static(DEVICE(obj), 1811 &arm_cpu_has_vfp_d32_property); 1812 } 1813 } 1814 } 1815 1816 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1817 cpu->has_neon = true; 1818 if (!kvm_enabled()) { 1819 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1820 } 1821 } 1822 1823 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1824 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1825 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1826 } 1827 1828 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1829 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1830 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1831 qdev_property_add_static(DEVICE(obj), 1832 &arm_cpu_pmsav7_dregion_property); 1833 } 1834 } 1835 1836 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1837 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1838 qdev_prop_allow_set_link_before_realize, 1839 OBJ_PROP_LINK_STRONG); 1840 /* 1841 * M profile: initial value of the Secure VTOR. We can't just use 1842 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1843 * the property to be set after realize. 1844 */ 1845 object_property_add_uint32_ptr(obj, "init-svtor", 1846 &cpu->init_svtor, 1847 OBJ_PROP_FLAG_READWRITE); 1848 } 1849 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1850 /* 1851 * Initial value of the NS VTOR (for cores without the Security 1852 * extension, this is the only VTOR) 1853 */ 1854 object_property_add_uint32_ptr(obj, "init-nsvtor", 1855 &cpu->init_nsvtor, 1856 OBJ_PROP_FLAG_READWRITE); 1857 } 1858 1859 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1860 object_property_add_uint32_ptr(obj, "psci-conduit", 1861 &cpu->psci_conduit, 1862 OBJ_PROP_FLAG_READWRITE); 1863 1864 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1865 1866 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1867 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1868 } 1869 1870 if (kvm_enabled()) { 1871 kvm_arm_add_vcpu_properties(cpu); 1872 } 1873 1874 #ifndef CONFIG_USER_ONLY 1875 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1876 cpu_isar_feature(aa64_mte, cpu)) { 1877 object_property_add_link(obj, "tag-memory", 1878 TYPE_MEMORY_REGION, 1879 (Object **)&cpu->tag_memory, 1880 qdev_prop_allow_set_link_before_realize, 1881 OBJ_PROP_LINK_STRONG); 1882 1883 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1884 object_property_add_link(obj, "secure-tag-memory", 1885 TYPE_MEMORY_REGION, 1886 (Object **)&cpu->secure_tag_memory, 1887 qdev_prop_allow_set_link_before_realize, 1888 OBJ_PROP_LINK_STRONG); 1889 } 1890 } 1891 #endif 1892 } 1893 1894 static void arm_cpu_finalizefn(Object *obj) 1895 { 1896 ARMCPU *cpu = ARM_CPU(obj); 1897 ARMELChangeHook *hook, *next; 1898 1899 g_hash_table_destroy(cpu->cp_regs); 1900 1901 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1902 QLIST_REMOVE(hook, node); 1903 g_free(hook); 1904 } 1905 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1906 QLIST_REMOVE(hook, node); 1907 g_free(hook); 1908 } 1909 #ifndef CONFIG_USER_ONLY 1910 if (cpu->pmu_timer) { 1911 timer_free(cpu->pmu_timer); 1912 } 1913 if (cpu->wfxt_timer) { 1914 timer_free(cpu->wfxt_timer); 1915 } 1916 #endif 1917 } 1918 1919 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1920 { 1921 Error *local_err = NULL; 1922 1923 #ifdef TARGET_AARCH64 1924 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1925 arm_cpu_sve_finalize(cpu, &local_err); 1926 if (local_err != NULL) { 1927 error_propagate(errp, local_err); 1928 return; 1929 } 1930 1931 /* 1932 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless 1933 * FEAT_SME_FA64 is present). However our implementation currently 1934 * assumes it, so if the user asked for sve=off then turn off SME also. 1935 * (KVM doesn't currently support SME at all.) 1936 */ 1937 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) { 1938 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort); 1939 } 1940 1941 arm_cpu_sme_finalize(cpu, &local_err); 1942 if (local_err != NULL) { 1943 error_propagate(errp, local_err); 1944 return; 1945 } 1946 1947 arm_cpu_pauth_finalize(cpu, &local_err); 1948 if (local_err != NULL) { 1949 error_propagate(errp, local_err); 1950 return; 1951 } 1952 1953 arm_cpu_lpa2_finalize(cpu, &local_err); 1954 if (local_err != NULL) { 1955 error_propagate(errp, local_err); 1956 return; 1957 } 1958 } 1959 #endif 1960 1961 if (kvm_enabled()) { 1962 kvm_arm_steal_time_finalize(cpu, &local_err); 1963 if (local_err != NULL) { 1964 error_propagate(errp, local_err); 1965 return; 1966 } 1967 } 1968 } 1969 1970 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1971 { 1972 CPUState *cs = CPU(dev); 1973 ARMCPU *cpu = ARM_CPU(dev); 1974 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1975 CPUARMState *env = &cpu->env; 1976 Error *local_err = NULL; 1977 1978 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 1979 /* Use pc-relative instructions in system-mode */ 1980 tcg_cflags_set(cs, CF_PCREL); 1981 #endif 1982 1983 /* If we needed to query the host kernel for the CPU features 1984 * then it's possible that might have failed in the initfn, but 1985 * this is the first point where we can report it. 1986 */ 1987 if (cpu->host_cpu_probe_failed) { 1988 if (!kvm_enabled() && !hvf_enabled()) { 1989 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1990 } else { 1991 error_setg(errp, "Failed to retrieve host CPU features"); 1992 } 1993 return; 1994 } 1995 1996 if (!cpu->gt_cntfrq_hz) { 1997 /* 1998 * 0 means "the board didn't set a value, use the default". (We also 1999 * get here for the CONFIG_USER_ONLY case.) 2000 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before 2001 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, 2002 * which gives a 16ns tick period. 2003 * 2004 * We will use the back-compat value: 2005 * - for QEMU CPU types added before we standardized on 1GHz 2006 * - for versioned machine types with a version of 9.0 or earlier 2007 */ 2008 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || 2009 cpu->backcompat_cntfrq) { 2010 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; 2011 } else { 2012 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; 2013 } 2014 } 2015 2016 #ifndef CONFIG_USER_ONLY 2017 /* The NVIC and M-profile CPU are two halves of a single piece of 2018 * hardware; trying to use one without the other is a command line 2019 * error and will result in segfaults if not caught here. 2020 */ 2021 if (arm_feature(env, ARM_FEATURE_M)) { 2022 if (!env->nvic) { 2023 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 2024 return; 2025 } 2026 } else { 2027 if (env->nvic) { 2028 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 2029 return; 2030 } 2031 } 2032 2033 if (!tcg_enabled() && !qtest_enabled()) { 2034 /* 2035 * We assume that no accelerator except TCG (and the "not really an 2036 * accelerator" qtest) can handle these features, because Arm hardware 2037 * virtualization can't virtualize them. 2038 * 2039 * Catch all the cases which might cause us to create more than one 2040 * address space for the CPU (otherwise we will assert() later in 2041 * cpu_address_space_init()). 2042 */ 2043 if (arm_feature(env, ARM_FEATURE_M)) { 2044 error_setg(errp, 2045 "Cannot enable %s when using an M-profile guest CPU", 2046 current_accel_name()); 2047 return; 2048 } 2049 if (cpu->has_el3) { 2050 error_setg(errp, 2051 "Cannot enable %s when guest CPU has EL3 enabled", 2052 current_accel_name()); 2053 return; 2054 } 2055 if (cpu->tag_memory) { 2056 error_setg(errp, 2057 "Cannot enable %s when guest CPUs has MTE enabled", 2058 current_accel_name()); 2059 return; 2060 } 2061 } 2062 2063 { 2064 uint64_t scale = gt_cntfrq_period_ns(cpu); 2065 2066 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2067 arm_gt_ptimer_cb, cpu); 2068 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2069 arm_gt_vtimer_cb, cpu); 2070 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2071 arm_gt_htimer_cb, cpu); 2072 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2073 arm_gt_stimer_cb, cpu); 2074 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2075 arm_gt_hvtimer_cb, cpu); 2076 } 2077 #endif 2078 2079 cpu_exec_realizefn(cs, &local_err); 2080 if (local_err != NULL) { 2081 error_propagate(errp, local_err); 2082 return; 2083 } 2084 2085 arm_cpu_finalize_features(cpu, &local_err); 2086 if (local_err != NULL) { 2087 error_propagate(errp, local_err); 2088 return; 2089 } 2090 2091 #ifdef CONFIG_USER_ONLY 2092 /* 2093 * User mode relies on IC IVAU instructions to catch modification of 2094 * dual-mapped code. 2095 * 2096 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 2097 * IC IVAU even if the emulated processor does not normally require it. 2098 */ 2099 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 2100 #endif 2101 2102 if (arm_feature(env, ARM_FEATURE_AARCH64) && 2103 cpu->has_vfp != cpu->has_neon) { 2104 /* 2105 * This is an architectural requirement for AArch64; AArch32 is 2106 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 2107 */ 2108 error_setg(errp, 2109 "AArch64 CPUs must have both VFP and Neon or neither"); 2110 return; 2111 } 2112 2113 if (cpu->has_vfp_d32 != cpu->has_neon) { 2114 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 2115 return; 2116 } 2117 2118 if (!cpu->has_vfp_d32) { 2119 uint32_t u; 2120 2121 u = cpu->isar.mvfr0; 2122 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 2123 cpu->isar.mvfr0 = u; 2124 } 2125 2126 if (!cpu->has_vfp) { 2127 uint64_t t; 2128 uint32_t u; 2129 2130 t = cpu->isar.id_aa64isar1; 2131 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 2132 cpu->isar.id_aa64isar1 = t; 2133 2134 t = cpu->isar.id_aa64pfr0; 2135 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 2136 cpu->isar.id_aa64pfr0 = t; 2137 2138 u = cpu->isar.id_isar6; 2139 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 2140 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2141 cpu->isar.id_isar6 = u; 2142 2143 u = cpu->isar.mvfr0; 2144 u = FIELD_DP32(u, MVFR0, FPSP, 0); 2145 u = FIELD_DP32(u, MVFR0, FPDP, 0); 2146 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 2147 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 2148 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 2149 if (!arm_feature(env, ARM_FEATURE_M)) { 2150 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 2151 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 2152 } 2153 cpu->isar.mvfr0 = u; 2154 2155 u = cpu->isar.mvfr1; 2156 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 2157 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 2158 u = FIELD_DP32(u, MVFR1, FPHP, 0); 2159 if (arm_feature(env, ARM_FEATURE_M)) { 2160 u = FIELD_DP32(u, MVFR1, FP16, 0); 2161 } 2162 cpu->isar.mvfr1 = u; 2163 2164 u = cpu->isar.mvfr2; 2165 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 2166 cpu->isar.mvfr2 = u; 2167 } 2168 2169 if (!cpu->has_neon) { 2170 uint64_t t; 2171 uint32_t u; 2172 2173 unset_feature(env, ARM_FEATURE_NEON); 2174 2175 t = cpu->isar.id_aa64isar0; 2176 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 2177 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 2178 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 2179 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 2180 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 2181 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 2182 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 2183 cpu->isar.id_aa64isar0 = t; 2184 2185 t = cpu->isar.id_aa64isar1; 2186 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 2187 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 2188 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 2189 cpu->isar.id_aa64isar1 = t; 2190 2191 t = cpu->isar.id_aa64pfr0; 2192 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 2193 cpu->isar.id_aa64pfr0 = t; 2194 2195 u = cpu->isar.id_isar5; 2196 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 2197 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 2198 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 2199 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 2200 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 2201 cpu->isar.id_isar5 = u; 2202 2203 u = cpu->isar.id_isar6; 2204 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 2205 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 2206 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2207 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 2208 cpu->isar.id_isar6 = u; 2209 2210 if (!arm_feature(env, ARM_FEATURE_M)) { 2211 u = cpu->isar.mvfr1; 2212 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 2213 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 2214 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 2215 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 2216 cpu->isar.mvfr1 = u; 2217 2218 u = cpu->isar.mvfr2; 2219 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 2220 cpu->isar.mvfr2 = u; 2221 } 2222 } 2223 2224 if (!cpu->has_neon && !cpu->has_vfp) { 2225 uint64_t t; 2226 uint32_t u; 2227 2228 t = cpu->isar.id_aa64isar0; 2229 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 2230 cpu->isar.id_aa64isar0 = t; 2231 2232 t = cpu->isar.id_aa64isar1; 2233 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 2234 cpu->isar.id_aa64isar1 = t; 2235 2236 u = cpu->isar.mvfr0; 2237 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 2238 cpu->isar.mvfr0 = u; 2239 2240 /* Despite the name, this field covers both VFP and Neon */ 2241 u = cpu->isar.mvfr1; 2242 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 2243 cpu->isar.mvfr1 = u; 2244 } 2245 2246 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 2247 uint32_t u; 2248 2249 unset_feature(env, ARM_FEATURE_THUMB_DSP); 2250 2251 u = cpu->isar.id_isar1; 2252 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 2253 cpu->isar.id_isar1 = u; 2254 2255 u = cpu->isar.id_isar2; 2256 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 2257 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 2258 cpu->isar.id_isar2 = u; 2259 2260 u = cpu->isar.id_isar3; 2261 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 2262 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 2263 cpu->isar.id_isar3 = u; 2264 } 2265 2266 2267 /* 2268 * We rely on no XScale CPU having VFP so we can use the same bits in the 2269 * TB flags field for VECSTRIDE and XSCALE_CPAR. 2270 */ 2271 assert(arm_feature(env, ARM_FEATURE_AARCH64) || 2272 !cpu_isar_feature(aa32_vfp_simd, cpu) || 2273 !arm_feature(env, ARM_FEATURE_XSCALE)); 2274 2275 #ifndef CONFIG_USER_ONLY 2276 { 2277 int pagebits; 2278 if (arm_feature(env, ARM_FEATURE_V7) && 2279 !arm_feature(env, ARM_FEATURE_M) && 2280 !arm_feature(env, ARM_FEATURE_PMSA)) { 2281 /* 2282 * v7VMSA drops support for the old ARMv5 tiny pages, 2283 * so we can use 4K pages. 2284 */ 2285 pagebits = 12; 2286 } else { 2287 /* 2288 * For CPUs which might have tiny 1K pages, or which have an 2289 * MPU and might have small region sizes, stick with 1K pages. 2290 */ 2291 pagebits = 10; 2292 } 2293 if (!set_preferred_target_page_bits(pagebits)) { 2294 /* 2295 * This can only ever happen for hotplugging a CPU, or if 2296 * the board code incorrectly creates a CPU which it has 2297 * promised via minimum_page_size that it will not. 2298 */ 2299 error_setg(errp, "This CPU requires a smaller page size " 2300 "than the system is using"); 2301 return; 2302 } 2303 } 2304 #endif 2305 2306 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 2307 * We don't support setting cluster ID ([16..23]) (known as Aff2 2308 * in later ARM ARM versions), or any of the higher affinity level fields, 2309 * so these bits always RAZ. 2310 */ 2311 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2312 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, 2313 ARM_DEFAULT_CPUS_PER_CLUSTER); 2314 } 2315 2316 if (cpu->reset_hivecs) { 2317 cpu->reset_sctlr |= (1 << 13); 2318 } 2319 2320 if (cpu->cfgend) { 2321 if (arm_feature(env, ARM_FEATURE_V7)) { 2322 cpu->reset_sctlr |= SCTLR_EE; 2323 } else { 2324 cpu->reset_sctlr |= SCTLR_B; 2325 } 2326 } 2327 2328 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2329 /* If the has_el3 CPU property is disabled then we need to disable the 2330 * feature. 2331 */ 2332 unset_feature(env, ARM_FEATURE_EL3); 2333 2334 /* 2335 * Disable the security extension feature bits in the processor 2336 * feature registers as well. 2337 */ 2338 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 2339 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 2340 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2341 ID_AA64PFR0, EL3, 0); 2342 2343 /* Disable the realm management extension, which requires EL3. */ 2344 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2345 ID_AA64PFR0, RME, 0); 2346 } 2347 2348 if (!cpu->has_el2) { 2349 unset_feature(env, ARM_FEATURE_EL2); 2350 } 2351 2352 if (!cpu->has_pmu) { 2353 unset_feature(env, ARM_FEATURE_PMU); 2354 } 2355 if (arm_feature(env, ARM_FEATURE_PMU)) { 2356 pmu_init(cpu); 2357 2358 if (!kvm_enabled()) { 2359 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2360 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2361 } 2362 2363 #ifndef CONFIG_USER_ONLY 2364 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2365 cpu); 2366 #endif 2367 } else { 2368 cpu->isar.id_aa64dfr0 = 2369 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 2370 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 2371 cpu->pmceid0 = 0; 2372 cpu->pmceid1 = 0; 2373 } 2374 2375 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2376 /* 2377 * Disable the hypervisor feature bits in the processor feature 2378 * registers if we don't have EL2. 2379 */ 2380 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2381 ID_AA64PFR0, EL2, 0); 2382 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 2383 ID_PFR1, VIRTUALIZATION, 0); 2384 } 2385 2386 if (cpu_isar_feature(aa64_mte, cpu)) { 2387 /* 2388 * The architectural range of GM blocksize is 2-6, however qemu 2389 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2390 */ 2391 if (tcg_enabled()) { 2392 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2393 } 2394 2395 #ifndef CONFIG_USER_ONLY 2396 /* 2397 * If we run with TCG and do not have tag-memory provided by 2398 * the machine, then reduce MTE support to instructions enabled at EL0. 2399 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2400 */ 2401 if (tcg_enabled() && cpu->tag_memory == NULL) { 2402 cpu->isar.id_aa64pfr1 = 2403 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); 2404 } 2405 2406 /* 2407 * If MTE is supported by the host, however it should not be 2408 * enabled on the guest (i.e mte=off), clear guest's MTE bits." 2409 */ 2410 if (kvm_enabled() && !cpu->kvm_mte) { 2411 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 2412 } 2413 #endif 2414 } 2415 2416 #ifndef CONFIG_USER_ONLY 2417 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) { 2418 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2419 arm_wfxt_timer_cb, cpu); 2420 } 2421 #endif 2422 2423 if (tcg_enabled()) { 2424 /* 2425 * Don't report some architectural features in the ID registers 2426 * where TCG does not yet implement it (not even a minimal 2427 * stub version). This avoids guests falling over when they 2428 * try to access the non-existent system registers for them. 2429 */ 2430 /* FEAT_SPE (Statistical Profiling Extension) */ 2431 cpu->isar.id_aa64dfr0 = 2432 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2433 /* FEAT_TRBE (Trace Buffer Extension) */ 2434 cpu->isar.id_aa64dfr0 = 2435 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); 2436 /* FEAT_TRF (Self-hosted Trace Extension) */ 2437 cpu->isar.id_aa64dfr0 = 2438 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2439 cpu->isar.id_dfr0 = 2440 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2441 /* Trace Macrocell system register access */ 2442 cpu->isar.id_aa64dfr0 = 2443 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2444 cpu->isar.id_dfr0 = 2445 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2446 /* Memory mapped trace */ 2447 cpu->isar.id_dfr0 = 2448 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2449 /* FEAT_AMU (Activity Monitors Extension) */ 2450 cpu->isar.id_aa64pfr0 = 2451 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2452 cpu->isar.id_pfr0 = 2453 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2454 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2455 cpu->isar.id_aa64pfr0 = 2456 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2457 } 2458 2459 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2460 * to false or by setting pmsav7-dregion to 0. 2461 */ 2462 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2463 cpu->has_mpu = false; 2464 cpu->pmsav7_dregion = 0; 2465 cpu->pmsav8r_hdregion = 0; 2466 } 2467 2468 if (arm_feature(env, ARM_FEATURE_PMSA) && 2469 arm_feature(env, ARM_FEATURE_V7)) { 2470 uint32_t nr = cpu->pmsav7_dregion; 2471 2472 if (nr > 0xff) { 2473 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2474 return; 2475 } 2476 2477 if (nr) { 2478 if (arm_feature(env, ARM_FEATURE_V8)) { 2479 /* PMSAv8 */ 2480 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2481 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2482 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2483 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2484 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2485 } 2486 } else { 2487 env->pmsav7.drbar = g_new0(uint32_t, nr); 2488 env->pmsav7.drsr = g_new0(uint32_t, nr); 2489 env->pmsav7.dracr = g_new0(uint32_t, nr); 2490 } 2491 } 2492 2493 if (cpu->pmsav8r_hdregion > 0xff) { 2494 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2495 cpu->pmsav8r_hdregion); 2496 return; 2497 } 2498 2499 if (cpu->pmsav8r_hdregion) { 2500 env->pmsav8.hprbar = g_new0(uint32_t, 2501 cpu->pmsav8r_hdregion); 2502 env->pmsav8.hprlar = g_new0(uint32_t, 2503 cpu->pmsav8r_hdregion); 2504 } 2505 } 2506 2507 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2508 uint32_t nr = cpu->sau_sregion; 2509 2510 if (nr > 0xff) { 2511 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2512 return; 2513 } 2514 2515 if (nr) { 2516 env->sau.rbar = g_new0(uint32_t, nr); 2517 env->sau.rlar = g_new0(uint32_t, nr); 2518 } 2519 } 2520 2521 if (arm_feature(env, ARM_FEATURE_EL3)) { 2522 set_feature(env, ARM_FEATURE_VBAR); 2523 } 2524 2525 #ifndef CONFIG_USER_ONLY 2526 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2527 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2528 } 2529 #endif 2530 2531 register_cp_regs_for_features(cpu); 2532 arm_cpu_register_gdb_regs_for_features(cpu); 2533 arm_cpu_register_gdb_commands(cpu); 2534 2535 init_cpreg_list(cpu); 2536 2537 #ifndef CONFIG_USER_ONLY 2538 MachineState *ms = MACHINE(qdev_get_machine()); 2539 unsigned int smp_cpus = ms->smp.cpus; 2540 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2541 2542 /* 2543 * We must set cs->num_ases to the final value before 2544 * the first call to cpu_address_space_init. 2545 */ 2546 if (cpu->tag_memory != NULL) { 2547 cs->num_ases = 3 + has_secure; 2548 } else { 2549 cs->num_ases = 1 + has_secure; 2550 } 2551 2552 if (has_secure) { 2553 if (!cpu->secure_memory) { 2554 cpu->secure_memory = cs->memory; 2555 } 2556 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2557 cpu->secure_memory); 2558 } 2559 2560 if (cpu->tag_memory != NULL) { 2561 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2562 cpu->tag_memory); 2563 if (has_secure) { 2564 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2565 cpu->secure_tag_memory); 2566 } 2567 } 2568 2569 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2570 2571 /* No core_count specified, default to smp_cpus. */ 2572 if (cpu->core_count == -1) { 2573 cpu->core_count = smp_cpus; 2574 } 2575 #endif 2576 2577 if (tcg_enabled()) { 2578 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2579 2580 /* 2581 * We only support DCZ blocklen that fits on one page. 2582 * 2583 * Architectually this is always true. However TARGET_PAGE_SIZE 2584 * is variable and, for compatibility with -machine virt-2.7, 2585 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2586 * But even then, while the largest architectural DCZ blocklen 2587 * is 2KiB, no cpu actually uses such a large blocklen. 2588 */ 2589 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2590 2591 /* 2592 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2593 * both nibbles of each byte storing tag data may be written at once. 2594 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2595 */ 2596 if (cpu_isar_feature(aa64_mte, cpu)) { 2597 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2598 } 2599 } 2600 2601 qemu_init_vcpu(cs); 2602 cpu_reset(cs); 2603 2604 acc->parent_realize(dev, errp); 2605 } 2606 2607 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2608 { 2609 ObjectClass *oc; 2610 char *typename; 2611 char **cpuname; 2612 const char *cpunamestr; 2613 2614 cpuname = g_strsplit(cpu_model, ",", 1); 2615 cpunamestr = cpuname[0]; 2616 #ifdef CONFIG_USER_ONLY 2617 /* For backwards compatibility usermode emulation allows "-cpu any", 2618 * which has the same semantics as "-cpu max". 2619 */ 2620 if (!strcmp(cpunamestr, "any")) { 2621 cpunamestr = "max"; 2622 } 2623 #endif 2624 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2625 oc = object_class_by_name(typename); 2626 g_strfreev(cpuname); 2627 g_free(typename); 2628 2629 return oc; 2630 } 2631 2632 static const Property arm_cpu_properties[] = { 2633 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2634 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2635 mp_affinity, ARM64_AFFINITY_INVALID), 2636 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2637 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2638 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ 2639 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), 2640 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, 2641 backcompat_pauth_default_use_qarma5, false), 2642 }; 2643 2644 static const gchar *arm_gdb_arch_name(CPUState *cs) 2645 { 2646 ARMCPU *cpu = ARM_CPU(cs); 2647 CPUARMState *env = &cpu->env; 2648 2649 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2650 return "iwmmxt"; 2651 } 2652 return "arm"; 2653 } 2654 2655 #ifndef CONFIG_USER_ONLY 2656 #include "hw/core/sysemu-cpu-ops.h" 2657 2658 static const struct SysemuCPUOps arm_sysemu_ops = { 2659 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2660 .asidx_from_attrs = arm_asidx_from_attrs, 2661 .write_elf32_note = arm_cpu_write_elf32_note, 2662 .write_elf64_note = arm_cpu_write_elf64_note, 2663 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2664 .legacy_vmsd = &vmstate_arm_cpu, 2665 }; 2666 #endif 2667 2668 #ifdef CONFIG_TCG 2669 static const TCGCPUOps arm_tcg_ops = { 2670 .initialize = arm_translate_init, 2671 .translate_code = arm_translate_code, 2672 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2673 .debug_excp_handler = arm_debug_excp_handler, 2674 .restore_state_to_opc = arm_restore_state_to_opc, 2675 2676 #ifdef CONFIG_USER_ONLY 2677 .record_sigsegv = arm_cpu_record_sigsegv, 2678 .record_sigbus = arm_cpu_record_sigbus, 2679 #else 2680 .tlb_fill_align = arm_cpu_tlb_fill_align, 2681 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2682 .cpu_exec_halt = arm_cpu_exec_halt, 2683 .do_interrupt = arm_cpu_do_interrupt, 2684 .do_transaction_failed = arm_cpu_do_transaction_failed, 2685 .do_unaligned_access = arm_cpu_do_unaligned_access, 2686 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2687 .debug_check_watchpoint = arm_debug_check_watchpoint, 2688 .debug_check_breakpoint = arm_debug_check_breakpoint, 2689 #endif /* !CONFIG_USER_ONLY */ 2690 }; 2691 #endif /* CONFIG_TCG */ 2692 2693 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2694 { 2695 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2696 CPUClass *cc = CPU_CLASS(acc); 2697 DeviceClass *dc = DEVICE_CLASS(oc); 2698 ResettableClass *rc = RESETTABLE_CLASS(oc); 2699 2700 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2701 &acc->parent_realize); 2702 2703 device_class_set_props(dc, arm_cpu_properties); 2704 2705 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2706 &acc->parent_phases); 2707 2708 cc->class_by_name = arm_cpu_class_by_name; 2709 cc->has_work = arm_cpu_has_work; 2710 cc->mmu_index = arm_cpu_mmu_index; 2711 cc->dump_state = arm_cpu_dump_state; 2712 cc->set_pc = arm_cpu_set_pc; 2713 cc->get_pc = arm_cpu_get_pc; 2714 cc->gdb_read_register = arm_cpu_gdb_read_register; 2715 cc->gdb_write_register = arm_cpu_gdb_write_register; 2716 #ifndef CONFIG_USER_ONLY 2717 cc->sysemu_ops = &arm_sysemu_ops; 2718 #endif 2719 cc->gdb_arch_name = arm_gdb_arch_name; 2720 cc->gdb_stop_before_watchpoint = true; 2721 cc->disas_set_info = arm_disas_set_info; 2722 2723 #ifdef CONFIG_TCG 2724 cc->tcg_ops = &arm_tcg_ops; 2725 #endif /* CONFIG_TCG */ 2726 } 2727 2728 static void arm_cpu_instance_init(Object *obj) 2729 { 2730 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2731 2732 acc->info->initfn(obj); 2733 arm_cpu_post_init(obj); 2734 } 2735 2736 static void cpu_register_class_init(ObjectClass *oc, void *data) 2737 { 2738 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2739 CPUClass *cc = CPU_CLASS(acc); 2740 2741 acc->info = data; 2742 cc->gdb_core_xml_file = "arm-core.xml"; 2743 if (acc->info->deprecation_note) { 2744 cc->deprecation_note = acc->info->deprecation_note; 2745 } 2746 } 2747 2748 void arm_cpu_register(const ARMCPUInfo *info) 2749 { 2750 TypeInfo type_info = { 2751 .parent = TYPE_ARM_CPU, 2752 .instance_init = arm_cpu_instance_init, 2753 .class_init = info->class_init ?: cpu_register_class_init, 2754 .class_data = (void *)info, 2755 }; 2756 2757 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2758 type_register_static(&type_info); 2759 g_free((void *)type_info.name); 2760 } 2761 2762 static const TypeInfo arm_cpu_type_info = { 2763 .name = TYPE_ARM_CPU, 2764 .parent = TYPE_CPU, 2765 .instance_size = sizeof(ARMCPU), 2766 .instance_align = __alignof__(ARMCPU), 2767 .instance_init = arm_cpu_initfn, 2768 .instance_finalize = arm_cpu_finalizefn, 2769 .abstract = true, 2770 .class_size = sizeof(ARMCPUClass), 2771 .class_init = arm_cpu_class_init, 2772 }; 2773 2774 static void arm_cpu_register_types(void) 2775 { 2776 type_register_static(&arm_cpu_type_info); 2777 } 2778 2779 type_init(arm_cpu_register_types) 2780