174433bf0SRichard Henderson /* 274433bf0SRichard Henderson * ARM cpu parameters for qemu. 374433bf0SRichard Henderson * 474433bf0SRichard Henderson * Copyright (c) 2003 Fabrice Bellard 5b14d0649SPhilippe Mathieu-Daudé * SPDX-License-Identifier: LGPL-2.0-or-later 674433bf0SRichard Henderson */ 774433bf0SRichard Henderson 874433bf0SRichard Henderson #ifndef ARM_CPU_PARAM_H 94f31b54bSMarkus Armbruster #define ARM_CPU_PARAM_H 1074433bf0SRichard Henderson 1174433bf0SRichard Henderson #ifdef TARGET_AARCH64 127a928f43SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 52 130af312b6SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 52 1474433bf0SRichard Henderson #else 1574433bf0SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 40 1674433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 1774433bf0SRichard Henderson #endif 1874433bf0SRichard Henderson 1974433bf0SRichard Henderson #ifdef CONFIG_USER_ONLY 200e0c030cSRichard Henderson # ifdef TARGET_AARCH64 210e0c030cSRichard Henderson # define TARGET_TAGGED_ADDRESSES 22b314fd06SWarner Losh # ifdef __FreeBSD__ 23b314fd06SWarner Losh # define TARGET_PAGE_BITS 12 24b314fd06SWarner Losh # else 25a575230fSRichard Henderson /* Allow user-only to vary page size from 4k */ 26a575230fSRichard Henderson # define TARGET_PAGE_BITS_VARY 27b314fd06SWarner Losh # endif 28a575230fSRichard Henderson # else 29a575230fSRichard Henderson # define TARGET_PAGE_BITS 12 300e0c030cSRichard Henderson # endif 31e92dd332SPhilippe Mathieu-Daudé #else /* !CONFIG_USER_ONLY */ 3274433bf0SRichard Henderson /* 3374433bf0SRichard Henderson * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 3474433bf0SRichard Henderson * have to support 1K tiny pages. 3574433bf0SRichard Henderson */ 3674433bf0SRichard Henderson # define TARGET_PAGE_BITS_VARY 37d11bf649SRichard Henderson # define TARGET_PAGE_BITS_LEGACY 10 38e92dd332SPhilippe Mathieu-Daudé #endif /* !CONFIG_USER_ONLY */ 3924d18d5dSRichard Henderson 40*21d41c56SPhilippe Mathieu-Daudé /* 41*21d41c56SPhilippe Mathieu-Daudé * ARM-specific extra insn start words: 42*21d41c56SPhilippe Mathieu-Daudé * 1: Conditional execution bits 43*21d41c56SPhilippe Mathieu-Daudé * 2: Partial exception syndrome for data aborts 44*21d41c56SPhilippe Mathieu-Daudé */ 45*21d41c56SPhilippe Mathieu-Daudé #define TARGET_INSN_START_EXTRA_WORDS 2 46*21d41c56SPhilippe Mathieu-Daudé 47e92dd332SPhilippe Mathieu-Daudé /* ARM processors have a weak memory model */ 48e92dd332SPhilippe Mathieu-Daudé #define TCG_GUEST_DEFAULT_MO (0) 4974433bf0SRichard Henderson 5074433bf0SRichard Henderson #endif 51