1 /* 2 * QEMU ARM CP Register access and descriptions 3 * 4 * Copyright (c) 2022 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #ifndef TARGET_ARM_CPREGS_H 22 #define TARGET_ARM_CPREGS_H 23 24 #include "hw/registerfields.h" 25 #include "target/arm/kvm-consts.h" 26 #include "cpu.h" 27 28 /* 29 * ARMCPRegInfo type field bits: 30 */ 31 enum { 32 /* 33 * Register must be handled specially during translation. 34 * The method is one of the values below: 35 */ 36 ARM_CP_SPECIAL_MASK = 0x000f, 37 /* Special: no change to PE state: writes ignored, reads ignored. */ 38 ARM_CP_NOP = 0x0001, 39 /* Special: sysreg is WFI, for v5 and v6. */ 40 ARM_CP_WFI = 0x0002, 41 /* Special: sysreg is NZCV. */ 42 ARM_CP_NZCV = 0x0003, 43 /* Special: sysreg is CURRENTEL. */ 44 ARM_CP_CURRENTEL = 0x0004, 45 /* Special: sysreg is DC ZVA or similar. */ 46 ARM_CP_DC_ZVA = 0x0005, 47 ARM_CP_DC_GVA = 0x0006, 48 ARM_CP_DC_GZVA = 0x0007, 49 50 /* Flag: reads produce resetvalue; writes ignored. */ 51 ARM_CP_CONST = 1 << 4, 52 /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ 53 ARM_CP_64BIT = 1 << 5, 54 /* 55 * Flag: TB should not be ended after a write to this register 56 * (the default is that the TB ends after cp writes). 57 */ 58 ARM_CP_SUPPRESS_TB_END = 1 << 6, 59 /* 60 * Flag: Permit a register definition to override a previous definition 61 * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new 62 * or the old must have the ARM_CP_OVERRIDE bit set. 63 */ 64 ARM_CP_OVERRIDE = 1 << 7, 65 /* 66 * Flag: Register is an alias view of some underlying state which is also 67 * visible via another register, and that the other register is handling 68 * migration and reset; registers marked ARM_CP_ALIAS will not be migrated 69 * but may have their state set by syncing of register state from KVM. 70 */ 71 ARM_CP_ALIAS = 1 << 8, 72 /* 73 * Flag: Register does I/O and therefore its accesses need to be marked 74 * with translator_io_start() and also end the TB. In particular, 75 * registers which implement clocks or timers require this. 76 */ 77 ARM_CP_IO = 1 << 9, 78 /* 79 * Flag: Register has no underlying state and does not support raw access 80 * for state saving/loading; it will not be used for either migration or 81 * KVM state synchronization. Typically this is for "registers" which are 82 * actually used as instructions for cache maintenance and so on. 83 */ 84 ARM_CP_NO_RAW = 1 << 10, 85 /* 86 * Flag: The read or write hook might raise an exception; the generated 87 * code will synchronize the CPU state before calling the hook so that it 88 * is safe for the hook to call raise_exception(). 89 */ 90 ARM_CP_RAISES_EXC = 1 << 11, 91 /* 92 * Flag: Writes to the sysreg might change the exception level - typically 93 * on older ARM chips. For those cases we need to re-read the new el when 94 * recomputing the translation flags. 95 */ 96 ARM_CP_NEWEL = 1 << 12, 97 /* 98 * Flag: Access check for this sysreg is identical to accessing FPU state 99 * from an instruction: use translation fp_access_check(). 100 */ 101 ARM_CP_FPU = 1 << 13, 102 /* 103 * Flag: Access check for this sysreg is identical to accessing SVE state 104 * from an instruction: use translation sve_access_check(). 105 */ 106 ARM_CP_SVE = 1 << 14, 107 /* Flag: Do not expose in gdb sysreg xml. */ 108 ARM_CP_NO_GDB = 1 << 15, 109 /* 110 * Flags: If EL3 but not EL2... 111 * - UNDEF: discard the cpreg, 112 * - KEEP: retain the cpreg as is, 113 * - C_NZ: set const on the cpreg, but retain resetvalue, 114 * - else: set const on the cpreg, zero resetvalue, aka RES0. 115 * See rule RJFFP in section D1.1.3 of DDI0487H.a. 116 */ 117 ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, 118 ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, 119 ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, 120 /* 121 * Flag: Access check for this sysreg is constrained by the 122 * ARM pseudocode function CheckSMEAccess(). 123 */ 124 ARM_CP_SME = 1 << 19, 125 /* 126 * Flag: one of the four EL2 registers which redirect to the 127 * equivalent EL1 register when FEAT_NV2 is enabled. 128 */ 129 ARM_CP_NV2_REDIRECT = 1 << 20, 130 /* 131 * Flag: this is a TLBI insn which (when FEAT_XS is present) also has 132 * an NXS variant at the same encoding except that crn is 1 greater, 133 * so when registering this cpreg automatically also register one 134 * for the TLBI NXS variant. (For QEMU the NXS variant behaves 135 * identically to the normal one, other than FGT trapping handling.) 136 */ 137 ARM_CP_ADD_TLBI_NXS = 1 << 21, 138 }; 139 140 /* 141 * Interface for defining coprocessor registers. 142 * Registers are defined in tables of arm_cp_reginfo structs 143 * which are passed to define_arm_cp_regs(). 144 */ 145 146 /* 147 * When looking up a coprocessor register we look for it 148 * via an integer which encodes all of: 149 * coprocessor number 150 * Crn, Crm, opc1, opc2 fields 151 * 32 or 64 bit register (ie is it accessed via MRC/MCR 152 * or via MRRC/MCRR?) 153 * non-secure/secure bank (AArch32 only) 154 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 155 * (In this case crn and opc2 should be zero.) 156 * For AArch64, there is no 32/64 bit size distinction; 157 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 158 * and 4 bit CRn and CRm. The encoding patterns are chosen 159 * to be easy to convert to and from the KVM encodings, and also 160 * so that the hashtable can contain both AArch32 and AArch64 161 * registers (to allow for interprocessing where we might run 162 * 32 bit code on a 64 bit core). 163 */ 164 /* 165 * This bit is private to our hashtable cpreg; in KVM register 166 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 167 * in the upper bits of the 64 bit ID. 168 */ 169 #define CP_REG_AA64_SHIFT 28 170 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 171 172 /* 173 * To enable banking of coprocessor registers depending on ns-bit we 174 * add a bit to distinguish between secure and non-secure cpregs in the 175 * hashtable. 176 */ 177 #define CP_REG_NS_SHIFT 29 178 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 179 180 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 181 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 182 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 183 184 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 185 (CP_REG_AA64_MASK | \ 186 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 187 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 188 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 189 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 190 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 191 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 192 193 /* 194 * Convert a full 64 bit KVM register ID to the truncated 32 bit 195 * version used as a key for the coprocessor register hashtable 196 */ 197 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 198 { 199 uint32_t cpregid = kvmid; 200 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 201 cpregid |= CP_REG_AA64_MASK; 202 } else { 203 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 204 cpregid |= (1 << 15); 205 } 206 207 /* 208 * KVM is always non-secure so add the NS flag on AArch32 register 209 * entries. 210 */ 211 cpregid |= 1 << CP_REG_NS_SHIFT; 212 } 213 return cpregid; 214 } 215 216 /* 217 * Convert a truncated 32 bit hashtable key into the full 218 * 64 bit KVM register ID. 219 */ 220 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 221 { 222 uint64_t kvmid; 223 224 if (cpregid & CP_REG_AA64_MASK) { 225 kvmid = cpregid & ~CP_REG_AA64_MASK; 226 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 227 } else { 228 kvmid = cpregid & ~(1 << 15); 229 if (cpregid & (1 << 15)) { 230 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 231 } else { 232 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 233 } 234 } 235 return kvmid; 236 } 237 238 /* 239 * Valid values for ARMCPRegInfo state field, indicating which of 240 * the AArch32 and AArch64 execution states this register is visible in. 241 * If the reginfo doesn't explicitly specify then it is AArch32 only. 242 * If the reginfo is declared to be visible in both states then a second 243 * reginfo is synthesised for the AArch32 view of the AArch64 register, 244 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 245 * Note that we rely on the values of these enums as we iterate through 246 * the various states in some places. 247 */ 248 typedef enum { 249 ARM_CP_STATE_AA32 = 0, 250 ARM_CP_STATE_AA64 = 1, 251 ARM_CP_STATE_BOTH = 2, 252 } CPState; 253 254 /* 255 * ARM CP register secure state flags. These flags identify security state 256 * attributes for a given CP register entry. 257 * The existence of both or neither secure and non-secure flags indicates that 258 * the register has both a secure and non-secure hash entry. A single one of 259 * these flags causes the register to only be hashed for the specified 260 * security state. 261 * Although definitions may have any combination of the S/NS bits, each 262 * registered entry will only have one to identify whether the entry is secure 263 * or non-secure. 264 */ 265 typedef enum { 266 ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */ 267 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 268 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 269 } CPSecureState; 270 271 /* 272 * Access rights: 273 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 274 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 275 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 276 * (ie any of the privileged modes in Secure state, or Monitor mode). 277 * If a register is accessible in one privilege level it's always accessible 278 * in higher privilege levels too. Since "Secure PL1" also follows this rule 279 * (ie anything visible in PL2 is visible in S-PL1, some things are only 280 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 281 * terminology a little and call this PL3. 282 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 283 * with the ELx exception levels. 284 * 285 * If access permissions for a register are more complex than can be 286 * described with these bits, then use a laxer set of restrictions, and 287 * do the more restrictive/complex check inside a helper function. 288 */ 289 typedef enum { 290 PL3_R = 0x80, 291 PL3_W = 0x40, 292 PL2_R = 0x20 | PL3_R, 293 PL2_W = 0x10 | PL3_W, 294 PL1_R = 0x08 | PL2_R, 295 PL1_W = 0x04 | PL2_W, 296 PL0_R = 0x02 | PL1_R, 297 PL0_W = 0x01 | PL1_W, 298 299 /* 300 * For user-mode some registers are accessible to EL0 via a kernel 301 * trap-and-emulate ABI. In this case we define the read permissions 302 * as actually being PL0_R. However some bits of any given register 303 * may still be masked. 304 */ 305 #ifdef CONFIG_USER_ONLY 306 PL0U_R = PL0_R, 307 #else 308 PL0U_R = PL1_R, 309 #endif 310 311 PL3_RW = PL3_R | PL3_W, 312 PL2_RW = PL2_R | PL2_W, 313 PL1_RW = PL1_R | PL1_W, 314 PL0_RW = PL0_R | PL0_W, 315 } CPAccessRights; 316 317 typedef enum CPAccessResult { 318 /* Access is permitted */ 319 CP_ACCESS_OK = 0, 320 321 /* 322 * Combined with one of the following, the low 2 bits indicate the 323 * target exception level. If 0, the exception is taken to the usual 324 * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). 325 */ 326 CP_ACCESS_EL_MASK = 3, 327 328 /* 329 * Access fails due to a configurable trap or enable which would 330 * result in a categorized exception syndrome giving information about 331 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 332 * 0xc or 0x18). These traps are always to a specified target EL, 333 * never to the usual target EL. 334 */ 335 CP_ACCESS_TRAP_BIT = (1 << 2), 336 CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP_BIT | 1, 337 CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP_BIT | 2, 338 CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP_BIT | 3, 339 340 /* 341 * Access fails with UNDEFINED, i.e. an exception syndrome 0x0 342 * ("uncategorized"), which is what an undefined insn produces. 343 * Note that this is not a catch-all case -- the set of cases which may 344 * result in this failure is specifically defined by the architecture. 345 * This trap is always to the usual target EL, never directly to a 346 * specified target EL. 347 */ 348 CP_ACCESS_UNDEFINED = (2 << 2), 349 } CPAccessResult; 350 351 /* Indexes into fgt_read[] */ 352 #define FGTREG_HFGRTR 0 353 #define FGTREG_HDFGRTR 1 354 /* Indexes into fgt_write[] */ 355 #define FGTREG_HFGWTR 0 356 #define FGTREG_HDFGWTR 1 357 /* Indexes into fgt_exec[] */ 358 #define FGTREG_HFGITR 0 359 360 FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) 361 FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1) 362 FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1) 363 FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1) 364 FIELD(HFGRTR_EL2, APDAKEY, 4, 1) 365 FIELD(HFGRTR_EL2, APDBKEY, 5, 1) 366 FIELD(HFGRTR_EL2, APGAKEY, 6, 1) 367 FIELD(HFGRTR_EL2, APIAKEY, 7, 1) 368 FIELD(HFGRTR_EL2, APIBKEY, 8, 1) 369 FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1) 370 FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1) 371 FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1) 372 FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1) 373 FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1) 374 FIELD(HFGRTR_EL2, CTR_EL0, 14, 1) 375 FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1) 376 FIELD(HFGRTR_EL2, ESR_EL1, 16, 1) 377 FIELD(HFGRTR_EL2, FAR_EL1, 17, 1) 378 FIELD(HFGRTR_EL2, ISR_EL1, 18, 1) 379 FIELD(HFGRTR_EL2, LORC_EL1, 19, 1) 380 FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1) 381 FIELD(HFGRTR_EL2, LORID_EL1, 21, 1) 382 FIELD(HFGRTR_EL2, LORN_EL1, 22, 1) 383 FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1) 384 FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1) 385 FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1) 386 FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1) 387 FIELD(HFGRTR_EL2, PAR_EL1, 27, 1) 388 FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1) 389 FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1) 390 FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1) 391 FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1) 392 FIELD(HFGRTR_EL2, TCR_EL1, 32, 1) 393 FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1) 394 FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1) 395 FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1) 396 FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1) 397 FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1) 398 FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1) 399 FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1) 400 FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1) 401 FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1) 402 FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1) 403 FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1) 404 FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1) 405 FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1) 406 FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1) 407 FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) 408 FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) 409 FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) 410 FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) 411 /* 51-53: RES0 */ 412 FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) 413 FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) 414 /* 56-63: RES0 */ 415 416 /* These match HFGRTR but bits for RO registers are RES0 */ 417 FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) 418 FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1) 419 FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1) 420 FIELD(HFGWTR_EL2, APDAKEY, 4, 1) 421 FIELD(HFGWTR_EL2, APDBKEY, 5, 1) 422 FIELD(HFGWTR_EL2, APGAKEY, 6, 1) 423 FIELD(HFGWTR_EL2, APIAKEY, 7, 1) 424 FIELD(HFGWTR_EL2, APIBKEY, 8, 1) 425 FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1) 426 FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1) 427 FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1) 428 FIELD(HFGWTR_EL2, ESR_EL1, 16, 1) 429 FIELD(HFGWTR_EL2, FAR_EL1, 17, 1) 430 FIELD(HFGWTR_EL2, LORC_EL1, 19, 1) 431 FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1) 432 FIELD(HFGWTR_EL2, LORN_EL1, 22, 1) 433 FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1) 434 FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1) 435 FIELD(HFGWTR_EL2, PAR_EL1, 27, 1) 436 FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1) 437 FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1) 438 FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1) 439 FIELD(HFGWTR_EL2, TCR_EL1, 32, 1) 440 FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1) 441 FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1) 442 FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1) 443 FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1) 444 FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1) 445 FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1) 446 FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1) 447 FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1) 448 FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1) 449 FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1) 450 FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1) 451 FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) 452 FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) 453 FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) 454 FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) 455 FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) 456 FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) 457 458 FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) 459 FIELD(HFGITR_EL2, ICIALLU, 1, 1) 460 FIELD(HFGITR_EL2, ICIVAU, 2, 1) 461 FIELD(HFGITR_EL2, DCIVAC, 3, 1) 462 FIELD(HFGITR_EL2, DCISW, 4, 1) 463 FIELD(HFGITR_EL2, DCCSW, 5, 1) 464 FIELD(HFGITR_EL2, DCCISW, 6, 1) 465 FIELD(HFGITR_EL2, DCCVAU, 7, 1) 466 FIELD(HFGITR_EL2, DCCVAP, 8, 1) 467 FIELD(HFGITR_EL2, DCCVADP, 9, 1) 468 FIELD(HFGITR_EL2, DCCIVAC, 10, 1) 469 FIELD(HFGITR_EL2, DCZVA, 11, 1) 470 FIELD(HFGITR_EL2, ATS1E1R, 12, 1) 471 FIELD(HFGITR_EL2, ATS1E1W, 13, 1) 472 FIELD(HFGITR_EL2, ATS1E0R, 14, 1) 473 FIELD(HFGITR_EL2, ATS1E0W, 15, 1) 474 FIELD(HFGITR_EL2, ATS1E1RP, 16, 1) 475 FIELD(HFGITR_EL2, ATS1E1WP, 17, 1) 476 FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1) 477 FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1) 478 FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1) 479 FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1) 480 FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1) 481 FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1) 482 FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1) 483 FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1) 484 FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1) 485 FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1) 486 FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1) 487 FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1) 488 FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1) 489 FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1) 490 FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1) 491 FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1) 492 FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1) 493 FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1) 494 FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1) 495 FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1) 496 FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1) 497 FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1) 498 FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1) 499 FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1) 500 FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1) 501 FIELD(HFGITR_EL2, TLBIVAE1, 43, 1) 502 FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1) 503 FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1) 504 FIELD(HFGITR_EL2, TLBIVALE1, 46, 1) 505 FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1) 506 FIELD(HFGITR_EL2, CFPRCTX, 48, 1) 507 FIELD(HFGITR_EL2, DVPRCTX, 49, 1) 508 FIELD(HFGITR_EL2, CPPRCTX, 50, 1) 509 FIELD(HFGITR_EL2, ERET, 51, 1) 510 FIELD(HFGITR_EL2, SVC_EL0, 52, 1) 511 FIELD(HFGITR_EL2, SVC_EL1, 53, 1) 512 FIELD(HFGITR_EL2, DCCVAC, 54, 1) 513 FIELD(HFGITR_EL2, NBRBINJ, 55, 1) 514 FIELD(HFGITR_EL2, NBRBIALL, 56, 1) 515 516 FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) 517 FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) 518 FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1) 519 FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1) 520 FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1) 521 FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1) 522 FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1) 523 FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1) 524 /* 8: RES0: OSLAR_EL1 is WO */ 525 FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1) 526 FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1) 527 FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1) 528 FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1) 529 FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1) 530 FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1) 531 FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1) 532 FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1) 533 FIELD(HDFGRTR_EL2, PMINTEN, 17, 1) 534 FIELD(HDFGRTR_EL2, PMOVS, 18, 1) 535 FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1) 536 /* 20: RES0: PMSWINC_EL0 is WO */ 537 /* 21: RES0: PMCR_EL0 is WO */ 538 FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1) 539 FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1) 540 FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1) 541 FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1) 542 FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1) 543 FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1) 544 FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1) 545 FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1) 546 FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1) 547 FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1) 548 FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1) 549 FIELD(HDFGRTR_EL2, TRC, 33, 1) 550 FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1) 551 FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1) 552 FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1) 553 FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1) 554 /* 38, 39: RES0 */ 555 FIELD(HDFGRTR_EL2, TRCID, 40, 1) 556 FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1) 557 /* 42: RES0: TRCOSLAR is WO */ 558 FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1) 559 FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1) 560 FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1) 561 FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1) 562 FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1) 563 FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1) 564 /* 49: RES0: TRFCR_EL1 is WO */ 565 FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1) 566 FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1) 567 FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1) 568 FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1) 569 FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1) 570 FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1) 571 FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1) 572 FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1) 573 FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1) 574 FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1) 575 FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1) 576 FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1) 577 FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1) 578 FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1) 579 580 /* 581 * These match HDFGRTR_EL2, but bits for RO registers are RES0. 582 * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0. 583 */ 584 FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1) 585 FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1) 586 FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1) 587 FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1) 588 FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1) 589 FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1) 590 FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1) 591 FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1) 592 FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1) 593 FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1) 594 FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1) 595 FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1) 596 FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1) 597 FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1) 598 FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1) 599 FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1) 600 FIELD(HDFGWTR_EL2, PMINTEN, 17, 1) 601 FIELD(HDFGWTR_EL2, PMOVS, 18, 1) 602 FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1) 603 FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1) 604 FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1) 605 FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1) 606 FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1) 607 FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1) 608 FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1) 609 FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1) 610 FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1) 611 FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1) 612 FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1) 613 FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1) 614 FIELD(HDFGWTR_EL2, TRC, 33, 1) 615 FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1) 616 FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1) 617 FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1) 618 FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1) 619 FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1) 620 FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1) 621 FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1) 622 FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1) 623 FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1) 624 FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1) 625 FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1) 626 FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1) 627 FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1) 628 FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1) 629 FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1) 630 FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1) 631 FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1) 632 FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) 633 FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) 634 FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) 635 636 FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */ 637 /* Which fine-grained trap bit register to check, if any */ 638 FIELD(FGT, TYPE, 10, 3) 639 FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */ 640 FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */ 641 FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */ 642 643 /* 644 * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt 645 * fields. We assume for brevity's sake that there are no duplicated 646 * bit names across the various FGT registers. 647 */ 648 #define DO_BIT(REG, BITNAME) \ 649 FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT 650 651 /* Some bits have reversed sense, so 0 means trap and 1 means not */ 652 #define DO_REV_BIT(REG, BITNAME) \ 653 FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT 654 655 /* 656 * The FGT bits for TLBI maintenance instructions accessible at EL1 always 657 * affect the "normal" TLBI insns; they affect the corresponding TLBI insns 658 * with the nXS qualifier only if HCRX_EL2.FGTnXS is 0. We define e.g. 659 * FGT_TLBIVAE1 to use for the normal insn, and FGT_TLBIVAE1NXS to use 660 * for the nXS qualified insn. 661 */ 662 #define DO_TLBINXS_BIT(REG, BITNAME) \ 663 FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT, \ 664 FGT_##BITNAME##NXS = FGT_##BITNAME | R_FGT_NXS_MASK 665 666 typedef enum FGTBit { 667 /* 668 * These bits tell us which register arrays to use: 669 * if FGT_R is set then reads are checked against fgt_read[]; 670 * if FGT_W is set then writes are checked against fgt_write[]; 671 * if FGT_EXEC is set then all accesses are checked against fgt_exec[]. 672 * 673 * For almost all bits in the R/W register pairs, the bit exists in 674 * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register 675 * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa 676 * for a WO register. There are unfortunately a couple of exceptions 677 * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but 678 * the FGT system only allows trapping of writes, not reads. 679 * 680 * Note that we arrange these bits so that a 0 FGTBit means "no trap". 681 */ 682 FGT_R = 1 << R_FGT_TYPE_SHIFT, 683 FGT_W = 2 << R_FGT_TYPE_SHIFT, 684 FGT_EXEC = 4 << R_FGT_TYPE_SHIFT, 685 FGT_RW = FGT_R | FGT_W, 686 /* Bit to identify whether trap bit is reversed sense */ 687 FGT_REV = R_FGT_REV_MASK, 688 689 /* 690 * If a bit exists in HFGRTR/HDFGRTR then either the register being 691 * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either 692 * want to trap for both reads and writes or else it's harmless to mark 693 * it as trap-on-writes. 694 * If a bit exists only in HFGWTR/HDFGWTR then either the register being 695 * trapped is WO, or else it is one of the two oddball special cases 696 * which are RW but have only a write trap. We mark these as only 697 * FGT_W so we get the right behaviour for those special cases. 698 * (If a bit was added in future that provided only a read trap for an 699 * RW register we'd need to do something special to get the FGT_R bit 700 * only. But this seems unlikely to happen.) 701 * 702 * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if 703 * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR. 704 */ 705 FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT), 706 FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT), 707 FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), 708 FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), 709 FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), 710 711 /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ 712 DO_BIT(HFGRTR, AFSR0_EL1), 713 DO_BIT(HFGRTR, AFSR1_EL1), 714 DO_BIT(HFGRTR, AIDR_EL1), 715 DO_BIT(HFGRTR, AMAIR_EL1), 716 DO_BIT(HFGRTR, APDAKEY), 717 DO_BIT(HFGRTR, APDBKEY), 718 DO_BIT(HFGRTR, APGAKEY), 719 DO_BIT(HFGRTR, APIAKEY), 720 DO_BIT(HFGRTR, APIBKEY), 721 DO_BIT(HFGRTR, CCSIDR_EL1), 722 DO_BIT(HFGRTR, CLIDR_EL1), 723 DO_BIT(HFGRTR, CONTEXTIDR_EL1), 724 DO_BIT(HFGRTR, CPACR_EL1), 725 DO_BIT(HFGRTR, CSSELR_EL1), 726 DO_BIT(HFGRTR, CTR_EL0), 727 DO_BIT(HFGRTR, DCZID_EL0), 728 DO_BIT(HFGRTR, ESR_EL1), 729 DO_BIT(HFGRTR, FAR_EL1), 730 DO_BIT(HFGRTR, ISR_EL1), 731 DO_BIT(HFGRTR, LORC_EL1), 732 DO_BIT(HFGRTR, LOREA_EL1), 733 DO_BIT(HFGRTR, LORID_EL1), 734 DO_BIT(HFGRTR, LORN_EL1), 735 DO_BIT(HFGRTR, LORSA_EL1), 736 DO_BIT(HFGRTR, MAIR_EL1), 737 DO_BIT(HFGRTR, MIDR_EL1), 738 DO_BIT(HFGRTR, MPIDR_EL1), 739 DO_BIT(HFGRTR, PAR_EL1), 740 DO_BIT(HFGRTR, REVIDR_EL1), 741 DO_BIT(HFGRTR, SCTLR_EL1), 742 DO_BIT(HFGRTR, SCXTNUM_EL1), 743 DO_BIT(HFGRTR, SCXTNUM_EL0), 744 DO_BIT(HFGRTR, TCR_EL1), 745 DO_BIT(HFGRTR, TPIDR_EL1), 746 DO_BIT(HFGRTR, TPIDRRO_EL0), 747 DO_BIT(HFGRTR, TPIDR_EL0), 748 DO_BIT(HFGRTR, TTBR0_EL1), 749 DO_BIT(HFGRTR, TTBR1_EL1), 750 DO_BIT(HFGRTR, VBAR_EL1), 751 DO_BIT(HFGRTR, ICC_IGRPENN_EL1), 752 DO_BIT(HFGRTR, ERRIDR_EL1), 753 DO_REV_BIT(HFGRTR, NSMPRI_EL1), 754 DO_REV_BIT(HFGRTR, NTPIDR2_EL0), 755 756 /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ 757 DO_BIT(HDFGRTR, DBGBCRN_EL1), 758 DO_BIT(HDFGRTR, DBGBVRN_EL1), 759 DO_BIT(HDFGRTR, DBGWCRN_EL1), 760 DO_BIT(HDFGRTR, DBGWVRN_EL1), 761 DO_BIT(HDFGRTR, MDSCR_EL1), 762 DO_BIT(HDFGRTR, DBGCLAIM), 763 DO_BIT(HDFGWTR, OSLAR_EL1), 764 DO_BIT(HDFGRTR, OSLSR_EL1), 765 DO_BIT(HDFGRTR, OSECCR_EL1), 766 DO_BIT(HDFGRTR, OSDLR_EL1), 767 DO_BIT(HDFGRTR, PMEVCNTRN_EL0), 768 DO_BIT(HDFGRTR, PMEVTYPERN_EL0), 769 DO_BIT(HDFGRTR, PMCCFILTR_EL0), 770 DO_BIT(HDFGRTR, PMCCNTR_EL0), 771 DO_BIT(HDFGRTR, PMCNTEN), 772 DO_BIT(HDFGRTR, PMINTEN), 773 DO_BIT(HDFGRTR, PMOVS), 774 DO_BIT(HDFGRTR, PMSELR_EL0), 775 DO_BIT(HDFGWTR, PMSWINC_EL0), 776 DO_BIT(HDFGWTR, PMCR_EL0), 777 DO_BIT(HDFGRTR, PMMIR_EL1), 778 DO_BIT(HDFGRTR, PMCEIDN_EL0), 779 780 /* Trap bits in HFGITR_EL2, starting from bit 0 */ 781 DO_BIT(HFGITR, ICIALLUIS), 782 DO_BIT(HFGITR, ICIALLU), 783 DO_BIT(HFGITR, ICIVAU), 784 DO_BIT(HFGITR, DCIVAC), 785 DO_BIT(HFGITR, DCISW), 786 DO_BIT(HFGITR, DCCSW), 787 DO_BIT(HFGITR, DCCISW), 788 DO_BIT(HFGITR, DCCVAU), 789 DO_BIT(HFGITR, DCCVAP), 790 DO_BIT(HFGITR, DCCVADP), 791 DO_BIT(HFGITR, DCCIVAC), 792 DO_BIT(HFGITR, DCZVA), 793 DO_BIT(HFGITR, ATS1E1R), 794 DO_BIT(HFGITR, ATS1E1W), 795 DO_BIT(HFGITR, ATS1E0R), 796 DO_BIT(HFGITR, ATS1E0W), 797 DO_BIT(HFGITR, ATS1E1RP), 798 DO_BIT(HFGITR, ATS1E1WP), 799 DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1OS), 800 DO_TLBINXS_BIT(HFGITR, TLBIVAE1OS), 801 DO_TLBINXS_BIT(HFGITR, TLBIASIDE1OS), 802 DO_TLBINXS_BIT(HFGITR, TLBIVAAE1OS), 803 DO_TLBINXS_BIT(HFGITR, TLBIVALE1OS), 804 DO_TLBINXS_BIT(HFGITR, TLBIVAALE1OS), 805 DO_TLBINXS_BIT(HFGITR, TLBIRVAE1OS), 806 DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1OS), 807 DO_TLBINXS_BIT(HFGITR, TLBIRVALE1OS), 808 DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1OS), 809 DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1IS), 810 DO_TLBINXS_BIT(HFGITR, TLBIVAE1IS), 811 DO_TLBINXS_BIT(HFGITR, TLBIASIDE1IS), 812 DO_TLBINXS_BIT(HFGITR, TLBIVAAE1IS), 813 DO_TLBINXS_BIT(HFGITR, TLBIVALE1IS), 814 DO_TLBINXS_BIT(HFGITR, TLBIVAALE1IS), 815 DO_TLBINXS_BIT(HFGITR, TLBIRVAE1IS), 816 DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1IS), 817 DO_TLBINXS_BIT(HFGITR, TLBIRVALE1IS), 818 DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1IS), 819 DO_TLBINXS_BIT(HFGITR, TLBIRVAE1), 820 DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1), 821 DO_TLBINXS_BIT(HFGITR, TLBIRVALE1), 822 DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1), 823 DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1), 824 DO_TLBINXS_BIT(HFGITR, TLBIVAE1), 825 DO_TLBINXS_BIT(HFGITR, TLBIASIDE1), 826 DO_TLBINXS_BIT(HFGITR, TLBIVAAE1), 827 DO_TLBINXS_BIT(HFGITR, TLBIVALE1), 828 DO_TLBINXS_BIT(HFGITR, TLBIVAALE1), 829 DO_BIT(HFGITR, CFPRCTX), 830 DO_BIT(HFGITR, DVPRCTX), 831 DO_BIT(HFGITR, CPPRCTX), 832 DO_BIT(HFGITR, DCCVAC), 833 } FGTBit; 834 835 #undef DO_BIT 836 #undef DO_REV_BIT 837 838 typedef struct ARMCPRegInfo ARMCPRegInfo; 839 840 /* 841 * Access functions for coprocessor registers. These cannot fail and 842 * may not raise exceptions. 843 */ 844 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 845 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 846 uint64_t value); 847 /* Access permission check functions for coprocessor registers. */ 848 typedef CPAccessResult CPAccessFn(CPUARMState *env, 849 const ARMCPRegInfo *opaque, 850 bool isread); 851 /* Hook function for register reset */ 852 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 853 854 #define CP_ANY 0xff 855 856 /* Flags in the high bits of nv2_redirect_offset */ 857 #define NV2_REDIR_NV1 0x4000 /* Only redirect when HCR_EL2.NV1 == 1 */ 858 #define NV2_REDIR_NO_NV1 0x8000 /* Only redirect when HCR_EL2.NV1 == 0 */ 859 #define NV2_REDIR_FLAG_MASK 0xc000 860 861 /* Definition of an ARM coprocessor register */ 862 struct ARMCPRegInfo { 863 /* Name of register (useful mainly for debugging, need not be unique) */ 864 const char *name; 865 /* 866 * Location of register: coprocessor number and (crn,crm,opc1,opc2) 867 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 868 * 'wildcard' field -- any value of that field in the MRC/MCR insn 869 * will be decoded to this register. The register read and write 870 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 871 * used by the program, so it is possible to register a wildcard and 872 * then behave differently on read/write if necessary. 873 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 874 * must both be zero. 875 * For AArch64-visible registers, opc0 is also used. 876 * Since there are no "coprocessors" in AArch64, cp is purely used as a 877 * way to distinguish (for KVM's benefit) guest-visible system registers 878 * from demuxed ones provided to preserve the "no side effects on 879 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 880 * visible (to match KVM's encoding); cp==0 will be converted to 881 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 882 */ 883 uint8_t cp; 884 uint8_t crn; 885 uint8_t crm; 886 uint8_t opc0; 887 uint8_t opc1; 888 uint8_t opc2; 889 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 890 CPState state; 891 /* Register type: ARM_CP_* bits/values */ 892 int type; 893 /* Access rights: PL*_[RW] */ 894 CPAccessRights access; 895 /* Security state: ARM_CP_SECSTATE_* bits/values */ 896 CPSecureState secure; 897 /* 898 * Which fine-grained trap register bit to check, if any. This 899 * value encodes both the trap register and bit within it. 900 */ 901 FGTBit fgt; 902 903 /* 904 * Offset from VNCR_EL2 when FEAT_NV2 redirects access to memory; 905 * may include an NV2_REDIR_* flag. 906 */ 907 uint32_t nv2_redirect_offset; 908 909 /* 910 * The opaque pointer passed to define_arm_cp_regs_with_opaque() when 911 * this register was defined: can be used to hand data through to the 912 * register read/write functions, since they are passed the ARMCPRegInfo*. 913 */ 914 void *opaque; 915 /* 916 * Value of this register, if it is ARM_CP_CONST. Otherwise, if 917 * fieldoffset is non-zero, the reset value of the register. 918 */ 919 uint64_t resetvalue; 920 /* 921 * Offset of the field in CPUARMState for this register. 922 * This is not needed if either: 923 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 924 * 2. both readfn and writefn are specified 925 */ 926 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 927 928 /* 929 * Offsets of the secure and non-secure fields in CPUARMState for the 930 * register if it is banked. These fields are only used during the static 931 * registration of a register. During hashing the bank associated 932 * with a given security state is copied to fieldoffset which is used from 933 * there on out. 934 * 935 * It is expected that register definitions use either fieldoffset or 936 * bank_fieldoffsets in the definition but not both. It is also expected 937 * that both bank offsets are set when defining a banked register. This 938 * use indicates that a register is banked. 939 */ 940 ptrdiff_t bank_fieldoffsets[2]; 941 942 /* 943 * Function for making any access checks for this register in addition to 944 * those specified by the 'access' permissions bits. If NULL, no extra 945 * checks required. The access check is performed at runtime, not at 946 * translate time. 947 */ 948 CPAccessFn *accessfn; 949 /* 950 * Function for handling reads of this register. If NULL, then reads 951 * will be done by loading from the offset into CPUARMState specified 952 * by fieldoffset. 953 */ 954 CPReadFn *readfn; 955 /* 956 * Function for handling writes of this register. If NULL, then writes 957 * will be done by writing to the offset into CPUARMState specified 958 * by fieldoffset. 959 */ 960 CPWriteFn *writefn; 961 /* 962 * Function for doing a "raw" read; used when we need to copy 963 * coprocessor state to the kernel for KVM or out for 964 * migration. This only needs to be provided if there is also a 965 * readfn and it has side effects (for instance clear-on-read bits). 966 */ 967 CPReadFn *raw_readfn; 968 /* 969 * Function for doing a "raw" write; used when we need to copy KVM 970 * kernel coprocessor state into userspace, or for inbound 971 * migration. This only needs to be provided if there is also a 972 * writefn and it masks out "unwritable" bits or has write-one-to-clear 973 * or similar behaviour. 974 */ 975 CPWriteFn *raw_writefn; 976 /* 977 * Function for resetting the register. If NULL, then reset will be done 978 * by writing resetvalue to the field specified in fieldoffset. If 979 * fieldoffset is 0 then no reset will be done. 980 */ 981 CPResetFn *resetfn; 982 983 /* 984 * "Original" readfn, writefn, accessfn. 985 * For ARMv8.1-VHE register aliases, we overwrite the read/write 986 * accessor functions of various EL1/EL0 to perform the runtime 987 * check for which sysreg should actually be modified, and then 988 * forwards the operation. Before overwriting the accessors, 989 * the original function is copied here, so that accesses that 990 * really do go to the EL1/EL0 version proceed normally. 991 * (The corresponding EL2 register is linked via opaque.) 992 */ 993 CPReadFn *orig_readfn; 994 CPWriteFn *orig_writefn; 995 CPAccessFn *orig_accessfn; 996 }; 997 998 /* 999 * Macros which are lvalues for the field in CPUARMState for the 1000 * ARMCPRegInfo *ri. 1001 */ 1002 #define CPREG_FIELD32(env, ri) \ 1003 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 1004 #define CPREG_FIELD64(env, ri) \ 1005 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 1006 1007 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg, 1008 void *opaque); 1009 1010 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 1011 { 1012 define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); 1013 } 1014 1015 void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, 1016 void *opaque, size_t len); 1017 1018 #define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ 1019 do { \ 1020 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ 1021 define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ 1022 ARRAY_SIZE(REGS)); \ 1023 } while (0) 1024 1025 #define define_arm_cp_regs(CPU, REGS) \ 1026 define_arm_cp_regs_with_opaque(CPU, REGS, NULL) 1027 1028 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1029 1030 /* 1031 * Definition of an ARM co-processor register as viewed from 1032 * userspace. This is used for presenting sanitised versions of 1033 * registers to userspace when emulating the Linux AArch64 CPU 1034 * ID/feature ABI (advertised as HWCAP_CPUID). 1035 */ 1036 typedef struct ARMCPRegUserSpaceInfo { 1037 /* Name of register */ 1038 const char *name; 1039 1040 /* Is the name actually a glob pattern */ 1041 bool is_glob; 1042 1043 /* Only some bits are exported to user space */ 1044 uint64_t exported_bits; 1045 1046 /* Fixed bits are applied after the mask */ 1047 uint64_t fixed_bits; 1048 } ARMCPRegUserSpaceInfo; 1049 1050 void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, 1051 const ARMCPRegUserSpaceInfo *mods, 1052 size_t mods_len); 1053 1054 #define modify_arm_cp_regs(REGS, MODS) \ 1055 do { \ 1056 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ 1057 QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \ 1058 modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ 1059 MODS, ARRAY_SIZE(MODS)); \ 1060 } while (0) 1061 1062 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1063 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1064 uint64_t value); 1065 /* CPReadFn that can be used for read-as-zero behaviour */ 1066 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1067 1068 /* CPWriteFn that just writes the value to ri->fieldoffset */ 1069 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); 1070 1071 /* 1072 * CPResetFn that does nothing, for use if no reset is required even 1073 * if fieldoffset is non zero. 1074 */ 1075 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1076 1077 /* 1078 * Return true if this reginfo struct's field in the cpu state struct 1079 * is 64 bits wide. 1080 */ 1081 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1082 { 1083 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1084 } 1085 1086 static inline bool cp_access_ok(int current_el, 1087 const ARMCPRegInfo *ri, int isread) 1088 { 1089 return (ri->access >> ((current_el * 2) + isread)) & 1; 1090 } 1091 1092 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1093 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1094 1095 /* 1096 * Return true if the cp register encoding is in the "feature ID space" as 1097 * defined by FEAT_IDST (and thus should be reported with ER_ELx.EC 1098 * as EC_SYSTEMREGISTERTRAP rather than EC_UNCATEGORIZED). 1099 */ 1100 static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1, 1101 uint8_t opc2, 1102 uint8_t crn, uint8_t crm) 1103 { 1104 return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) && 1105 crn == 0 && crm < 8; 1106 } 1107 1108 /* 1109 * As arm_cpreg_encoding_in_idspace(), but take the encoding from an 1110 * ARMCPRegInfo. 1111 */ 1112 static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri) 1113 { 1114 return ri->state == ARM_CP_STATE_AA64 && 1115 arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2, 1116 ri->crn, ri->crm); 1117 } 1118 1119 #ifdef CONFIG_USER_ONLY 1120 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } 1121 #else 1122 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); 1123 #endif 1124 1125 CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); 1126 1127 /** 1128 * arm_cpreg_trap_in_nv: Return true if cpreg traps in nested virtualization 1129 * 1130 * Return true if this cpreg is one which should be trapped to EL2 if 1131 * it is executed at EL1 when nested virtualization is enabled via HCR_EL2.NV. 1132 */ 1133 static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri) 1134 { 1135 /* 1136 * The Arm ARM defines the registers to be trapped in terms of 1137 * their names (I_TZTZL). However the underlying principle is "if 1138 * it would UNDEF at EL1 but work at EL2 then it should trap", and 1139 * the way the encoding of sysregs and system instructions is done 1140 * means that the right set of registers is exactly those where 1141 * the opc1 field is 4 or 5. (You can see this also in the assert 1142 * we do that the opc1 field and the permissions mask line up in 1143 * define_one_arm_cp_reg_with_opaque().) 1144 * Checking the opc1 field is easier for us and avoids the problem 1145 * that we do not consistently use the right architectural names 1146 * for all sysregs, since we treat the name field as largely for debug. 1147 * 1148 * However we do this check, it is going to be at least potentially 1149 * fragile to future new sysregs, but this seems the least likely 1150 * to break. 1151 * 1152 * In particular, note that the released sysreg XML defines that 1153 * the FEAT_MEC sysregs and instructions do not follow this FEAT_NV 1154 * trapping rule, so we will need to add an ARM_CP_* flag to indicate 1155 * "register does not trap on NV" to handle those if/when we implement 1156 * FEAT_MEC. 1157 */ 1158 return ri->opc1 == 4 || ri->opc1 == 5; 1159 } 1160 1161 /* Macros for accessing a specified CP register bank */ 1162 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1163 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1164 1165 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1166 do { \ 1167 if (_secure) { \ 1168 (_env)->cp15._regname##_s = (_val); \ 1169 } else { \ 1170 (_env)->cp15._regname##_ns = (_val); \ 1171 } \ 1172 } while (0) 1173 1174 /* 1175 * Macros for automatically accessing a specific CP register bank depending on 1176 * the current secure state of the system. These macros are not intended for 1177 * supporting instruction translation reads/writes as these are dependent 1178 * solely on the SCR.NS bit and not the mode. 1179 */ 1180 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1181 A32_BANKED_REG_GET((_env), _regname, \ 1182 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1183 1184 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1185 A32_BANKED_REG_SET((_env), _regname, \ 1186 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1187 (_val)) 1188 1189 #endif /* TARGET_ARM_CPREGS_H */ 1190