14c9649a9Sj_mayer /* 24c9649a9Sj_mayer * Alpha emulation cpu helpers for qemu. 34c9649a9Sj_mayer * 44c9649a9Sj_mayer * Copyright (c) 2007 Jocelyn Mayer 54c9649a9Sj_mayer * 64c9649a9Sj_mayer * This library is free software; you can redistribute it and/or 74c9649a9Sj_mayer * modify it under the terms of the GNU Lesser General Public 84c9649a9Sj_mayer * License as published by the Free Software Foundation; either 94c9649a9Sj_mayer * version 2 of the License, or (at your option) any later version. 104c9649a9Sj_mayer * 114c9649a9Sj_mayer * This library is distributed in the hope that it will be useful, 124c9649a9Sj_mayer * but WITHOUT ANY WARRANTY; without even the implied warranty of 134c9649a9Sj_mayer * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 144c9649a9Sj_mayer * Lesser General Public License for more details. 154c9649a9Sj_mayer * 164c9649a9Sj_mayer * You should have received a copy of the GNU Lesser General Public 178167ee88SBlue Swirl * License along with this library; if not, see <http://www.gnu.org/licenses/>. 184c9649a9Sj_mayer */ 194c9649a9Sj_mayer 20e2e5e114SPeter Maydell #include "qemu/osdep.h" 214c9649a9Sj_mayer 224c9649a9Sj_mayer #include "cpu.h" 2363c91552SPaolo Bonzini #include "exec/exec-all.h" 245f8ab000SAlex Bennée #include "fpu/softfloat-types.h" 252ef6175aSRichard Henderson #include "exec/helper-proto.h" 2690c84c56SMarkus Armbruster #include "qemu/qemu-print.h" 27ba0e276dSRichard Henderson 28f3d3aad4SRichard Henderson 29f3d3aad4SRichard Henderson #define CONVERT_BIT(X, SRC, DST) \ 30f3d3aad4SRichard Henderson (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 31f3d3aad4SRichard Henderson 324d5712f1SAndreas Färber uint64_t cpu_alpha_load_fpcr(CPUAlphaState *env) 33ba0e276dSRichard Henderson { 34f3d3aad4SRichard Henderson return (uint64_t)env->fpcr << 32; 35ba0e276dSRichard Henderson } 36ba0e276dSRichard Henderson 374d5712f1SAndreas Färber void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val) 38ba0e276dSRichard Henderson { 39ea937dedSRichard Henderson static const uint8_t rm_map[] = { 40ea937dedSRichard Henderson [FPCR_DYN_NORMAL >> FPCR_DYN_SHIFT] = float_round_nearest_even, 41ea937dedSRichard Henderson [FPCR_DYN_CHOPPED >> FPCR_DYN_SHIFT] = float_round_to_zero, 42ea937dedSRichard Henderson [FPCR_DYN_MINUS >> FPCR_DYN_SHIFT] = float_round_down, 43ea937dedSRichard Henderson [FPCR_DYN_PLUS >> FPCR_DYN_SHIFT] = float_round_up, 44ea937dedSRichard Henderson }; 45ea937dedSRichard Henderson 46f3d3aad4SRichard Henderson uint32_t fpcr = val >> 32; 47f3d3aad4SRichard Henderson uint32_t t = 0; 48ba0e276dSRichard Henderson 49106e1319SRichard Henderson /* Record the raw value before adjusting for linux-user. */ 50f3d3aad4SRichard Henderson env->fpcr = fpcr; 5121ba8564SRichard Henderson 5221ba8564SRichard Henderson #ifdef CONFIG_USER_ONLY 5321ba8564SRichard Henderson /* 5421ba8564SRichard Henderson * Override some of these bits with the contents of ENV->SWCR. 5521ba8564SRichard Henderson * In system mode, some of these would trap to the kernel, at 5621ba8564SRichard Henderson * which point the kernel's handler would emulate and apply 5721ba8564SRichard Henderson * the software exception mask. 5821ba8564SRichard Henderson */ 59106e1319SRichard Henderson uint32_t soft_fpcr = alpha_ieee_swcr_to_fpcr(env->swcr) >> 32; 60*8cd99905SRichard Henderson fpcr |= soft_fpcr & (FPCR_STATUS_MASK | FPCR_DNZ); 61106e1319SRichard Henderson #endif 62106e1319SRichard Henderson 63106e1319SRichard Henderson t |= CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE); 64106e1319SRichard Henderson t |= CONVERT_BIT(fpcr, FPCR_UNFD, FPCR_UNF); 65106e1319SRichard Henderson t |= CONVERT_BIT(fpcr, FPCR_OVFD, FPCR_OVF); 66106e1319SRichard Henderson t |= CONVERT_BIT(fpcr, FPCR_DZED, FPCR_DZE); 67106e1319SRichard Henderson t |= CONVERT_BIT(fpcr, FPCR_INVD, FPCR_INV); 68106e1319SRichard Henderson 69106e1319SRichard Henderson env->fpcr_exc_enable = ~t & FPCR_STATUS_MASK; 70106e1319SRichard Henderson 71106e1319SRichard Henderson env->fpcr_dyn_round = rm_map[(fpcr & FPCR_DYN_MASK) >> FPCR_DYN_SHIFT]; 72106e1319SRichard Henderson 73106e1319SRichard Henderson env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ); 74106e1319SRichard Henderson env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0; 75106e1319SRichard Henderson #ifdef CONFIG_USER_ONLY 7621ba8564SRichard Henderson if (env->swcr & SWCR_MAP_UMZ) { 77712e7c61SRichard Henderson env->fpcr_flush_to_zero = 1; 7821ba8564SRichard Henderson } 7921ba8564SRichard Henderson #endif 80ba0e276dSRichard Henderson } 814c9649a9Sj_mayer 82a44a2777SRichard Henderson uint64_t helper_load_fpcr(CPUAlphaState *env) 83a44a2777SRichard Henderson { 84a44a2777SRichard Henderson return cpu_alpha_load_fpcr(env); 85a44a2777SRichard Henderson } 86a44a2777SRichard Henderson 87a44a2777SRichard Henderson void helper_store_fpcr(CPUAlphaState *env, uint64_t val) 88a44a2777SRichard Henderson { 89a44a2777SRichard Henderson cpu_alpha_store_fpcr(env, val); 90a44a2777SRichard Henderson } 91a44a2777SRichard Henderson 9259124384SRichard Henderson static uint64_t *cpu_alpha_addr_gr(CPUAlphaState *env, unsigned reg) 9359124384SRichard Henderson { 9459124384SRichard Henderson #ifndef CONFIG_USER_ONLY 95bcd2625dSRichard Henderson if (env->flags & ENV_FLAG_PAL_MODE) { 9659124384SRichard Henderson if (reg >= 8 && reg <= 14) { 9759124384SRichard Henderson return &env->shadow[reg - 8]; 9859124384SRichard Henderson } else if (reg == 25) { 9959124384SRichard Henderson return &env->shadow[7]; 10059124384SRichard Henderson } 10159124384SRichard Henderson } 10259124384SRichard Henderson #endif 10359124384SRichard Henderson return &env->ir[reg]; 10459124384SRichard Henderson } 10559124384SRichard Henderson 10659124384SRichard Henderson uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg) 10759124384SRichard Henderson { 10859124384SRichard Henderson return *cpu_alpha_addr_gr(env, reg); 10959124384SRichard Henderson } 11059124384SRichard Henderson 11159124384SRichard Henderson void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val) 11259124384SRichard Henderson { 11359124384SRichard Henderson *cpu_alpha_addr_gr(env, reg) = val; 11459124384SRichard Henderson } 11559124384SRichard Henderson 1164c9649a9Sj_mayer #if defined(CONFIG_USER_ONLY) 117e41c9452SRichard Henderson bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 118e41c9452SRichard Henderson MMUAccessType access_type, int mmu_idx, 119e41c9452SRichard Henderson bool probe, uintptr_t retaddr) 1204c9649a9Sj_mayer { 1217510454eSAndreas Färber AlphaCPU *cpu = ALPHA_CPU(cs); 1227510454eSAndreas Färber 12327103424SAndreas Färber cs->exception_index = EXCP_MMFAULT; 1247510454eSAndreas Färber cpu->env.trap_arg0 = address; 125e41c9452SRichard Henderson cpu_loop_exit_restore(cs, retaddr); 1264c9649a9Sj_mayer } 1274c9649a9Sj_mayer #else 128a3b9af16SRichard Henderson /* Returns the OSF/1 entMM failure indication, or -1 on success. */ 1294d5712f1SAndreas Färber static int get_physical_address(CPUAlphaState *env, target_ulong addr, 130a3b9af16SRichard Henderson int prot_need, int mmu_idx, 131a3b9af16SRichard Henderson target_ulong *pphys, int *pprot) 1324c9649a9Sj_mayer { 1331c7ad260SRichard Henderson CPUState *cs = env_cpu(env); 134a3b9af16SRichard Henderson target_long saddr = addr; 135a3b9af16SRichard Henderson target_ulong phys = 0; 136a3b9af16SRichard Henderson target_ulong L1pte, L2pte, L3pte; 137a3b9af16SRichard Henderson target_ulong pt, index; 138a3b9af16SRichard Henderson int prot = 0; 139a3b9af16SRichard Henderson int ret = MM_K_ACV; 140a3b9af16SRichard Henderson 1416a73ecf5SRichard Henderson /* Handle physical accesses. */ 1426a73ecf5SRichard Henderson if (mmu_idx == MMU_PHYS_IDX) { 1436a73ecf5SRichard Henderson phys = addr; 1446a73ecf5SRichard Henderson prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 1456a73ecf5SRichard Henderson ret = -1; 1466a73ecf5SRichard Henderson goto exit; 1476a73ecf5SRichard Henderson } 1486a73ecf5SRichard Henderson 149a3b9af16SRichard Henderson /* Ensure that the virtual address is properly sign-extended from 150a3b9af16SRichard Henderson the last implemented virtual address bit. */ 151a3b9af16SRichard Henderson if (saddr >> TARGET_VIRT_ADDR_SPACE_BITS != saddr >> 63) { 152a3b9af16SRichard Henderson goto exit; 1534c9649a9Sj_mayer } 1544c9649a9Sj_mayer 155a3b9af16SRichard Henderson /* Translate the superpage. */ 156a3b9af16SRichard Henderson /* ??? When we do more than emulate Unix PALcode, we'll need to 157fa6e0a63SRichard Henderson determine which KSEG is actually active. */ 158fa6e0a63SRichard Henderson if (saddr < 0 && ((saddr >> 41) & 3) == 2) { 159fa6e0a63SRichard Henderson /* User-space cannot access KSEG addresses. */ 160a3b9af16SRichard Henderson if (mmu_idx != MMU_KERNEL_IDX) { 161a3b9af16SRichard Henderson goto exit; 162a3b9af16SRichard Henderson } 163a3b9af16SRichard Henderson 164fa6e0a63SRichard Henderson /* For the benefit of the Typhoon chipset, move bit 40 to bit 43. 165fa6e0a63SRichard Henderson We would not do this if the 48-bit KSEG is enabled. */ 166a3b9af16SRichard Henderson phys = saddr & ((1ull << 40) - 1); 167fa6e0a63SRichard Henderson phys |= (saddr & (1ull << 40)) << 3; 168fa6e0a63SRichard Henderson 169a3b9af16SRichard Henderson prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 170a3b9af16SRichard Henderson ret = -1; 171a3b9af16SRichard Henderson goto exit; 172a3b9af16SRichard Henderson } 173a3b9af16SRichard Henderson 174a3b9af16SRichard Henderson /* Interpret the page table exactly like PALcode does. */ 175a3b9af16SRichard Henderson 176a3b9af16SRichard Henderson pt = env->ptbr; 177a3b9af16SRichard Henderson 1786ad4d7eeSPeter Maydell /* TODO: rather than using ldq_phys() to read the page table we should 1796ad4d7eeSPeter Maydell * use address_space_ldq() so that we can handle the case when 1806ad4d7eeSPeter Maydell * the page table read gives a bus fault, rather than ignoring it. 1816ad4d7eeSPeter Maydell * For the existing code the zero data that ldq_phys will return for 1826ad4d7eeSPeter Maydell * an access to invalid memory will result in our treating the page 1836ad4d7eeSPeter Maydell * table as invalid, which may even be the right behaviour. 1846ad4d7eeSPeter Maydell */ 1856ad4d7eeSPeter Maydell 186a3b9af16SRichard Henderson /* L1 page table read. */ 187a3b9af16SRichard Henderson index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff; 1882c17449bSEdgar E. Iglesias L1pte = ldq_phys(cs->as, pt + index*8); 189a3b9af16SRichard Henderson 190a3b9af16SRichard Henderson if (unlikely((L1pte & PTE_VALID) == 0)) { 191a3b9af16SRichard Henderson ret = MM_K_TNV; 192a3b9af16SRichard Henderson goto exit; 193a3b9af16SRichard Henderson } 194a3b9af16SRichard Henderson if (unlikely((L1pte & PTE_KRE) == 0)) { 195a3b9af16SRichard Henderson goto exit; 196a3b9af16SRichard Henderson } 197a3b9af16SRichard Henderson pt = L1pte >> 32 << TARGET_PAGE_BITS; 198a3b9af16SRichard Henderson 199a3b9af16SRichard Henderson /* L2 page table read. */ 200a3b9af16SRichard Henderson index = (addr >> (TARGET_PAGE_BITS + 10)) & 0x3ff; 2012c17449bSEdgar E. Iglesias L2pte = ldq_phys(cs->as, pt + index*8); 202a3b9af16SRichard Henderson 203a3b9af16SRichard Henderson if (unlikely((L2pte & PTE_VALID) == 0)) { 204a3b9af16SRichard Henderson ret = MM_K_TNV; 205a3b9af16SRichard Henderson goto exit; 206a3b9af16SRichard Henderson } 207a3b9af16SRichard Henderson if (unlikely((L2pte & PTE_KRE) == 0)) { 208a3b9af16SRichard Henderson goto exit; 209a3b9af16SRichard Henderson } 210a3b9af16SRichard Henderson pt = L2pte >> 32 << TARGET_PAGE_BITS; 211a3b9af16SRichard Henderson 212a3b9af16SRichard Henderson /* L3 page table read. */ 213a3b9af16SRichard Henderson index = (addr >> TARGET_PAGE_BITS) & 0x3ff; 2142c17449bSEdgar E. Iglesias L3pte = ldq_phys(cs->as, pt + index*8); 215a3b9af16SRichard Henderson 216a3b9af16SRichard Henderson phys = L3pte >> 32 << TARGET_PAGE_BITS; 217a3b9af16SRichard Henderson if (unlikely((L3pte & PTE_VALID) == 0)) { 218a3b9af16SRichard Henderson ret = MM_K_TNV; 219a3b9af16SRichard Henderson goto exit; 220a3b9af16SRichard Henderson } 221a3b9af16SRichard Henderson 222a3b9af16SRichard Henderson #if PAGE_READ != 1 || PAGE_WRITE != 2 || PAGE_EXEC != 4 223a3b9af16SRichard Henderson # error page bits out of date 224a3b9af16SRichard Henderson #endif 225a3b9af16SRichard Henderson 226a3b9af16SRichard Henderson /* Check access violations. */ 227a3b9af16SRichard Henderson if (L3pte & (PTE_KRE << mmu_idx)) { 228a3b9af16SRichard Henderson prot |= PAGE_READ | PAGE_EXEC; 229a3b9af16SRichard Henderson } 230a3b9af16SRichard Henderson if (L3pte & (PTE_KWE << mmu_idx)) { 231a3b9af16SRichard Henderson prot |= PAGE_WRITE; 232a3b9af16SRichard Henderson } 233a3b9af16SRichard Henderson if (unlikely((prot & prot_need) == 0 && prot_need)) { 234a3b9af16SRichard Henderson goto exit; 235a3b9af16SRichard Henderson } 236a3b9af16SRichard Henderson 237a3b9af16SRichard Henderson /* Check fault-on-operation violations. */ 238a3b9af16SRichard Henderson prot &= ~(L3pte >> 1); 239a3b9af16SRichard Henderson ret = -1; 240a3b9af16SRichard Henderson if (unlikely((prot & prot_need) == 0)) { 241a3b9af16SRichard Henderson ret = (prot_need & PAGE_EXEC ? MM_K_FOE : 242a3b9af16SRichard Henderson prot_need & PAGE_WRITE ? MM_K_FOW : 243a3b9af16SRichard Henderson prot_need & PAGE_READ ? MM_K_FOR : -1); 244a3b9af16SRichard Henderson } 245a3b9af16SRichard Henderson 246a3b9af16SRichard Henderson exit: 247a3b9af16SRichard Henderson *pphys = phys; 248a3b9af16SRichard Henderson *pprot = prot; 249a3b9af16SRichard Henderson return ret; 250a3b9af16SRichard Henderson } 251a3b9af16SRichard Henderson 25200b941e5SAndreas Färber hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 253a3b9af16SRichard Henderson { 25400b941e5SAndreas Färber AlphaCPU *cpu = ALPHA_CPU(cs); 255a3b9af16SRichard Henderson target_ulong phys; 256a3b9af16SRichard Henderson int prot, fail; 257a3b9af16SRichard Henderson 25800b941e5SAndreas Färber fail = get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot); 259a3b9af16SRichard Henderson return (fail >= 0 ? -1 : phys); 260a3b9af16SRichard Henderson } 261a3b9af16SRichard Henderson 262e41c9452SRichard Henderson bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, 263e41c9452SRichard Henderson MMUAccessType access_type, int mmu_idx, 264e41c9452SRichard Henderson bool probe, uintptr_t retaddr) 2654c9649a9Sj_mayer { 2667510454eSAndreas Färber AlphaCPU *cpu = ALPHA_CPU(cs); 2677510454eSAndreas Färber CPUAlphaState *env = &cpu->env; 268a3b9af16SRichard Henderson target_ulong phys; 269a3b9af16SRichard Henderson int prot, fail; 270a3b9af16SRichard Henderson 271e41c9452SRichard Henderson fail = get_physical_address(env, addr, 1 << access_type, 272e41c9452SRichard Henderson mmu_idx, &phys, &prot); 273a3b9af16SRichard Henderson if (unlikely(fail >= 0)) { 274e41c9452SRichard Henderson if (probe) { 275e41c9452SRichard Henderson return false; 276e41c9452SRichard Henderson } 27727103424SAndreas Färber cs->exception_index = EXCP_MMFAULT; 278a3b9af16SRichard Henderson env->trap_arg0 = addr; 279a3b9af16SRichard Henderson env->trap_arg1 = fail; 280cb1de55aSAurelien Jarno env->trap_arg2 = (access_type == MMU_DATA_LOAD ? 0ull : 281cb1de55aSAurelien Jarno access_type == MMU_DATA_STORE ? 1ull : 282cb1de55aSAurelien Jarno /* access_type == MMU_INST_FETCH */ -1ull); 283e41c9452SRichard Henderson cpu_loop_exit_restore(cs, retaddr); 284a3b9af16SRichard Henderson } 285a3b9af16SRichard Henderson 2860c591eb0SAndreas Färber tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, 287a3b9af16SRichard Henderson prot, mmu_idx, TARGET_PAGE_SIZE); 288e41c9452SRichard Henderson return true; 289e41c9452SRichard Henderson } 2903a6fa678SRichard Henderson #endif /* USER_ONLY */ 2914c9649a9Sj_mayer 29297a8ea5aSAndreas Färber void alpha_cpu_do_interrupt(CPUState *cs) 2934c9649a9Sj_mayer { 29497a8ea5aSAndreas Färber AlphaCPU *cpu = ALPHA_CPU(cs); 29597a8ea5aSAndreas Färber CPUAlphaState *env = &cpu->env; 29627103424SAndreas Färber int i = cs->exception_index; 2973a6fa678SRichard Henderson 2983a6fa678SRichard Henderson if (qemu_loglevel_mask(CPU_LOG_INT)) { 2993a6fa678SRichard Henderson static int count; 3003a6fa678SRichard Henderson const char *name = "<unknown>"; 3013a6fa678SRichard Henderson 3023a6fa678SRichard Henderson switch (i) { 3033a6fa678SRichard Henderson case EXCP_RESET: 3043a6fa678SRichard Henderson name = "reset"; 3053a6fa678SRichard Henderson break; 3063a6fa678SRichard Henderson case EXCP_MCHK: 3073a6fa678SRichard Henderson name = "mchk"; 3083a6fa678SRichard Henderson break; 3093a6fa678SRichard Henderson case EXCP_SMP_INTERRUPT: 3103a6fa678SRichard Henderson name = "smp_interrupt"; 3113a6fa678SRichard Henderson break; 3123a6fa678SRichard Henderson case EXCP_CLK_INTERRUPT: 3133a6fa678SRichard Henderson name = "clk_interrupt"; 3143a6fa678SRichard Henderson break; 3153a6fa678SRichard Henderson case EXCP_DEV_INTERRUPT: 3163a6fa678SRichard Henderson name = "dev_interrupt"; 3173a6fa678SRichard Henderson break; 3183a6fa678SRichard Henderson case EXCP_MMFAULT: 3193a6fa678SRichard Henderson name = "mmfault"; 3203a6fa678SRichard Henderson break; 3213a6fa678SRichard Henderson case EXCP_UNALIGN: 3223a6fa678SRichard Henderson name = "unalign"; 3233a6fa678SRichard Henderson break; 3243a6fa678SRichard Henderson case EXCP_OPCDEC: 3253a6fa678SRichard Henderson name = "opcdec"; 3263a6fa678SRichard Henderson break; 3273a6fa678SRichard Henderson case EXCP_ARITH: 3283a6fa678SRichard Henderson name = "arith"; 3293a6fa678SRichard Henderson break; 3303a6fa678SRichard Henderson case EXCP_FEN: 3313a6fa678SRichard Henderson name = "fen"; 3323a6fa678SRichard Henderson break; 3333a6fa678SRichard Henderson case EXCP_CALL_PAL: 3343a6fa678SRichard Henderson name = "call_pal"; 3353a6fa678SRichard Henderson break; 3364c9649a9Sj_mayer } 337022f52e0SRichard Henderson qemu_log("INT %6d: %s(%#x) cpu=%d pc=%016" 338022f52e0SRichard Henderson PRIx64 " sp=%016" PRIx64 "\n", 339022f52e0SRichard Henderson ++count, name, env->error_code, cs->cpu_index, 340022f52e0SRichard Henderson env->pc, env->ir[IR_SP]); 3413a6fa678SRichard Henderson } 3423a6fa678SRichard Henderson 34327103424SAndreas Färber cs->exception_index = -1; 3443a6fa678SRichard Henderson 3453a6fa678SRichard Henderson #if !defined(CONFIG_USER_ONLY) 3463a6fa678SRichard Henderson switch (i) { 3473a6fa678SRichard Henderson case EXCP_RESET: 3483a6fa678SRichard Henderson i = 0x0000; 3493a6fa678SRichard Henderson break; 3503a6fa678SRichard Henderson case EXCP_MCHK: 3513a6fa678SRichard Henderson i = 0x0080; 3523a6fa678SRichard Henderson break; 3533a6fa678SRichard Henderson case EXCP_SMP_INTERRUPT: 3543a6fa678SRichard Henderson i = 0x0100; 3553a6fa678SRichard Henderson break; 3563a6fa678SRichard Henderson case EXCP_CLK_INTERRUPT: 3573a6fa678SRichard Henderson i = 0x0180; 3583a6fa678SRichard Henderson break; 3593a6fa678SRichard Henderson case EXCP_DEV_INTERRUPT: 3603a6fa678SRichard Henderson i = 0x0200; 3613a6fa678SRichard Henderson break; 3623a6fa678SRichard Henderson case EXCP_MMFAULT: 3633a6fa678SRichard Henderson i = 0x0280; 3643a6fa678SRichard Henderson break; 3653a6fa678SRichard Henderson case EXCP_UNALIGN: 3663a6fa678SRichard Henderson i = 0x0300; 3673a6fa678SRichard Henderson break; 3683a6fa678SRichard Henderson case EXCP_OPCDEC: 3693a6fa678SRichard Henderson i = 0x0380; 3703a6fa678SRichard Henderson break; 3713a6fa678SRichard Henderson case EXCP_ARITH: 3723a6fa678SRichard Henderson i = 0x0400; 3733a6fa678SRichard Henderson break; 3743a6fa678SRichard Henderson case EXCP_FEN: 3753a6fa678SRichard Henderson i = 0x0480; 3763a6fa678SRichard Henderson break; 3773a6fa678SRichard Henderson case EXCP_CALL_PAL: 3783a6fa678SRichard Henderson i = env->error_code; 3793a6fa678SRichard Henderson /* There are 64 entry points for both privileged and unprivileged, 3803a6fa678SRichard Henderson with bit 0x80 indicating unprivileged. Each entry point gets 3813a6fa678SRichard Henderson 64 bytes to do its job. */ 3823a6fa678SRichard Henderson if (i & 0x80) { 3833a6fa678SRichard Henderson i = 0x2000 + (i - 0x80) * 64; 3843a6fa678SRichard Henderson } else { 3853a6fa678SRichard Henderson i = 0x1000 + i * 64; 3863a6fa678SRichard Henderson } 3873a6fa678SRichard Henderson break; 3883a6fa678SRichard Henderson default: 389a47dddd7SAndreas Färber cpu_abort(cs, "Unhandled CPU exception"); 3903a6fa678SRichard Henderson } 3913a6fa678SRichard Henderson 3923a6fa678SRichard Henderson /* Remember where the exception happened. Emulate real hardware in 3933a6fa678SRichard Henderson that the low bit of the PC indicates PALmode. */ 394bcd2625dSRichard Henderson env->exc_addr = env->pc | (env->flags & ENV_FLAG_PAL_MODE); 3953a6fa678SRichard Henderson 3963a6fa678SRichard Henderson /* Continue execution at the PALcode entry point. */ 3973a6fa678SRichard Henderson env->pc = env->palbr + i; 3983a6fa678SRichard Henderson 3993a6fa678SRichard Henderson /* Switch to PALmode. */ 400bcd2625dSRichard Henderson env->flags |= ENV_FLAG_PAL_MODE; 4013a6fa678SRichard Henderson #endif /* !USER_ONLY */ 4023a6fa678SRichard Henderson } 4034c9649a9Sj_mayer 404dde7c241SRichard Henderson bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 405dde7c241SRichard Henderson { 406dde7c241SRichard Henderson AlphaCPU *cpu = ALPHA_CPU(cs); 407dde7c241SRichard Henderson CPUAlphaState *env = &cpu->env; 408dde7c241SRichard Henderson int idx = -1; 409dde7c241SRichard Henderson 410dde7c241SRichard Henderson /* We never take interrupts while in PALmode. */ 411bcd2625dSRichard Henderson if (env->flags & ENV_FLAG_PAL_MODE) { 412dde7c241SRichard Henderson return false; 413dde7c241SRichard Henderson } 414dde7c241SRichard Henderson 415dde7c241SRichard Henderson /* Fall through the switch, collecting the highest priority 416dde7c241SRichard Henderson interrupt that isn't masked by the processor status IPL. */ 417dde7c241SRichard Henderson /* ??? This hard-codes the OSF/1 interrupt levels. */ 418bcd2625dSRichard Henderson switch ((env->flags >> ENV_FLAG_PS_SHIFT) & PS_INT_MASK) { 419dde7c241SRichard Henderson case 0 ... 3: 420dde7c241SRichard Henderson if (interrupt_request & CPU_INTERRUPT_HARD) { 421dde7c241SRichard Henderson idx = EXCP_DEV_INTERRUPT; 422dde7c241SRichard Henderson } 423dde7c241SRichard Henderson /* FALLTHRU */ 424dde7c241SRichard Henderson case 4: 425dde7c241SRichard Henderson if (interrupt_request & CPU_INTERRUPT_TIMER) { 426dde7c241SRichard Henderson idx = EXCP_CLK_INTERRUPT; 427dde7c241SRichard Henderson } 428dde7c241SRichard Henderson /* FALLTHRU */ 429dde7c241SRichard Henderson case 5: 430dde7c241SRichard Henderson if (interrupt_request & CPU_INTERRUPT_SMP) { 431dde7c241SRichard Henderson idx = EXCP_SMP_INTERRUPT; 432dde7c241SRichard Henderson } 433dde7c241SRichard Henderson /* FALLTHRU */ 434dde7c241SRichard Henderson case 6: 435dde7c241SRichard Henderson if (interrupt_request & CPU_INTERRUPT_MCHK) { 436dde7c241SRichard Henderson idx = EXCP_MCHK; 437dde7c241SRichard Henderson } 438dde7c241SRichard Henderson } 439dde7c241SRichard Henderson if (idx >= 0) { 440dde7c241SRichard Henderson cs->exception_index = idx; 441dde7c241SRichard Henderson env->error_code = 0; 442dde7c241SRichard Henderson alpha_cpu_do_interrupt(cs); 443dde7c241SRichard Henderson return true; 444dde7c241SRichard Henderson } 445dde7c241SRichard Henderson return false; 446dde7c241SRichard Henderson } 447dde7c241SRichard Henderson 44890c84c56SMarkus Armbruster void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) 4494c9649a9Sj_mayer { 4504a247932SRichard Henderson static const char linux_reg_names[31][4] = { 4514c9649a9Sj_mayer "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", 4524c9649a9Sj_mayer "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", 4534c9649a9Sj_mayer "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", 4544a247932SRichard Henderson "t10", "t11", "ra", "t12", "at", "gp", "sp" 4554c9649a9Sj_mayer }; 456878096eeSAndreas Färber AlphaCPU *cpu = ALPHA_CPU(cs); 457878096eeSAndreas Färber CPUAlphaState *env = &cpu->env; 4584c9649a9Sj_mayer int i; 4594c9649a9Sj_mayer 46090c84c56SMarkus Armbruster qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n", 461bcd2625dSRichard Henderson env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8)); 4624c9649a9Sj_mayer for (i = 0; i < 31; i++) { 4634a247932SRichard Henderson qemu_fprintf(f, "%-8s" TARGET_FMT_lx "%c", 464a68d82b8SRichard Henderson linux_reg_names[i], cpu_alpha_load_gr(env, i), 465a68d82b8SRichard Henderson (i % 3) == 2 ? '\n' : ' '); 4664c9649a9Sj_mayer } 4676910b8f6SRichard Henderson 46890c84c56SMarkus Armbruster qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n", 4696910b8f6SRichard Henderson env->lock_addr, env->lock_value); 4706910b8f6SRichard Henderson 471a68d82b8SRichard Henderson if (flags & CPU_DUMP_FPU) { 4724c9649a9Sj_mayer for (i = 0; i < 31; i++) { 4734a247932SRichard Henderson qemu_fprintf(f, "f%-7d%016" PRIx64 "%c", i, env->fir[i], 474a68d82b8SRichard Henderson (i % 3) == 2 ? '\n' : ' '); 475a68d82b8SRichard Henderson } 4764a247932SRichard Henderson qemu_fprintf(f, "fpcr %016" PRIx64 "\n", cpu_alpha_load_fpcr(env)); 4774c9649a9Sj_mayer } 47890c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 4794c9649a9Sj_mayer } 480b9f0923eSRichard Henderson 481b9f0923eSRichard Henderson /* This should only be called from translate, via gen_excp. 482b9f0923eSRichard Henderson We expect that ENV->PC has already been updated. */ 483b9f0923eSRichard Henderson void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) 484b9f0923eSRichard Henderson { 4851c7ad260SRichard Henderson CPUState *cs = env_cpu(env); 48627103424SAndreas Färber 48727103424SAndreas Färber cs->exception_index = excp; 488b9f0923eSRichard Henderson env->error_code = error; 4895638d180SAndreas Färber cpu_loop_exit(cs); 490b9f0923eSRichard Henderson } 491b9f0923eSRichard Henderson 492b9f0923eSRichard Henderson /* This may be called from any of the helpers to set up EXCEPTION_INDEX. */ 49320503968SBlue Swirl void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, 494b9f0923eSRichard Henderson int excp, int error) 495b9f0923eSRichard Henderson { 4961c7ad260SRichard Henderson CPUState *cs = env_cpu(env); 49727103424SAndreas Färber 49827103424SAndreas Färber cs->exception_index = excp; 499b9f0923eSRichard Henderson env->error_code = error; 500a8a826a3SBlue Swirl if (retaddr) { 501afd46fcaSPavel Dovgalyuk cpu_restore_state(cs, retaddr, true); 502ba9c5de5SRichard Henderson /* Floating-point exceptions (our only users) point to the next PC. */ 503ba9c5de5SRichard Henderson env->pc += 4; 504a8a826a3SBlue Swirl } 5055638d180SAndreas Färber cpu_loop_exit(cs); 506b9f0923eSRichard Henderson } 507b9f0923eSRichard Henderson 50820503968SBlue Swirl void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr, 509b9f0923eSRichard Henderson int exc, uint64_t mask) 510b9f0923eSRichard Henderson { 511b9f0923eSRichard Henderson env->trap_arg0 = exc; 512b9f0923eSRichard Henderson env->trap_arg1 = mask; 513b9f0923eSRichard Henderson dynamic_excp(env, retaddr, EXCP_ARITH, 0); 514b9f0923eSRichard Henderson } 515