xref: /qemu/target/alpha/cpu.h (revision b36e239e08a031025e52c4191198ee8381e2e6de)
14c9649a9Sj_mayer /*
24c9649a9Sj_mayer  *  Alpha emulation cpu definitions for qemu.
34c9649a9Sj_mayer  *
44c9649a9Sj_mayer  *  Copyright (c) 2007 Jocelyn Mayer
54c9649a9Sj_mayer  *
64c9649a9Sj_mayer  * This library is free software; you can redistribute it and/or
74c9649a9Sj_mayer  * modify it under the terms of the GNU Lesser General Public
84c9649a9Sj_mayer  * License as published by the Free Software Foundation; either
9d6ea4236SChetan Pant  * version 2.1 of the License, or (at your option) any later version.
104c9649a9Sj_mayer  *
114c9649a9Sj_mayer  * This library is distributed in the hope that it will be useful,
124c9649a9Sj_mayer  * but WITHOUT ANY WARRANTY; without even the implied warranty of
134c9649a9Sj_mayer  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
144c9649a9Sj_mayer  * Lesser General Public License for more details.
154c9649a9Sj_mayer  *
164c9649a9Sj_mayer  * You should have received a copy of the GNU Lesser General Public
178167ee88SBlue Swirl  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
184c9649a9Sj_mayer  */
194c9649a9Sj_mayer 
2007f5a258SMarkus Armbruster #ifndef ALPHA_CPU_H
2107f5a258SMarkus Armbruster #define ALPHA_CPU_H
224c9649a9Sj_mayer 
231dc8e6b7SPaolo Bonzini #include "cpu-qom.h"
2474433bf0SRichard Henderson #include "exec/cpu-defs.h"
254c9649a9Sj_mayer 
265ee4f3c2SRichard Henderson /* Alpha processors have a weak memory model */
275ee4f3c2SRichard Henderson #define TCG_GUEST_DEFAULT_MO      (0)
285ee4f3c2SRichard Henderson 
294c9649a9Sj_mayer #define ICACHE_LINE_SIZE 32
304c9649a9Sj_mayer #define DCACHE_LINE_SIZE 32
314c9649a9Sj_mayer 
324c9649a9Sj_mayer /* Alpha major type */
334c9649a9Sj_mayer enum {
344c9649a9Sj_mayer     ALPHA_EV3  = 1,
354c9649a9Sj_mayer     ALPHA_EV4  = 2,
364c9649a9Sj_mayer     ALPHA_SIM  = 3,
374c9649a9Sj_mayer     ALPHA_LCA  = 4,
384c9649a9Sj_mayer     ALPHA_EV5  = 5, /* 21164 */
394c9649a9Sj_mayer     ALPHA_EV45 = 6, /* 21064A */
404c9649a9Sj_mayer     ALPHA_EV56 = 7, /* 21164A */
414c9649a9Sj_mayer };
424c9649a9Sj_mayer 
434c9649a9Sj_mayer /* EV4 minor type */
444c9649a9Sj_mayer enum {
454c9649a9Sj_mayer     ALPHA_EV4_2 = 0,
464c9649a9Sj_mayer     ALPHA_EV4_3 = 1,
474c9649a9Sj_mayer };
484c9649a9Sj_mayer 
494c9649a9Sj_mayer /* LCA minor type */
504c9649a9Sj_mayer enum {
514c9649a9Sj_mayer     ALPHA_LCA_1 = 1, /* 21066 */
524c9649a9Sj_mayer     ALPHA_LCA_2 = 2, /* 20166 */
534c9649a9Sj_mayer     ALPHA_LCA_3 = 3, /* 21068 */
544c9649a9Sj_mayer     ALPHA_LCA_4 = 4, /* 21068 */
554c9649a9Sj_mayer     ALPHA_LCA_5 = 5, /* 21066A */
564c9649a9Sj_mayer     ALPHA_LCA_6 = 6, /* 21068A */
574c9649a9Sj_mayer };
584c9649a9Sj_mayer 
594c9649a9Sj_mayer /* EV5 minor type */
604c9649a9Sj_mayer enum {
614c9649a9Sj_mayer     ALPHA_EV5_1 = 1, /* Rev BA, CA */
624c9649a9Sj_mayer     ALPHA_EV5_2 = 2, /* Rev DA, EA */
634c9649a9Sj_mayer     ALPHA_EV5_3 = 3, /* Pass 3 */
644c9649a9Sj_mayer     ALPHA_EV5_4 = 4, /* Pass 3.2 */
654c9649a9Sj_mayer     ALPHA_EV5_5 = 5, /* Pass 4 */
664c9649a9Sj_mayer };
674c9649a9Sj_mayer 
684c9649a9Sj_mayer /* EV45 minor type */
694c9649a9Sj_mayer enum {
704c9649a9Sj_mayer     ALPHA_EV45_1 = 1, /* Pass 1 */
714c9649a9Sj_mayer     ALPHA_EV45_2 = 2, /* Pass 1.1 */
724c9649a9Sj_mayer     ALPHA_EV45_3 = 3, /* Pass 2 */
734c9649a9Sj_mayer };
744c9649a9Sj_mayer 
754c9649a9Sj_mayer /* EV56 minor type */
764c9649a9Sj_mayer enum {
774c9649a9Sj_mayer     ALPHA_EV56_1 = 1, /* Pass 1 */
784c9649a9Sj_mayer     ALPHA_EV56_2 = 2, /* Pass 2 */
794c9649a9Sj_mayer };
804c9649a9Sj_mayer 
814c9649a9Sj_mayer enum {
824c9649a9Sj_mayer     IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
834c9649a9Sj_mayer     IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
844c9649a9Sj_mayer     IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
854c9649a9Sj_mayer     IMPLVER_21364 = 3, /* EV7 & EV79 */
864c9649a9Sj_mayer };
874c9649a9Sj_mayer 
884c9649a9Sj_mayer enum {
894c9649a9Sj_mayer     AMASK_BWX      = 0x00000001,
904c9649a9Sj_mayer     AMASK_FIX      = 0x00000002,
914c9649a9Sj_mayer     AMASK_CIX      = 0x00000004,
924c9649a9Sj_mayer     AMASK_MVI      = 0x00000100,
934c9649a9Sj_mayer     AMASK_TRAP     = 0x00000200,
944c9649a9Sj_mayer     AMASK_PREFETCH = 0x00001000,
954c9649a9Sj_mayer };
964c9649a9Sj_mayer 
974c9649a9Sj_mayer enum {
984c9649a9Sj_mayer     VAX_ROUND_NORMAL = 0,
994c9649a9Sj_mayer     VAX_ROUND_CHOPPED,
1004c9649a9Sj_mayer };
1014c9649a9Sj_mayer 
1024c9649a9Sj_mayer enum {
1034c9649a9Sj_mayer     IEEE_ROUND_NORMAL = 0,
1044c9649a9Sj_mayer     IEEE_ROUND_DYNAMIC,
1054c9649a9Sj_mayer     IEEE_ROUND_PLUS,
1064c9649a9Sj_mayer     IEEE_ROUND_MINUS,
1074c9649a9Sj_mayer     IEEE_ROUND_CHOPPED,
1084c9649a9Sj_mayer };
1094c9649a9Sj_mayer 
1104c9649a9Sj_mayer /* IEEE floating-point operations encoding */
1114c9649a9Sj_mayer /* Trap mode */
1124c9649a9Sj_mayer enum {
1134c9649a9Sj_mayer     FP_TRAP_I   = 0x0,
1144c9649a9Sj_mayer     FP_TRAP_U   = 0x1,
1154c9649a9Sj_mayer     FP_TRAP_S  = 0x4,
1164c9649a9Sj_mayer     FP_TRAP_SU  = 0x5,
1174c9649a9Sj_mayer     FP_TRAP_SUI = 0x7,
1184c9649a9Sj_mayer };
1194c9649a9Sj_mayer 
1204c9649a9Sj_mayer /* Rounding mode */
1214c9649a9Sj_mayer enum {
1224c9649a9Sj_mayer     FP_ROUND_CHOPPED = 0x0,
1234c9649a9Sj_mayer     FP_ROUND_MINUS   = 0x1,
1244c9649a9Sj_mayer     FP_ROUND_NORMAL  = 0x2,
1254c9649a9Sj_mayer     FP_ROUND_DYNAMIC = 0x3,
1264c9649a9Sj_mayer };
1274c9649a9Sj_mayer 
128f3d3aad4SRichard Henderson /* FPCR bits -- right-shifted 32 so we can use a uint32_t.  */
129f3d3aad4SRichard Henderson #define FPCR_SUM                (1U << (63 - 32))
130f3d3aad4SRichard Henderson #define FPCR_INED               (1U << (62 - 32))
131f3d3aad4SRichard Henderson #define FPCR_UNFD               (1U << (61 - 32))
132f3d3aad4SRichard Henderson #define FPCR_UNDZ               (1U << (60 - 32))
133f3d3aad4SRichard Henderson #define FPCR_DYN_SHIFT          (58 - 32)
134f3d3aad4SRichard Henderson #define FPCR_DYN_CHOPPED        (0U << FPCR_DYN_SHIFT)
135f3d3aad4SRichard Henderson #define FPCR_DYN_MINUS          (1U << FPCR_DYN_SHIFT)
136f3d3aad4SRichard Henderson #define FPCR_DYN_NORMAL         (2U << FPCR_DYN_SHIFT)
137f3d3aad4SRichard Henderson #define FPCR_DYN_PLUS           (3U << FPCR_DYN_SHIFT)
138f3d3aad4SRichard Henderson #define FPCR_DYN_MASK           (3U << FPCR_DYN_SHIFT)
139f3d3aad4SRichard Henderson #define FPCR_IOV                (1U << (57 - 32))
140f3d3aad4SRichard Henderson #define FPCR_INE                (1U << (56 - 32))
141f3d3aad4SRichard Henderson #define FPCR_UNF                (1U << (55 - 32))
142f3d3aad4SRichard Henderson #define FPCR_OVF                (1U << (54 - 32))
143f3d3aad4SRichard Henderson #define FPCR_DZE                (1U << (53 - 32))
144f3d3aad4SRichard Henderson #define FPCR_INV                (1U << (52 - 32))
145f3d3aad4SRichard Henderson #define FPCR_OVFD               (1U << (51 - 32))
146f3d3aad4SRichard Henderson #define FPCR_DZED               (1U << (50 - 32))
147f3d3aad4SRichard Henderson #define FPCR_INVD               (1U << (49 - 32))
148f3d3aad4SRichard Henderson #define FPCR_DNZ                (1U << (48 - 32))
149f3d3aad4SRichard Henderson #define FPCR_DNOD               (1U << (47 - 32))
150ba0e276dSRichard Henderson #define FPCR_STATUS_MASK        (FPCR_IOV | FPCR_INE | FPCR_UNF \
151ba0e276dSRichard Henderson                                  | FPCR_OVF | FPCR_DZE | FPCR_INV)
152ba0e276dSRichard Henderson 
153ba0e276dSRichard Henderson /* The silly software trap enables implemented by the kernel emulation.
154ba0e276dSRichard Henderson    These are more or less architecturally required, since the real hardware
155ba0e276dSRichard Henderson    has read-as-zero bits in the FPCR when the features aren't implemented.
156ba0e276dSRichard Henderson    For the purposes of QEMU, we pretend the FPCR can hold everything.  */
157f3d3aad4SRichard Henderson #define SWCR_TRAP_ENABLE_INV    (1U << 1)
158f3d3aad4SRichard Henderson #define SWCR_TRAP_ENABLE_DZE    (1U << 2)
159f3d3aad4SRichard Henderson #define SWCR_TRAP_ENABLE_OVF    (1U << 3)
160f3d3aad4SRichard Henderson #define SWCR_TRAP_ENABLE_UNF    (1U << 4)
161f3d3aad4SRichard Henderson #define SWCR_TRAP_ENABLE_INE    (1U << 5)
162f3d3aad4SRichard Henderson #define SWCR_TRAP_ENABLE_DNO    (1U << 6)
163f3d3aad4SRichard Henderson #define SWCR_TRAP_ENABLE_MASK   ((1U << 7) - (1U << 1))
164ba0e276dSRichard Henderson 
165f3d3aad4SRichard Henderson #define SWCR_MAP_DMZ            (1U << 12)
166f3d3aad4SRichard Henderson #define SWCR_MAP_UMZ            (1U << 13)
167ba0e276dSRichard Henderson #define SWCR_MAP_MASK           (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
168ba0e276dSRichard Henderson 
169f3d3aad4SRichard Henderson #define SWCR_STATUS_INV         (1U << 17)
170f3d3aad4SRichard Henderson #define SWCR_STATUS_DZE         (1U << 18)
171f3d3aad4SRichard Henderson #define SWCR_STATUS_OVF         (1U << 19)
172f3d3aad4SRichard Henderson #define SWCR_STATUS_UNF         (1U << 20)
173f3d3aad4SRichard Henderson #define SWCR_STATUS_INE         (1U << 21)
174f3d3aad4SRichard Henderson #define SWCR_STATUS_DNO         (1U << 22)
175f3d3aad4SRichard Henderson #define SWCR_STATUS_MASK        ((1U << 23) - (1U << 17))
176ba0e276dSRichard Henderson 
17721ba8564SRichard Henderson #define SWCR_STATUS_TO_EXCSUM_SHIFT  16
17821ba8564SRichard Henderson 
179ba0e276dSRichard Henderson #define SWCR_MASK  (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
180ba0e276dSRichard Henderson 
1818417845eSRichard Henderson /* MMU modes definitions */
1824c9649a9Sj_mayer 
1836a73ecf5SRichard Henderson /* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User.
1848417845eSRichard Henderson    The Unix PALcode only exposes the kernel and user modes; presumably
1858417845eSRichard Henderson    executive and supervisor are used by VMS.
1868417845eSRichard Henderson 
1878417845eSRichard Henderson    PALcode itself uses physical mode for code and kernel mode for data;
1888417845eSRichard Henderson    there are PALmode instructions that can access data via physical mode
1898417845eSRichard Henderson    or via an os-installed "alternate mode", which is one of the 4 above.
1908417845eSRichard Henderson 
1916a73ecf5SRichard Henderson    That said, we're only emulating Unix PALcode, and not attempting VMS,
1926a73ecf5SRichard Henderson    so we don't need to implement Executive and Supervisor.  QEMU's own
1936a73ecf5SRichard Henderson    PALcode cheats and usees the KSEG mapping for its code+data rather than
1946a73ecf5SRichard Henderson    physical addresses.  */
1958417845eSRichard Henderson 
1968417845eSRichard Henderson #define MMU_KERNEL_IDX   0
1978417845eSRichard Henderson #define MMU_USER_IDX     1
1986a73ecf5SRichard Henderson #define MMU_PHYS_IDX     2
1998417845eSRichard Henderson 
2001ea4a06aSPhilippe Mathieu-Daudé typedef struct CPUArchState {
2014c9649a9Sj_mayer     uint64_t ir[31];
2024c9649a9Sj_mayer     float64 fir[31];
2034c9649a9Sj_mayer     uint64_t pc;
2044c9649a9Sj_mayer     uint64_t unique;
2056910b8f6SRichard Henderson     uint64_t lock_addr;
2066910b8f6SRichard Henderson     uint64_t lock_value;
207f3d3aad4SRichard Henderson 
208f3d3aad4SRichard Henderson     /* The FPCR, and disassembled portions thereof.  */
209f3d3aad4SRichard Henderson     uint32_t fpcr;
21021ba8564SRichard Henderson #ifdef CONFIG_USER_ONLY
21121ba8564SRichard Henderson     uint32_t swcr;
21221ba8564SRichard Henderson #endif
213f3d3aad4SRichard Henderson     uint32_t fpcr_exc_enable;
2148443effbSRichard Henderson     float_status fp_status;
2158443effbSRichard Henderson     uint8_t fpcr_dyn_round;
2168443effbSRichard Henderson     uint8_t fpcr_flush_to_zero;
2178443effbSRichard Henderson 
218bcd2625dSRichard Henderson     /* Mask of PALmode, Processor State et al.  Most of this gets copied
219bcd2625dSRichard Henderson        into the TranslatorBlock flags and controls code generation.  */
220bcd2625dSRichard Henderson     uint32_t flags;
22126b46094SRichard Henderson 
222bcd2625dSRichard Henderson     /* The high 32-bits of the processor cycle counter.  */
22326b46094SRichard Henderson     uint32_t pcc_ofs;
224129d8aa5SRichard Henderson 
225129d8aa5SRichard Henderson     /* These pass data from the exception logic in the translator and
226129d8aa5SRichard Henderson        helpers to the OS entry point.  This is used for both system
227129d8aa5SRichard Henderson        emulation and user-mode.  */
228129d8aa5SRichard Henderson     uint64_t trap_arg0;
229129d8aa5SRichard Henderson     uint64_t trap_arg1;
230129d8aa5SRichard Henderson     uint64_t trap_arg2;
2314c9649a9Sj_mayer 
23226b46094SRichard Henderson #if !defined(CONFIG_USER_ONLY)
23326b46094SRichard Henderson     /* The internal data required by our emulation of the Unix PALcode.  */
23426b46094SRichard Henderson     uint64_t exc_addr;
23526b46094SRichard Henderson     uint64_t palbr;
23626b46094SRichard Henderson     uint64_t ptbr;
23726b46094SRichard Henderson     uint64_t vptptr;
23826b46094SRichard Henderson     uint64_t sysval;
23926b46094SRichard Henderson     uint64_t usp;
24026b46094SRichard Henderson     uint64_t shadow[8];
24126b46094SRichard Henderson     uint64_t scratch[24];
24226b46094SRichard Henderson #endif
24326b46094SRichard Henderson 
244c781cf96SRichard Henderson     /* This alarm doesn't exist in real hardware; we wish it did.  */
245c781cf96SRichard Henderson     uint64_t alarm_expire;
246c781cf96SRichard Henderson 
2474c9649a9Sj_mayer     int error_code;
2484c9649a9Sj_mayer 
2494c9649a9Sj_mayer     uint32_t features;
2504c9649a9Sj_mayer     uint32_t amask;
2514c9649a9Sj_mayer     int implver;
2521ea4a06aSPhilippe Mathieu-Daudé } CPUAlphaState;
2534c9649a9Sj_mayer 
2541dc8e6b7SPaolo Bonzini /**
2551dc8e6b7SPaolo Bonzini  * AlphaCPU:
2561dc8e6b7SPaolo Bonzini  * @env: #CPUAlphaState
2571dc8e6b7SPaolo Bonzini  *
2581dc8e6b7SPaolo Bonzini  * An Alpha CPU.
2591dc8e6b7SPaolo Bonzini  */
260*b36e239eSPhilippe Mathieu-Daudé struct ArchCPU {
2611dc8e6b7SPaolo Bonzini     /*< private >*/
2621dc8e6b7SPaolo Bonzini     CPUState parent_obj;
2631dc8e6b7SPaolo Bonzini     /*< public >*/
2641dc8e6b7SPaolo Bonzini 
2655b146dc7SRichard Henderson     CPUNegativeOffsetState neg;
2661dc8e6b7SPaolo Bonzini     CPUAlphaState env;
2671dc8e6b7SPaolo Bonzini 
2681dc8e6b7SPaolo Bonzini     /* This alarm doesn't exist in real hardware; we wish it did.  */
2691dc8e6b7SPaolo Bonzini     QEMUTimer *alarm_timer;
2701dc8e6b7SPaolo Bonzini };
2711dc8e6b7SPaolo Bonzini 
2721dc8e6b7SPaolo Bonzini 
2731dc8e6b7SPaolo Bonzini #ifndef CONFIG_USER_ONLY
2748a9358ccSMarkus Armbruster extern const VMStateDescription vmstate_alpha_cpu;
2751dc8e6b7SPaolo Bonzini 
2761dc8e6b7SPaolo Bonzini void alpha_cpu_do_interrupt(CPUState *cpu);
2771dc8e6b7SPaolo Bonzini bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
2789354e694SPhilippe Mathieu-Daudé #endif /* !CONFIG_USER_ONLY */
27990c84c56SMarkus Armbruster void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
2801dc8e6b7SPaolo Bonzini hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
281a010bdbeSAlex Bennée int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
2821dc8e6b7SPaolo Bonzini int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
2831dc8e6b7SPaolo Bonzini 
284494342b3SAndreas Färber #define cpu_list alpha_cpu_list
2859467d44cSths 
286022c62cbSPaolo Bonzini #include "exec/cpu-all.h"
2874c9649a9Sj_mayer 
2884c9649a9Sj_mayer enum {
2894c9649a9Sj_mayer     FEATURE_ASN    = 0x00000001,
2904c9649a9Sj_mayer     FEATURE_SPS    = 0x00000002,
2914c9649a9Sj_mayer     FEATURE_VIRBND = 0x00000004,
2924c9649a9Sj_mayer     FEATURE_TBCHK  = 0x00000008,
2934c9649a9Sj_mayer };
2944c9649a9Sj_mayer 
2954c9649a9Sj_mayer enum {
29607b6c13bSRichard Henderson     EXCP_RESET,
29707b6c13bSRichard Henderson     EXCP_MCHK,
29807b6c13bSRichard Henderson     EXCP_SMP_INTERRUPT,
29907b6c13bSRichard Henderson     EXCP_CLK_INTERRUPT,
30007b6c13bSRichard Henderson     EXCP_DEV_INTERRUPT,
30107b6c13bSRichard Henderson     EXCP_MMFAULT,
30207b6c13bSRichard Henderson     EXCP_UNALIGN,
30307b6c13bSRichard Henderson     EXCP_OPCDEC,
30407b6c13bSRichard Henderson     EXCP_ARITH,
30507b6c13bSRichard Henderson     EXCP_FEN,
30607b6c13bSRichard Henderson     EXCP_CALL_PAL,
3074c9649a9Sj_mayer };
3084c9649a9Sj_mayer 
3096a80e088SRichard Henderson /* Alpha-specific interrupt pending bits.  */
3106a80e088SRichard Henderson #define CPU_INTERRUPT_TIMER	CPU_INTERRUPT_TGT_EXT_0
3116a80e088SRichard Henderson #define CPU_INTERRUPT_SMP	CPU_INTERRUPT_TGT_EXT_1
3126a80e088SRichard Henderson #define CPU_INTERRUPT_MCHK	CPU_INTERRUPT_TGT_EXT_2
3136a80e088SRichard Henderson 
314a3b9af16SRichard Henderson /* OSF/1 Page table bits.  */
315a3b9af16SRichard Henderson enum {
316a3b9af16SRichard Henderson     PTE_VALID = 0x0001,
317a3b9af16SRichard Henderson     PTE_FOR   = 0x0002,  /* used for page protection (fault on read) */
318a3b9af16SRichard Henderson     PTE_FOW   = 0x0004,  /* used for page protection (fault on write) */
319a3b9af16SRichard Henderson     PTE_FOE   = 0x0008,  /* used for page protection (fault on exec) */
320a3b9af16SRichard Henderson     PTE_ASM   = 0x0010,
321a3b9af16SRichard Henderson     PTE_KRE   = 0x0100,
322a3b9af16SRichard Henderson     PTE_URE   = 0x0200,
323a3b9af16SRichard Henderson     PTE_KWE   = 0x1000,
324a3b9af16SRichard Henderson     PTE_UWE   = 0x2000
325a3b9af16SRichard Henderson };
326a3b9af16SRichard Henderson 
327ea879fc7SRichard Henderson /* Hardware interrupt (entInt) constants.  */
328ea879fc7SRichard Henderson enum {
329ea879fc7SRichard Henderson     INT_K_IP,
330ea879fc7SRichard Henderson     INT_K_CLK,
331ea879fc7SRichard Henderson     INT_K_MCHK,
332ea879fc7SRichard Henderson     INT_K_DEV,
333ea879fc7SRichard Henderson     INT_K_PERF,
334ea879fc7SRichard Henderson };
335ea879fc7SRichard Henderson 
336ea879fc7SRichard Henderson /* Memory management (entMM) constants.  */
337ea879fc7SRichard Henderson enum {
338ea879fc7SRichard Henderson     MM_K_TNV,
339ea879fc7SRichard Henderson     MM_K_ACV,
340ea879fc7SRichard Henderson     MM_K_FOR,
341ea879fc7SRichard Henderson     MM_K_FOE,
342ea879fc7SRichard Henderson     MM_K_FOW
343ea879fc7SRichard Henderson };
344ea879fc7SRichard Henderson 
345ea879fc7SRichard Henderson /* Arithmetic exception (entArith) constants.  */
346ea879fc7SRichard Henderson enum {
347ea879fc7SRichard Henderson     EXC_M_SWC = 1,      /* Software completion */
348ea879fc7SRichard Henderson     EXC_M_INV = 2,      /* Invalid operation */
349ea879fc7SRichard Henderson     EXC_M_DZE = 4,      /* Division by zero */
350ea879fc7SRichard Henderson     EXC_M_FOV = 8,      /* Overflow */
351ea879fc7SRichard Henderson     EXC_M_UNF = 16,     /* Underflow */
352ea879fc7SRichard Henderson     EXC_M_INE = 32,     /* Inexact result */
353ea879fc7SRichard Henderson     EXC_M_IOV = 64      /* Integer Overflow */
354ea879fc7SRichard Henderson };
355ea879fc7SRichard Henderson 
356ea879fc7SRichard Henderson /* Processor status constants.  */
357ea879fc7SRichard Henderson /* Low 3 bits are interrupt mask level.  */
358bcd2625dSRichard Henderson #define PS_INT_MASK   7u
359ea879fc7SRichard Henderson 
360ea879fc7SRichard Henderson /* Bits 4 and 5 are the mmu mode.  The VMS PALcode uses all 4 modes;
361ea879fc7SRichard Henderson    The Unix PALcode only uses bit 4.  */
362bcd2625dSRichard Henderson #define PS_USER_MODE  8u
363bcd2625dSRichard Henderson 
364bcd2625dSRichard Henderson /* CPUAlphaState->flags constants.  These are layed out so that we
365bcd2625dSRichard Henderson    can set or reset the pieces individually by assigning to the byte,
366bcd2625dSRichard Henderson    or manipulated as a whole.  */
367bcd2625dSRichard Henderson 
368bcd2625dSRichard Henderson #define ENV_FLAG_PAL_SHIFT    0
369bcd2625dSRichard Henderson #define ENV_FLAG_PS_SHIFT     8
370bcd2625dSRichard Henderson #define ENV_FLAG_RX_SHIFT     16
371bcd2625dSRichard Henderson #define ENV_FLAG_FEN_SHIFT    24
372bcd2625dSRichard Henderson 
373bcd2625dSRichard Henderson #define ENV_FLAG_PAL_MODE     (1u << ENV_FLAG_PAL_SHIFT)
374bcd2625dSRichard Henderson #define ENV_FLAG_PS_USER      (PS_USER_MODE << ENV_FLAG_PS_SHIFT)
375bcd2625dSRichard Henderson #define ENV_FLAG_RX_FLAG      (1u << ENV_FLAG_RX_SHIFT)
376bcd2625dSRichard Henderson #define ENV_FLAG_FEN          (1u << ENV_FLAG_FEN_SHIFT)
377bcd2625dSRichard Henderson 
378bcd2625dSRichard Henderson #define ENV_FLAG_TB_MASK \
379bcd2625dSRichard Henderson     (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN)
380ea879fc7SRichard Henderson 
381fed14246SRichard Henderson #define TB_FLAG_UNALIGN       (1u << 1)
382fed14246SRichard Henderson 
38397ed5ccdSBenjamin Herrenschmidt static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
384ea879fc7SRichard Henderson {
385bcd2625dSRichard Henderson     int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
386bcd2625dSRichard Henderson     if (env->flags & ENV_FLAG_PAL_MODE) {
387bcd2625dSRichard Henderson         ret = MMU_KERNEL_IDX;
388bba9bdceSRichard Henderson     }
389bcd2625dSRichard Henderson     return ret;
390ea879fc7SRichard Henderson }
3914c9649a9Sj_mayer 
3924c9649a9Sj_mayer enum {
3934c9649a9Sj_mayer     IR_V0   = 0,
3944c9649a9Sj_mayer     IR_T0   = 1,
3954c9649a9Sj_mayer     IR_T1   = 2,
3964c9649a9Sj_mayer     IR_T2   = 3,
3974c9649a9Sj_mayer     IR_T3   = 4,
3984c9649a9Sj_mayer     IR_T4   = 5,
3994c9649a9Sj_mayer     IR_T5   = 6,
4004c9649a9Sj_mayer     IR_T6   = 7,
4014c9649a9Sj_mayer     IR_T7   = 8,
4024c9649a9Sj_mayer     IR_S0   = 9,
4034c9649a9Sj_mayer     IR_S1   = 10,
4044c9649a9Sj_mayer     IR_S2   = 11,
4054c9649a9Sj_mayer     IR_S3   = 12,
4064c9649a9Sj_mayer     IR_S4   = 13,
4074c9649a9Sj_mayer     IR_S5   = 14,
4084c9649a9Sj_mayer     IR_S6   = 15,
409a4b388ffSRichard Henderson     IR_FP   = IR_S6,
4104c9649a9Sj_mayer     IR_A0   = 16,
4114c9649a9Sj_mayer     IR_A1   = 17,
4124c9649a9Sj_mayer     IR_A2   = 18,
4134c9649a9Sj_mayer     IR_A3   = 19,
4144c9649a9Sj_mayer     IR_A4   = 20,
4154c9649a9Sj_mayer     IR_A5   = 21,
4164c9649a9Sj_mayer     IR_T8   = 22,
4174c9649a9Sj_mayer     IR_T9   = 23,
4184c9649a9Sj_mayer     IR_T10  = 24,
4194c9649a9Sj_mayer     IR_T11  = 25,
4204c9649a9Sj_mayer     IR_RA   = 26,
4214c9649a9Sj_mayer     IR_T12  = 27,
422a4b388ffSRichard Henderson     IR_PV   = IR_T12,
4234c9649a9Sj_mayer     IR_AT   = 28,
4244c9649a9Sj_mayer     IR_GP   = 29,
4254c9649a9Sj_mayer     IR_SP   = 30,
4264c9649a9Sj_mayer     IR_ZERO = 31,
4274c9649a9Sj_mayer };
4284c9649a9Sj_mayer 
4290c28246fSAndreas Färber void alpha_translate_init(void);
4300c28246fSAndreas Färber 
43173a25e83SIgor Mammedov #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
43273a25e83SIgor Mammedov #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
4330dacec87SIgor Mammedov #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
43473a25e83SIgor Mammedov 
4350442428aSMarkus Armbruster void alpha_cpu_list(void);
43620503968SBlue Swirl void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
43720503968SBlue Swirl void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
43895870356Saurel32 
4394d5712f1SAndreas Färber uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
4404d5712f1SAndreas Färber void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
44159124384SRichard Henderson uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);
44259124384SRichard Henderson void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);
44390113883SRichard Henderson 
44490113883SRichard Henderson #ifdef CONFIG_USER_ONLY
44590113883SRichard Henderson void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
44690113883SRichard Henderson                               MMUAccessType access_type,
44790113883SRichard Henderson                               bool maperr, uintptr_t retaddr);
448e7424abcSRichard Henderson void alpha_cpu_record_sigbus(CPUState *cs, vaddr address,
449e7424abcSRichard Henderson                              MMUAccessType access_type, uintptr_t retaddr);
45090113883SRichard Henderson #else
45190113883SRichard Henderson bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
45290113883SRichard Henderson                         MMUAccessType access_type, int mmu_idx,
45390113883SRichard Henderson                         bool probe, uintptr_t retaddr);
454e7424abcSRichard Henderson void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
455e7424abcSRichard Henderson                                    MMUAccessType access_type, int mmu_idx,
456e7424abcSRichard Henderson                                    uintptr_t retaddr) QEMU_NORETURN;
4576ad4d7eeSPeter Maydell void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
4586ad4d7eeSPeter Maydell                                      vaddr addr, unsigned size,
4596ad4d7eeSPeter Maydell                                      MMUAccessType access_type,
4606ad4d7eeSPeter Maydell                                      int mmu_idx, MemTxAttrs attrs,
4616ad4d7eeSPeter Maydell                                      MemTxResult response, uintptr_t retaddr);
4625b450407SRichard Henderson #endif
4634c9649a9Sj_mayer 
4644d5712f1SAndreas Färber static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
46589fee74aSEmilio G. Cota                                         target_ulong *cs_base, uint32_t *pflags)
4666b917547Saliguori {
4676b917547Saliguori     *pc = env->pc;
4686b917547Saliguori     *cs_base = 0;
469bcd2625dSRichard Henderson     *pflags = env->flags & ENV_FLAG_TB_MASK;
470fed14246SRichard Henderson #ifdef CONFIG_USER_ONLY
471fed14246SRichard Henderson     *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
472fed14246SRichard Henderson #endif
4736b917547Saliguori }
4746b917547Saliguori 
47521ba8564SRichard Henderson #ifdef CONFIG_USER_ONLY
47621ba8564SRichard Henderson /* Copied from linux ieee_swcr_to_fpcr.  */
47721ba8564SRichard Henderson static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
47821ba8564SRichard Henderson {
47921ba8564SRichard Henderson     uint64_t fpcr = 0;
48021ba8564SRichard Henderson 
48121ba8564SRichard Henderson     fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
48221ba8564SRichard Henderson     fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
48321ba8564SRichard Henderson     fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
48421ba8564SRichard Henderson                       | SWCR_TRAP_ENABLE_DZE
48521ba8564SRichard Henderson                       | SWCR_TRAP_ENABLE_OVF)) << 48;
48621ba8564SRichard Henderson     fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
48721ba8564SRichard Henderson                       | SWCR_TRAP_ENABLE_INE)) << 57;
48821ba8564SRichard Henderson     fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
48921ba8564SRichard Henderson     fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
49021ba8564SRichard Henderson 
49121ba8564SRichard Henderson     return fpcr;
49221ba8564SRichard Henderson }
49321ba8564SRichard Henderson 
49421ba8564SRichard Henderson /* Copied from linux ieee_fpcr_to_swcr.  */
49521ba8564SRichard Henderson static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr)
49621ba8564SRichard Henderson {
49721ba8564SRichard Henderson     uint64_t swcr = 0;
49821ba8564SRichard Henderson 
49921ba8564SRichard Henderson     swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
50021ba8564SRichard Henderson     swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
50121ba8564SRichard Henderson     swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
50221ba8564SRichard Henderson                              | SWCR_TRAP_ENABLE_DZE
50321ba8564SRichard Henderson                              | SWCR_TRAP_ENABLE_OVF);
50421ba8564SRichard Henderson     swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE);
50521ba8564SRichard Henderson     swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
50621ba8564SRichard Henderson     swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
50721ba8564SRichard Henderson 
50821ba8564SRichard Henderson     return swcr;
50921ba8564SRichard Henderson }
51021ba8564SRichard Henderson #endif /* CONFIG_USER_ONLY */
51121ba8564SRichard Henderson 
51207f5a258SMarkus Armbruster #endif /* ALPHA_CPU_H */
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