1 /* 2 * QEMU Alpha CPU 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "exec/translation-block.h" 27 #include "exec/target_page.h" 28 #include "accel/tcg/cpu-ops.h" 29 #include "fpu/softfloat.h" 30 31 32 static void alpha_cpu_set_pc(CPUState *cs, vaddr value) 33 { 34 CPUAlphaState *env = cpu_env(cs); 35 env->pc = value; 36 } 37 38 static vaddr alpha_cpu_get_pc(CPUState *cs) 39 { 40 CPUAlphaState *env = cpu_env(cs); 41 return env->pc; 42 } 43 44 static TCGTBCPUState alpha_get_tb_cpu_state(CPUState *cs) 45 { 46 CPUAlphaState *env = cpu_env(cs); 47 uint32_t flags = env->flags & ENV_FLAG_TB_MASK; 48 49 #ifdef CONFIG_USER_ONLY 50 flags |= TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; 51 #endif 52 53 return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; 54 } 55 56 static void alpha_cpu_synchronize_from_tb(CPUState *cs, 57 const TranslationBlock *tb) 58 { 59 /* The program counter is always up to date with CF_PCREL. */ 60 if (!(tb_cflags(tb) & CF_PCREL)) { 61 CPUAlphaState *env = cpu_env(cs); 62 env->pc = tb->pc; 63 } 64 } 65 66 static void alpha_restore_state_to_opc(CPUState *cs, 67 const TranslationBlock *tb, 68 const uint64_t *data) 69 { 70 CPUAlphaState *env = cpu_env(cs); 71 72 if (tb_cflags(tb) & CF_PCREL) { 73 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 74 } else { 75 env->pc = data[0]; 76 } 77 } 78 79 #ifndef CONFIG_USER_ONLY 80 static bool alpha_cpu_has_work(CPUState *cs) 81 { 82 /* Here we are checking to see if the CPU should wake up from HALT. 83 We will have gotten into this state only for WTINT from PALmode. */ 84 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU 85 asleep even if (some) interrupts have been asserted. For now, 86 assume that if a CPU really wants to stay asleep, it will mask 87 interrupts at the chipset level, which will prevent these bits 88 from being set in the first place. */ 89 return cs->interrupt_request & (CPU_INTERRUPT_HARD 90 | CPU_INTERRUPT_TIMER 91 | CPU_INTERRUPT_SMP 92 | CPU_INTERRUPT_MCHK); 93 } 94 #endif /* !CONFIG_USER_ONLY */ 95 96 static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) 97 { 98 return alpha_env_mmu_index(cpu_env(cs)); 99 } 100 101 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 102 { 103 info->endian = BFD_ENDIAN_LITTLE; 104 info->mach = bfd_mach_alpha_ev6; 105 info->print_insn = print_insn_alpha; 106 } 107 108 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) 109 { 110 CPUState *cs = CPU(dev); 111 AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); 112 Error *local_err = NULL; 113 114 #ifndef CONFIG_USER_ONLY 115 /* Use pc-relative instructions in system-mode */ 116 cs->tcg_cflags |= CF_PCREL; 117 #endif 118 119 cpu_exec_realizefn(cs, &local_err); 120 if (local_err != NULL) { 121 error_propagate(errp, local_err); 122 return; 123 } 124 125 qemu_init_vcpu(cs); 126 127 acc->parent_realize(dev, errp); 128 } 129 130 /* Models */ 131 typedef struct AlphaCPUAlias { 132 const char *alias; 133 const char *typename; 134 } AlphaCPUAlias; 135 136 static const AlphaCPUAlias alpha_cpu_aliases[] = { 137 { "21064", ALPHA_CPU_TYPE_NAME("ev4") }, 138 { "21164", ALPHA_CPU_TYPE_NAME("ev5") }, 139 { "21164a", ALPHA_CPU_TYPE_NAME("ev56") }, 140 { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") }, 141 { "21264", ALPHA_CPU_TYPE_NAME("ev6") }, 142 { "21264a", ALPHA_CPU_TYPE_NAME("ev67") }, 143 }; 144 145 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) 146 { 147 ObjectClass *oc; 148 char *typename; 149 int i; 150 151 oc = object_class_by_name(cpu_model); 152 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) { 153 return oc; 154 } 155 156 for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { 157 if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { 158 oc = object_class_by_name(alpha_cpu_aliases[i].typename); 159 assert(oc != NULL && !object_class_is_abstract(oc)); 160 return oc; 161 } 162 } 163 164 typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model); 165 oc = object_class_by_name(typename); 166 g_free(typename); 167 168 return oc; 169 } 170 171 static void ev4_cpu_initfn(Object *obj) 172 { 173 cpu_env(CPU(obj))->implver = IMPLVER_2106x; 174 } 175 176 static void ev5_cpu_initfn(Object *obj) 177 { 178 cpu_env(CPU(obj))->implver = IMPLVER_21164; 179 } 180 181 static void ev56_cpu_initfn(Object *obj) 182 { 183 cpu_env(CPU(obj))->amask |= AMASK_BWX; 184 } 185 186 static void pca56_cpu_initfn(Object *obj) 187 { 188 cpu_env(CPU(obj))->amask |= AMASK_MVI; 189 } 190 191 static void ev6_cpu_initfn(Object *obj) 192 { 193 CPUAlphaState *env = cpu_env(CPU(obj)); 194 195 env->implver = IMPLVER_21264; 196 env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; 197 } 198 199 static void ev67_cpu_initfn(Object *obj) 200 { 201 cpu_env(CPU(obj))->amask |= AMASK_CIX | AMASK_PREFETCH; 202 } 203 204 static void alpha_cpu_initfn(Object *obj) 205 { 206 CPUAlphaState *env = cpu_env(CPU(obj)); 207 208 /* TODO all this should be done in reset, not init */ 209 210 env->lock_addr = -1; 211 212 /* 213 * TODO: this is incorrect. The Alpha Architecture Handbook version 4 214 * describes NaN propagation in section 4.7.10.4. We should prefer 215 * the operand in Fb (whether it is a QNaN or an SNaN), then the 216 * operand in Fa. That is float_2nan_prop_ba. 217 */ 218 set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); 219 /* Default NaN: sign bit clear, msb frac bit set */ 220 set_float_default_nan_pattern(0b01000000, &env->fp_status); 221 /* 222 * TODO: this is incorrect. The Alpha Architecture Handbook version 4 223 * section 4.7.7.11 says that we flush to zero for underflow cases, so 224 * this should be float_ftz_after_rounding to match the 225 * tininess_after_rounding (which is specified in section 4.7.5). 226 */ 227 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); 228 #if defined(CONFIG_USER_ONLY) 229 env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; 230 cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD 231 | FPCR_UNFD | FPCR_INED | FPCR_DNOD 232 | FPCR_DYN_NORMAL) << 32); 233 #else 234 env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; 235 #endif 236 } 237 238 #ifndef CONFIG_USER_ONLY 239 #include "hw/core/sysemu-cpu-ops.h" 240 241 static const struct SysemuCPUOps alpha_sysemu_ops = { 242 .has_work = alpha_cpu_has_work, 243 .get_phys_page_debug = alpha_cpu_get_phys_page_debug, 244 }; 245 #endif 246 247 static const TCGCPUOps alpha_tcg_ops = { 248 /* Alpha processors have a weak memory model */ 249 .guest_default_memory_order = 0, 250 .mttcg_supported = true, 251 252 .initialize = alpha_translate_init, 253 .translate_code = alpha_translate_code, 254 .get_tb_cpu_state = alpha_get_tb_cpu_state, 255 .synchronize_from_tb = alpha_cpu_synchronize_from_tb, 256 .restore_state_to_opc = alpha_restore_state_to_opc, 257 .mmu_index = alpha_cpu_mmu_index, 258 259 #ifdef CONFIG_USER_ONLY 260 .record_sigsegv = alpha_cpu_record_sigsegv, 261 .record_sigbus = alpha_cpu_record_sigbus, 262 #else 263 .tlb_fill = alpha_cpu_tlb_fill, 264 .pointer_wrap = cpu_pointer_wrap_notreached, 265 .cpu_exec_interrupt = alpha_cpu_exec_interrupt, 266 .cpu_exec_halt = alpha_cpu_has_work, 267 .cpu_exec_reset = cpu_reset, 268 .do_interrupt = alpha_cpu_do_interrupt, 269 .do_transaction_failed = alpha_cpu_do_transaction_failed, 270 .do_unaligned_access = alpha_cpu_do_unaligned_access, 271 #endif /* !CONFIG_USER_ONLY */ 272 }; 273 274 static void alpha_cpu_class_init(ObjectClass *oc, const void *data) 275 { 276 DeviceClass *dc = DEVICE_CLASS(oc); 277 CPUClass *cc = CPU_CLASS(oc); 278 AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc); 279 280 device_class_set_parent_realize(dc, alpha_cpu_realizefn, 281 &acc->parent_realize); 282 283 cc->class_by_name = alpha_cpu_class_by_name; 284 cc->dump_state = alpha_cpu_dump_state; 285 cc->set_pc = alpha_cpu_set_pc; 286 cc->get_pc = alpha_cpu_get_pc; 287 cc->gdb_read_register = alpha_cpu_gdb_read_register; 288 cc->gdb_write_register = alpha_cpu_gdb_write_register; 289 #ifndef CONFIG_USER_ONLY 290 dc->vmsd = &vmstate_alpha_cpu; 291 cc->sysemu_ops = &alpha_sysemu_ops; 292 #endif 293 cc->disas_set_info = alpha_cpu_disas_set_info; 294 295 cc->tcg_ops = &alpha_tcg_ops; 296 cc->gdb_num_core_regs = 67; 297 } 298 299 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ 300 { \ 301 .parent = base_type, \ 302 .instance_init = initfn, \ 303 .name = ALPHA_CPU_TYPE_NAME(cpu_model), \ 304 } 305 306 static const TypeInfo alpha_cpu_type_infos[] = { 307 { 308 .name = TYPE_ALPHA_CPU, 309 .parent = TYPE_CPU, 310 .instance_size = sizeof(AlphaCPU), 311 .instance_align = __alignof(AlphaCPU), 312 .instance_init = alpha_cpu_initfn, 313 .abstract = true, 314 .class_size = sizeof(AlphaCPUClass), 315 .class_init = alpha_cpu_class_init, 316 }, 317 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn), 318 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn), 319 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn), 320 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56", 321 pca56_cpu_initfn), 322 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn), 323 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn), 324 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL), 325 }; 326 327 DEFINE_TYPES(alpha_cpu_type_infos) 328