174433bf0SRichard Henderson /* 274433bf0SRichard Henderson * Alpha cpu parameters for qemu. 374433bf0SRichard Henderson * 474433bf0SRichard Henderson * Copyright (c) 2007 Jocelyn Mayer 5*b14d0649SPhilippe Mathieu-Daudé * SPDX-License-Identifier: LGPL-2.0-or-later 674433bf0SRichard Henderson */ 774433bf0SRichard Henderson 874433bf0SRichard Henderson #ifndef ALPHA_CPU_PARAM_H 94f31b54bSMarkus Armbruster #define ALPHA_CPU_PARAM_H 1074433bf0SRichard Henderson 1174433bf0SRichard Henderson #define TARGET_LONG_BITS 64 127d8cbbabSRichard Henderson 1374433bf0SRichard Henderson /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ 1474433bf0SRichard Henderson #define TARGET_PHYS_ADDR_SPACE_BITS 44 15f2ffdfabSRichard Henderson 16f2ffdfabSRichard Henderson #ifdef CONFIG_USER_ONLY 17f2ffdfabSRichard Henderson /* 18f2ffdfabSRichard Henderson * Allow user-only to vary page size. Real hardware allows only 8k and 64k, 19f2ffdfabSRichard Henderson * but since any variance means guests cannot assume a fixed value, allow 20f2ffdfabSRichard Henderson * a 4k minimum to match x86 host, which can minimize emulation issues. 21f2ffdfabSRichard Henderson */ 22f2ffdfabSRichard Henderson # define TARGET_PAGE_BITS_VARY 23f2ffdfabSRichard Henderson # define TARGET_PAGE_BITS_MIN 12 24f2ffdfabSRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 63 25f2ffdfabSRichard Henderson #else 26f2ffdfabSRichard Henderson # define TARGET_PAGE_BITS 13 2774433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) 28f2ffdfabSRichard Henderson #endif 297d8cbbabSRichard Henderson 30e92dd332SPhilippe Mathieu-Daudé /* Alpha processors have a weak memory model */ 31e92dd332SPhilippe Mathieu-Daudé #define TCG_GUEST_DEFAULT_MO (0) 32e92dd332SPhilippe Mathieu-Daudé 3374433bf0SRichard Henderson #endif 34