1 // Copyright (C) 2024 Intel Corporation. 2 // Author(s): Zhao Liu <zhai1.liu@intel.com> 3 // SPDX-License-Identifier: GPL-2.0-or-later 4 5 use std::{ 6 ffi::{c_int, c_void, CStr}, 7 pin::Pin, 8 ptr::{addr_of_mut, null_mut, NonNull}, 9 slice::from_ref, 10 }; 11 12 use qemu_api::{ 13 bindings::{ 14 address_space_memory, address_space_stl_le, qdev_prop_bit, qdev_prop_bool, 15 qdev_prop_uint32, qdev_prop_uint8, 16 }, 17 c_str, 18 cell::{BqlCell, BqlRefCell}, 19 irq::InterruptSource, 20 memory::{ 21 hwaddr, MemoryRegion, MemoryRegionOps, MemoryRegionOpsBuilder, MEMTXATTRS_UNSPECIFIED, 22 }, 23 prelude::*, 24 qdev::{DeviceImpl, DeviceMethods, DeviceState, Property, ResetType, ResettablePhasesImpl}, 25 qom::{ObjectImpl, ObjectType, ParentField}, 26 qom_isa, 27 sysbus::{SysBusDevice, SysBusDeviceImpl}, 28 timer::{Timer, CLOCK_VIRTUAL, NANOSECONDS_PER_SECOND}, 29 vmstate::VMStateDescription, 30 vmstate_fields, vmstate_of, vmstate_struct, vmstate_subsections, vmstate_validate, 31 zeroable::Zeroable, 32 }; 33 34 use crate::fw_cfg::HPETFwConfig; 35 36 /// Register space for each timer block (`HPET_BASE` is defined in hpet.h). 37 const HPET_REG_SPACE_LEN: u64 = 0x400; // 1024 bytes 38 39 /// Minimum recommended hardware implementation. 40 const HPET_MIN_TIMERS: u8 = 3; 41 /// Maximum timers in each timer block. 42 const HPET_MAX_TIMERS: u8 = 32; 43 44 /// Flags that HPETState.flags supports. 45 const HPET_FLAG_MSI_SUPPORT_SHIFT: usize = 0; 46 47 const HPET_NUM_IRQ_ROUTES: usize = 32; 48 const HPET_LEGACY_PIT_INT: u32 = 0; // HPET_LEGACY_RTC_INT isn't defined here. 49 const RTC_ISA_IRQ: usize = 8; 50 51 const HPET_CLK_PERIOD: u64 = 10; // 10 ns 52 const FS_PER_NS: u64 = 1000000; // 1000000 femtoseconds == 1 ns 53 54 /// Revision ID (bits 0:7). Revision 1 is implemented (refer to v1.0a spec). 55 const HPET_CAP_REV_ID_VALUE: u64 = 0x1; 56 const HPET_CAP_REV_ID_SHIFT: usize = 0; 57 /// Number of Timers (bits 8:12) 58 const HPET_CAP_NUM_TIM_SHIFT: usize = 8; 59 /// Counter Size (bit 13) 60 const HPET_CAP_COUNT_SIZE_CAP_SHIFT: usize = 13; 61 /// Legacy Replacement Route Capable (bit 15) 62 const HPET_CAP_LEG_RT_CAP_SHIFT: usize = 15; 63 /// Vendor ID (bits 16:31) 64 const HPET_CAP_VENDER_ID_VALUE: u64 = 0x8086; 65 const HPET_CAP_VENDER_ID_SHIFT: usize = 16; 66 /// Main Counter Tick Period (bits 32:63) 67 const HPET_CAP_CNT_CLK_PERIOD_SHIFT: usize = 32; 68 69 /// Overall Enable (bit 0) 70 const HPET_CFG_ENABLE_SHIFT: usize = 0; 71 /// Legacy Replacement Route (bit 1) 72 const HPET_CFG_LEG_RT_SHIFT: usize = 1; 73 /// Other bits are reserved. 74 const HPET_CFG_WRITE_MASK: u64 = 0x003; 75 76 /// bit 0, 7, and bits 16:31 are reserved. 77 /// bit 4, 5, 15, and bits 32:64 are read-only. 78 const HPET_TN_CFG_WRITE_MASK: u64 = 0x7f4e; 79 /// Timer N Interrupt Type (bit 1) 80 const HPET_TN_CFG_INT_TYPE_SHIFT: usize = 1; 81 /// Timer N Interrupt Enable (bit 2) 82 const HPET_TN_CFG_INT_ENABLE_SHIFT: usize = 2; 83 /// Timer N Type (Periodic enabled or not, bit 3) 84 const HPET_TN_CFG_PERIODIC_SHIFT: usize = 3; 85 /// Timer N Periodic Interrupt Capable (support Periodic or not, bit 4) 86 const HPET_TN_CFG_PERIODIC_CAP_SHIFT: usize = 4; 87 /// Timer N Size (timer size is 64-bits or 32 bits, bit 5) 88 const HPET_TN_CFG_SIZE_CAP_SHIFT: usize = 5; 89 /// Timer N Value Set (bit 6) 90 const HPET_TN_CFG_SETVAL_SHIFT: usize = 6; 91 /// Timer N 32-bit Mode (bit 8) 92 const HPET_TN_CFG_32BIT_SHIFT: usize = 8; 93 /// Timer N Interrupt Rout (bits 9:13) 94 const HPET_TN_CFG_INT_ROUTE_MASK: u64 = 0x3e00; 95 const HPET_TN_CFG_INT_ROUTE_SHIFT: usize = 9; 96 /// Timer N FSB Interrupt Enable (bit 14) 97 const HPET_TN_CFG_FSB_ENABLE_SHIFT: usize = 14; 98 /// Timer N FSB Interrupt Delivery (bit 15) 99 const HPET_TN_CFG_FSB_CAP_SHIFT: usize = 15; 100 /// Timer N Interrupt Routing Capability (bits 32:63) 101 const HPET_TN_CFG_INT_ROUTE_CAP_SHIFT: usize = 32; 102 103 #[derive(qemu_api_macros::TryInto)] 104 #[repr(u64)] 105 #[allow(non_camel_case_types)] 106 /// Timer registers, masked by 0x18 107 enum TimerRegister { 108 /// Timer N Configuration and Capability Register 109 CFG = 0, 110 /// Timer N Comparator Value Register 111 CMP = 8, 112 /// Timer N FSB Interrupt Route Register 113 ROUTE = 16, 114 } 115 116 #[derive(qemu_api_macros::TryInto)] 117 #[repr(u64)] 118 #[allow(non_camel_case_types)] 119 /// Global registers 120 enum GlobalRegister { 121 /// General Capabilities and ID Register 122 CAP = 0, 123 /// General Configuration Register 124 CFG = 0x10, 125 /// General Interrupt Status Register 126 INT_STATUS = 0x20, 127 /// Main Counter Value Register 128 COUNTER = 0xF0, 129 } 130 131 enum HPETRegister<'a> { 132 /// Global register in the range from `0` to `0xff` 133 Global(GlobalRegister), 134 135 /// Register in the timer block `0x100`...`0x3ff` 136 Timer(&'a BqlRefCell<HPETTimer>, TimerRegister), 137 138 /// Invalid address 139 #[allow(dead_code)] 140 Unknown(hwaddr), 141 } 142 143 struct HPETAddrDecode<'a> { 144 shift: u32, 145 len: u32, 146 reg: HPETRegister<'a>, 147 } 148 149 const fn hpet_next_wrap(cur_tick: u64) -> u64 { 150 (cur_tick | 0xffffffff) + 1 151 } 152 153 const fn hpet_time_after(a: u64, b: u64) -> bool { 154 ((b - a) as i64) < 0 155 } 156 157 const fn ticks_to_ns(value: u64) -> u64 { 158 value * HPET_CLK_PERIOD 159 } 160 161 const fn ns_to_ticks(value: u64) -> u64 { 162 value / HPET_CLK_PERIOD 163 } 164 165 // Avoid touching the bits that cannot be written. 166 const fn hpet_fixup_reg(new: u64, old: u64, mask: u64) -> u64 { 167 (new & mask) | (old & !mask) 168 } 169 170 const fn activating_bit(old: u64, new: u64, shift: usize) -> bool { 171 let mask: u64 = 1 << shift; 172 (old & mask == 0) && (new & mask != 0) 173 } 174 175 const fn deactivating_bit(old: u64, new: u64, shift: usize) -> bool { 176 let mask: u64 = 1 << shift; 177 (old & mask != 0) && (new & mask == 0) 178 } 179 180 fn timer_handler(timer_cell: &BqlRefCell<HPETTimer>) { 181 timer_cell.borrow_mut().callback() 182 } 183 184 /// HPET Timer Abstraction 185 #[repr(C)] 186 #[derive(Debug, qemu_api_macros::offsets)] 187 pub struct HPETTimer { 188 /// timer N index within the timer block (`HPETState`) 189 #[doc(alias = "tn")] 190 index: u8, 191 qemu_timer: Timer, 192 /// timer block abstraction containing this timer 193 state: NonNull<HPETState>, 194 195 // Memory-mapped, software visible timer registers 196 /// Timer N Configuration and Capability Register 197 config: u64, 198 /// Timer N Comparator Value Register 199 cmp: u64, 200 /// Timer N FSB Interrupt Route Register 201 fsb: u64, 202 203 // Hidden register state 204 /// comparator (extended to counter width) 205 cmp64: u64, 206 /// Last value written to comparator 207 period: u64, 208 /// timer pop will indicate wrap for one-shot 32-bit 209 /// mode. Next pop will be actual timer expiration. 210 wrap_flag: u8, 211 /// last value armed, to avoid timer storms 212 last: u64, 213 } 214 215 impl HPETTimer { 216 fn init(&mut self, index: u8, state: &HPETState) { 217 *self = HPETTimer { 218 index, 219 // SAFETY: the HPETTimer will only be used after the timer 220 // is initialized below. 221 qemu_timer: unsafe { Timer::new() }, 222 state: NonNull::new(state as *const _ as *mut _).unwrap(), 223 config: 0, 224 cmp: 0, 225 fsb: 0, 226 cmp64: 0, 227 period: 0, 228 wrap_flag: 0, 229 last: 0, 230 }; 231 232 // SAFETY: HPETTimer is only used as part of HPETState, which is 233 // always pinned. 234 let qemu_timer = unsafe { Pin::new_unchecked(&mut self.qemu_timer) }; 235 qemu_timer.init_full( 236 None, 237 CLOCK_VIRTUAL, 238 Timer::NS, 239 0, 240 timer_handler, 241 &state.timers[self.index as usize], 242 ) 243 } 244 245 fn get_state(&self) -> &HPETState { 246 // SAFETY: 247 // the pointer is convertible to a reference 248 unsafe { self.state.as_ref() } 249 } 250 251 fn is_int_active(&self) -> bool { 252 self.get_state().is_timer_int_active(self.index.into()) 253 } 254 255 const fn is_fsb_route_enabled(&self) -> bool { 256 self.config & (1 << HPET_TN_CFG_FSB_ENABLE_SHIFT) != 0 257 } 258 259 const fn is_periodic(&self) -> bool { 260 self.config & (1 << HPET_TN_CFG_PERIODIC_SHIFT) != 0 261 } 262 263 const fn is_int_enabled(&self) -> bool { 264 self.config & (1 << HPET_TN_CFG_INT_ENABLE_SHIFT) != 0 265 } 266 267 const fn is_32bit_mod(&self) -> bool { 268 self.config & (1 << HPET_TN_CFG_32BIT_SHIFT) != 0 269 } 270 271 const fn is_valset_enabled(&self) -> bool { 272 self.config & (1 << HPET_TN_CFG_SETVAL_SHIFT) != 0 273 } 274 275 fn clear_valset(&mut self) { 276 self.config &= !(1 << HPET_TN_CFG_SETVAL_SHIFT); 277 } 278 279 /// True if timer interrupt is level triggered; otherwise, edge triggered. 280 const fn is_int_level_triggered(&self) -> bool { 281 self.config & (1 << HPET_TN_CFG_INT_TYPE_SHIFT) != 0 282 } 283 284 /// calculate next value of the general counter that matches the 285 /// target (either entirely, or the low 32-bit only depending on 286 /// the timer mode). 287 fn calculate_cmp64(&self, cur_tick: u64, target: u64) -> u64 { 288 if self.is_32bit_mod() { 289 let mut result: u64 = cur_tick.deposit(0, 32, target); 290 if result < cur_tick { 291 result += 0x100000000; 292 } 293 result 294 } else { 295 target 296 } 297 } 298 299 const fn get_individual_route(&self) -> usize { 300 ((self.config & HPET_TN_CFG_INT_ROUTE_MASK) >> HPET_TN_CFG_INT_ROUTE_SHIFT) as usize 301 } 302 303 fn get_int_route(&self) -> usize { 304 if self.index <= 1 && self.get_state().is_legacy_mode() { 305 // If LegacyReplacement Route bit is set, HPET specification requires 306 // timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, 307 // timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. 308 // 309 // If the LegacyReplacement Route bit is set, the individual routing 310 // bits for timers 0 and 1 (APIC or FSB) will have no impact. 311 // 312 // FIXME: Consider I/O APIC case. 313 if self.index == 0 { 314 0 315 } else { 316 RTC_ISA_IRQ 317 } 318 } else { 319 // (If the LegacyReplacement Route bit is set) Timer 2-n will be 320 // routed as per the routing in the timer n config registers. 321 // ... 322 // If the LegacyReplacement Route bit is not set, the individual 323 // routing bits for each of the timers are used. 324 self.get_individual_route() 325 } 326 } 327 328 fn set_irq(&mut self, set: bool) { 329 let route = self.get_int_route(); 330 331 if set && self.is_int_enabled() && self.get_state().is_hpet_enabled() { 332 if self.is_fsb_route_enabled() { 333 // SAFETY: 334 // the parameters are valid. 335 unsafe { 336 address_space_stl_le( 337 addr_of_mut!(address_space_memory), 338 self.fsb >> 32, // Timer N FSB int addr 339 self.fsb as u32, // Timer N FSB int value, truncate! 340 MEMTXATTRS_UNSPECIFIED, 341 null_mut(), 342 ); 343 } 344 } else if self.is_int_level_triggered() { 345 self.get_state().irqs[route].raise(); 346 } else { 347 self.get_state().irqs[route].pulse(); 348 } 349 } else if !self.is_fsb_route_enabled() { 350 self.get_state().irqs[route].lower(); 351 } 352 } 353 354 fn update_irq(&mut self, set: bool) { 355 // If Timer N Interrupt Enable bit is 0, "the timer will 356 // still operate and generate appropriate status bits, but 357 // will not cause an interrupt" 358 self.get_state() 359 .update_int_status(self.index.into(), set && self.is_int_level_triggered()); 360 self.set_irq(set); 361 } 362 363 fn arm_timer(&mut self, tick: u64) { 364 let mut ns = self.get_state().get_ns(tick); 365 366 // Clamp period to reasonable min value (1 us) 367 if self.is_periodic() && ns - self.last < 1000 { 368 ns = self.last + 1000; 369 } 370 371 self.last = ns; 372 self.qemu_timer.modify(self.last); 373 } 374 375 fn set_timer(&mut self) { 376 let cur_tick: u64 = self.get_state().get_ticks(); 377 378 self.wrap_flag = 0; 379 self.cmp64 = self.calculate_cmp64(cur_tick, self.cmp); 380 if self.is_32bit_mod() { 381 // HPET spec says in one-shot 32-bit mode, generate an interrupt when 382 // counter wraps in addition to an interrupt with comparator match. 383 if !self.is_periodic() && self.cmp64 > hpet_next_wrap(cur_tick) { 384 self.wrap_flag = 1; 385 self.arm_timer(hpet_next_wrap(cur_tick)); 386 return; 387 } 388 } 389 self.arm_timer(self.cmp64); 390 } 391 392 fn del_timer(&mut self) { 393 // Just remove the timer from the timer_list without destroying 394 // this timer instance. 395 self.qemu_timer.delete(); 396 397 if self.is_int_active() { 398 // For level-triggered interrupt, this leaves interrupt status 399 // register set but lowers irq. 400 self.update_irq(true); 401 } 402 } 403 404 /// Configuration and Capability Register 405 fn set_tn_cfg_reg(&mut self, shift: u32, len: u32, val: u64) { 406 // TODO: Add trace point - trace_hpet_ram_write_tn_cfg(addr & 4) 407 let old_val: u64 = self.config; 408 let mut new_val: u64 = old_val.deposit(shift, len, val); 409 new_val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); 410 411 // Switch level-type interrupt to edge-type. 412 if deactivating_bit(old_val, new_val, HPET_TN_CFG_INT_TYPE_SHIFT) { 413 // Do this before changing timer.config; otherwise, if 414 // HPET_TN_FSB is set, update_irq will not lower the qemu_irq. 415 self.update_irq(false); 416 } 417 418 self.config = new_val; 419 420 if activating_bit(old_val, new_val, HPET_TN_CFG_INT_ENABLE_SHIFT) && self.is_int_active() { 421 self.update_irq(true); 422 } 423 424 if self.is_32bit_mod() { 425 self.cmp = u64::from(self.cmp as u32); // truncate! 426 self.period = u64::from(self.period as u32); // truncate! 427 } 428 429 if self.get_state().is_hpet_enabled() { 430 self.set_timer(); 431 } 432 } 433 434 /// Comparator Value Register 435 fn set_tn_cmp_reg(&mut self, shift: u32, len: u32, val: u64) { 436 let mut length = len; 437 let mut value = val; 438 439 // TODO: Add trace point - trace_hpet_ram_write_tn_cmp(addr & 4) 440 if self.is_32bit_mod() { 441 // High 32-bits are zero, leave them untouched. 442 if shift != 0 { 443 // TODO: Add trace point - trace_hpet_ram_write_invalid_tn_cmp() 444 return; 445 } 446 length = 64; 447 value = u64::from(value as u32); // truncate! 448 } 449 450 if !self.is_periodic() || self.is_valset_enabled() { 451 self.cmp = self.cmp.deposit(shift, length, value); 452 } 453 454 if self.is_periodic() { 455 self.period = self.period.deposit(shift, length, value); 456 } 457 458 self.clear_valset(); 459 if self.get_state().is_hpet_enabled() { 460 self.set_timer(); 461 } 462 } 463 464 /// FSB Interrupt Route Register 465 fn set_tn_fsb_route_reg(&mut self, shift: u32, len: u32, val: u64) { 466 self.fsb = self.fsb.deposit(shift, len, val); 467 } 468 469 fn reset(&mut self) { 470 self.del_timer(); 471 self.cmp = u64::MAX; // Comparator Match Registers reset to all 1's. 472 self.config = (1 << HPET_TN_CFG_PERIODIC_CAP_SHIFT) | (1 << HPET_TN_CFG_SIZE_CAP_SHIFT); 473 if self.get_state().has_msi_flag() { 474 self.config |= 1 << HPET_TN_CFG_FSB_CAP_SHIFT; 475 } 476 // advertise availability of ioapic int 477 self.config |= 478 (u64::from(self.get_state().int_route_cap)) << HPET_TN_CFG_INT_ROUTE_CAP_SHIFT; 479 self.period = 0; 480 self.wrap_flag = 0; 481 } 482 483 /// timer expiration callback 484 fn callback(&mut self) { 485 let period: u64 = self.period; 486 let cur_tick: u64 = self.get_state().get_ticks(); 487 488 if self.is_periodic() && period != 0 { 489 while hpet_time_after(cur_tick, self.cmp64) { 490 self.cmp64 += period; 491 } 492 if self.is_32bit_mod() { 493 self.cmp = u64::from(self.cmp64 as u32); // truncate! 494 } else { 495 self.cmp = self.cmp64; 496 } 497 self.arm_timer(self.cmp64); 498 } else if self.wrap_flag != 0 { 499 self.wrap_flag = 0; 500 self.arm_timer(self.cmp64); 501 } 502 self.update_irq(true); 503 } 504 505 const fn read(&self, reg: TimerRegister) -> u64 { 506 use TimerRegister::*; 507 match reg { 508 CFG => self.config, // including interrupt capabilities 509 CMP => self.cmp, // comparator register 510 ROUTE => self.fsb, 511 } 512 } 513 514 fn write(&mut self, reg: TimerRegister, value: u64, shift: u32, len: u32) { 515 use TimerRegister::*; 516 match reg { 517 CFG => self.set_tn_cfg_reg(shift, len, value), 518 CMP => self.set_tn_cmp_reg(shift, len, value), 519 ROUTE => self.set_tn_fsb_route_reg(shift, len, value), 520 } 521 } 522 } 523 524 /// HPET Event Timer Block Abstraction 525 #[repr(C)] 526 #[derive(qemu_api_macros::Object, qemu_api_macros::offsets)] 527 pub struct HPETState { 528 parent_obj: ParentField<SysBusDevice>, 529 iomem: MemoryRegion, 530 531 // HPET block Registers: Memory-mapped, software visible registers 532 /// General Capabilities and ID Register 533 capability: BqlCell<u64>, 534 /// General Configuration Register 535 config: BqlCell<u64>, 536 /// General Interrupt Status Register 537 #[doc(alias = "isr")] 538 int_status: BqlCell<u64>, 539 /// Main Counter Value Register 540 #[doc(alias = "hpet_counter")] 541 counter: BqlCell<u64>, 542 543 // Internal state 544 /// Capabilities that QEMU HPET supports. 545 /// bit 0: MSI (or FSB) support. 546 flags: u32, 547 548 /// Offset of main counter relative to qemu clock. 549 hpet_offset: BqlCell<u64>, 550 hpet_offset_saved: bool, 551 552 irqs: [InterruptSource; HPET_NUM_IRQ_ROUTES], 553 rtc_irq_level: BqlCell<u32>, 554 pit_enabled: InterruptSource, 555 556 /// Interrupt Routing Capability. 557 /// This field indicates to which interrupts in the I/O (x) APIC 558 /// the timers' interrupt can be routed, and is encoded in the 559 /// bits 32:64 of timer N's config register: 560 #[doc(alias = "intcap")] 561 int_route_cap: u32, 562 563 /// HPET timer array managed by this timer block. 564 #[doc(alias = "timer")] 565 timers: [BqlRefCell<HPETTimer>; HPET_MAX_TIMERS as usize], 566 num_timers: BqlCell<u8>, 567 num_timers_save: BqlCell<u8>, 568 569 /// Instance id (HPET timer block ID). 570 hpet_id: BqlCell<usize>, 571 } 572 573 impl HPETState { 574 // Get num_timers with `usize` type, which is useful to play with array index. 575 fn get_num_timers(&self) -> usize { 576 self.num_timers.get().into() 577 } 578 579 const fn has_msi_flag(&self) -> bool { 580 self.flags & (1 << HPET_FLAG_MSI_SUPPORT_SHIFT) != 0 581 } 582 583 fn is_legacy_mode(&self) -> bool { 584 self.config.get() & (1 << HPET_CFG_LEG_RT_SHIFT) != 0 585 } 586 587 fn is_hpet_enabled(&self) -> bool { 588 self.config.get() & (1 << HPET_CFG_ENABLE_SHIFT) != 0 589 } 590 591 fn is_timer_int_active(&self, index: usize) -> bool { 592 self.int_status.get() & (1 << index) != 0 593 } 594 595 fn get_ticks(&self) -> u64 { 596 ns_to_ticks(CLOCK_VIRTUAL.get_ns() + self.hpet_offset.get()) 597 } 598 599 fn get_ns(&self, tick: u64) -> u64 { 600 ticks_to_ns(tick) - self.hpet_offset.get() 601 } 602 603 fn handle_legacy_irq(&self, irq: u32, level: u32) { 604 if irq == HPET_LEGACY_PIT_INT { 605 if !self.is_legacy_mode() { 606 self.irqs[0].set(level != 0); 607 } 608 } else { 609 self.rtc_irq_level.set(level); 610 if !self.is_legacy_mode() { 611 self.irqs[RTC_ISA_IRQ].set(level != 0); 612 } 613 } 614 } 615 616 fn init_timer(&self) { 617 for (index, timer) in self.timers.iter().enumerate() { 618 timer.borrow_mut().init(index.try_into().unwrap(), self); 619 } 620 } 621 622 fn update_int_status(&self, index: u32, level: bool) { 623 self.int_status 624 .set(self.int_status.get().deposit(index, 1, u64::from(level))); 625 } 626 627 /// General Configuration Register 628 fn set_cfg_reg(&self, shift: u32, len: u32, val: u64) { 629 let old_val = self.config.get(); 630 let mut new_val = old_val.deposit(shift, len, val); 631 632 new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); 633 self.config.set(new_val); 634 635 if activating_bit(old_val, new_val, HPET_CFG_ENABLE_SHIFT) { 636 // Enable main counter and interrupt generation. 637 self.hpet_offset 638 .set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns()); 639 640 for timer in self.timers.iter().take(self.get_num_timers()) { 641 let mut t = timer.borrow_mut(); 642 643 if t.is_int_enabled() && t.is_int_active() { 644 t.update_irq(true); 645 } 646 t.set_timer(); 647 } 648 } else if deactivating_bit(old_val, new_val, HPET_CFG_ENABLE_SHIFT) { 649 // Halt main counter and disable interrupt generation. 650 self.counter.set(self.get_ticks()); 651 652 for timer in self.timers.iter().take(self.get_num_timers()) { 653 timer.borrow_mut().del_timer(); 654 } 655 } 656 657 // i8254 and RTC output pins are disabled when HPET is in legacy mode 658 if activating_bit(old_val, new_val, HPET_CFG_LEG_RT_SHIFT) { 659 self.pit_enabled.set(false); 660 self.irqs[0].lower(); 661 self.irqs[RTC_ISA_IRQ].lower(); 662 } else if deactivating_bit(old_val, new_val, HPET_CFG_LEG_RT_SHIFT) { 663 // TODO: Add irq binding: qemu_irq_lower(s->irqs[0]) 664 self.irqs[0].lower(); 665 self.pit_enabled.set(true); 666 self.irqs[RTC_ISA_IRQ].set(self.rtc_irq_level.get() != 0); 667 } 668 } 669 670 /// General Interrupt Status Register: Read/Write Clear 671 fn set_int_status_reg(&self, shift: u32, _len: u32, val: u64) { 672 let new_val = val << shift; 673 let cleared = new_val & self.int_status.get(); 674 675 for (index, timer) in self.timers.iter().take(self.get_num_timers()).enumerate() { 676 if cleared & (1 << index) != 0 { 677 timer.borrow_mut().update_irq(false); 678 } 679 } 680 } 681 682 /// Main Counter Value Register 683 fn set_counter_reg(&self, shift: u32, len: u32, val: u64) { 684 if self.is_hpet_enabled() { 685 // TODO: Add trace point - 686 // trace_hpet_ram_write_counter_write_while_enabled() 687 // 688 // HPET spec says that writes to this register should only be 689 // done while the counter is halted. So this is an undefined 690 // behavior. There's no need to forbid it, but when HPET is 691 // enabled, the changed counter value will not affect the 692 // tick count (i.e., the previously calculated offset will 693 // not be changed as well). 694 } 695 self.counter 696 .set(self.counter.get().deposit(shift, len, val)); 697 } 698 699 unsafe fn init(&mut self) { 700 static HPET_RAM_OPS: MemoryRegionOps<HPETState> = 701 MemoryRegionOpsBuilder::<HPETState>::new() 702 .read(&HPETState::read) 703 .write(&HPETState::write) 704 .native_endian() 705 .valid_sizes(4, 8) 706 .impl_sizes(4, 8) 707 .build(); 708 709 // SAFETY: 710 // self and self.iomem are guaranteed to be valid at this point since callers 711 // must make sure the `self` reference is valid. 712 MemoryRegion::init_io( 713 unsafe { &mut *addr_of_mut!(self.iomem) }, 714 addr_of_mut!(*self), 715 &HPET_RAM_OPS, 716 "hpet", 717 HPET_REG_SPACE_LEN, 718 ); 719 } 720 721 fn post_init(&self) { 722 self.init_mmio(&self.iomem); 723 for irq in self.irqs.iter() { 724 self.init_irq(irq); 725 } 726 } 727 728 fn realize(&self) { 729 if self.int_route_cap == 0 { 730 // TODO: Add error binding: warn_report() 731 println!("Hpet's hpet-intcap property not initialized"); 732 } 733 734 self.hpet_id.set(HPETFwConfig::assign_hpet_id()); 735 736 if self.num_timers.get() < HPET_MIN_TIMERS { 737 self.num_timers.set(HPET_MIN_TIMERS); 738 } else if self.num_timers.get() > HPET_MAX_TIMERS { 739 self.num_timers.set(HPET_MAX_TIMERS); 740 } 741 742 self.init_timer(); 743 // 64-bit General Capabilities and ID Register; LegacyReplacementRoute. 744 self.capability.set( 745 HPET_CAP_REV_ID_VALUE << HPET_CAP_REV_ID_SHIFT | 746 1 << HPET_CAP_COUNT_SIZE_CAP_SHIFT | 747 1 << HPET_CAP_LEG_RT_CAP_SHIFT | 748 HPET_CAP_VENDER_ID_VALUE << HPET_CAP_VENDER_ID_SHIFT | 749 ((self.get_num_timers() - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT | // indicate the last timer 750 (HPET_CLK_PERIOD * FS_PER_NS) << HPET_CAP_CNT_CLK_PERIOD_SHIFT, // 10 ns 751 ); 752 753 self.init_gpio_in(2, HPETState::handle_legacy_irq); 754 self.init_gpio_out(from_ref(&self.pit_enabled)); 755 } 756 757 fn reset_hold(&self, _type: ResetType) { 758 for timer in self.timers.iter().take(self.get_num_timers()) { 759 timer.borrow_mut().reset(); 760 } 761 762 self.counter.set(0); 763 self.config.set(0); 764 self.pit_enabled.set(true); 765 self.hpet_offset.set(0); 766 767 HPETFwConfig::update_hpet_cfg( 768 self.hpet_id.get(), 769 self.capability.get() as u32, 770 self.mmio_addr(0).unwrap(), 771 ); 772 773 // to document that the RTC lowers its output on reset as well 774 self.rtc_irq_level.set(0); 775 } 776 777 fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode { 778 let shift = ((addr & 4) * 8) as u32; 779 let len = std::cmp::min(size * 8, 64 - shift); 780 781 addr &= !4; 782 let reg = if (0..=0xff).contains(&addr) { 783 GlobalRegister::try_from(addr).map(HPETRegister::Global) 784 } else { 785 let timer_id: usize = ((addr - 0x100) / 0x20) as usize; 786 if timer_id <= self.get_num_timers() { 787 // TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id) 788 TimerRegister::try_from(addr & 0x18) 789 .map(|reg| HPETRegister::Timer(&self.timers[timer_id], reg)) 790 } else { 791 // TODO: Add trace point - trace_hpet_timer_id_out_of_range(timer_id) 792 Err(addr) 793 } 794 }; 795 796 // reg is now a Result<HPETRegister, hwaddr> 797 // convert the Err case into HPETRegister as well 798 let reg = reg.unwrap_or_else(HPETRegister::Unknown); 799 HPETAddrDecode { shift, len, reg } 800 } 801 802 fn read(&self, addr: hwaddr, size: u32) -> u64 { 803 // TODO: Add trace point - trace_hpet_ram_read(addr) 804 let HPETAddrDecode { shift, reg, .. } = self.decode(addr, size); 805 806 use GlobalRegister::*; 807 use HPETRegister::*; 808 (match reg { 809 Timer(timer, tn_reg) => timer.borrow_mut().read(tn_reg), 810 Global(CAP) => self.capability.get(), /* including HPET_PERIOD 0x004 */ 811 Global(CFG) => self.config.get(), 812 Global(INT_STATUS) => self.int_status.get(), 813 Global(COUNTER) => { 814 // TODO: Add trace point 815 // trace_hpet_ram_read_reading_counter(addr & 4, cur_tick) 816 if self.is_hpet_enabled() { 817 self.get_ticks() 818 } else { 819 self.counter.get() 820 } 821 } 822 Unknown(_) => { 823 // TODO: Add trace point- trace_hpet_ram_read_invalid() 824 0 825 } 826 }) >> shift 827 } 828 829 fn write(&self, addr: hwaddr, value: u64, size: u32) { 830 let HPETAddrDecode { shift, len, reg } = self.decode(addr, size); 831 832 // TODO: Add trace point - trace_hpet_ram_write(addr, value) 833 use GlobalRegister::*; 834 use HPETRegister::*; 835 match reg { 836 Timer(timer, tn_reg) => timer.borrow_mut().write(tn_reg, value, shift, len), 837 Global(CAP) => {} // General Capabilities and ID Register: Read Only 838 Global(CFG) => self.set_cfg_reg(shift, len, value), 839 Global(INT_STATUS) => self.set_int_status_reg(shift, len, value), 840 Global(COUNTER) => self.set_counter_reg(shift, len, value), 841 Unknown(_) => { 842 // TODO: Add trace point - trace_hpet_ram_write_invalid() 843 } 844 } 845 } 846 847 fn pre_save(&self) -> i32 { 848 if self.is_hpet_enabled() { 849 self.counter.set(self.get_ticks()); 850 } 851 852 /* 853 * The number of timers must match on source and destination, but it was 854 * also added to the migration stream. Check that it matches the value 855 * that was configured. 856 */ 857 self.num_timers_save.set(self.num_timers.get()); 858 0 859 } 860 861 fn post_load(&self, _version_id: u8) -> i32 { 862 for timer in self.timers.iter().take(self.get_num_timers()) { 863 let mut t = timer.borrow_mut(); 864 865 t.cmp64 = t.calculate_cmp64(t.get_state().counter.get(), t.cmp); 866 t.last = CLOCK_VIRTUAL.get_ns() - NANOSECONDS_PER_SECOND; 867 } 868 869 // Recalculate the offset between the main counter and guest time 870 if !self.hpet_offset_saved { 871 self.hpet_offset 872 .set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns()); 873 } 874 875 0 876 } 877 878 fn is_rtc_irq_level_needed(&self) -> bool { 879 self.rtc_irq_level.get() != 0 880 } 881 882 fn is_offset_needed(&self) -> bool { 883 self.is_hpet_enabled() && self.hpet_offset_saved 884 } 885 886 fn validate_num_timers(&self, _version_id: u8) -> bool { 887 self.num_timers.get() == self.num_timers_save.get() 888 } 889 } 890 891 qom_isa!(HPETState: SysBusDevice, DeviceState, Object); 892 893 unsafe impl ObjectType for HPETState { 894 // No need for HPETClass. Just like OBJECT_DECLARE_SIMPLE_TYPE in C. 895 type Class = <SysBusDevice as ObjectType>::Class; 896 const TYPE_NAME: &'static CStr = crate::TYPE_HPET; 897 } 898 899 impl ObjectImpl for HPETState { 900 type ParentType = SysBusDevice; 901 902 const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = Some(Self::init); 903 const INSTANCE_POST_INIT: Option<fn(&Self)> = Some(Self::post_init); 904 const CLASS_INIT: fn(&mut Self::Class) = Self::Class::class_init::<Self>; 905 } 906 907 // TODO: Make these properties user-configurable! 908 qemu_api::declare_properties! { 909 HPET_PROPERTIES, 910 qemu_api::define_property!( 911 c_str!("timers"), 912 HPETState, 913 num_timers, 914 unsafe { &qdev_prop_uint8 }, 915 u8, 916 default = HPET_MIN_TIMERS 917 ), 918 qemu_api::define_property!( 919 c_str!("msi"), 920 HPETState, 921 flags, 922 unsafe { &qdev_prop_bit }, 923 u32, 924 bit = HPET_FLAG_MSI_SUPPORT_SHIFT as u8, 925 default = false, 926 ), 927 qemu_api::define_property!( 928 c_str!("hpet-intcap"), 929 HPETState, 930 int_route_cap, 931 unsafe { &qdev_prop_uint32 }, 932 u32, 933 default = 0 934 ), 935 qemu_api::define_property!( 936 c_str!("hpet-offset-saved"), 937 HPETState, 938 hpet_offset_saved, 939 unsafe { &qdev_prop_bool }, 940 bool, 941 default = true 942 ), 943 } 944 945 unsafe extern "C" fn hpet_rtc_irq_level_needed(opaque: *mut c_void) -> bool { 946 // SAFETY: 947 // the pointer is convertible to a reference 948 let state: &HPETState = unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_ref() }; 949 state.is_rtc_irq_level_needed() 950 } 951 952 unsafe extern "C" fn hpet_offset_needed(opaque: *mut c_void) -> bool { 953 // SAFETY: 954 // the pointer is convertible to a reference 955 let state: &HPETState = unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_ref() }; 956 state.is_offset_needed() 957 } 958 959 unsafe extern "C" fn hpet_pre_save(opaque: *mut c_void) -> c_int { 960 // SAFETY: 961 // the pointer is convertible to a reference 962 let state: &mut HPETState = 963 unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_mut() }; 964 state.pre_save() as c_int 965 } 966 967 unsafe extern "C" fn hpet_post_load(opaque: *mut c_void, version_id: c_int) -> c_int { 968 // SAFETY: 969 // the pointer is convertible to a reference 970 let state: &mut HPETState = 971 unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_mut() }; 972 let version: u8 = version_id.try_into().unwrap(); 973 state.post_load(version) as c_int 974 } 975 976 static VMSTATE_HPET_RTC_IRQ_LEVEL: VMStateDescription = VMStateDescription { 977 name: c_str!("hpet/rtc_irq_level").as_ptr(), 978 version_id: 1, 979 minimum_version_id: 1, 980 needed: Some(hpet_rtc_irq_level_needed), 981 fields: vmstate_fields! { 982 vmstate_of!(HPETState, rtc_irq_level), 983 }, 984 ..Zeroable::ZERO 985 }; 986 987 static VMSTATE_HPET_OFFSET: VMStateDescription = VMStateDescription { 988 name: c_str!("hpet/offset").as_ptr(), 989 version_id: 1, 990 minimum_version_id: 1, 991 needed: Some(hpet_offset_needed), 992 fields: vmstate_fields! { 993 vmstate_of!(HPETState, hpet_offset), 994 }, 995 ..Zeroable::ZERO 996 }; 997 998 static VMSTATE_HPET_TIMER: VMStateDescription = VMStateDescription { 999 name: c_str!("hpet_timer").as_ptr(), 1000 version_id: 1, 1001 minimum_version_id: 1, 1002 fields: vmstate_fields! { 1003 vmstate_of!(HPETTimer, index), 1004 vmstate_of!(HPETTimer, config), 1005 vmstate_of!(HPETTimer, cmp), 1006 vmstate_of!(HPETTimer, fsb), 1007 vmstate_of!(HPETTimer, period), 1008 vmstate_of!(HPETTimer, wrap_flag), 1009 vmstate_of!(HPETTimer, qemu_timer), 1010 }, 1011 ..Zeroable::ZERO 1012 }; 1013 1014 const VALIDATE_TIMERS_NAME: &CStr = c_str!("num_timers must match"); 1015 1016 static VMSTATE_HPET: VMStateDescription = VMStateDescription { 1017 name: c_str!("hpet").as_ptr(), 1018 version_id: 2, 1019 minimum_version_id: 1, 1020 pre_save: Some(hpet_pre_save), 1021 post_load: Some(hpet_post_load), 1022 fields: vmstate_fields! { 1023 vmstate_of!(HPETState, config), 1024 vmstate_of!(HPETState, int_status), 1025 vmstate_of!(HPETState, counter), 1026 vmstate_of!(HPETState, num_timers_save).with_version_id(2), 1027 vmstate_validate!(HPETState, VALIDATE_TIMERS_NAME, HPETState::validate_num_timers), 1028 vmstate_struct!(HPETState, timers[0 .. num_timers], &VMSTATE_HPET_TIMER, BqlRefCell<HPETTimer>, HPETState::validate_num_timers).with_version_id(0), 1029 }, 1030 subsections: vmstate_subsections! { 1031 VMSTATE_HPET_RTC_IRQ_LEVEL, 1032 VMSTATE_HPET_OFFSET, 1033 }, 1034 ..Zeroable::ZERO 1035 }; 1036 1037 impl DeviceImpl for HPETState { 1038 fn properties() -> &'static [Property] { 1039 &HPET_PROPERTIES 1040 } 1041 1042 fn vmsd() -> Option<&'static VMStateDescription> { 1043 Some(&VMSTATE_HPET) 1044 } 1045 1046 const REALIZE: Option<fn(&Self)> = Some(Self::realize); 1047 } 1048 1049 impl ResettablePhasesImpl for HPETState { 1050 const HOLD: Option<fn(&Self, ResetType)> = Some(Self::reset_hold); 1051 } 1052 1053 impl SysBusDeviceImpl for HPETState {} 1054