1 // Copyright (C) 2024 Intel Corporation. 2 // Author(s): Zhao Liu <zhao1.liu@intel.com> 3 // SPDX-License-Identifier: GPL-2.0-or-later 4 5 use std::{ 6 ffi::{c_int, c_void, CStr}, 7 pin::Pin, 8 ptr::{addr_of_mut, null_mut, NonNull}, 9 slice::from_ref, 10 }; 11 12 use qemu_api::{ 13 bindings::{ 14 address_space_memory, address_space_stl_le, qdev_prop_bit, qdev_prop_bool, 15 qdev_prop_uint32, qdev_prop_usize, 16 }, 17 cell::{BqlCell, BqlRefCell}, 18 irq::InterruptSource, 19 memory::{ 20 hwaddr, MemoryRegion, MemoryRegionOps, MemoryRegionOpsBuilder, MEMTXATTRS_UNSPECIFIED, 21 }, 22 prelude::*, 23 qdev::{DeviceImpl, DeviceMethods, DeviceState, Property, ResetType, ResettablePhasesImpl}, 24 qom::{ObjectImpl, ObjectType, ParentField}, 25 qom_isa, 26 sysbus::{SysBusDevice, SysBusDeviceImpl}, 27 timer::{Timer, CLOCK_VIRTUAL, NANOSECONDS_PER_SECOND}, 28 vmstate::VMStateDescription, 29 vmstate_fields, vmstate_of, vmstate_struct, vmstate_subsections, vmstate_validate, 30 zeroable::Zeroable, 31 }; 32 33 use crate::fw_cfg::HPETFwConfig; 34 35 /// Register space for each timer block (`HPET_BASE` is defined in hpet.h). 36 const HPET_REG_SPACE_LEN: u64 = 0x400; // 1024 bytes 37 38 /// Minimum recommended hardware implementation. 39 const HPET_MIN_TIMERS: usize = 3; 40 /// Maximum timers in each timer block. 41 const HPET_MAX_TIMERS: usize = 32; 42 43 /// Flags that HPETState.flags supports. 44 const HPET_FLAG_MSI_SUPPORT_SHIFT: usize = 0; 45 46 const HPET_NUM_IRQ_ROUTES: usize = 32; 47 const HPET_LEGACY_PIT_INT: u32 = 0; // HPET_LEGACY_RTC_INT isn't defined here. 48 const RTC_ISA_IRQ: usize = 8; 49 50 const HPET_CLK_PERIOD: u64 = 10; // 10 ns 51 const FS_PER_NS: u64 = 1000000; // 1000000 femtoseconds == 1 ns 52 53 /// Revision ID (bits 0:7). Revision 1 is implemented (refer to v1.0a spec). 54 const HPET_CAP_REV_ID_VALUE: u64 = 0x1; 55 const HPET_CAP_REV_ID_SHIFT: usize = 0; 56 /// Number of Timers (bits 8:12) 57 const HPET_CAP_NUM_TIM_SHIFT: usize = 8; 58 /// Counter Size (bit 13) 59 const HPET_CAP_COUNT_SIZE_CAP_SHIFT: usize = 13; 60 /// Legacy Replacement Route Capable (bit 15) 61 const HPET_CAP_LEG_RT_CAP_SHIFT: usize = 15; 62 /// Vendor ID (bits 16:31) 63 const HPET_CAP_VENDER_ID_VALUE: u64 = 0x8086; 64 const HPET_CAP_VENDER_ID_SHIFT: usize = 16; 65 /// Main Counter Tick Period (bits 32:63) 66 const HPET_CAP_CNT_CLK_PERIOD_SHIFT: usize = 32; 67 68 /// Overall Enable (bit 0) 69 const HPET_CFG_ENABLE_SHIFT: usize = 0; 70 /// Legacy Replacement Route (bit 1) 71 const HPET_CFG_LEG_RT_SHIFT: usize = 1; 72 /// Other bits are reserved. 73 const HPET_CFG_WRITE_MASK: u64 = 0x003; 74 75 /// bit 0, 7, and bits 16:31 are reserved. 76 /// bit 4, 5, 15, and bits 32:64 are read-only. 77 const HPET_TN_CFG_WRITE_MASK: u64 = 0x7f4e; 78 /// Timer N Interrupt Type (bit 1) 79 const HPET_TN_CFG_INT_TYPE_SHIFT: usize = 1; 80 /// Timer N Interrupt Enable (bit 2) 81 const HPET_TN_CFG_INT_ENABLE_SHIFT: usize = 2; 82 /// Timer N Type (Periodic enabled or not, bit 3) 83 const HPET_TN_CFG_PERIODIC_SHIFT: usize = 3; 84 /// Timer N Periodic Interrupt Capable (support Periodic or not, bit 4) 85 const HPET_TN_CFG_PERIODIC_CAP_SHIFT: usize = 4; 86 /// Timer N Size (timer size is 64-bits or 32 bits, bit 5) 87 const HPET_TN_CFG_SIZE_CAP_SHIFT: usize = 5; 88 /// Timer N Value Set (bit 6) 89 const HPET_TN_CFG_SETVAL_SHIFT: usize = 6; 90 /// Timer N 32-bit Mode (bit 8) 91 const HPET_TN_CFG_32BIT_SHIFT: usize = 8; 92 /// Timer N Interrupt Rout (bits 9:13) 93 const HPET_TN_CFG_INT_ROUTE_MASK: u64 = 0x3e00; 94 const HPET_TN_CFG_INT_ROUTE_SHIFT: usize = 9; 95 /// Timer N FSB Interrupt Enable (bit 14) 96 const HPET_TN_CFG_FSB_ENABLE_SHIFT: usize = 14; 97 /// Timer N FSB Interrupt Delivery (bit 15) 98 const HPET_TN_CFG_FSB_CAP_SHIFT: usize = 15; 99 /// Timer N Interrupt Routing Capability (bits 32:63) 100 const HPET_TN_CFG_INT_ROUTE_CAP_SHIFT: usize = 32; 101 102 #[derive(qemu_api_macros::TryInto)] 103 #[repr(u64)] 104 #[allow(non_camel_case_types)] 105 /// Timer registers, masked by 0x18 106 enum TimerRegister { 107 /// Timer N Configuration and Capability Register 108 CFG = 0, 109 /// Timer N Comparator Value Register 110 CMP = 8, 111 /// Timer N FSB Interrupt Route Register 112 ROUTE = 16, 113 } 114 115 #[derive(qemu_api_macros::TryInto)] 116 #[repr(u64)] 117 #[allow(non_camel_case_types)] 118 /// Global registers 119 enum GlobalRegister { 120 /// General Capabilities and ID Register 121 CAP = 0, 122 /// General Configuration Register 123 CFG = 0x10, 124 /// General Interrupt Status Register 125 INT_STATUS = 0x20, 126 /// Main Counter Value Register 127 COUNTER = 0xF0, 128 } 129 130 enum HPETRegister<'a> { 131 /// Global register in the range from `0` to `0xff` 132 Global(GlobalRegister), 133 134 /// Register in the timer block `0x100`...`0x3ff` 135 Timer(&'a BqlRefCell<HPETTimer>, TimerRegister), 136 137 /// Invalid address 138 #[allow(dead_code)] 139 Unknown(hwaddr), 140 } 141 142 struct HPETAddrDecode<'a> { 143 shift: u32, 144 len: u32, 145 reg: HPETRegister<'a>, 146 } 147 148 const fn hpet_next_wrap(cur_tick: u64) -> u64 { 149 (cur_tick | 0xffffffff) + 1 150 } 151 152 const fn hpet_time_after(a: u64, b: u64) -> bool { 153 ((b - a) as i64) < 0 154 } 155 156 const fn ticks_to_ns(value: u64) -> u64 { 157 value * HPET_CLK_PERIOD 158 } 159 160 const fn ns_to_ticks(value: u64) -> u64 { 161 value / HPET_CLK_PERIOD 162 } 163 164 // Avoid touching the bits that cannot be written. 165 const fn hpet_fixup_reg(new: u64, old: u64, mask: u64) -> u64 { 166 (new & mask) | (old & !mask) 167 } 168 169 const fn activating_bit(old: u64, new: u64, shift: usize) -> bool { 170 let mask: u64 = 1 << shift; 171 (old & mask == 0) && (new & mask != 0) 172 } 173 174 const fn deactivating_bit(old: u64, new: u64, shift: usize) -> bool { 175 let mask: u64 = 1 << shift; 176 (old & mask != 0) && (new & mask == 0) 177 } 178 179 fn timer_handler(timer_cell: &BqlRefCell<HPETTimer>) { 180 timer_cell.borrow_mut().callback() 181 } 182 183 /// HPET Timer Abstraction 184 #[repr(C)] 185 #[derive(Debug)] 186 pub struct HPETTimer { 187 /// timer N index within the timer block (`HPETState`) 188 #[doc(alias = "tn")] 189 index: u8, 190 qemu_timer: Timer, 191 /// timer block abstraction containing this timer 192 state: NonNull<HPETState>, 193 194 // Memory-mapped, software visible timer registers 195 /// Timer N Configuration and Capability Register 196 config: u64, 197 /// Timer N Comparator Value Register 198 cmp: u64, 199 /// Timer N FSB Interrupt Route Register 200 fsb: u64, 201 202 // Hidden register state 203 /// comparator (extended to counter width) 204 cmp64: u64, 205 /// Last value written to comparator 206 period: u64, 207 /// timer pop will indicate wrap for one-shot 32-bit 208 /// mode. Next pop will be actual timer expiration. 209 wrap_flag: u8, 210 /// last value armed, to avoid timer storms 211 last: u64, 212 } 213 214 impl HPETTimer { 215 fn init(&mut self, index: u8, state: &HPETState) { 216 *self = HPETTimer { 217 index, 218 // SAFETY: the HPETTimer will only be used after the timer 219 // is initialized below. 220 qemu_timer: unsafe { Timer::new() }, 221 state: NonNull::new((state as *const HPETState).cast_mut()).unwrap(), 222 config: 0, 223 cmp: 0, 224 fsb: 0, 225 cmp64: 0, 226 period: 0, 227 wrap_flag: 0, 228 last: 0, 229 }; 230 231 // SAFETY: HPETTimer is only used as part of HPETState, which is 232 // always pinned. 233 let qemu_timer = unsafe { Pin::new_unchecked(&mut self.qemu_timer) }; 234 qemu_timer.init_full( 235 None, 236 CLOCK_VIRTUAL, 237 Timer::NS, 238 0, 239 timer_handler, 240 &state.timers[self.index as usize], 241 ) 242 } 243 244 fn get_state(&self) -> &HPETState { 245 // SAFETY: 246 // the pointer is convertible to a reference 247 unsafe { self.state.as_ref() } 248 } 249 250 fn is_int_active(&self) -> bool { 251 self.get_state().is_timer_int_active(self.index.into()) 252 } 253 254 const fn is_fsb_route_enabled(&self) -> bool { 255 self.config & (1 << HPET_TN_CFG_FSB_ENABLE_SHIFT) != 0 256 } 257 258 const fn is_periodic(&self) -> bool { 259 self.config & (1 << HPET_TN_CFG_PERIODIC_SHIFT) != 0 260 } 261 262 const fn is_int_enabled(&self) -> bool { 263 self.config & (1 << HPET_TN_CFG_INT_ENABLE_SHIFT) != 0 264 } 265 266 const fn is_32bit_mod(&self) -> bool { 267 self.config & (1 << HPET_TN_CFG_32BIT_SHIFT) != 0 268 } 269 270 const fn is_valset_enabled(&self) -> bool { 271 self.config & (1 << HPET_TN_CFG_SETVAL_SHIFT) != 0 272 } 273 274 fn clear_valset(&mut self) { 275 self.config &= !(1 << HPET_TN_CFG_SETVAL_SHIFT); 276 } 277 278 /// True if timer interrupt is level triggered; otherwise, edge triggered. 279 const fn is_int_level_triggered(&self) -> bool { 280 self.config & (1 << HPET_TN_CFG_INT_TYPE_SHIFT) != 0 281 } 282 283 /// calculate next value of the general counter that matches the 284 /// target (either entirely, or the low 32-bit only depending on 285 /// the timer mode). 286 fn calculate_cmp64(&self, cur_tick: u64, target: u64) -> u64 { 287 if self.is_32bit_mod() { 288 let mut result: u64 = cur_tick.deposit(0, 32, target); 289 if result < cur_tick { 290 result += 0x100000000; 291 } 292 result 293 } else { 294 target 295 } 296 } 297 298 const fn get_individual_route(&self) -> usize { 299 ((self.config & HPET_TN_CFG_INT_ROUTE_MASK) >> HPET_TN_CFG_INT_ROUTE_SHIFT) as usize 300 } 301 302 fn get_int_route(&self) -> usize { 303 if self.index <= 1 && self.get_state().is_legacy_mode() { 304 // If LegacyReplacement Route bit is set, HPET specification requires 305 // timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, 306 // timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. 307 // 308 // If the LegacyReplacement Route bit is set, the individual routing 309 // bits for timers 0 and 1 (APIC or FSB) will have no impact. 310 // 311 // FIXME: Consider I/O APIC case. 312 if self.index == 0 { 313 0 314 } else { 315 RTC_ISA_IRQ 316 } 317 } else { 318 // (If the LegacyReplacement Route bit is set) Timer 2-n will be 319 // routed as per the routing in the timer n config registers. 320 // ... 321 // If the LegacyReplacement Route bit is not set, the individual 322 // routing bits for each of the timers are used. 323 self.get_individual_route() 324 } 325 } 326 327 fn set_irq(&mut self, set: bool) { 328 let route = self.get_int_route(); 329 330 if set && self.is_int_enabled() && self.get_state().is_hpet_enabled() { 331 if self.is_fsb_route_enabled() { 332 // SAFETY: 333 // the parameters are valid. 334 unsafe { 335 address_space_stl_le( 336 addr_of_mut!(address_space_memory), 337 self.fsb >> 32, // Timer N FSB int addr 338 self.fsb as u32, // Timer N FSB int value, truncate! 339 MEMTXATTRS_UNSPECIFIED, 340 null_mut(), 341 ); 342 } 343 } else if self.is_int_level_triggered() { 344 self.get_state().irqs[route].raise(); 345 } else { 346 self.get_state().irqs[route].pulse(); 347 } 348 } else if !self.is_fsb_route_enabled() { 349 self.get_state().irqs[route].lower(); 350 } 351 } 352 353 fn update_irq(&mut self, set: bool) { 354 // If Timer N Interrupt Enable bit is 0, "the timer will 355 // still operate and generate appropriate status bits, but 356 // will not cause an interrupt" 357 self.get_state() 358 .update_int_status(self.index.into(), set && self.is_int_level_triggered()); 359 self.set_irq(set); 360 } 361 362 fn arm_timer(&mut self, tick: u64) { 363 let mut ns = self.get_state().get_ns(tick); 364 365 // Clamp period to reasonable min value (1 us) 366 if self.is_periodic() && ns - self.last < 1000 { 367 ns = self.last + 1000; 368 } 369 370 self.last = ns; 371 self.qemu_timer.modify(self.last); 372 } 373 374 fn set_timer(&mut self) { 375 let cur_tick: u64 = self.get_state().get_ticks(); 376 377 self.wrap_flag = 0; 378 self.cmp64 = self.calculate_cmp64(cur_tick, self.cmp); 379 if self.is_32bit_mod() { 380 // HPET spec says in one-shot 32-bit mode, generate an interrupt when 381 // counter wraps in addition to an interrupt with comparator match. 382 if !self.is_periodic() && self.cmp64 > hpet_next_wrap(cur_tick) { 383 self.wrap_flag = 1; 384 self.arm_timer(hpet_next_wrap(cur_tick)); 385 return; 386 } 387 } 388 self.arm_timer(self.cmp64); 389 } 390 391 fn del_timer(&mut self) { 392 // Just remove the timer from the timer_list without destroying 393 // this timer instance. 394 self.qemu_timer.delete(); 395 396 if self.is_int_active() { 397 // For level-triggered interrupt, this leaves interrupt status 398 // register set but lowers irq. 399 self.update_irq(true); 400 } 401 } 402 403 /// Configuration and Capability Register 404 fn set_tn_cfg_reg(&mut self, shift: u32, len: u32, val: u64) { 405 // TODO: Add trace point - trace_hpet_ram_write_tn_cfg(addr & 4) 406 let old_val: u64 = self.config; 407 let mut new_val: u64 = old_val.deposit(shift, len, val); 408 new_val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); 409 410 // Switch level-type interrupt to edge-type. 411 if deactivating_bit(old_val, new_val, HPET_TN_CFG_INT_TYPE_SHIFT) { 412 // Do this before changing timer.config; otherwise, if 413 // HPET_TN_FSB is set, update_irq will not lower the qemu_irq. 414 self.update_irq(false); 415 } 416 417 self.config = new_val; 418 419 if activating_bit(old_val, new_val, HPET_TN_CFG_INT_ENABLE_SHIFT) && self.is_int_active() { 420 self.update_irq(true); 421 } 422 423 if self.is_32bit_mod() { 424 self.cmp = u64::from(self.cmp as u32); // truncate! 425 self.period = u64::from(self.period as u32); // truncate! 426 } 427 428 if self.get_state().is_hpet_enabled() { 429 self.set_timer(); 430 } 431 } 432 433 /// Comparator Value Register 434 fn set_tn_cmp_reg(&mut self, shift: u32, len: u32, val: u64) { 435 let mut length = len; 436 let mut value = val; 437 438 // TODO: Add trace point - trace_hpet_ram_write_tn_cmp(addr & 4) 439 if self.is_32bit_mod() { 440 // High 32-bits are zero, leave them untouched. 441 if shift != 0 { 442 // TODO: Add trace point - trace_hpet_ram_write_invalid_tn_cmp() 443 return; 444 } 445 length = 64; 446 value = u64::from(value as u32); // truncate! 447 } 448 449 if !self.is_periodic() || self.is_valset_enabled() { 450 self.cmp = self.cmp.deposit(shift, length, value); 451 } 452 453 if self.is_periodic() { 454 self.period = self.period.deposit(shift, length, value); 455 } 456 457 self.clear_valset(); 458 if self.get_state().is_hpet_enabled() { 459 self.set_timer(); 460 } 461 } 462 463 /// FSB Interrupt Route Register 464 fn set_tn_fsb_route_reg(&mut self, shift: u32, len: u32, val: u64) { 465 self.fsb = self.fsb.deposit(shift, len, val); 466 } 467 468 fn reset(&mut self) { 469 self.del_timer(); 470 self.cmp = u64::MAX; // Comparator Match Registers reset to all 1's. 471 self.config = (1 << HPET_TN_CFG_PERIODIC_CAP_SHIFT) | (1 << HPET_TN_CFG_SIZE_CAP_SHIFT); 472 if self.get_state().has_msi_flag() { 473 self.config |= 1 << HPET_TN_CFG_FSB_CAP_SHIFT; 474 } 475 // advertise availability of ioapic int 476 self.config |= 477 (u64::from(self.get_state().int_route_cap)) << HPET_TN_CFG_INT_ROUTE_CAP_SHIFT; 478 self.period = 0; 479 self.wrap_flag = 0; 480 } 481 482 /// timer expiration callback 483 fn callback(&mut self) { 484 let period: u64 = self.period; 485 let cur_tick: u64 = self.get_state().get_ticks(); 486 487 if self.is_periodic() && period != 0 { 488 while hpet_time_after(cur_tick, self.cmp64) { 489 self.cmp64 += period; 490 } 491 if self.is_32bit_mod() { 492 self.cmp = u64::from(self.cmp64 as u32); // truncate! 493 } else { 494 self.cmp = self.cmp64; 495 } 496 self.arm_timer(self.cmp64); 497 } else if self.wrap_flag != 0 { 498 self.wrap_flag = 0; 499 self.arm_timer(self.cmp64); 500 } 501 self.update_irq(true); 502 } 503 504 const fn read(&self, reg: TimerRegister) -> u64 { 505 use TimerRegister::*; 506 match reg { 507 CFG => self.config, // including interrupt capabilities 508 CMP => self.cmp, // comparator register 509 ROUTE => self.fsb, 510 } 511 } 512 513 fn write(&mut self, reg: TimerRegister, value: u64, shift: u32, len: u32) { 514 use TimerRegister::*; 515 match reg { 516 CFG => self.set_tn_cfg_reg(shift, len, value), 517 CMP => self.set_tn_cmp_reg(shift, len, value), 518 ROUTE => self.set_tn_fsb_route_reg(shift, len, value), 519 } 520 } 521 } 522 523 /// HPET Event Timer Block Abstraction 524 #[repr(C)] 525 #[derive(qemu_api_macros::Object)] 526 pub struct HPETState { 527 parent_obj: ParentField<SysBusDevice>, 528 iomem: MemoryRegion, 529 530 // HPET block Registers: Memory-mapped, software visible registers 531 /// General Capabilities and ID Register 532 capability: BqlCell<u64>, 533 /// General Configuration Register 534 config: BqlCell<u64>, 535 /// General Interrupt Status Register 536 #[doc(alias = "isr")] 537 int_status: BqlCell<u64>, 538 /// Main Counter Value Register 539 #[doc(alias = "hpet_counter")] 540 counter: BqlCell<u64>, 541 542 // Internal state 543 /// Capabilities that QEMU HPET supports. 544 /// bit 0: MSI (or FSB) support. 545 flags: u32, 546 547 /// Offset of main counter relative to qemu clock. 548 hpet_offset: BqlCell<u64>, 549 hpet_offset_saved: bool, 550 551 irqs: [InterruptSource; HPET_NUM_IRQ_ROUTES], 552 rtc_irq_level: BqlCell<u32>, 553 pit_enabled: InterruptSource, 554 555 /// Interrupt Routing Capability. 556 /// This field indicates to which interrupts in the I/O (x) APIC 557 /// the timers' interrupt can be routed, and is encoded in the 558 /// bits 32:64 of timer N's config register: 559 #[doc(alias = "intcap")] 560 int_route_cap: u32, 561 562 /// HPET timer array managed by this timer block. 563 #[doc(alias = "timer")] 564 timers: [BqlRefCell<HPETTimer>; HPET_MAX_TIMERS], 565 num_timers: BqlCell<usize>, 566 num_timers_save: BqlCell<u8>, 567 568 /// Instance id (HPET timer block ID). 569 hpet_id: BqlCell<usize>, 570 } 571 572 impl HPETState { 573 // Get num_timers with `usize` type, which is useful to play with array index. 574 fn get_num_timers(&self) -> usize { 575 self.num_timers.get() 576 } 577 578 const fn has_msi_flag(&self) -> bool { 579 self.flags & (1 << HPET_FLAG_MSI_SUPPORT_SHIFT) != 0 580 } 581 582 fn is_legacy_mode(&self) -> bool { 583 self.config.get() & (1 << HPET_CFG_LEG_RT_SHIFT) != 0 584 } 585 586 fn is_hpet_enabled(&self) -> bool { 587 self.config.get() & (1 << HPET_CFG_ENABLE_SHIFT) != 0 588 } 589 590 fn is_timer_int_active(&self, index: usize) -> bool { 591 self.int_status.get() & (1 << index) != 0 592 } 593 594 fn get_ticks(&self) -> u64 { 595 ns_to_ticks(CLOCK_VIRTUAL.get_ns() + self.hpet_offset.get()) 596 } 597 598 fn get_ns(&self, tick: u64) -> u64 { 599 ticks_to_ns(tick) - self.hpet_offset.get() 600 } 601 602 fn handle_legacy_irq(&self, irq: u32, level: u32) { 603 if irq == HPET_LEGACY_PIT_INT { 604 if !self.is_legacy_mode() { 605 self.irqs[0].set(level != 0); 606 } 607 } else { 608 self.rtc_irq_level.set(level); 609 if !self.is_legacy_mode() { 610 self.irqs[RTC_ISA_IRQ].set(level != 0); 611 } 612 } 613 } 614 615 fn init_timer(&self) { 616 for (index, timer) in self.timers.iter().enumerate() { 617 timer.borrow_mut().init(index.try_into().unwrap(), self); 618 } 619 } 620 621 fn update_int_status(&self, index: u32, level: bool) { 622 self.int_status 623 .set(self.int_status.get().deposit(index, 1, u64::from(level))); 624 } 625 626 /// General Configuration Register 627 fn set_cfg_reg(&self, shift: u32, len: u32, val: u64) { 628 let old_val = self.config.get(); 629 let mut new_val = old_val.deposit(shift, len, val); 630 631 new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); 632 self.config.set(new_val); 633 634 if activating_bit(old_val, new_val, HPET_CFG_ENABLE_SHIFT) { 635 // Enable main counter and interrupt generation. 636 self.hpet_offset 637 .set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns()); 638 639 for timer in self.timers.iter().take(self.get_num_timers()) { 640 let mut t = timer.borrow_mut(); 641 642 if t.is_int_enabled() && t.is_int_active() { 643 t.update_irq(true); 644 } 645 t.set_timer(); 646 } 647 } else if deactivating_bit(old_val, new_val, HPET_CFG_ENABLE_SHIFT) { 648 // Halt main counter and disable interrupt generation. 649 self.counter.set(self.get_ticks()); 650 651 for timer in self.timers.iter().take(self.get_num_timers()) { 652 timer.borrow_mut().del_timer(); 653 } 654 } 655 656 // i8254 and RTC output pins are disabled when HPET is in legacy mode 657 if activating_bit(old_val, new_val, HPET_CFG_LEG_RT_SHIFT) { 658 self.pit_enabled.set(false); 659 self.irqs[0].lower(); 660 self.irqs[RTC_ISA_IRQ].lower(); 661 } else if deactivating_bit(old_val, new_val, HPET_CFG_LEG_RT_SHIFT) { 662 // TODO: Add irq binding: qemu_irq_lower(s->irqs[0]) 663 self.irqs[0].lower(); 664 self.pit_enabled.set(true); 665 self.irqs[RTC_ISA_IRQ].set(self.rtc_irq_level.get() != 0); 666 } 667 } 668 669 /// General Interrupt Status Register: Read/Write Clear 670 fn set_int_status_reg(&self, shift: u32, _len: u32, val: u64) { 671 let new_val = val << shift; 672 let cleared = new_val & self.int_status.get(); 673 674 for (index, timer) in self.timers.iter().take(self.get_num_timers()).enumerate() { 675 if cleared & (1 << index) != 0 { 676 timer.borrow_mut().update_irq(false); 677 } 678 } 679 } 680 681 /// Main Counter Value Register 682 fn set_counter_reg(&self, shift: u32, len: u32, val: u64) { 683 if self.is_hpet_enabled() { 684 // TODO: Add trace point - 685 // trace_hpet_ram_write_counter_write_while_enabled() 686 // 687 // HPET spec says that writes to this register should only be 688 // done while the counter is halted. So this is an undefined 689 // behavior. There's no need to forbid it, but when HPET is 690 // enabled, the changed counter value will not affect the 691 // tick count (i.e., the previously calculated offset will 692 // not be changed as well). 693 } 694 self.counter 695 .set(self.counter.get().deposit(shift, len, val)); 696 } 697 698 unsafe fn init(&mut self) { 699 static HPET_RAM_OPS: MemoryRegionOps<HPETState> = 700 MemoryRegionOpsBuilder::<HPETState>::new() 701 .read(&HPETState::read) 702 .write(&HPETState::write) 703 .native_endian() 704 .valid_sizes(4, 8) 705 .impl_sizes(4, 8) 706 .build(); 707 708 // SAFETY: 709 // self and self.iomem are guaranteed to be valid at this point since callers 710 // must make sure the `self` reference is valid. 711 MemoryRegion::init_io( 712 unsafe { &mut *addr_of_mut!(self.iomem) }, 713 addr_of_mut!(*self), 714 &HPET_RAM_OPS, 715 "hpet", 716 HPET_REG_SPACE_LEN, 717 ); 718 } 719 720 fn post_init(&self) { 721 self.init_mmio(&self.iomem); 722 for irq in self.irqs.iter() { 723 self.init_irq(irq); 724 } 725 } 726 727 fn realize(&self) -> qemu_api::Result<()> { 728 if self.num_timers.get() < HPET_MIN_TIMERS || self.num_timers.get() > HPET_MAX_TIMERS { 729 Err(format!( 730 "hpet.num_timers must be between {HPET_MIN_TIMERS} and {HPET_MAX_TIMERS}" 731 ))?; 732 } 733 if self.int_route_cap == 0 { 734 Err("hpet.hpet-intcap property not initialized")?; 735 } 736 737 self.hpet_id.set(HPETFwConfig::assign_hpet_id()?); 738 739 self.init_timer(); 740 // 64-bit General Capabilities and ID Register; LegacyReplacementRoute. 741 self.capability.set( 742 HPET_CAP_REV_ID_VALUE << HPET_CAP_REV_ID_SHIFT | 743 1 << HPET_CAP_COUNT_SIZE_CAP_SHIFT | 744 1 << HPET_CAP_LEG_RT_CAP_SHIFT | 745 HPET_CAP_VENDER_ID_VALUE << HPET_CAP_VENDER_ID_SHIFT | 746 ((self.get_num_timers() - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT | // indicate the last timer 747 (HPET_CLK_PERIOD * FS_PER_NS) << HPET_CAP_CNT_CLK_PERIOD_SHIFT, // 10 ns 748 ); 749 750 self.init_gpio_in(2, HPETState::handle_legacy_irq); 751 self.init_gpio_out(from_ref(&self.pit_enabled)); 752 Ok(()) 753 } 754 755 fn reset_hold(&self, _type: ResetType) { 756 for timer in self.timers.iter().take(self.get_num_timers()) { 757 timer.borrow_mut().reset(); 758 } 759 760 self.counter.set(0); 761 self.config.set(0); 762 self.pit_enabled.set(true); 763 self.hpet_offset.set(0); 764 765 HPETFwConfig::update_hpet_cfg( 766 self.hpet_id.get(), 767 self.capability.get() as u32, 768 self.mmio_addr(0).unwrap(), 769 ); 770 771 // to document that the RTC lowers its output on reset as well 772 self.rtc_irq_level.set(0); 773 } 774 775 fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode { 776 let shift = ((addr & 4) * 8) as u32; 777 let len = std::cmp::min(size * 8, 64 - shift); 778 779 addr &= !4; 780 let reg = if (0..=0xff).contains(&addr) { 781 GlobalRegister::try_from(addr).map(HPETRegister::Global) 782 } else { 783 let timer_id: usize = ((addr - 0x100) / 0x20) as usize; 784 if timer_id <= self.get_num_timers() { 785 // TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id) 786 TimerRegister::try_from(addr & 0x18) 787 .map(|reg| HPETRegister::Timer(&self.timers[timer_id], reg)) 788 } else { 789 // TODO: Add trace point - trace_hpet_timer_id_out_of_range(timer_id) 790 Err(addr) 791 } 792 }; 793 794 // reg is now a Result<HPETRegister, hwaddr> 795 // convert the Err case into HPETRegister as well 796 let reg = reg.unwrap_or_else(HPETRegister::Unknown); 797 HPETAddrDecode { shift, len, reg } 798 } 799 800 fn read(&self, addr: hwaddr, size: u32) -> u64 { 801 // TODO: Add trace point - trace_hpet_ram_read(addr) 802 let HPETAddrDecode { shift, reg, .. } = self.decode(addr, size); 803 804 use GlobalRegister::*; 805 use HPETRegister::*; 806 (match reg { 807 Timer(timer, tn_reg) => timer.borrow_mut().read(tn_reg), 808 Global(CAP) => self.capability.get(), /* including HPET_PERIOD 0x004 */ 809 Global(CFG) => self.config.get(), 810 Global(INT_STATUS) => self.int_status.get(), 811 Global(COUNTER) => { 812 // TODO: Add trace point 813 // trace_hpet_ram_read_reading_counter(addr & 4, cur_tick) 814 if self.is_hpet_enabled() { 815 self.get_ticks() 816 } else { 817 self.counter.get() 818 } 819 } 820 Unknown(_) => { 821 // TODO: Add trace point- trace_hpet_ram_read_invalid() 822 0 823 } 824 }) >> shift 825 } 826 827 fn write(&self, addr: hwaddr, value: u64, size: u32) { 828 let HPETAddrDecode { shift, len, reg } = self.decode(addr, size); 829 830 // TODO: Add trace point - trace_hpet_ram_write(addr, value) 831 use GlobalRegister::*; 832 use HPETRegister::*; 833 match reg { 834 Timer(timer, tn_reg) => timer.borrow_mut().write(tn_reg, value, shift, len), 835 Global(CAP) => {} // General Capabilities and ID Register: Read Only 836 Global(CFG) => self.set_cfg_reg(shift, len, value), 837 Global(INT_STATUS) => self.set_int_status_reg(shift, len, value), 838 Global(COUNTER) => self.set_counter_reg(shift, len, value), 839 Unknown(_) => { 840 // TODO: Add trace point - trace_hpet_ram_write_invalid() 841 } 842 } 843 } 844 845 fn pre_save(&self) -> i32 { 846 if self.is_hpet_enabled() { 847 self.counter.set(self.get_ticks()); 848 } 849 850 /* 851 * The number of timers must match on source and destination, but it was 852 * also added to the migration stream. Check that it matches the value 853 * that was configured. 854 */ 855 self.num_timers_save.set(self.num_timers.get() as u8); 856 0 857 } 858 859 fn post_load(&self, _version_id: u8) -> i32 { 860 for timer in self.timers.iter().take(self.get_num_timers()) { 861 let mut t = timer.borrow_mut(); 862 863 t.cmp64 = t.calculate_cmp64(t.get_state().counter.get(), t.cmp); 864 t.last = CLOCK_VIRTUAL.get_ns() - NANOSECONDS_PER_SECOND; 865 } 866 867 // Recalculate the offset between the main counter and guest time 868 if !self.hpet_offset_saved { 869 self.hpet_offset 870 .set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns()); 871 } 872 873 0 874 } 875 876 fn is_rtc_irq_level_needed(&self) -> bool { 877 self.rtc_irq_level.get() != 0 878 } 879 880 fn is_offset_needed(&self) -> bool { 881 self.is_hpet_enabled() && self.hpet_offset_saved 882 } 883 884 fn validate_num_timers(&self, _version_id: u8) -> bool { 885 self.num_timers.get() == self.num_timers_save.get().into() 886 } 887 } 888 889 qom_isa!(HPETState: SysBusDevice, DeviceState, Object); 890 891 unsafe impl ObjectType for HPETState { 892 // No need for HPETClass. Just like OBJECT_DECLARE_SIMPLE_TYPE in C. 893 type Class = <SysBusDevice as ObjectType>::Class; 894 const TYPE_NAME: &'static CStr = crate::TYPE_HPET; 895 } 896 897 impl ObjectImpl for HPETState { 898 type ParentType = SysBusDevice; 899 900 const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = Some(Self::init); 901 const INSTANCE_POST_INIT: Option<fn(&Self)> = Some(Self::post_init); 902 const CLASS_INIT: fn(&mut Self::Class) = Self::Class::class_init::<Self>; 903 } 904 905 // TODO: Make these properties user-configurable! 906 qemu_api::declare_properties! { 907 HPET_PROPERTIES, 908 qemu_api::define_property!( 909 c"timers", 910 HPETState, 911 num_timers, 912 unsafe { &qdev_prop_usize }, 913 u8, 914 default = HPET_MIN_TIMERS 915 ), 916 qemu_api::define_property!( 917 c"msi", 918 HPETState, 919 flags, 920 unsafe { &qdev_prop_bit }, 921 u32, 922 bit = HPET_FLAG_MSI_SUPPORT_SHIFT as u8, 923 default = false, 924 ), 925 qemu_api::define_property!( 926 c"hpet-intcap", 927 HPETState, 928 int_route_cap, 929 unsafe { &qdev_prop_uint32 }, 930 u32, 931 default = 0 932 ), 933 qemu_api::define_property!( 934 c"hpet-offset-saved", 935 HPETState, 936 hpet_offset_saved, 937 unsafe { &qdev_prop_bool }, 938 bool, 939 default = true 940 ), 941 } 942 943 unsafe extern "C" fn hpet_rtc_irq_level_needed(opaque: *mut c_void) -> bool { 944 // SAFETY: 945 // the pointer is convertible to a reference 946 let state: &HPETState = unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_ref() }; 947 state.is_rtc_irq_level_needed() 948 } 949 950 unsafe extern "C" fn hpet_offset_needed(opaque: *mut c_void) -> bool { 951 // SAFETY: 952 // the pointer is convertible to a reference 953 let state: &HPETState = unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_ref() }; 954 state.is_offset_needed() 955 } 956 957 unsafe extern "C" fn hpet_pre_save(opaque: *mut c_void) -> c_int { 958 // SAFETY: 959 // the pointer is convertible to a reference 960 let state: &mut HPETState = 961 unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_mut() }; 962 state.pre_save() as c_int 963 } 964 965 unsafe extern "C" fn hpet_post_load(opaque: *mut c_void, version_id: c_int) -> c_int { 966 // SAFETY: 967 // the pointer is convertible to a reference 968 let state: &mut HPETState = 969 unsafe { NonNull::new(opaque.cast::<HPETState>()).unwrap().as_mut() }; 970 let version: u8 = version_id.try_into().unwrap(); 971 state.post_load(version) as c_int 972 } 973 974 static VMSTATE_HPET_RTC_IRQ_LEVEL: VMStateDescription = VMStateDescription { 975 name: c"hpet/rtc_irq_level".as_ptr(), 976 version_id: 1, 977 minimum_version_id: 1, 978 needed: Some(hpet_rtc_irq_level_needed), 979 fields: vmstate_fields! { 980 vmstate_of!(HPETState, rtc_irq_level), 981 }, 982 ..Zeroable::ZERO 983 }; 984 985 static VMSTATE_HPET_OFFSET: VMStateDescription = VMStateDescription { 986 name: c"hpet/offset".as_ptr(), 987 version_id: 1, 988 minimum_version_id: 1, 989 needed: Some(hpet_offset_needed), 990 fields: vmstate_fields! { 991 vmstate_of!(HPETState, hpet_offset), 992 }, 993 ..Zeroable::ZERO 994 }; 995 996 static VMSTATE_HPET_TIMER: VMStateDescription = VMStateDescription { 997 name: c"hpet_timer".as_ptr(), 998 version_id: 1, 999 minimum_version_id: 1, 1000 fields: vmstate_fields! { 1001 vmstate_of!(HPETTimer, index), 1002 vmstate_of!(HPETTimer, config), 1003 vmstate_of!(HPETTimer, cmp), 1004 vmstate_of!(HPETTimer, fsb), 1005 vmstate_of!(HPETTimer, period), 1006 vmstate_of!(HPETTimer, wrap_flag), 1007 vmstate_of!(HPETTimer, qemu_timer), 1008 }, 1009 ..Zeroable::ZERO 1010 }; 1011 1012 const VALIDATE_TIMERS_NAME: &CStr = c"num_timers must match"; 1013 1014 static VMSTATE_HPET: VMStateDescription = VMStateDescription { 1015 name: c"hpet".as_ptr(), 1016 version_id: 2, 1017 minimum_version_id: 2, 1018 pre_save: Some(hpet_pre_save), 1019 post_load: Some(hpet_post_load), 1020 fields: vmstate_fields! { 1021 vmstate_of!(HPETState, config), 1022 vmstate_of!(HPETState, int_status), 1023 vmstate_of!(HPETState, counter), 1024 vmstate_of!(HPETState, num_timers_save), 1025 vmstate_validate!(HPETState, VALIDATE_TIMERS_NAME, HPETState::validate_num_timers), 1026 vmstate_struct!(HPETState, timers[0 .. num_timers_save], &VMSTATE_HPET_TIMER, BqlRefCell<HPETTimer>, HPETState::validate_num_timers).with_version_id(0), 1027 }, 1028 subsections: vmstate_subsections! { 1029 VMSTATE_HPET_RTC_IRQ_LEVEL, 1030 VMSTATE_HPET_OFFSET, 1031 }, 1032 ..Zeroable::ZERO 1033 }; 1034 1035 impl DeviceImpl for HPETState { 1036 fn properties() -> &'static [Property] { 1037 &HPET_PROPERTIES 1038 } 1039 1040 fn vmsd() -> Option<&'static VMStateDescription> { 1041 Some(&VMSTATE_HPET) 1042 } 1043 1044 const REALIZE: Option<fn(&Self) -> qemu_api::Result<()>> = Some(Self::realize); 1045 } 1046 1047 impl ResettablePhasesImpl for HPETState { 1048 const HOLD: Option<fn(&Self, ResetType)> = Some(Self::reset_hold); 1049 } 1050 1051 impl SysBusDeviceImpl for HPETState {} 1052