1*ba7651fbSMax Filippov #ifndef XTENSA_TARGET_SYSCALL_H 2*ba7651fbSMax Filippov #define XTENSA_TARGET_SYSCALL_H 3*ba7651fbSMax Filippov 4*ba7651fbSMax Filippov #define UNAME_MACHINE "xtensa" 5*ba7651fbSMax Filippov 6*ba7651fbSMax Filippov #define UNAME_MINIMUM_RELEASE "3.19" 7*ba7651fbSMax Filippov #define TARGET_CLONE_BACKWARDS 8*ba7651fbSMax Filippov 9*ba7651fbSMax Filippov #define MMAP_SHIFT TARGET_PAGE_BITS 10*ba7651fbSMax Filippov 11*ba7651fbSMax Filippov typedef uint32_t xtensa_reg_t; 12*ba7651fbSMax Filippov typedef struct { 13*ba7651fbSMax Filippov } xtregs_opt_t; /* TODO */ 14*ba7651fbSMax Filippov 15*ba7651fbSMax Filippov struct target_pt_regs { 16*ba7651fbSMax Filippov xtensa_reg_t pc; /* 4 */ 17*ba7651fbSMax Filippov xtensa_reg_t ps; /* 8 */ 18*ba7651fbSMax Filippov xtensa_reg_t depc; /* 12 */ 19*ba7651fbSMax Filippov xtensa_reg_t exccause; /* 16 */ 20*ba7651fbSMax Filippov xtensa_reg_t excvaddr; /* 20 */ 21*ba7651fbSMax Filippov xtensa_reg_t debugcause; /* 24 */ 22*ba7651fbSMax Filippov xtensa_reg_t wmask; /* 28 */ 23*ba7651fbSMax Filippov xtensa_reg_t lbeg; /* 32 */ 24*ba7651fbSMax Filippov xtensa_reg_t lend; /* 36 */ 25*ba7651fbSMax Filippov xtensa_reg_t lcount; /* 40 */ 26*ba7651fbSMax Filippov xtensa_reg_t sar; /* 44 */ 27*ba7651fbSMax Filippov xtensa_reg_t windowbase; /* 48 */ 28*ba7651fbSMax Filippov xtensa_reg_t windowstart; /* 52 */ 29*ba7651fbSMax Filippov xtensa_reg_t syscall; /* 56 */ 30*ba7651fbSMax Filippov xtensa_reg_t icountlevel; /* 60 */ 31*ba7651fbSMax Filippov xtensa_reg_t scompare1; /* 64 */ 32*ba7651fbSMax Filippov xtensa_reg_t threadptr; /* 68 */ 33*ba7651fbSMax Filippov 34*ba7651fbSMax Filippov /* Additional configurable registers that are used by the compiler. */ 35*ba7651fbSMax Filippov xtregs_opt_t xtregs_opt; 36*ba7651fbSMax Filippov 37*ba7651fbSMax Filippov /* Make sure the areg field is 16 bytes aligned. */ 38*ba7651fbSMax Filippov int align[0] __attribute__ ((aligned(16))); 39*ba7651fbSMax Filippov 40*ba7651fbSMax Filippov /* current register frame. 41*ba7651fbSMax Filippov * Note: The ESF for kernel exceptions ends after 16 registers! 42*ba7651fbSMax Filippov */ 43*ba7651fbSMax Filippov xtensa_reg_t areg[16]; 44*ba7651fbSMax Filippov }; 45*ba7651fbSMax Filippov 46*ba7651fbSMax Filippov #define TARGET_MLOCKALL_MCL_CURRENT 1 47*ba7651fbSMax Filippov #define TARGET_MLOCKALL_MCL_FUTURE 2 48*ba7651fbSMax Filippov 49*ba7651fbSMax Filippov #endif 50