1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include <stdlib.h> 20 #include <stdio.h> 21 #include <stdarg.h> 22 #include <string.h> 23 #include <errno.h> 24 #include <unistd.h> 25 #include <sys/mman.h> 26 #include <sys/syscall.h> 27 #include <sys/resource.h> 28 29 #include "qemu.h" 30 #include "qemu-common.h" 31 #include "qemu/cache-utils.h" 32 #include "cpu.h" 33 #include "tcg.h" 34 #include "qemu/timer.h" 35 #include "qemu/envlist.h" 36 #include "elf.h" 37 38 char *exec_path; 39 40 int singlestep; 41 const char *filename; 42 const char *argv0; 43 int gdbstub_port; 44 envlist_t *envlist; 45 static const char *cpu_model; 46 unsigned long mmap_min_addr; 47 #if defined(CONFIG_USE_GUEST_BASE) 48 unsigned long guest_base; 49 int have_guest_base; 50 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) 51 /* 52 * When running 32-on-64 we should make sure we can fit all of the possible 53 * guest address space into a contiguous chunk of virtual host memory. 54 * 55 * This way we will never overlap with our own libraries or binaries or stack 56 * or anything else that QEMU maps. 57 */ 58 # ifdef TARGET_MIPS 59 /* MIPS only supports 31 bits of virtual address space for user space */ 60 unsigned long reserved_va = 0x77000000; 61 # else 62 unsigned long reserved_va = 0xf7000000; 63 # endif 64 #else 65 unsigned long reserved_va; 66 #endif 67 #endif 68 69 static void usage(void); 70 71 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; 72 const char *qemu_uname_release = CONFIG_UNAME_RELEASE; 73 74 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 75 we allocate a bigger stack. Need a better solution, for example 76 by remapping the process stack directly at the right place */ 77 unsigned long guest_stack_size = 8 * 1024 * 1024UL; 78 79 void gemu_log(const char *fmt, ...) 80 { 81 va_list ap; 82 83 va_start(ap, fmt); 84 vfprintf(stderr, fmt, ap); 85 va_end(ap); 86 } 87 88 #if defined(TARGET_I386) 89 int cpu_get_pic_interrupt(CPUX86State *env) 90 { 91 return -1; 92 } 93 #endif 94 95 /***********************************************************/ 96 /* Helper routines for implementing atomic operations. */ 97 98 /* To implement exclusive operations we force all cpus to syncronise. 99 We don't require a full sync, only that no cpus are executing guest code. 100 The alternative is to map target atomic ops onto host equivalents, 101 which requires quite a lot of per host/target work. */ 102 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; 103 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; 104 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; 105 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; 106 static int pending_cpus; 107 108 /* Make sure everything is in a consistent state for calling fork(). */ 109 void fork_start(void) 110 { 111 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); 112 pthread_mutex_lock(&exclusive_lock); 113 mmap_fork_start(); 114 } 115 116 void fork_end(int child) 117 { 118 mmap_fork_end(child); 119 if (child) { 120 CPUState *cpu, *next_cpu; 121 /* Child processes created by fork() only have a single thread. 122 Discard information about the parent threads. */ 123 CPU_FOREACH_SAFE(cpu, next_cpu) { 124 if (cpu != thread_cpu) { 125 QTAILQ_REMOVE(&cpus, thread_cpu, node); 126 } 127 } 128 pending_cpus = 0; 129 pthread_mutex_init(&exclusive_lock, NULL); 130 pthread_mutex_init(&cpu_list_mutex, NULL); 131 pthread_cond_init(&exclusive_cond, NULL); 132 pthread_cond_init(&exclusive_resume, NULL); 133 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL); 134 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr); 135 } else { 136 pthread_mutex_unlock(&exclusive_lock); 137 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); 138 } 139 } 140 141 /* Wait for pending exclusive operations to complete. The exclusive lock 142 must be held. */ 143 static inline void exclusive_idle(void) 144 { 145 while (pending_cpus) { 146 pthread_cond_wait(&exclusive_resume, &exclusive_lock); 147 } 148 } 149 150 /* Start an exclusive operation. 151 Must only be called from outside cpu_arm_exec. */ 152 static inline void start_exclusive(void) 153 { 154 CPUState *other_cpu; 155 156 pthread_mutex_lock(&exclusive_lock); 157 exclusive_idle(); 158 159 pending_cpus = 1; 160 /* Make all other cpus stop executing. */ 161 CPU_FOREACH(other_cpu) { 162 if (other_cpu->running) { 163 pending_cpus++; 164 cpu_exit(other_cpu); 165 } 166 } 167 if (pending_cpus > 1) { 168 pthread_cond_wait(&exclusive_cond, &exclusive_lock); 169 } 170 } 171 172 /* Finish an exclusive operation. */ 173 static inline void end_exclusive(void) 174 { 175 pending_cpus = 0; 176 pthread_cond_broadcast(&exclusive_resume); 177 pthread_mutex_unlock(&exclusive_lock); 178 } 179 180 /* Wait for exclusive ops to finish, and begin cpu execution. */ 181 static inline void cpu_exec_start(CPUState *cpu) 182 { 183 pthread_mutex_lock(&exclusive_lock); 184 exclusive_idle(); 185 cpu->running = true; 186 pthread_mutex_unlock(&exclusive_lock); 187 } 188 189 /* Mark cpu as not executing, and release pending exclusive ops. */ 190 static inline void cpu_exec_end(CPUState *cpu) 191 { 192 pthread_mutex_lock(&exclusive_lock); 193 cpu->running = false; 194 if (pending_cpus > 1) { 195 pending_cpus--; 196 if (pending_cpus == 1) { 197 pthread_cond_signal(&exclusive_cond); 198 } 199 } 200 exclusive_idle(); 201 pthread_mutex_unlock(&exclusive_lock); 202 } 203 204 void cpu_list_lock(void) 205 { 206 pthread_mutex_lock(&cpu_list_mutex); 207 } 208 209 void cpu_list_unlock(void) 210 { 211 pthread_mutex_unlock(&cpu_list_mutex); 212 } 213 214 215 #ifdef TARGET_I386 216 /***********************************************************/ 217 /* CPUX86 core interface */ 218 219 void cpu_smm_update(CPUX86State *env) 220 { 221 } 222 223 uint64_t cpu_get_tsc(CPUX86State *env) 224 { 225 return cpu_get_real_ticks(); 226 } 227 228 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 229 int flags) 230 { 231 unsigned int e1, e2; 232 uint32_t *p; 233 e1 = (addr << 16) | (limit & 0xffff); 234 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 235 e2 |= flags; 236 p = ptr; 237 p[0] = tswap32(e1); 238 p[1] = tswap32(e2); 239 } 240 241 static uint64_t *idt_table; 242 #ifdef TARGET_X86_64 243 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 244 uint64_t addr, unsigned int sel) 245 { 246 uint32_t *p, e1, e2; 247 e1 = (addr & 0xffff) | (sel << 16); 248 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 249 p = ptr; 250 p[0] = tswap32(e1); 251 p[1] = tswap32(e2); 252 p[2] = tswap32(addr >> 32); 253 p[3] = 0; 254 } 255 /* only dpl matters as we do only user space emulation */ 256 static void set_idt(int n, unsigned int dpl) 257 { 258 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 259 } 260 #else 261 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 262 uint32_t addr, unsigned int sel) 263 { 264 uint32_t *p, e1, e2; 265 e1 = (addr & 0xffff) | (sel << 16); 266 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 267 p = ptr; 268 p[0] = tswap32(e1); 269 p[1] = tswap32(e2); 270 } 271 272 /* only dpl matters as we do only user space emulation */ 273 static void set_idt(int n, unsigned int dpl) 274 { 275 set_gate(idt_table + n, 0, dpl, 0, 0); 276 } 277 #endif 278 279 void cpu_loop(CPUX86State *env) 280 { 281 CPUState *cs = CPU(x86_env_get_cpu(env)); 282 int trapnr; 283 abi_ulong pc; 284 target_siginfo_t info; 285 286 for(;;) { 287 trapnr = cpu_x86_exec(env); 288 switch(trapnr) { 289 case 0x80: 290 /* linux syscall from int $0x80 */ 291 env->regs[R_EAX] = do_syscall(env, 292 env->regs[R_EAX], 293 env->regs[R_EBX], 294 env->regs[R_ECX], 295 env->regs[R_EDX], 296 env->regs[R_ESI], 297 env->regs[R_EDI], 298 env->regs[R_EBP], 299 0, 0); 300 break; 301 #ifndef TARGET_ABI32 302 case EXCP_SYSCALL: 303 /* linux syscall from syscall instruction */ 304 env->regs[R_EAX] = do_syscall(env, 305 env->regs[R_EAX], 306 env->regs[R_EDI], 307 env->regs[R_ESI], 308 env->regs[R_EDX], 309 env->regs[10], 310 env->regs[8], 311 env->regs[9], 312 0, 0); 313 env->eip = env->exception_next_eip; 314 break; 315 #endif 316 case EXCP0B_NOSEG: 317 case EXCP0C_STACK: 318 info.si_signo = SIGBUS; 319 info.si_errno = 0; 320 info.si_code = TARGET_SI_KERNEL; 321 info._sifields._sigfault._addr = 0; 322 queue_signal(env, info.si_signo, &info); 323 break; 324 case EXCP0D_GPF: 325 /* XXX: potential problem if ABI32 */ 326 #ifndef TARGET_X86_64 327 if (env->eflags & VM_MASK) { 328 handle_vm86_fault(env); 329 } else 330 #endif 331 { 332 info.si_signo = SIGSEGV; 333 info.si_errno = 0; 334 info.si_code = TARGET_SI_KERNEL; 335 info._sifields._sigfault._addr = 0; 336 queue_signal(env, info.si_signo, &info); 337 } 338 break; 339 case EXCP0E_PAGE: 340 info.si_signo = SIGSEGV; 341 info.si_errno = 0; 342 if (!(env->error_code & 1)) 343 info.si_code = TARGET_SEGV_MAPERR; 344 else 345 info.si_code = TARGET_SEGV_ACCERR; 346 info._sifields._sigfault._addr = env->cr[2]; 347 queue_signal(env, info.si_signo, &info); 348 break; 349 case EXCP00_DIVZ: 350 #ifndef TARGET_X86_64 351 if (env->eflags & VM_MASK) { 352 handle_vm86_trap(env, trapnr); 353 } else 354 #endif 355 { 356 /* division by zero */ 357 info.si_signo = SIGFPE; 358 info.si_errno = 0; 359 info.si_code = TARGET_FPE_INTDIV; 360 info._sifields._sigfault._addr = env->eip; 361 queue_signal(env, info.si_signo, &info); 362 } 363 break; 364 case EXCP01_DB: 365 case EXCP03_INT3: 366 #ifndef TARGET_X86_64 367 if (env->eflags & VM_MASK) { 368 handle_vm86_trap(env, trapnr); 369 } else 370 #endif 371 { 372 info.si_signo = SIGTRAP; 373 info.si_errno = 0; 374 if (trapnr == EXCP01_DB) { 375 info.si_code = TARGET_TRAP_BRKPT; 376 info._sifields._sigfault._addr = env->eip; 377 } else { 378 info.si_code = TARGET_SI_KERNEL; 379 info._sifields._sigfault._addr = 0; 380 } 381 queue_signal(env, info.si_signo, &info); 382 } 383 break; 384 case EXCP04_INTO: 385 case EXCP05_BOUND: 386 #ifndef TARGET_X86_64 387 if (env->eflags & VM_MASK) { 388 handle_vm86_trap(env, trapnr); 389 } else 390 #endif 391 { 392 info.si_signo = SIGSEGV; 393 info.si_errno = 0; 394 info.si_code = TARGET_SI_KERNEL; 395 info._sifields._sigfault._addr = 0; 396 queue_signal(env, info.si_signo, &info); 397 } 398 break; 399 case EXCP06_ILLOP: 400 info.si_signo = SIGILL; 401 info.si_errno = 0; 402 info.si_code = TARGET_ILL_ILLOPN; 403 info._sifields._sigfault._addr = env->eip; 404 queue_signal(env, info.si_signo, &info); 405 break; 406 case EXCP_INTERRUPT: 407 /* just indicate that signals should be handled asap */ 408 break; 409 case EXCP_DEBUG: 410 { 411 int sig; 412 413 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 414 if (sig) 415 { 416 info.si_signo = sig; 417 info.si_errno = 0; 418 info.si_code = TARGET_TRAP_BRKPT; 419 queue_signal(env, info.si_signo, &info); 420 } 421 } 422 break; 423 default: 424 pc = env->segs[R_CS].base + env->eip; 425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 426 (long)pc, trapnr); 427 abort(); 428 } 429 process_pending_signals(env); 430 } 431 } 432 #endif 433 434 #ifdef TARGET_ARM 435 436 #define get_user_code_u32(x, gaddr, doswap) \ 437 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 438 if (!__r && (doswap)) { \ 439 (x) = bswap32(x); \ 440 } \ 441 __r; \ 442 }) 443 444 #define get_user_code_u16(x, gaddr, doswap) \ 445 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 446 if (!__r && (doswap)) { \ 447 (x) = bswap16(x); \ 448 } \ 449 __r; \ 450 }) 451 452 #ifdef TARGET_ABI32 453 /* Commpage handling -- there is no commpage for AArch64 */ 454 455 /* 456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt 457 * Input: 458 * r0 = pointer to oldval 459 * r1 = pointer to newval 460 * r2 = pointer to target value 461 * 462 * Output: 463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 464 * C set if *ptr was changed, clear if no exchange happened 465 * 466 * Note segv's in kernel helpers are a bit tricky, we can set the 467 * data address sensibly but the PC address is just the entry point. 468 */ 469 static void arm_kernel_cmpxchg64_helper(CPUARMState *env) 470 { 471 uint64_t oldval, newval, val; 472 uint32_t addr, cpsr; 473 target_siginfo_t info; 474 475 /* Based on the 32 bit code in do_kernel_trap */ 476 477 /* XXX: This only works between threads, not between processes. 478 It's probably possible to implement this with native host 479 operations. However things like ldrex/strex are much harder so 480 there's not much point trying. */ 481 start_exclusive(); 482 cpsr = cpsr_read(env); 483 addr = env->regs[2]; 484 485 if (get_user_u64(oldval, env->regs[0])) { 486 env->cp15.c6_data = env->regs[0]; 487 goto segv; 488 }; 489 490 if (get_user_u64(newval, env->regs[1])) { 491 env->cp15.c6_data = env->regs[1]; 492 goto segv; 493 }; 494 495 if (get_user_u64(val, addr)) { 496 env->cp15.c6_data = addr; 497 goto segv; 498 } 499 500 if (val == oldval) { 501 val = newval; 502 503 if (put_user_u64(val, addr)) { 504 env->cp15.c6_data = addr; 505 goto segv; 506 }; 507 508 env->regs[0] = 0; 509 cpsr |= CPSR_C; 510 } else { 511 env->regs[0] = -1; 512 cpsr &= ~CPSR_C; 513 } 514 cpsr_write(env, cpsr, CPSR_C); 515 end_exclusive(); 516 return; 517 518 segv: 519 end_exclusive(); 520 /* We get the PC of the entry address - which is as good as anything, 521 on a real kernel what you get depends on which mode it uses. */ 522 info.si_signo = SIGSEGV; 523 info.si_errno = 0; 524 /* XXX: check env->error_code */ 525 info.si_code = TARGET_SEGV_MAPERR; 526 info._sifields._sigfault._addr = env->cp15.c6_data; 527 queue_signal(env, info.si_signo, &info); 528 529 end_exclusive(); 530 } 531 532 /* Handle a jump to the kernel code page. */ 533 static int 534 do_kernel_trap(CPUARMState *env) 535 { 536 uint32_t addr; 537 uint32_t cpsr; 538 uint32_t val; 539 540 switch (env->regs[15]) { 541 case 0xffff0fa0: /* __kernel_memory_barrier */ 542 /* ??? No-op. Will need to do better for SMP. */ 543 break; 544 case 0xffff0fc0: /* __kernel_cmpxchg */ 545 /* XXX: This only works between threads, not between processes. 546 It's probably possible to implement this with native host 547 operations. However things like ldrex/strex are much harder so 548 there's not much point trying. */ 549 start_exclusive(); 550 cpsr = cpsr_read(env); 551 addr = env->regs[2]; 552 /* FIXME: This should SEGV if the access fails. */ 553 if (get_user_u32(val, addr)) 554 val = ~env->regs[0]; 555 if (val == env->regs[0]) { 556 val = env->regs[1]; 557 /* FIXME: Check for segfaults. */ 558 put_user_u32(val, addr); 559 env->regs[0] = 0; 560 cpsr |= CPSR_C; 561 } else { 562 env->regs[0] = -1; 563 cpsr &= ~CPSR_C; 564 } 565 cpsr_write(env, cpsr, CPSR_C); 566 end_exclusive(); 567 break; 568 case 0xffff0fe0: /* __kernel_get_tls */ 569 env->regs[0] = env->cp15.tpidrro_el0; 570 break; 571 case 0xffff0f60: /* __kernel_cmpxchg64 */ 572 arm_kernel_cmpxchg64_helper(env); 573 break; 574 575 default: 576 return 1; 577 } 578 /* Jump back to the caller. */ 579 addr = env->regs[14]; 580 if (addr & 1) { 581 env->thumb = 1; 582 addr &= ~1; 583 } 584 env->regs[15] = addr; 585 586 return 0; 587 } 588 589 /* Store exclusive handling for AArch32 */ 590 static int do_strex(CPUARMState *env) 591 { 592 uint64_t val; 593 int size; 594 int rc = 1; 595 int segv = 0; 596 uint32_t addr; 597 start_exclusive(); 598 if (env->exclusive_addr != env->exclusive_test) { 599 goto fail; 600 } 601 /* We know we're always AArch32 so the address is in uint32_t range 602 * unless it was the -1 exclusive-monitor-lost value (which won't 603 * match exclusive_test above). 604 */ 605 assert(extract64(env->exclusive_addr, 32, 32) == 0); 606 addr = env->exclusive_addr; 607 size = env->exclusive_info & 0xf; 608 switch (size) { 609 case 0: 610 segv = get_user_u8(val, addr); 611 break; 612 case 1: 613 segv = get_user_u16(val, addr); 614 break; 615 case 2: 616 case 3: 617 segv = get_user_u32(val, addr); 618 break; 619 default: 620 abort(); 621 } 622 if (segv) { 623 env->cp15.c6_data = addr; 624 goto done; 625 } 626 if (size == 3) { 627 uint32_t valhi; 628 segv = get_user_u32(valhi, addr + 4); 629 if (segv) { 630 env->cp15.c6_data = addr + 4; 631 goto done; 632 } 633 val = deposit64(val, 32, 32, valhi); 634 } 635 if (val != env->exclusive_val) { 636 goto fail; 637 } 638 639 val = env->regs[(env->exclusive_info >> 8) & 0xf]; 640 switch (size) { 641 case 0: 642 segv = put_user_u8(val, addr); 643 break; 644 case 1: 645 segv = put_user_u16(val, addr); 646 break; 647 case 2: 648 case 3: 649 segv = put_user_u32(val, addr); 650 break; 651 } 652 if (segv) { 653 env->cp15.c6_data = addr; 654 goto done; 655 } 656 if (size == 3) { 657 val = env->regs[(env->exclusive_info >> 12) & 0xf]; 658 segv = put_user_u32(val, addr + 4); 659 if (segv) { 660 env->cp15.c6_data = addr + 4; 661 goto done; 662 } 663 } 664 rc = 0; 665 fail: 666 env->regs[15] += 4; 667 env->regs[(env->exclusive_info >> 4) & 0xf] = rc; 668 done: 669 end_exclusive(); 670 return segv; 671 } 672 673 void cpu_loop(CPUARMState *env) 674 { 675 CPUState *cs = CPU(arm_env_get_cpu(env)); 676 int trapnr; 677 unsigned int n, insn; 678 target_siginfo_t info; 679 uint32_t addr; 680 681 for(;;) { 682 cpu_exec_start(cs); 683 trapnr = cpu_arm_exec(env); 684 cpu_exec_end(cs); 685 switch(trapnr) { 686 case EXCP_UDEF: 687 { 688 TaskState *ts = env->opaque; 689 uint32_t opcode; 690 int rc; 691 692 /* we handle the FPU emulation here, as Linux */ 693 /* we get the opcode */ 694 /* FIXME - what to do if get_user() fails? */ 695 get_user_code_u32(opcode, env->regs[15], env->bswap_code); 696 697 rc = EmulateAll(opcode, &ts->fpa, env); 698 if (rc == 0) { /* illegal instruction */ 699 info.si_signo = SIGILL; 700 info.si_errno = 0; 701 info.si_code = TARGET_ILL_ILLOPN; 702 info._sifields._sigfault._addr = env->regs[15]; 703 queue_signal(env, info.si_signo, &info); 704 } else if (rc < 0) { /* FP exception */ 705 int arm_fpe=0; 706 707 /* translate softfloat flags to FPSR flags */ 708 if (-rc & float_flag_invalid) 709 arm_fpe |= BIT_IOC; 710 if (-rc & float_flag_divbyzero) 711 arm_fpe |= BIT_DZC; 712 if (-rc & float_flag_overflow) 713 arm_fpe |= BIT_OFC; 714 if (-rc & float_flag_underflow) 715 arm_fpe |= BIT_UFC; 716 if (-rc & float_flag_inexact) 717 arm_fpe |= BIT_IXC; 718 719 FPSR fpsr = ts->fpa.fpsr; 720 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 721 722 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 723 info.si_signo = SIGFPE; 724 info.si_errno = 0; 725 726 /* ordered by priority, least first */ 727 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 728 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 729 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 730 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 731 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 732 733 info._sifields._sigfault._addr = env->regs[15]; 734 queue_signal(env, info.si_signo, &info); 735 } else { 736 env->regs[15] += 4; 737 } 738 739 /* accumulate unenabled exceptions */ 740 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 741 fpsr |= BIT_IXC; 742 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 743 fpsr |= BIT_UFC; 744 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 745 fpsr |= BIT_OFC; 746 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 747 fpsr |= BIT_DZC; 748 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 749 fpsr |= BIT_IOC; 750 ts->fpa.fpsr=fpsr; 751 } else { /* everything OK */ 752 /* increment PC */ 753 env->regs[15] += 4; 754 } 755 } 756 break; 757 case EXCP_SWI: 758 case EXCP_BKPT: 759 { 760 env->eabi = 1; 761 /* system call */ 762 if (trapnr == EXCP_BKPT) { 763 if (env->thumb) { 764 /* FIXME - what to do if get_user() fails? */ 765 get_user_code_u16(insn, env->regs[15], env->bswap_code); 766 n = insn & 0xff; 767 env->regs[15] += 2; 768 } else { 769 /* FIXME - what to do if get_user() fails? */ 770 get_user_code_u32(insn, env->regs[15], env->bswap_code); 771 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 772 env->regs[15] += 4; 773 } 774 } else { 775 if (env->thumb) { 776 /* FIXME - what to do if get_user() fails? */ 777 get_user_code_u16(insn, env->regs[15] - 2, 778 env->bswap_code); 779 n = insn & 0xff; 780 } else { 781 /* FIXME - what to do if get_user() fails? */ 782 get_user_code_u32(insn, env->regs[15] - 4, 783 env->bswap_code); 784 n = insn & 0xffffff; 785 } 786 } 787 788 if (n == ARM_NR_cacheflush) { 789 /* nop */ 790 } else if (n == ARM_NR_semihosting 791 || n == ARM_NR_thumb_semihosting) { 792 env->regs[0] = do_arm_semihosting (env); 793 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { 794 /* linux syscall */ 795 if (env->thumb || n == 0) { 796 n = env->regs[7]; 797 } else { 798 n -= ARM_SYSCALL_BASE; 799 env->eabi = 0; 800 } 801 if ( n > ARM_NR_BASE) { 802 switch (n) { 803 case ARM_NR_cacheflush: 804 /* nop */ 805 break; 806 case ARM_NR_set_tls: 807 cpu_set_tls(env, env->regs[0]); 808 env->regs[0] = 0; 809 break; 810 default: 811 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 812 n); 813 env->regs[0] = -TARGET_ENOSYS; 814 break; 815 } 816 } else { 817 env->regs[0] = do_syscall(env, 818 n, 819 env->regs[0], 820 env->regs[1], 821 env->regs[2], 822 env->regs[3], 823 env->regs[4], 824 env->regs[5], 825 0, 0); 826 } 827 } else { 828 goto error; 829 } 830 } 831 break; 832 case EXCP_INTERRUPT: 833 /* just indicate that signals should be handled asap */ 834 break; 835 case EXCP_PREFETCH_ABORT: 836 addr = env->cp15.c6_insn; 837 goto do_segv; 838 case EXCP_DATA_ABORT: 839 addr = env->cp15.c6_data; 840 do_segv: 841 { 842 info.si_signo = SIGSEGV; 843 info.si_errno = 0; 844 /* XXX: check env->error_code */ 845 info.si_code = TARGET_SEGV_MAPERR; 846 info._sifields._sigfault._addr = addr; 847 queue_signal(env, info.si_signo, &info); 848 } 849 break; 850 case EXCP_DEBUG: 851 { 852 int sig; 853 854 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 855 if (sig) 856 { 857 info.si_signo = sig; 858 info.si_errno = 0; 859 info.si_code = TARGET_TRAP_BRKPT; 860 queue_signal(env, info.si_signo, &info); 861 } 862 } 863 break; 864 case EXCP_KERNEL_TRAP: 865 if (do_kernel_trap(env)) 866 goto error; 867 break; 868 case EXCP_STREX: 869 if (do_strex(env)) { 870 addr = env->cp15.c6_data; 871 goto do_segv; 872 } 873 break; 874 default: 875 error: 876 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 877 trapnr); 878 cpu_dump_state(cs, stderr, fprintf, 0); 879 abort(); 880 } 881 process_pending_signals(env); 882 } 883 } 884 885 #else 886 887 /* 888 * Handle AArch64 store-release exclusive 889 * 890 * rs = gets the status result of store exclusive 891 * rt = is the register that is stored 892 * rt2 = is the second register store (in STP) 893 * 894 */ 895 static int do_strex_a64(CPUARMState *env) 896 { 897 uint64_t val; 898 int size; 899 bool is_pair; 900 int rc = 1; 901 int segv = 0; 902 uint64_t addr; 903 int rs, rt, rt2; 904 905 start_exclusive(); 906 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */ 907 size = extract32(env->exclusive_info, 0, 2); 908 is_pair = extract32(env->exclusive_info, 2, 1); 909 rs = extract32(env->exclusive_info, 4, 5); 910 rt = extract32(env->exclusive_info, 9, 5); 911 rt2 = extract32(env->exclusive_info, 14, 5); 912 913 addr = env->exclusive_addr; 914 915 if (addr != env->exclusive_test) { 916 goto finish; 917 } 918 919 switch (size) { 920 case 0: 921 segv = get_user_u8(val, addr); 922 break; 923 case 1: 924 segv = get_user_u16(val, addr); 925 break; 926 case 2: 927 segv = get_user_u32(val, addr); 928 break; 929 case 3: 930 segv = get_user_u64(val, addr); 931 break; 932 default: 933 abort(); 934 } 935 if (segv) { 936 env->cp15.c6_data = addr; 937 goto error; 938 } 939 if (val != env->exclusive_val) { 940 goto finish; 941 } 942 if (is_pair) { 943 if (size == 2) { 944 segv = get_user_u32(val, addr + 4); 945 } else { 946 segv = get_user_u64(val, addr + 8); 947 } 948 if (segv) { 949 env->cp15.c6_data = addr + (size == 2 ? 4 : 8); 950 goto error; 951 } 952 if (val != env->exclusive_high) { 953 goto finish; 954 } 955 } 956 /* handle the zero register */ 957 val = rt == 31 ? 0 : env->xregs[rt]; 958 switch (size) { 959 case 0: 960 segv = put_user_u8(val, addr); 961 break; 962 case 1: 963 segv = put_user_u16(val, addr); 964 break; 965 case 2: 966 segv = put_user_u32(val, addr); 967 break; 968 case 3: 969 segv = put_user_u64(val, addr); 970 break; 971 } 972 if (segv) { 973 goto error; 974 } 975 if (is_pair) { 976 /* handle the zero register */ 977 val = rt2 == 31 ? 0 : env->xregs[rt2]; 978 if (size == 2) { 979 segv = put_user_u32(val, addr + 4); 980 } else { 981 segv = put_user_u64(val, addr + 8); 982 } 983 if (segv) { 984 env->cp15.c6_data = addr + (size == 2 ? 4 : 8); 985 goto error; 986 } 987 } 988 rc = 0; 989 finish: 990 env->pc += 4; 991 /* rs == 31 encodes a write to the ZR, thus throwing away 992 * the status return. This is rather silly but valid. 993 */ 994 if (rs < 31) { 995 env->xregs[rs] = rc; 996 } 997 error: 998 /* instruction faulted, PC does not advance */ 999 /* either way a strex releases any exclusive lock we have */ 1000 env->exclusive_addr = -1; 1001 end_exclusive(); 1002 return segv; 1003 } 1004 1005 /* AArch64 main loop */ 1006 void cpu_loop(CPUARMState *env) 1007 { 1008 CPUState *cs = CPU(arm_env_get_cpu(env)); 1009 int trapnr, sig; 1010 target_siginfo_t info; 1011 uint32_t addr; 1012 1013 for (;;) { 1014 cpu_exec_start(cs); 1015 trapnr = cpu_arm_exec(env); 1016 cpu_exec_end(cs); 1017 1018 switch (trapnr) { 1019 case EXCP_SWI: 1020 env->xregs[0] = do_syscall(env, 1021 env->xregs[8], 1022 env->xregs[0], 1023 env->xregs[1], 1024 env->xregs[2], 1025 env->xregs[3], 1026 env->xregs[4], 1027 env->xregs[5], 1028 0, 0); 1029 break; 1030 case EXCP_INTERRUPT: 1031 /* just indicate that signals should be handled asap */ 1032 break; 1033 case EXCP_UDEF: 1034 info.si_signo = SIGILL; 1035 info.si_errno = 0; 1036 info.si_code = TARGET_ILL_ILLOPN; 1037 info._sifields._sigfault._addr = env->pc; 1038 queue_signal(env, info.si_signo, &info); 1039 break; 1040 case EXCP_PREFETCH_ABORT: 1041 addr = env->cp15.c6_insn; 1042 goto do_segv; 1043 case EXCP_DATA_ABORT: 1044 addr = env->cp15.c6_data; 1045 do_segv: 1046 info.si_signo = SIGSEGV; 1047 info.si_errno = 0; 1048 /* XXX: check env->error_code */ 1049 info.si_code = TARGET_SEGV_MAPERR; 1050 info._sifields._sigfault._addr = addr; 1051 queue_signal(env, info.si_signo, &info); 1052 break; 1053 case EXCP_DEBUG: 1054 case EXCP_BKPT: 1055 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1056 if (sig) { 1057 info.si_signo = sig; 1058 info.si_errno = 0; 1059 info.si_code = TARGET_TRAP_BRKPT; 1060 queue_signal(env, info.si_signo, &info); 1061 } 1062 break; 1063 case EXCP_STREX: 1064 if (do_strex_a64(env)) { 1065 addr = env->cp15.c6_data; 1066 goto do_segv; 1067 } 1068 break; 1069 default: 1070 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 1071 trapnr); 1072 cpu_dump_state(cs, stderr, fprintf, 0); 1073 abort(); 1074 } 1075 process_pending_signals(env); 1076 /* Exception return on AArch64 always clears the exclusive monitor, 1077 * so any return to running guest code implies this. 1078 * A strex (successful or otherwise) also clears the monitor, so 1079 * we don't need to specialcase EXCP_STREX. 1080 */ 1081 env->exclusive_addr = -1; 1082 } 1083 } 1084 #endif /* ndef TARGET_ABI32 */ 1085 1086 #endif 1087 1088 #ifdef TARGET_UNICORE32 1089 1090 void cpu_loop(CPUUniCore32State *env) 1091 { 1092 CPUState *cs = CPU(uc32_env_get_cpu(env)); 1093 int trapnr; 1094 unsigned int n, insn; 1095 target_siginfo_t info; 1096 1097 for (;;) { 1098 cpu_exec_start(cs); 1099 trapnr = uc32_cpu_exec(env); 1100 cpu_exec_end(cs); 1101 switch (trapnr) { 1102 case UC32_EXCP_PRIV: 1103 { 1104 /* system call */ 1105 get_user_u32(insn, env->regs[31] - 4); 1106 n = insn & 0xffffff; 1107 1108 if (n >= UC32_SYSCALL_BASE) { 1109 /* linux syscall */ 1110 n -= UC32_SYSCALL_BASE; 1111 if (n == UC32_SYSCALL_NR_set_tls) { 1112 cpu_set_tls(env, env->regs[0]); 1113 env->regs[0] = 0; 1114 } else { 1115 env->regs[0] = do_syscall(env, 1116 n, 1117 env->regs[0], 1118 env->regs[1], 1119 env->regs[2], 1120 env->regs[3], 1121 env->regs[4], 1122 env->regs[5], 1123 0, 0); 1124 } 1125 } else { 1126 goto error; 1127 } 1128 } 1129 break; 1130 case UC32_EXCP_DTRAP: 1131 case UC32_EXCP_ITRAP: 1132 info.si_signo = SIGSEGV; 1133 info.si_errno = 0; 1134 /* XXX: check env->error_code */ 1135 info.si_code = TARGET_SEGV_MAPERR; 1136 info._sifields._sigfault._addr = env->cp0.c4_faultaddr; 1137 queue_signal(env, info.si_signo, &info); 1138 break; 1139 case EXCP_INTERRUPT: 1140 /* just indicate that signals should be handled asap */ 1141 break; 1142 case EXCP_DEBUG: 1143 { 1144 int sig; 1145 1146 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1147 if (sig) { 1148 info.si_signo = sig; 1149 info.si_errno = 0; 1150 info.si_code = TARGET_TRAP_BRKPT; 1151 queue_signal(env, info.si_signo, &info); 1152 } 1153 } 1154 break; 1155 default: 1156 goto error; 1157 } 1158 process_pending_signals(env); 1159 } 1160 1161 error: 1162 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1163 cpu_dump_state(cs, stderr, fprintf, 0); 1164 abort(); 1165 } 1166 #endif 1167 1168 #ifdef TARGET_SPARC 1169 #define SPARC64_STACK_BIAS 2047 1170 1171 //#define DEBUG_WIN 1172 1173 /* WARNING: dealing with register windows _is_ complicated. More info 1174 can be found at http://www.sics.se/~psm/sparcstack.html */ 1175 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 1176 { 1177 index = (index + cwp * 16) % (16 * env->nwindows); 1178 /* wrap handling : if cwp is on the last window, then we use the 1179 registers 'after' the end */ 1180 if (index < 8 && env->cwp == env->nwindows - 1) 1181 index += 16 * env->nwindows; 1182 return index; 1183 } 1184 1185 /* save the register window 'cwp1' */ 1186 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 1187 { 1188 unsigned int i; 1189 abi_ulong sp_ptr; 1190 1191 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1192 #ifdef TARGET_SPARC64 1193 if (sp_ptr & 3) 1194 sp_ptr += SPARC64_STACK_BIAS; 1195 #endif 1196 #if defined(DEBUG_WIN) 1197 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 1198 sp_ptr, cwp1); 1199 #endif 1200 for(i = 0; i < 16; i++) { 1201 /* FIXME - what to do if put_user() fails? */ 1202 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1203 sp_ptr += sizeof(abi_ulong); 1204 } 1205 } 1206 1207 static void save_window(CPUSPARCState *env) 1208 { 1209 #ifndef TARGET_SPARC64 1210 unsigned int new_wim; 1211 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 1212 ((1LL << env->nwindows) - 1); 1213 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1214 env->wim = new_wim; 1215 #else 1216 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1217 env->cansave++; 1218 env->canrestore--; 1219 #endif 1220 } 1221 1222 static void restore_window(CPUSPARCState *env) 1223 { 1224 #ifndef TARGET_SPARC64 1225 unsigned int new_wim; 1226 #endif 1227 unsigned int i, cwp1; 1228 abi_ulong sp_ptr; 1229 1230 #ifndef TARGET_SPARC64 1231 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 1232 ((1LL << env->nwindows) - 1); 1233 #endif 1234 1235 /* restore the invalid window */ 1236 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1237 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1238 #ifdef TARGET_SPARC64 1239 if (sp_ptr & 3) 1240 sp_ptr += SPARC64_STACK_BIAS; 1241 #endif 1242 #if defined(DEBUG_WIN) 1243 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 1244 sp_ptr, cwp1); 1245 #endif 1246 for(i = 0; i < 16; i++) { 1247 /* FIXME - what to do if get_user() fails? */ 1248 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1249 sp_ptr += sizeof(abi_ulong); 1250 } 1251 #ifdef TARGET_SPARC64 1252 env->canrestore++; 1253 if (env->cleanwin < env->nwindows - 1) 1254 env->cleanwin++; 1255 env->cansave--; 1256 #else 1257 env->wim = new_wim; 1258 #endif 1259 } 1260 1261 static void flush_windows(CPUSPARCState *env) 1262 { 1263 int offset, cwp1; 1264 1265 offset = 1; 1266 for(;;) { 1267 /* if restore would invoke restore_window(), then we can stop */ 1268 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 1269 #ifndef TARGET_SPARC64 1270 if (env->wim & (1 << cwp1)) 1271 break; 1272 #else 1273 if (env->canrestore == 0) 1274 break; 1275 env->cansave++; 1276 env->canrestore--; 1277 #endif 1278 save_window_offset(env, cwp1); 1279 offset++; 1280 } 1281 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1282 #ifndef TARGET_SPARC64 1283 /* set wim so that restore will reload the registers */ 1284 env->wim = 1 << cwp1; 1285 #endif 1286 #if defined(DEBUG_WIN) 1287 printf("flush_windows: nb=%d\n", offset - 1); 1288 #endif 1289 } 1290 1291 void cpu_loop (CPUSPARCState *env) 1292 { 1293 CPUState *cs = CPU(sparc_env_get_cpu(env)); 1294 int trapnr; 1295 abi_long ret; 1296 target_siginfo_t info; 1297 1298 while (1) { 1299 trapnr = cpu_sparc_exec (env); 1300 1301 /* Compute PSR before exposing state. */ 1302 if (env->cc_op != CC_OP_FLAGS) { 1303 cpu_get_psr(env); 1304 } 1305 1306 switch (trapnr) { 1307 #ifndef TARGET_SPARC64 1308 case 0x88: 1309 case 0x90: 1310 #else 1311 case 0x110: 1312 case 0x16d: 1313 #endif 1314 ret = do_syscall (env, env->gregs[1], 1315 env->regwptr[0], env->regwptr[1], 1316 env->regwptr[2], env->regwptr[3], 1317 env->regwptr[4], env->regwptr[5], 1318 0, 0); 1319 if ((abi_ulong)ret >= (abi_ulong)(-515)) { 1320 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1321 env->xcc |= PSR_CARRY; 1322 #else 1323 env->psr |= PSR_CARRY; 1324 #endif 1325 ret = -ret; 1326 } else { 1327 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1328 env->xcc &= ~PSR_CARRY; 1329 #else 1330 env->psr &= ~PSR_CARRY; 1331 #endif 1332 } 1333 env->regwptr[0] = ret; 1334 /* next instruction */ 1335 env->pc = env->npc; 1336 env->npc = env->npc + 4; 1337 break; 1338 case 0x83: /* flush windows */ 1339 #ifdef TARGET_ABI32 1340 case 0x103: 1341 #endif 1342 flush_windows(env); 1343 /* next instruction */ 1344 env->pc = env->npc; 1345 env->npc = env->npc + 4; 1346 break; 1347 #ifndef TARGET_SPARC64 1348 case TT_WIN_OVF: /* window overflow */ 1349 save_window(env); 1350 break; 1351 case TT_WIN_UNF: /* window underflow */ 1352 restore_window(env); 1353 break; 1354 case TT_TFAULT: 1355 case TT_DFAULT: 1356 { 1357 info.si_signo = TARGET_SIGSEGV; 1358 info.si_errno = 0; 1359 /* XXX: check env->error_code */ 1360 info.si_code = TARGET_SEGV_MAPERR; 1361 info._sifields._sigfault._addr = env->mmuregs[4]; 1362 queue_signal(env, info.si_signo, &info); 1363 } 1364 break; 1365 #else 1366 case TT_SPILL: /* window overflow */ 1367 save_window(env); 1368 break; 1369 case TT_FILL: /* window underflow */ 1370 restore_window(env); 1371 break; 1372 case TT_TFAULT: 1373 case TT_DFAULT: 1374 { 1375 info.si_signo = TARGET_SIGSEGV; 1376 info.si_errno = 0; 1377 /* XXX: check env->error_code */ 1378 info.si_code = TARGET_SEGV_MAPERR; 1379 if (trapnr == TT_DFAULT) 1380 info._sifields._sigfault._addr = env->dmmuregs[4]; 1381 else 1382 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; 1383 queue_signal(env, info.si_signo, &info); 1384 } 1385 break; 1386 #ifndef TARGET_ABI32 1387 case 0x16e: 1388 flush_windows(env); 1389 sparc64_get_context(env); 1390 break; 1391 case 0x16f: 1392 flush_windows(env); 1393 sparc64_set_context(env); 1394 break; 1395 #endif 1396 #endif 1397 case EXCP_INTERRUPT: 1398 /* just indicate that signals should be handled asap */ 1399 break; 1400 case TT_ILL_INSN: 1401 { 1402 info.si_signo = TARGET_SIGILL; 1403 info.si_errno = 0; 1404 info.si_code = TARGET_ILL_ILLOPC; 1405 info._sifields._sigfault._addr = env->pc; 1406 queue_signal(env, info.si_signo, &info); 1407 } 1408 break; 1409 case EXCP_DEBUG: 1410 { 1411 int sig; 1412 1413 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1414 if (sig) 1415 { 1416 info.si_signo = sig; 1417 info.si_errno = 0; 1418 info.si_code = TARGET_TRAP_BRKPT; 1419 queue_signal(env, info.si_signo, &info); 1420 } 1421 } 1422 break; 1423 default: 1424 printf ("Unhandled trap: 0x%x\n", trapnr); 1425 cpu_dump_state(cs, stderr, fprintf, 0); 1426 exit (1); 1427 } 1428 process_pending_signals (env); 1429 } 1430 } 1431 1432 #endif 1433 1434 #ifdef TARGET_PPC 1435 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) 1436 { 1437 /* TO FIX */ 1438 return 0; 1439 } 1440 1441 uint64_t cpu_ppc_load_tbl(CPUPPCState *env) 1442 { 1443 return cpu_ppc_get_tb(env); 1444 } 1445 1446 uint32_t cpu_ppc_load_tbu(CPUPPCState *env) 1447 { 1448 return cpu_ppc_get_tb(env) >> 32; 1449 } 1450 1451 uint64_t cpu_ppc_load_atbl(CPUPPCState *env) 1452 { 1453 return cpu_ppc_get_tb(env); 1454 } 1455 1456 uint32_t cpu_ppc_load_atbu(CPUPPCState *env) 1457 { 1458 return cpu_ppc_get_tb(env) >> 32; 1459 } 1460 1461 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) 1462 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1463 1464 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) 1465 { 1466 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1467 } 1468 1469 /* XXX: to be fixed */ 1470 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1471 { 1472 return -1; 1473 } 1474 1475 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1476 { 1477 return -1; 1478 } 1479 1480 #define EXCP_DUMP(env, fmt, ...) \ 1481 do { \ 1482 CPUState *cs = ENV_GET_CPU(env); \ 1483 fprintf(stderr, fmt , ## __VA_ARGS__); \ 1484 cpu_dump_state(cs, stderr, fprintf, 0); \ 1485 qemu_log(fmt, ## __VA_ARGS__); \ 1486 if (qemu_log_enabled()) { \ 1487 log_cpu_state(cs, 0); \ 1488 } \ 1489 } while (0) 1490 1491 static int do_store_exclusive(CPUPPCState *env) 1492 { 1493 target_ulong addr; 1494 target_ulong page_addr; 1495 target_ulong val; 1496 int flags; 1497 int segv = 0; 1498 1499 addr = env->reserve_ea; 1500 page_addr = addr & TARGET_PAGE_MASK; 1501 start_exclusive(); 1502 mmap_lock(); 1503 flags = page_get_flags(page_addr); 1504 if ((flags & PAGE_READ) == 0) { 1505 segv = 1; 1506 } else { 1507 int reg = env->reserve_info & 0x1f; 1508 int size = (env->reserve_info >> 5) & 0xf; 1509 int stored = 0; 1510 1511 if (addr == env->reserve_addr) { 1512 switch (size) { 1513 case 1: segv = get_user_u8(val, addr); break; 1514 case 2: segv = get_user_u16(val, addr); break; 1515 case 4: segv = get_user_u32(val, addr); break; 1516 #if defined(TARGET_PPC64) 1517 case 8: segv = get_user_u64(val, addr); break; 1518 #endif 1519 default: abort(); 1520 } 1521 if (!segv && val == env->reserve_val) { 1522 val = env->gpr[reg]; 1523 switch (size) { 1524 case 1: segv = put_user_u8(val, addr); break; 1525 case 2: segv = put_user_u16(val, addr); break; 1526 case 4: segv = put_user_u32(val, addr); break; 1527 #if defined(TARGET_PPC64) 1528 case 8: segv = put_user_u64(val, addr); break; 1529 #endif 1530 default: abort(); 1531 } 1532 if (!segv) { 1533 stored = 1; 1534 } 1535 } 1536 } 1537 env->crf[0] = (stored << 1) | xer_so; 1538 env->reserve_addr = (target_ulong)-1; 1539 } 1540 if (!segv) { 1541 env->nip += 4; 1542 } 1543 mmap_unlock(); 1544 end_exclusive(); 1545 return segv; 1546 } 1547 1548 void cpu_loop(CPUPPCState *env) 1549 { 1550 CPUState *cs = CPU(ppc_env_get_cpu(env)); 1551 target_siginfo_t info; 1552 int trapnr; 1553 target_ulong ret; 1554 1555 for(;;) { 1556 cpu_exec_start(cs); 1557 trapnr = cpu_ppc_exec(env); 1558 cpu_exec_end(cs); 1559 switch(trapnr) { 1560 case POWERPC_EXCP_NONE: 1561 /* Just go on */ 1562 break; 1563 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1564 cpu_abort(env, "Critical interrupt while in user mode. " 1565 "Aborting\n"); 1566 break; 1567 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1568 cpu_abort(env, "Machine check exception while in user mode. " 1569 "Aborting\n"); 1570 break; 1571 case POWERPC_EXCP_DSI: /* Data storage exception */ 1572 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n", 1573 env->spr[SPR_DAR]); 1574 /* XXX: check this. Seems bugged */ 1575 switch (env->error_code & 0xFF000000) { 1576 case 0x40000000: 1577 info.si_signo = TARGET_SIGSEGV; 1578 info.si_errno = 0; 1579 info.si_code = TARGET_SEGV_MAPERR; 1580 break; 1581 case 0x04000000: 1582 info.si_signo = TARGET_SIGILL; 1583 info.si_errno = 0; 1584 info.si_code = TARGET_ILL_ILLADR; 1585 break; 1586 case 0x08000000: 1587 info.si_signo = TARGET_SIGSEGV; 1588 info.si_errno = 0; 1589 info.si_code = TARGET_SEGV_ACCERR; 1590 break; 1591 default: 1592 /* Let's send a regular segfault... */ 1593 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1594 env->error_code); 1595 info.si_signo = TARGET_SIGSEGV; 1596 info.si_errno = 0; 1597 info.si_code = TARGET_SEGV_MAPERR; 1598 break; 1599 } 1600 info._sifields._sigfault._addr = env->nip; 1601 queue_signal(env, info.si_signo, &info); 1602 break; 1603 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1604 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx 1605 "\n", env->spr[SPR_SRR0]); 1606 /* XXX: check this */ 1607 switch (env->error_code & 0xFF000000) { 1608 case 0x40000000: 1609 info.si_signo = TARGET_SIGSEGV; 1610 info.si_errno = 0; 1611 info.si_code = TARGET_SEGV_MAPERR; 1612 break; 1613 case 0x10000000: 1614 case 0x08000000: 1615 info.si_signo = TARGET_SIGSEGV; 1616 info.si_errno = 0; 1617 info.si_code = TARGET_SEGV_ACCERR; 1618 break; 1619 default: 1620 /* Let's send a regular segfault... */ 1621 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1622 env->error_code); 1623 info.si_signo = TARGET_SIGSEGV; 1624 info.si_errno = 0; 1625 info.si_code = TARGET_SEGV_MAPERR; 1626 break; 1627 } 1628 info._sifields._sigfault._addr = env->nip - 4; 1629 queue_signal(env, info.si_signo, &info); 1630 break; 1631 case POWERPC_EXCP_EXTERNAL: /* External input */ 1632 cpu_abort(env, "External interrupt while in user mode. " 1633 "Aborting\n"); 1634 break; 1635 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1636 EXCP_DUMP(env, "Unaligned memory access\n"); 1637 /* XXX: check this */ 1638 info.si_signo = TARGET_SIGBUS; 1639 info.si_errno = 0; 1640 info.si_code = TARGET_BUS_ADRALN; 1641 info._sifields._sigfault._addr = env->nip - 4; 1642 queue_signal(env, info.si_signo, &info); 1643 break; 1644 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1645 /* XXX: check this */ 1646 switch (env->error_code & ~0xF) { 1647 case POWERPC_EXCP_FP: 1648 EXCP_DUMP(env, "Floating point program exception\n"); 1649 info.si_signo = TARGET_SIGFPE; 1650 info.si_errno = 0; 1651 switch (env->error_code & 0xF) { 1652 case POWERPC_EXCP_FP_OX: 1653 info.si_code = TARGET_FPE_FLTOVF; 1654 break; 1655 case POWERPC_EXCP_FP_UX: 1656 info.si_code = TARGET_FPE_FLTUND; 1657 break; 1658 case POWERPC_EXCP_FP_ZX: 1659 case POWERPC_EXCP_FP_VXZDZ: 1660 info.si_code = TARGET_FPE_FLTDIV; 1661 break; 1662 case POWERPC_EXCP_FP_XX: 1663 info.si_code = TARGET_FPE_FLTRES; 1664 break; 1665 case POWERPC_EXCP_FP_VXSOFT: 1666 info.si_code = TARGET_FPE_FLTINV; 1667 break; 1668 case POWERPC_EXCP_FP_VXSNAN: 1669 case POWERPC_EXCP_FP_VXISI: 1670 case POWERPC_EXCP_FP_VXIDI: 1671 case POWERPC_EXCP_FP_VXIMZ: 1672 case POWERPC_EXCP_FP_VXVC: 1673 case POWERPC_EXCP_FP_VXSQRT: 1674 case POWERPC_EXCP_FP_VXCVI: 1675 info.si_code = TARGET_FPE_FLTSUB; 1676 break; 1677 default: 1678 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1679 env->error_code); 1680 break; 1681 } 1682 break; 1683 case POWERPC_EXCP_INVAL: 1684 EXCP_DUMP(env, "Invalid instruction\n"); 1685 info.si_signo = TARGET_SIGILL; 1686 info.si_errno = 0; 1687 switch (env->error_code & 0xF) { 1688 case POWERPC_EXCP_INVAL_INVAL: 1689 info.si_code = TARGET_ILL_ILLOPC; 1690 break; 1691 case POWERPC_EXCP_INVAL_LSWX: 1692 info.si_code = TARGET_ILL_ILLOPN; 1693 break; 1694 case POWERPC_EXCP_INVAL_SPR: 1695 info.si_code = TARGET_ILL_PRVREG; 1696 break; 1697 case POWERPC_EXCP_INVAL_FP: 1698 info.si_code = TARGET_ILL_COPROC; 1699 break; 1700 default: 1701 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1702 env->error_code & 0xF); 1703 info.si_code = TARGET_ILL_ILLADR; 1704 break; 1705 } 1706 break; 1707 case POWERPC_EXCP_PRIV: 1708 EXCP_DUMP(env, "Privilege violation\n"); 1709 info.si_signo = TARGET_SIGILL; 1710 info.si_errno = 0; 1711 switch (env->error_code & 0xF) { 1712 case POWERPC_EXCP_PRIV_OPC: 1713 info.si_code = TARGET_ILL_PRVOPC; 1714 break; 1715 case POWERPC_EXCP_PRIV_REG: 1716 info.si_code = TARGET_ILL_PRVREG; 1717 break; 1718 default: 1719 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1720 env->error_code & 0xF); 1721 info.si_code = TARGET_ILL_PRVOPC; 1722 break; 1723 } 1724 break; 1725 case POWERPC_EXCP_TRAP: 1726 cpu_abort(env, "Tried to call a TRAP\n"); 1727 break; 1728 default: 1729 /* Should not happen ! */ 1730 cpu_abort(env, "Unknown program exception (%02x)\n", 1731 env->error_code); 1732 break; 1733 } 1734 info._sifields._sigfault._addr = env->nip - 4; 1735 queue_signal(env, info.si_signo, &info); 1736 break; 1737 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1738 EXCP_DUMP(env, "No floating point allowed\n"); 1739 info.si_signo = TARGET_SIGILL; 1740 info.si_errno = 0; 1741 info.si_code = TARGET_ILL_COPROC; 1742 info._sifields._sigfault._addr = env->nip - 4; 1743 queue_signal(env, info.si_signo, &info); 1744 break; 1745 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1746 cpu_abort(env, "Syscall exception while in user mode. " 1747 "Aborting\n"); 1748 break; 1749 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1750 EXCP_DUMP(env, "No APU instruction allowed\n"); 1751 info.si_signo = TARGET_SIGILL; 1752 info.si_errno = 0; 1753 info.si_code = TARGET_ILL_COPROC; 1754 info._sifields._sigfault._addr = env->nip - 4; 1755 queue_signal(env, info.si_signo, &info); 1756 break; 1757 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1758 cpu_abort(env, "Decrementer interrupt while in user mode. " 1759 "Aborting\n"); 1760 break; 1761 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1762 cpu_abort(env, "Fix interval timer interrupt while in user mode. " 1763 "Aborting\n"); 1764 break; 1765 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1766 cpu_abort(env, "Watchdog timer interrupt while in user mode. " 1767 "Aborting\n"); 1768 break; 1769 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1770 cpu_abort(env, "Data TLB exception while in user mode. " 1771 "Aborting\n"); 1772 break; 1773 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1774 cpu_abort(env, "Instruction TLB exception while in user mode. " 1775 "Aborting\n"); 1776 break; 1777 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1778 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); 1779 info.si_signo = TARGET_SIGILL; 1780 info.si_errno = 0; 1781 info.si_code = TARGET_ILL_COPROC; 1782 info._sifields._sigfault._addr = env->nip - 4; 1783 queue_signal(env, info.si_signo, &info); 1784 break; 1785 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1786 cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); 1787 break; 1788 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1789 cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); 1790 break; 1791 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1792 cpu_abort(env, "Performance monitor exception not handled\n"); 1793 break; 1794 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1795 cpu_abort(env, "Doorbell interrupt while in user mode. " 1796 "Aborting\n"); 1797 break; 1798 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1799 cpu_abort(env, "Doorbell critical interrupt while in user mode. " 1800 "Aborting\n"); 1801 break; 1802 case POWERPC_EXCP_RESET: /* System reset exception */ 1803 cpu_abort(env, "Reset interrupt while in user mode. " 1804 "Aborting\n"); 1805 break; 1806 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1807 cpu_abort(env, "Data segment exception while in user mode. " 1808 "Aborting\n"); 1809 break; 1810 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1811 cpu_abort(env, "Instruction segment exception " 1812 "while in user mode. Aborting\n"); 1813 break; 1814 /* PowerPC 64 with hypervisor mode support */ 1815 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1816 cpu_abort(env, "Hypervisor decrementer interrupt " 1817 "while in user mode. Aborting\n"); 1818 break; 1819 case POWERPC_EXCP_TRACE: /* Trace exception */ 1820 /* Nothing to do: 1821 * we use this exception to emulate step-by-step execution mode. 1822 */ 1823 break; 1824 /* PowerPC 64 with hypervisor mode support */ 1825 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1826 cpu_abort(env, "Hypervisor data storage exception " 1827 "while in user mode. Aborting\n"); 1828 break; 1829 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1830 cpu_abort(env, "Hypervisor instruction storage exception " 1831 "while in user mode. Aborting\n"); 1832 break; 1833 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1834 cpu_abort(env, "Hypervisor data segment exception " 1835 "while in user mode. Aborting\n"); 1836 break; 1837 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1838 cpu_abort(env, "Hypervisor instruction segment exception " 1839 "while in user mode. Aborting\n"); 1840 break; 1841 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1842 EXCP_DUMP(env, "No Altivec instructions allowed\n"); 1843 info.si_signo = TARGET_SIGILL; 1844 info.si_errno = 0; 1845 info.si_code = TARGET_ILL_COPROC; 1846 info._sifields._sigfault._addr = env->nip - 4; 1847 queue_signal(env, info.si_signo, &info); 1848 break; 1849 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1850 cpu_abort(env, "Programmable interval timer interrupt " 1851 "while in user mode. Aborting\n"); 1852 break; 1853 case POWERPC_EXCP_IO: /* IO error exception */ 1854 cpu_abort(env, "IO error exception while in user mode. " 1855 "Aborting\n"); 1856 break; 1857 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1858 cpu_abort(env, "Run mode exception while in user mode. " 1859 "Aborting\n"); 1860 break; 1861 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1862 cpu_abort(env, "Emulation trap exception not handled\n"); 1863 break; 1864 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1865 cpu_abort(env, "Instruction fetch TLB exception " 1866 "while in user-mode. Aborting"); 1867 break; 1868 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1869 cpu_abort(env, "Data load TLB exception while in user-mode. " 1870 "Aborting"); 1871 break; 1872 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1873 cpu_abort(env, "Data store TLB exception while in user-mode. " 1874 "Aborting"); 1875 break; 1876 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1877 cpu_abort(env, "Floating-point assist exception not handled\n"); 1878 break; 1879 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1880 cpu_abort(env, "Instruction address breakpoint exception " 1881 "not handled\n"); 1882 break; 1883 case POWERPC_EXCP_SMI: /* System management interrupt */ 1884 cpu_abort(env, "System management interrupt while in user mode. " 1885 "Aborting\n"); 1886 break; 1887 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1888 cpu_abort(env, "Thermal interrupt interrupt while in user mode. " 1889 "Aborting\n"); 1890 break; 1891 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1892 cpu_abort(env, "Performance monitor exception not handled\n"); 1893 break; 1894 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1895 cpu_abort(env, "Vector assist exception not handled\n"); 1896 break; 1897 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1898 cpu_abort(env, "Soft patch exception not handled\n"); 1899 break; 1900 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1901 cpu_abort(env, "Maintenance exception while in user mode. " 1902 "Aborting\n"); 1903 break; 1904 case POWERPC_EXCP_STOP: /* stop translation */ 1905 /* We did invalidate the instruction cache. Go on */ 1906 break; 1907 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1908 /* We just stopped because of a branch. Go on */ 1909 break; 1910 case POWERPC_EXCP_SYSCALL_USER: 1911 /* system call in user-mode emulation */ 1912 /* WARNING: 1913 * PPC ABI uses overflow flag in cr0 to signal an error 1914 * in syscalls. 1915 */ 1916 env->crf[0] &= ~0x1; 1917 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1918 env->gpr[5], env->gpr[6], env->gpr[7], 1919 env->gpr[8], 0, 0); 1920 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { 1921 /* Returning from a successful sigreturn syscall. 1922 Avoid corrupting register state. */ 1923 break; 1924 } 1925 if (ret > (target_ulong)(-515)) { 1926 env->crf[0] |= 0x1; 1927 ret = -ret; 1928 } 1929 env->gpr[3] = ret; 1930 break; 1931 case POWERPC_EXCP_STCX: 1932 if (do_store_exclusive(env)) { 1933 info.si_signo = TARGET_SIGSEGV; 1934 info.si_errno = 0; 1935 info.si_code = TARGET_SEGV_MAPERR; 1936 info._sifields._sigfault._addr = env->nip; 1937 queue_signal(env, info.si_signo, &info); 1938 } 1939 break; 1940 case EXCP_DEBUG: 1941 { 1942 int sig; 1943 1944 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1945 if (sig) { 1946 info.si_signo = sig; 1947 info.si_errno = 0; 1948 info.si_code = TARGET_TRAP_BRKPT; 1949 queue_signal(env, info.si_signo, &info); 1950 } 1951 } 1952 break; 1953 case EXCP_INTERRUPT: 1954 /* just indicate that signals should be handled asap */ 1955 break; 1956 default: 1957 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); 1958 break; 1959 } 1960 process_pending_signals(env); 1961 } 1962 } 1963 #endif 1964 1965 #ifdef TARGET_MIPS 1966 1967 # ifdef TARGET_ABI_MIPSO32 1968 # define MIPS_SYS(name, args) args, 1969 static const uint8_t mips_syscall_args[] = { 1970 MIPS_SYS(sys_syscall , 8) /* 4000 */ 1971 MIPS_SYS(sys_exit , 1) 1972 MIPS_SYS(sys_fork , 0) 1973 MIPS_SYS(sys_read , 3) 1974 MIPS_SYS(sys_write , 3) 1975 MIPS_SYS(sys_open , 3) /* 4005 */ 1976 MIPS_SYS(sys_close , 1) 1977 MIPS_SYS(sys_waitpid , 3) 1978 MIPS_SYS(sys_creat , 2) 1979 MIPS_SYS(sys_link , 2) 1980 MIPS_SYS(sys_unlink , 1) /* 4010 */ 1981 MIPS_SYS(sys_execve , 0) 1982 MIPS_SYS(sys_chdir , 1) 1983 MIPS_SYS(sys_time , 1) 1984 MIPS_SYS(sys_mknod , 3) 1985 MIPS_SYS(sys_chmod , 2) /* 4015 */ 1986 MIPS_SYS(sys_lchown , 3) 1987 MIPS_SYS(sys_ni_syscall , 0) 1988 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 1989 MIPS_SYS(sys_lseek , 3) 1990 MIPS_SYS(sys_getpid , 0) /* 4020 */ 1991 MIPS_SYS(sys_mount , 5) 1992 MIPS_SYS(sys_umount , 1) 1993 MIPS_SYS(sys_setuid , 1) 1994 MIPS_SYS(sys_getuid , 0) 1995 MIPS_SYS(sys_stime , 1) /* 4025 */ 1996 MIPS_SYS(sys_ptrace , 4) 1997 MIPS_SYS(sys_alarm , 1) 1998 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 1999 MIPS_SYS(sys_pause , 0) 2000 MIPS_SYS(sys_utime , 2) /* 4030 */ 2001 MIPS_SYS(sys_ni_syscall , 0) 2002 MIPS_SYS(sys_ni_syscall , 0) 2003 MIPS_SYS(sys_access , 2) 2004 MIPS_SYS(sys_nice , 1) 2005 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 2006 MIPS_SYS(sys_sync , 0) 2007 MIPS_SYS(sys_kill , 2) 2008 MIPS_SYS(sys_rename , 2) 2009 MIPS_SYS(sys_mkdir , 2) 2010 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 2011 MIPS_SYS(sys_dup , 1) 2012 MIPS_SYS(sys_pipe , 0) 2013 MIPS_SYS(sys_times , 1) 2014 MIPS_SYS(sys_ni_syscall , 0) 2015 MIPS_SYS(sys_brk , 1) /* 4045 */ 2016 MIPS_SYS(sys_setgid , 1) 2017 MIPS_SYS(sys_getgid , 0) 2018 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 2019 MIPS_SYS(sys_geteuid , 0) 2020 MIPS_SYS(sys_getegid , 0) /* 4050 */ 2021 MIPS_SYS(sys_acct , 0) 2022 MIPS_SYS(sys_umount2 , 2) 2023 MIPS_SYS(sys_ni_syscall , 0) 2024 MIPS_SYS(sys_ioctl , 3) 2025 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 2026 MIPS_SYS(sys_ni_syscall , 2) 2027 MIPS_SYS(sys_setpgid , 2) 2028 MIPS_SYS(sys_ni_syscall , 0) 2029 MIPS_SYS(sys_olduname , 1) 2030 MIPS_SYS(sys_umask , 1) /* 4060 */ 2031 MIPS_SYS(sys_chroot , 1) 2032 MIPS_SYS(sys_ustat , 2) 2033 MIPS_SYS(sys_dup2 , 2) 2034 MIPS_SYS(sys_getppid , 0) 2035 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 2036 MIPS_SYS(sys_setsid , 0) 2037 MIPS_SYS(sys_sigaction , 3) 2038 MIPS_SYS(sys_sgetmask , 0) 2039 MIPS_SYS(sys_ssetmask , 1) 2040 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 2041 MIPS_SYS(sys_setregid , 2) 2042 MIPS_SYS(sys_sigsuspend , 0) 2043 MIPS_SYS(sys_sigpending , 1) 2044 MIPS_SYS(sys_sethostname , 2) 2045 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 2046 MIPS_SYS(sys_getrlimit , 2) 2047 MIPS_SYS(sys_getrusage , 2) 2048 MIPS_SYS(sys_gettimeofday, 2) 2049 MIPS_SYS(sys_settimeofday, 2) 2050 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 2051 MIPS_SYS(sys_setgroups , 2) 2052 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 2053 MIPS_SYS(sys_symlink , 2) 2054 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 2055 MIPS_SYS(sys_readlink , 3) /* 4085 */ 2056 MIPS_SYS(sys_uselib , 1) 2057 MIPS_SYS(sys_swapon , 2) 2058 MIPS_SYS(sys_reboot , 3) 2059 MIPS_SYS(old_readdir , 3) 2060 MIPS_SYS(old_mmap , 6) /* 4090 */ 2061 MIPS_SYS(sys_munmap , 2) 2062 MIPS_SYS(sys_truncate , 2) 2063 MIPS_SYS(sys_ftruncate , 2) 2064 MIPS_SYS(sys_fchmod , 2) 2065 MIPS_SYS(sys_fchown , 3) /* 4095 */ 2066 MIPS_SYS(sys_getpriority , 2) 2067 MIPS_SYS(sys_setpriority , 3) 2068 MIPS_SYS(sys_ni_syscall , 0) 2069 MIPS_SYS(sys_statfs , 2) 2070 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 2071 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 2072 MIPS_SYS(sys_socketcall , 2) 2073 MIPS_SYS(sys_syslog , 3) 2074 MIPS_SYS(sys_setitimer , 3) 2075 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 2076 MIPS_SYS(sys_newstat , 2) 2077 MIPS_SYS(sys_newlstat , 2) 2078 MIPS_SYS(sys_newfstat , 2) 2079 MIPS_SYS(sys_uname , 1) 2080 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 2081 MIPS_SYS(sys_vhangup , 0) 2082 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 2083 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 2084 MIPS_SYS(sys_wait4 , 4) 2085 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 2086 MIPS_SYS(sys_sysinfo , 1) 2087 MIPS_SYS(sys_ipc , 6) 2088 MIPS_SYS(sys_fsync , 1) 2089 MIPS_SYS(sys_sigreturn , 0) 2090 MIPS_SYS(sys_clone , 6) /* 4120 */ 2091 MIPS_SYS(sys_setdomainname, 2) 2092 MIPS_SYS(sys_newuname , 1) 2093 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 2094 MIPS_SYS(sys_adjtimex , 1) 2095 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 2096 MIPS_SYS(sys_sigprocmask , 3) 2097 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 2098 MIPS_SYS(sys_init_module , 5) 2099 MIPS_SYS(sys_delete_module, 1) 2100 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 2101 MIPS_SYS(sys_quotactl , 0) 2102 MIPS_SYS(sys_getpgid , 1) 2103 MIPS_SYS(sys_fchdir , 1) 2104 MIPS_SYS(sys_bdflush , 2) 2105 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 2106 MIPS_SYS(sys_personality , 1) 2107 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 2108 MIPS_SYS(sys_setfsuid , 1) 2109 MIPS_SYS(sys_setfsgid , 1) 2110 MIPS_SYS(sys_llseek , 5) /* 4140 */ 2111 MIPS_SYS(sys_getdents , 3) 2112 MIPS_SYS(sys_select , 5) 2113 MIPS_SYS(sys_flock , 2) 2114 MIPS_SYS(sys_msync , 3) 2115 MIPS_SYS(sys_readv , 3) /* 4145 */ 2116 MIPS_SYS(sys_writev , 3) 2117 MIPS_SYS(sys_cacheflush , 3) 2118 MIPS_SYS(sys_cachectl , 3) 2119 MIPS_SYS(sys_sysmips , 4) 2120 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 2121 MIPS_SYS(sys_getsid , 1) 2122 MIPS_SYS(sys_fdatasync , 0) 2123 MIPS_SYS(sys_sysctl , 1) 2124 MIPS_SYS(sys_mlock , 2) 2125 MIPS_SYS(sys_munlock , 2) /* 4155 */ 2126 MIPS_SYS(sys_mlockall , 1) 2127 MIPS_SYS(sys_munlockall , 0) 2128 MIPS_SYS(sys_sched_setparam, 2) 2129 MIPS_SYS(sys_sched_getparam, 2) 2130 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 2131 MIPS_SYS(sys_sched_getscheduler, 1) 2132 MIPS_SYS(sys_sched_yield , 0) 2133 MIPS_SYS(sys_sched_get_priority_max, 1) 2134 MIPS_SYS(sys_sched_get_priority_min, 1) 2135 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 2136 MIPS_SYS(sys_nanosleep, 2) 2137 MIPS_SYS(sys_mremap , 5) 2138 MIPS_SYS(sys_accept , 3) 2139 MIPS_SYS(sys_bind , 3) 2140 MIPS_SYS(sys_connect , 3) /* 4170 */ 2141 MIPS_SYS(sys_getpeername , 3) 2142 MIPS_SYS(sys_getsockname , 3) 2143 MIPS_SYS(sys_getsockopt , 5) 2144 MIPS_SYS(sys_listen , 2) 2145 MIPS_SYS(sys_recv , 4) /* 4175 */ 2146 MIPS_SYS(sys_recvfrom , 6) 2147 MIPS_SYS(sys_recvmsg , 3) 2148 MIPS_SYS(sys_send , 4) 2149 MIPS_SYS(sys_sendmsg , 3) 2150 MIPS_SYS(sys_sendto , 6) /* 4180 */ 2151 MIPS_SYS(sys_setsockopt , 5) 2152 MIPS_SYS(sys_shutdown , 2) 2153 MIPS_SYS(sys_socket , 3) 2154 MIPS_SYS(sys_socketpair , 4) 2155 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 2156 MIPS_SYS(sys_getresuid , 3) 2157 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 2158 MIPS_SYS(sys_poll , 3) 2159 MIPS_SYS(sys_nfsservctl , 3) 2160 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 2161 MIPS_SYS(sys_getresgid , 3) 2162 MIPS_SYS(sys_prctl , 5) 2163 MIPS_SYS(sys_rt_sigreturn, 0) 2164 MIPS_SYS(sys_rt_sigaction, 4) 2165 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 2166 MIPS_SYS(sys_rt_sigpending, 2) 2167 MIPS_SYS(sys_rt_sigtimedwait, 4) 2168 MIPS_SYS(sys_rt_sigqueueinfo, 3) 2169 MIPS_SYS(sys_rt_sigsuspend, 0) 2170 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 2171 MIPS_SYS(sys_pwrite64 , 6) 2172 MIPS_SYS(sys_chown , 3) 2173 MIPS_SYS(sys_getcwd , 2) 2174 MIPS_SYS(sys_capget , 2) 2175 MIPS_SYS(sys_capset , 2) /* 4205 */ 2176 MIPS_SYS(sys_sigaltstack , 2) 2177 MIPS_SYS(sys_sendfile , 4) 2178 MIPS_SYS(sys_ni_syscall , 0) 2179 MIPS_SYS(sys_ni_syscall , 0) 2180 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 2181 MIPS_SYS(sys_truncate64 , 4) 2182 MIPS_SYS(sys_ftruncate64 , 4) 2183 MIPS_SYS(sys_stat64 , 2) 2184 MIPS_SYS(sys_lstat64 , 2) 2185 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 2186 MIPS_SYS(sys_pivot_root , 2) 2187 MIPS_SYS(sys_mincore , 3) 2188 MIPS_SYS(sys_madvise , 3) 2189 MIPS_SYS(sys_getdents64 , 3) 2190 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 2191 MIPS_SYS(sys_ni_syscall , 0) 2192 MIPS_SYS(sys_gettid , 0) 2193 MIPS_SYS(sys_readahead , 5) 2194 MIPS_SYS(sys_setxattr , 5) 2195 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 2196 MIPS_SYS(sys_fsetxattr , 5) 2197 MIPS_SYS(sys_getxattr , 4) 2198 MIPS_SYS(sys_lgetxattr , 4) 2199 MIPS_SYS(sys_fgetxattr , 4) 2200 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 2201 MIPS_SYS(sys_llistxattr , 3) 2202 MIPS_SYS(sys_flistxattr , 3) 2203 MIPS_SYS(sys_removexattr , 2) 2204 MIPS_SYS(sys_lremovexattr, 2) 2205 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 2206 MIPS_SYS(sys_tkill , 2) 2207 MIPS_SYS(sys_sendfile64 , 5) 2208 MIPS_SYS(sys_futex , 6) 2209 MIPS_SYS(sys_sched_setaffinity, 3) 2210 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 2211 MIPS_SYS(sys_io_setup , 2) 2212 MIPS_SYS(sys_io_destroy , 1) 2213 MIPS_SYS(sys_io_getevents, 5) 2214 MIPS_SYS(sys_io_submit , 3) 2215 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 2216 MIPS_SYS(sys_exit_group , 1) 2217 MIPS_SYS(sys_lookup_dcookie, 3) 2218 MIPS_SYS(sys_epoll_create, 1) 2219 MIPS_SYS(sys_epoll_ctl , 4) 2220 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 2221 MIPS_SYS(sys_remap_file_pages, 5) 2222 MIPS_SYS(sys_set_tid_address, 1) 2223 MIPS_SYS(sys_restart_syscall, 0) 2224 MIPS_SYS(sys_fadvise64_64, 7) 2225 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 2226 MIPS_SYS(sys_fstatfs64 , 2) 2227 MIPS_SYS(sys_timer_create, 3) 2228 MIPS_SYS(sys_timer_settime, 4) 2229 MIPS_SYS(sys_timer_gettime, 2) 2230 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 2231 MIPS_SYS(sys_timer_delete, 1) 2232 MIPS_SYS(sys_clock_settime, 2) 2233 MIPS_SYS(sys_clock_gettime, 2) 2234 MIPS_SYS(sys_clock_getres, 2) 2235 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 2236 MIPS_SYS(sys_tgkill , 3) 2237 MIPS_SYS(sys_utimes , 2) 2238 MIPS_SYS(sys_mbind , 4) 2239 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 2240 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 2241 MIPS_SYS(sys_mq_open , 4) 2242 MIPS_SYS(sys_mq_unlink , 1) 2243 MIPS_SYS(sys_mq_timedsend, 5) 2244 MIPS_SYS(sys_mq_timedreceive, 5) 2245 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 2246 MIPS_SYS(sys_mq_getsetattr, 3) 2247 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 2248 MIPS_SYS(sys_waitid , 4) 2249 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 2250 MIPS_SYS(sys_add_key , 5) 2251 MIPS_SYS(sys_request_key, 4) 2252 MIPS_SYS(sys_keyctl , 5) 2253 MIPS_SYS(sys_set_thread_area, 1) 2254 MIPS_SYS(sys_inotify_init, 0) 2255 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 2256 MIPS_SYS(sys_inotify_rm_watch, 2) 2257 MIPS_SYS(sys_migrate_pages, 4) 2258 MIPS_SYS(sys_openat, 4) 2259 MIPS_SYS(sys_mkdirat, 3) 2260 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 2261 MIPS_SYS(sys_fchownat, 5) 2262 MIPS_SYS(sys_futimesat, 3) 2263 MIPS_SYS(sys_fstatat64, 4) 2264 MIPS_SYS(sys_unlinkat, 3) 2265 MIPS_SYS(sys_renameat, 4) /* 4295 */ 2266 MIPS_SYS(sys_linkat, 5) 2267 MIPS_SYS(sys_symlinkat, 3) 2268 MIPS_SYS(sys_readlinkat, 4) 2269 MIPS_SYS(sys_fchmodat, 3) 2270 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 2271 MIPS_SYS(sys_pselect6, 6) 2272 MIPS_SYS(sys_ppoll, 5) 2273 MIPS_SYS(sys_unshare, 1) 2274 MIPS_SYS(sys_splice, 6) 2275 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 2276 MIPS_SYS(sys_tee, 4) 2277 MIPS_SYS(sys_vmsplice, 4) 2278 MIPS_SYS(sys_move_pages, 6) 2279 MIPS_SYS(sys_set_robust_list, 2) 2280 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 2281 MIPS_SYS(sys_kexec_load, 4) 2282 MIPS_SYS(sys_getcpu, 3) 2283 MIPS_SYS(sys_epoll_pwait, 6) 2284 MIPS_SYS(sys_ioprio_set, 3) 2285 MIPS_SYS(sys_ioprio_get, 2) 2286 MIPS_SYS(sys_utimensat, 4) 2287 MIPS_SYS(sys_signalfd, 3) 2288 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ 2289 MIPS_SYS(sys_eventfd, 1) 2290 MIPS_SYS(sys_fallocate, 6) /* 4320 */ 2291 MIPS_SYS(sys_timerfd_create, 2) 2292 MIPS_SYS(sys_timerfd_gettime, 2) 2293 MIPS_SYS(sys_timerfd_settime, 4) 2294 MIPS_SYS(sys_signalfd4, 4) 2295 MIPS_SYS(sys_eventfd2, 2) /* 4325 */ 2296 MIPS_SYS(sys_epoll_create1, 1) 2297 MIPS_SYS(sys_dup3, 3) 2298 MIPS_SYS(sys_pipe2, 2) 2299 MIPS_SYS(sys_inotify_init1, 1) 2300 MIPS_SYS(sys_preadv, 6) /* 4330 */ 2301 MIPS_SYS(sys_pwritev, 6) 2302 MIPS_SYS(sys_rt_tgsigqueueinfo, 4) 2303 MIPS_SYS(sys_perf_event_open, 5) 2304 MIPS_SYS(sys_accept4, 4) 2305 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ 2306 MIPS_SYS(sys_fanotify_init, 2) 2307 MIPS_SYS(sys_fanotify_mark, 6) 2308 MIPS_SYS(sys_prlimit64, 4) 2309 MIPS_SYS(sys_name_to_handle_at, 5) 2310 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ 2311 MIPS_SYS(sys_clock_adjtime, 2) 2312 MIPS_SYS(sys_syncfs, 1) 2313 }; 2314 # undef MIPS_SYS 2315 # endif /* O32 */ 2316 2317 static int do_store_exclusive(CPUMIPSState *env) 2318 { 2319 target_ulong addr; 2320 target_ulong page_addr; 2321 target_ulong val; 2322 int flags; 2323 int segv = 0; 2324 int reg; 2325 int d; 2326 2327 addr = env->lladdr; 2328 page_addr = addr & TARGET_PAGE_MASK; 2329 start_exclusive(); 2330 mmap_lock(); 2331 flags = page_get_flags(page_addr); 2332 if ((flags & PAGE_READ) == 0) { 2333 segv = 1; 2334 } else { 2335 reg = env->llreg & 0x1f; 2336 d = (env->llreg & 0x20) != 0; 2337 if (d) { 2338 segv = get_user_s64(val, addr); 2339 } else { 2340 segv = get_user_s32(val, addr); 2341 } 2342 if (!segv) { 2343 if (val != env->llval) { 2344 env->active_tc.gpr[reg] = 0; 2345 } else { 2346 if (d) { 2347 segv = put_user_u64(env->llnewval, addr); 2348 } else { 2349 segv = put_user_u32(env->llnewval, addr); 2350 } 2351 if (!segv) { 2352 env->active_tc.gpr[reg] = 1; 2353 } 2354 } 2355 } 2356 } 2357 env->lladdr = -1; 2358 if (!segv) { 2359 env->active_tc.PC += 4; 2360 } 2361 mmap_unlock(); 2362 end_exclusive(); 2363 return segv; 2364 } 2365 2366 /* Break codes */ 2367 enum { 2368 BRK_OVERFLOW = 6, 2369 BRK_DIVZERO = 7 2370 }; 2371 2372 static int do_break(CPUMIPSState *env, target_siginfo_t *info, 2373 unsigned int code) 2374 { 2375 int ret = -1; 2376 2377 switch (code) { 2378 case BRK_OVERFLOW: 2379 case BRK_DIVZERO: 2380 info->si_signo = TARGET_SIGFPE; 2381 info->si_errno = 0; 2382 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; 2383 queue_signal(env, info->si_signo, &*info); 2384 ret = 0; 2385 break; 2386 default: 2387 info->si_signo = TARGET_SIGTRAP; 2388 info->si_errno = 0; 2389 queue_signal(env, info->si_signo, &*info); 2390 ret = 0; 2391 break; 2392 } 2393 2394 return ret; 2395 } 2396 2397 void cpu_loop(CPUMIPSState *env) 2398 { 2399 CPUState *cs = CPU(mips_env_get_cpu(env)); 2400 target_siginfo_t info; 2401 int trapnr; 2402 abi_long ret; 2403 # ifdef TARGET_ABI_MIPSO32 2404 unsigned int syscall_num; 2405 # endif 2406 2407 for(;;) { 2408 cpu_exec_start(cs); 2409 trapnr = cpu_mips_exec(env); 2410 cpu_exec_end(cs); 2411 switch(trapnr) { 2412 case EXCP_SYSCALL: 2413 env->active_tc.PC += 4; 2414 # ifdef TARGET_ABI_MIPSO32 2415 syscall_num = env->active_tc.gpr[2] - 4000; 2416 if (syscall_num >= sizeof(mips_syscall_args)) { 2417 ret = -TARGET_ENOSYS; 2418 } else { 2419 int nb_args; 2420 abi_ulong sp_reg; 2421 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 2422 2423 nb_args = mips_syscall_args[syscall_num]; 2424 sp_reg = env->active_tc.gpr[29]; 2425 switch (nb_args) { 2426 /* these arguments are taken from the stack */ 2427 case 8: 2428 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 2429 goto done_syscall; 2430 } 2431 case 7: 2432 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 2433 goto done_syscall; 2434 } 2435 case 6: 2436 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 2437 goto done_syscall; 2438 } 2439 case 5: 2440 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 2441 goto done_syscall; 2442 } 2443 default: 2444 break; 2445 } 2446 ret = do_syscall(env, env->active_tc.gpr[2], 2447 env->active_tc.gpr[4], 2448 env->active_tc.gpr[5], 2449 env->active_tc.gpr[6], 2450 env->active_tc.gpr[7], 2451 arg5, arg6, arg7, arg8); 2452 } 2453 done_syscall: 2454 # else 2455 ret = do_syscall(env, env->active_tc.gpr[2], 2456 env->active_tc.gpr[4], env->active_tc.gpr[5], 2457 env->active_tc.gpr[6], env->active_tc.gpr[7], 2458 env->active_tc.gpr[8], env->active_tc.gpr[9], 2459 env->active_tc.gpr[10], env->active_tc.gpr[11]); 2460 # endif /* O32 */ 2461 if (ret == -TARGET_QEMU_ESIGRETURN) { 2462 /* Returning from a successful sigreturn syscall. 2463 Avoid clobbering register state. */ 2464 break; 2465 } 2466 if ((abi_ulong)ret >= (abi_ulong)-1133) { 2467 env->active_tc.gpr[7] = 1; /* error flag */ 2468 ret = -ret; 2469 } else { 2470 env->active_tc.gpr[7] = 0; /* error flag */ 2471 } 2472 env->active_tc.gpr[2] = ret; 2473 break; 2474 case EXCP_TLBL: 2475 case EXCP_TLBS: 2476 case EXCP_AdEL: 2477 case EXCP_AdES: 2478 info.si_signo = TARGET_SIGSEGV; 2479 info.si_errno = 0; 2480 /* XXX: check env->error_code */ 2481 info.si_code = TARGET_SEGV_MAPERR; 2482 info._sifields._sigfault._addr = env->CP0_BadVAddr; 2483 queue_signal(env, info.si_signo, &info); 2484 break; 2485 case EXCP_CpU: 2486 case EXCP_RI: 2487 info.si_signo = TARGET_SIGILL; 2488 info.si_errno = 0; 2489 info.si_code = 0; 2490 queue_signal(env, info.si_signo, &info); 2491 break; 2492 case EXCP_INTERRUPT: 2493 /* just indicate that signals should be handled asap */ 2494 break; 2495 case EXCP_DEBUG: 2496 { 2497 int sig; 2498 2499 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2500 if (sig) 2501 { 2502 info.si_signo = sig; 2503 info.si_errno = 0; 2504 info.si_code = TARGET_TRAP_BRKPT; 2505 queue_signal(env, info.si_signo, &info); 2506 } 2507 } 2508 break; 2509 case EXCP_SC: 2510 if (do_store_exclusive(env)) { 2511 info.si_signo = TARGET_SIGSEGV; 2512 info.si_errno = 0; 2513 info.si_code = TARGET_SEGV_MAPERR; 2514 info._sifields._sigfault._addr = env->active_tc.PC; 2515 queue_signal(env, info.si_signo, &info); 2516 } 2517 break; 2518 case EXCP_DSPDIS: 2519 info.si_signo = TARGET_SIGILL; 2520 info.si_errno = 0; 2521 info.si_code = TARGET_ILL_ILLOPC; 2522 queue_signal(env, info.si_signo, &info); 2523 break; 2524 /* The code below was inspired by the MIPS Linux kernel trap 2525 * handling code in arch/mips/kernel/traps.c. 2526 */ 2527 case EXCP_BREAK: 2528 { 2529 abi_ulong trap_instr; 2530 unsigned int code; 2531 2532 if (env->hflags & MIPS_HFLAG_M16) { 2533 if (env->insn_flags & ASE_MICROMIPS) { 2534 /* microMIPS mode */ 2535 ret = get_user_u16(trap_instr, env->active_tc.PC); 2536 if (ret != 0) { 2537 goto error; 2538 } 2539 2540 if ((trap_instr >> 10) == 0x11) { 2541 /* 16-bit instruction */ 2542 code = trap_instr & 0xf; 2543 } else { 2544 /* 32-bit instruction */ 2545 abi_ulong instr_lo; 2546 2547 ret = get_user_u16(instr_lo, 2548 env->active_tc.PC + 2); 2549 if (ret != 0) { 2550 goto error; 2551 } 2552 trap_instr = (trap_instr << 16) | instr_lo; 2553 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2554 /* Unfortunately, microMIPS also suffers from 2555 the old assembler bug... */ 2556 if (code >= (1 << 10)) { 2557 code >>= 10; 2558 } 2559 } 2560 } else { 2561 /* MIPS16e mode */ 2562 ret = get_user_u16(trap_instr, env->active_tc.PC); 2563 if (ret != 0) { 2564 goto error; 2565 } 2566 code = (trap_instr >> 6) & 0x3f; 2567 } 2568 } else { 2569 ret = get_user_ual(trap_instr, env->active_tc.PC); 2570 if (ret != 0) { 2571 goto error; 2572 } 2573 2574 /* As described in the original Linux kernel code, the 2575 * below checks on 'code' are to work around an old 2576 * assembly bug. 2577 */ 2578 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2579 if (code >= (1 << 10)) { 2580 code >>= 10; 2581 } 2582 } 2583 2584 if (do_break(env, &info, code) != 0) { 2585 goto error; 2586 } 2587 } 2588 break; 2589 case EXCP_TRAP: 2590 { 2591 abi_ulong trap_instr; 2592 unsigned int code = 0; 2593 2594 if (env->hflags & MIPS_HFLAG_M16) { 2595 /* microMIPS mode */ 2596 abi_ulong instr[2]; 2597 2598 ret = get_user_u16(instr[0], env->active_tc.PC) || 2599 get_user_u16(instr[1], env->active_tc.PC + 2); 2600 2601 trap_instr = (instr[0] << 16) | instr[1]; 2602 } else { 2603 ret = get_user_ual(trap_instr, env->active_tc.PC); 2604 } 2605 2606 if (ret != 0) { 2607 goto error; 2608 } 2609 2610 /* The immediate versions don't provide a code. */ 2611 if (!(trap_instr & 0xFC000000)) { 2612 if (env->hflags & MIPS_HFLAG_M16) { 2613 /* microMIPS mode */ 2614 code = ((trap_instr >> 12) & ((1 << 4) - 1)); 2615 } else { 2616 code = ((trap_instr >> 6) & ((1 << 10) - 1)); 2617 } 2618 } 2619 2620 if (do_break(env, &info, code) != 0) { 2621 goto error; 2622 } 2623 } 2624 break; 2625 default: 2626 error: 2627 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 2628 trapnr); 2629 cpu_dump_state(cs, stderr, fprintf, 0); 2630 abort(); 2631 } 2632 process_pending_signals(env); 2633 } 2634 } 2635 #endif 2636 2637 #ifdef TARGET_OPENRISC 2638 2639 void cpu_loop(CPUOpenRISCState *env) 2640 { 2641 CPUState *cs = CPU(openrisc_env_get_cpu(env)); 2642 int trapnr, gdbsig; 2643 2644 for (;;) { 2645 trapnr = cpu_exec(env); 2646 gdbsig = 0; 2647 2648 switch (trapnr) { 2649 case EXCP_RESET: 2650 qemu_log("\nReset request, exit, pc is %#x\n", env->pc); 2651 exit(1); 2652 break; 2653 case EXCP_BUSERR: 2654 qemu_log("\nBus error, exit, pc is %#x\n", env->pc); 2655 gdbsig = SIGBUS; 2656 break; 2657 case EXCP_DPF: 2658 case EXCP_IPF: 2659 cpu_dump_state(cs, stderr, fprintf, 0); 2660 gdbsig = TARGET_SIGSEGV; 2661 break; 2662 case EXCP_TICK: 2663 qemu_log("\nTick time interrupt pc is %#x\n", env->pc); 2664 break; 2665 case EXCP_ALIGN: 2666 qemu_log("\nAlignment pc is %#x\n", env->pc); 2667 gdbsig = SIGBUS; 2668 break; 2669 case EXCP_ILLEGAL: 2670 qemu_log("\nIllegal instructionpc is %#x\n", env->pc); 2671 gdbsig = SIGILL; 2672 break; 2673 case EXCP_INT: 2674 qemu_log("\nExternal interruptpc is %#x\n", env->pc); 2675 break; 2676 case EXCP_DTLBMISS: 2677 case EXCP_ITLBMISS: 2678 qemu_log("\nTLB miss\n"); 2679 break; 2680 case EXCP_RANGE: 2681 qemu_log("\nRange\n"); 2682 gdbsig = SIGSEGV; 2683 break; 2684 case EXCP_SYSCALL: 2685 env->pc += 4; /* 0xc00; */ 2686 env->gpr[11] = do_syscall(env, 2687 env->gpr[11], /* return value */ 2688 env->gpr[3], /* r3 - r7 are params */ 2689 env->gpr[4], 2690 env->gpr[5], 2691 env->gpr[6], 2692 env->gpr[7], 2693 env->gpr[8], 0, 0); 2694 break; 2695 case EXCP_FPE: 2696 qemu_log("\nFloating point error\n"); 2697 break; 2698 case EXCP_TRAP: 2699 qemu_log("\nTrap\n"); 2700 gdbsig = SIGTRAP; 2701 break; 2702 case EXCP_NR: 2703 qemu_log("\nNR\n"); 2704 break; 2705 default: 2706 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n", 2707 trapnr); 2708 cpu_dump_state(cs, stderr, fprintf, 0); 2709 gdbsig = TARGET_SIGILL; 2710 break; 2711 } 2712 if (gdbsig) { 2713 gdb_handlesig(cs, gdbsig); 2714 if (gdbsig != TARGET_SIGTRAP) { 2715 exit(1); 2716 } 2717 } 2718 2719 process_pending_signals(env); 2720 } 2721 } 2722 2723 #endif /* TARGET_OPENRISC */ 2724 2725 #ifdef TARGET_SH4 2726 void cpu_loop(CPUSH4State *env) 2727 { 2728 CPUState *cs = CPU(sh_env_get_cpu(env)); 2729 int trapnr, ret; 2730 target_siginfo_t info; 2731 2732 while (1) { 2733 trapnr = cpu_sh4_exec (env); 2734 2735 switch (trapnr) { 2736 case 0x160: 2737 env->pc += 2; 2738 ret = do_syscall(env, 2739 env->gregs[3], 2740 env->gregs[4], 2741 env->gregs[5], 2742 env->gregs[6], 2743 env->gregs[7], 2744 env->gregs[0], 2745 env->gregs[1], 2746 0, 0); 2747 env->gregs[0] = ret; 2748 break; 2749 case EXCP_INTERRUPT: 2750 /* just indicate that signals should be handled asap */ 2751 break; 2752 case EXCP_DEBUG: 2753 { 2754 int sig; 2755 2756 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2757 if (sig) 2758 { 2759 info.si_signo = sig; 2760 info.si_errno = 0; 2761 info.si_code = TARGET_TRAP_BRKPT; 2762 queue_signal(env, info.si_signo, &info); 2763 } 2764 } 2765 break; 2766 case 0xa0: 2767 case 0xc0: 2768 info.si_signo = SIGSEGV; 2769 info.si_errno = 0; 2770 info.si_code = TARGET_SEGV_MAPERR; 2771 info._sifields._sigfault._addr = env->tea; 2772 queue_signal(env, info.si_signo, &info); 2773 break; 2774 2775 default: 2776 printf ("Unhandled trap: 0x%x\n", trapnr); 2777 cpu_dump_state(cs, stderr, fprintf, 0); 2778 exit (1); 2779 } 2780 process_pending_signals (env); 2781 } 2782 } 2783 #endif 2784 2785 #ifdef TARGET_CRIS 2786 void cpu_loop(CPUCRISState *env) 2787 { 2788 CPUState *cs = CPU(cris_env_get_cpu(env)); 2789 int trapnr, ret; 2790 target_siginfo_t info; 2791 2792 while (1) { 2793 trapnr = cpu_cris_exec (env); 2794 switch (trapnr) { 2795 case 0xaa: 2796 { 2797 info.si_signo = SIGSEGV; 2798 info.si_errno = 0; 2799 /* XXX: check env->error_code */ 2800 info.si_code = TARGET_SEGV_MAPERR; 2801 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 2802 queue_signal(env, info.si_signo, &info); 2803 } 2804 break; 2805 case EXCP_INTERRUPT: 2806 /* just indicate that signals should be handled asap */ 2807 break; 2808 case EXCP_BREAK: 2809 ret = do_syscall(env, 2810 env->regs[9], 2811 env->regs[10], 2812 env->regs[11], 2813 env->regs[12], 2814 env->regs[13], 2815 env->pregs[7], 2816 env->pregs[11], 2817 0, 0); 2818 env->regs[10] = ret; 2819 break; 2820 case EXCP_DEBUG: 2821 { 2822 int sig; 2823 2824 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2825 if (sig) 2826 { 2827 info.si_signo = sig; 2828 info.si_errno = 0; 2829 info.si_code = TARGET_TRAP_BRKPT; 2830 queue_signal(env, info.si_signo, &info); 2831 } 2832 } 2833 break; 2834 default: 2835 printf ("Unhandled trap: 0x%x\n", trapnr); 2836 cpu_dump_state(cs, stderr, fprintf, 0); 2837 exit (1); 2838 } 2839 process_pending_signals (env); 2840 } 2841 } 2842 #endif 2843 2844 #ifdef TARGET_MICROBLAZE 2845 void cpu_loop(CPUMBState *env) 2846 { 2847 CPUState *cs = CPU(mb_env_get_cpu(env)); 2848 int trapnr, ret; 2849 target_siginfo_t info; 2850 2851 while (1) { 2852 trapnr = cpu_mb_exec (env); 2853 switch (trapnr) { 2854 case 0xaa: 2855 { 2856 info.si_signo = SIGSEGV; 2857 info.si_errno = 0; 2858 /* XXX: check env->error_code */ 2859 info.si_code = TARGET_SEGV_MAPERR; 2860 info._sifields._sigfault._addr = 0; 2861 queue_signal(env, info.si_signo, &info); 2862 } 2863 break; 2864 case EXCP_INTERRUPT: 2865 /* just indicate that signals should be handled asap */ 2866 break; 2867 case EXCP_BREAK: 2868 /* Return address is 4 bytes after the call. */ 2869 env->regs[14] += 4; 2870 env->sregs[SR_PC] = env->regs[14]; 2871 ret = do_syscall(env, 2872 env->regs[12], 2873 env->regs[5], 2874 env->regs[6], 2875 env->regs[7], 2876 env->regs[8], 2877 env->regs[9], 2878 env->regs[10], 2879 0, 0); 2880 env->regs[3] = ret; 2881 break; 2882 case EXCP_HW_EXCP: 2883 env->regs[17] = env->sregs[SR_PC] + 4; 2884 if (env->iflags & D_FLAG) { 2885 env->sregs[SR_ESR] |= 1 << 12; 2886 env->sregs[SR_PC] -= 4; 2887 /* FIXME: if branch was immed, replay the imm as well. */ 2888 } 2889 2890 env->iflags &= ~(IMM_FLAG | D_FLAG); 2891 2892 switch (env->sregs[SR_ESR] & 31) { 2893 case ESR_EC_DIVZERO: 2894 info.si_signo = SIGFPE; 2895 info.si_errno = 0; 2896 info.si_code = TARGET_FPE_FLTDIV; 2897 info._sifields._sigfault._addr = 0; 2898 queue_signal(env, info.si_signo, &info); 2899 break; 2900 case ESR_EC_FPU: 2901 info.si_signo = SIGFPE; 2902 info.si_errno = 0; 2903 if (env->sregs[SR_FSR] & FSR_IO) { 2904 info.si_code = TARGET_FPE_FLTINV; 2905 } 2906 if (env->sregs[SR_FSR] & FSR_DZ) { 2907 info.si_code = TARGET_FPE_FLTDIV; 2908 } 2909 info._sifields._sigfault._addr = 0; 2910 queue_signal(env, info.si_signo, &info); 2911 break; 2912 default: 2913 printf ("Unhandled hw-exception: 0x%x\n", 2914 env->sregs[SR_ESR] & ESR_EC_MASK); 2915 cpu_dump_state(cs, stderr, fprintf, 0); 2916 exit (1); 2917 break; 2918 } 2919 break; 2920 case EXCP_DEBUG: 2921 { 2922 int sig; 2923 2924 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2925 if (sig) 2926 { 2927 info.si_signo = sig; 2928 info.si_errno = 0; 2929 info.si_code = TARGET_TRAP_BRKPT; 2930 queue_signal(env, info.si_signo, &info); 2931 } 2932 } 2933 break; 2934 default: 2935 printf ("Unhandled trap: 0x%x\n", trapnr); 2936 cpu_dump_state(cs, stderr, fprintf, 0); 2937 exit (1); 2938 } 2939 process_pending_signals (env); 2940 } 2941 } 2942 #endif 2943 2944 #ifdef TARGET_M68K 2945 2946 void cpu_loop(CPUM68KState *env) 2947 { 2948 CPUState *cs = CPU(m68k_env_get_cpu(env)); 2949 int trapnr; 2950 unsigned int n; 2951 target_siginfo_t info; 2952 TaskState *ts = env->opaque; 2953 2954 for(;;) { 2955 trapnr = cpu_m68k_exec(env); 2956 switch(trapnr) { 2957 case EXCP_ILLEGAL: 2958 { 2959 if (ts->sim_syscalls) { 2960 uint16_t nr; 2961 nr = lduw(env->pc + 2); 2962 env->pc += 4; 2963 do_m68k_simcall(env, nr); 2964 } else { 2965 goto do_sigill; 2966 } 2967 } 2968 break; 2969 case EXCP_HALT_INSN: 2970 /* Semihosing syscall. */ 2971 env->pc += 4; 2972 do_m68k_semihosting(env, env->dregs[0]); 2973 break; 2974 case EXCP_LINEA: 2975 case EXCP_LINEF: 2976 case EXCP_UNSUPPORTED: 2977 do_sigill: 2978 info.si_signo = SIGILL; 2979 info.si_errno = 0; 2980 info.si_code = TARGET_ILL_ILLOPN; 2981 info._sifields._sigfault._addr = env->pc; 2982 queue_signal(env, info.si_signo, &info); 2983 break; 2984 case EXCP_TRAP0: 2985 { 2986 ts->sim_syscalls = 0; 2987 n = env->dregs[0]; 2988 env->pc += 2; 2989 env->dregs[0] = do_syscall(env, 2990 n, 2991 env->dregs[1], 2992 env->dregs[2], 2993 env->dregs[3], 2994 env->dregs[4], 2995 env->dregs[5], 2996 env->aregs[0], 2997 0, 0); 2998 } 2999 break; 3000 case EXCP_INTERRUPT: 3001 /* just indicate that signals should be handled asap */ 3002 break; 3003 case EXCP_ACCESS: 3004 { 3005 info.si_signo = SIGSEGV; 3006 info.si_errno = 0; 3007 /* XXX: check env->error_code */ 3008 info.si_code = TARGET_SEGV_MAPERR; 3009 info._sifields._sigfault._addr = env->mmu.ar; 3010 queue_signal(env, info.si_signo, &info); 3011 } 3012 break; 3013 case EXCP_DEBUG: 3014 { 3015 int sig; 3016 3017 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3018 if (sig) 3019 { 3020 info.si_signo = sig; 3021 info.si_errno = 0; 3022 info.si_code = TARGET_TRAP_BRKPT; 3023 queue_signal(env, info.si_signo, &info); 3024 } 3025 } 3026 break; 3027 default: 3028 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 3029 trapnr); 3030 cpu_dump_state(cs, stderr, fprintf, 0); 3031 abort(); 3032 } 3033 process_pending_signals(env); 3034 } 3035 } 3036 #endif /* TARGET_M68K */ 3037 3038 #ifdef TARGET_ALPHA 3039 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) 3040 { 3041 target_ulong addr, val, tmp; 3042 target_siginfo_t info; 3043 int ret = 0; 3044 3045 addr = env->lock_addr; 3046 tmp = env->lock_st_addr; 3047 env->lock_addr = -1; 3048 env->lock_st_addr = 0; 3049 3050 start_exclusive(); 3051 mmap_lock(); 3052 3053 if (addr == tmp) { 3054 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3055 goto do_sigsegv; 3056 } 3057 3058 if (val == env->lock_value) { 3059 tmp = env->ir[reg]; 3060 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { 3061 goto do_sigsegv; 3062 } 3063 ret = 1; 3064 } 3065 } 3066 env->ir[reg] = ret; 3067 env->pc += 4; 3068 3069 mmap_unlock(); 3070 end_exclusive(); 3071 return; 3072 3073 do_sigsegv: 3074 mmap_unlock(); 3075 end_exclusive(); 3076 3077 info.si_signo = TARGET_SIGSEGV; 3078 info.si_errno = 0; 3079 info.si_code = TARGET_SEGV_MAPERR; 3080 info._sifields._sigfault._addr = addr; 3081 queue_signal(env, TARGET_SIGSEGV, &info); 3082 } 3083 3084 void cpu_loop(CPUAlphaState *env) 3085 { 3086 CPUState *cs = CPU(alpha_env_get_cpu(env)); 3087 int trapnr; 3088 target_siginfo_t info; 3089 abi_long sysret; 3090 3091 while (1) { 3092 trapnr = cpu_alpha_exec (env); 3093 3094 /* All of the traps imply a transition through PALcode, which 3095 implies an REI instruction has been executed. Which means 3096 that the intr_flag should be cleared. */ 3097 env->intr_flag = 0; 3098 3099 switch (trapnr) { 3100 case EXCP_RESET: 3101 fprintf(stderr, "Reset requested. Exit\n"); 3102 exit(1); 3103 break; 3104 case EXCP_MCHK: 3105 fprintf(stderr, "Machine check exception. Exit\n"); 3106 exit(1); 3107 break; 3108 case EXCP_SMP_INTERRUPT: 3109 case EXCP_CLK_INTERRUPT: 3110 case EXCP_DEV_INTERRUPT: 3111 fprintf(stderr, "External interrupt. Exit\n"); 3112 exit(1); 3113 break; 3114 case EXCP_MMFAULT: 3115 env->lock_addr = -1; 3116 info.si_signo = TARGET_SIGSEGV; 3117 info.si_errno = 0; 3118 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID 3119 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); 3120 info._sifields._sigfault._addr = env->trap_arg0; 3121 queue_signal(env, info.si_signo, &info); 3122 break; 3123 case EXCP_UNALIGN: 3124 env->lock_addr = -1; 3125 info.si_signo = TARGET_SIGBUS; 3126 info.si_errno = 0; 3127 info.si_code = TARGET_BUS_ADRALN; 3128 info._sifields._sigfault._addr = env->trap_arg0; 3129 queue_signal(env, info.si_signo, &info); 3130 break; 3131 case EXCP_OPCDEC: 3132 do_sigill: 3133 env->lock_addr = -1; 3134 info.si_signo = TARGET_SIGILL; 3135 info.si_errno = 0; 3136 info.si_code = TARGET_ILL_ILLOPC; 3137 info._sifields._sigfault._addr = env->pc; 3138 queue_signal(env, info.si_signo, &info); 3139 break; 3140 case EXCP_ARITH: 3141 env->lock_addr = -1; 3142 info.si_signo = TARGET_SIGFPE; 3143 info.si_errno = 0; 3144 info.si_code = TARGET_FPE_FLTINV; 3145 info._sifields._sigfault._addr = env->pc; 3146 queue_signal(env, info.si_signo, &info); 3147 break; 3148 case EXCP_FEN: 3149 /* No-op. Linux simply re-enables the FPU. */ 3150 break; 3151 case EXCP_CALL_PAL: 3152 env->lock_addr = -1; 3153 switch (env->error_code) { 3154 case 0x80: 3155 /* BPT */ 3156 info.si_signo = TARGET_SIGTRAP; 3157 info.si_errno = 0; 3158 info.si_code = TARGET_TRAP_BRKPT; 3159 info._sifields._sigfault._addr = env->pc; 3160 queue_signal(env, info.si_signo, &info); 3161 break; 3162 case 0x81: 3163 /* BUGCHK */ 3164 info.si_signo = TARGET_SIGTRAP; 3165 info.si_errno = 0; 3166 info.si_code = 0; 3167 info._sifields._sigfault._addr = env->pc; 3168 queue_signal(env, info.si_signo, &info); 3169 break; 3170 case 0x83: 3171 /* CALLSYS */ 3172 trapnr = env->ir[IR_V0]; 3173 sysret = do_syscall(env, trapnr, 3174 env->ir[IR_A0], env->ir[IR_A1], 3175 env->ir[IR_A2], env->ir[IR_A3], 3176 env->ir[IR_A4], env->ir[IR_A5], 3177 0, 0); 3178 if (trapnr == TARGET_NR_sigreturn 3179 || trapnr == TARGET_NR_rt_sigreturn) { 3180 break; 3181 } 3182 /* Syscall writes 0 to V0 to bypass error check, similar 3183 to how this is handled internal to Linux kernel. 3184 (Ab)use trapnr temporarily as boolean indicating error. */ 3185 trapnr = (env->ir[IR_V0] != 0 && sysret < 0); 3186 env->ir[IR_V0] = (trapnr ? -sysret : sysret); 3187 env->ir[IR_A3] = trapnr; 3188 break; 3189 case 0x86: 3190 /* IMB */ 3191 /* ??? We can probably elide the code using page_unprotect 3192 that is checking for self-modifying code. Instead we 3193 could simply call tb_flush here. Until we work out the 3194 changes required to turn off the extra write protection, 3195 this can be a no-op. */ 3196 break; 3197 case 0x9E: 3198 /* RDUNIQUE */ 3199 /* Handled in the translator for usermode. */ 3200 abort(); 3201 case 0x9F: 3202 /* WRUNIQUE */ 3203 /* Handled in the translator for usermode. */ 3204 abort(); 3205 case 0xAA: 3206 /* GENTRAP */ 3207 info.si_signo = TARGET_SIGFPE; 3208 switch (env->ir[IR_A0]) { 3209 case TARGET_GEN_INTOVF: 3210 info.si_code = TARGET_FPE_INTOVF; 3211 break; 3212 case TARGET_GEN_INTDIV: 3213 info.si_code = TARGET_FPE_INTDIV; 3214 break; 3215 case TARGET_GEN_FLTOVF: 3216 info.si_code = TARGET_FPE_FLTOVF; 3217 break; 3218 case TARGET_GEN_FLTUND: 3219 info.si_code = TARGET_FPE_FLTUND; 3220 break; 3221 case TARGET_GEN_FLTINV: 3222 info.si_code = TARGET_FPE_FLTINV; 3223 break; 3224 case TARGET_GEN_FLTINE: 3225 info.si_code = TARGET_FPE_FLTRES; 3226 break; 3227 case TARGET_GEN_ROPRAND: 3228 info.si_code = 0; 3229 break; 3230 default: 3231 info.si_signo = TARGET_SIGTRAP; 3232 info.si_code = 0; 3233 break; 3234 } 3235 info.si_errno = 0; 3236 info._sifields._sigfault._addr = env->pc; 3237 queue_signal(env, info.si_signo, &info); 3238 break; 3239 default: 3240 goto do_sigill; 3241 } 3242 break; 3243 case EXCP_DEBUG: 3244 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP); 3245 if (info.si_signo) { 3246 env->lock_addr = -1; 3247 info.si_errno = 0; 3248 info.si_code = TARGET_TRAP_BRKPT; 3249 queue_signal(env, info.si_signo, &info); 3250 } 3251 break; 3252 case EXCP_STL_C: 3253 case EXCP_STQ_C: 3254 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); 3255 break; 3256 case EXCP_INTERRUPT: 3257 /* Just indicate that signals should be handled asap. */ 3258 break; 3259 default: 3260 printf ("Unhandled trap: 0x%x\n", trapnr); 3261 cpu_dump_state(cs, stderr, fprintf, 0); 3262 exit (1); 3263 } 3264 process_pending_signals (env); 3265 } 3266 } 3267 #endif /* TARGET_ALPHA */ 3268 3269 #ifdef TARGET_S390X 3270 void cpu_loop(CPUS390XState *env) 3271 { 3272 CPUState *cs = CPU(s390_env_get_cpu(env)); 3273 int trapnr, n, sig; 3274 target_siginfo_t info; 3275 target_ulong addr; 3276 3277 while (1) { 3278 trapnr = cpu_s390x_exec(env); 3279 switch (trapnr) { 3280 case EXCP_INTERRUPT: 3281 /* Just indicate that signals should be handled asap. */ 3282 break; 3283 3284 case EXCP_SVC: 3285 n = env->int_svc_code; 3286 if (!n) { 3287 /* syscalls > 255 */ 3288 n = env->regs[1]; 3289 } 3290 env->psw.addr += env->int_svc_ilen; 3291 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3], 3292 env->regs[4], env->regs[5], 3293 env->regs[6], env->regs[7], 0, 0); 3294 break; 3295 3296 case EXCP_DEBUG: 3297 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3298 if (sig) { 3299 n = TARGET_TRAP_BRKPT; 3300 goto do_signal_pc; 3301 } 3302 break; 3303 case EXCP_PGM: 3304 n = env->int_pgm_code; 3305 switch (n) { 3306 case PGM_OPERATION: 3307 case PGM_PRIVILEGED: 3308 sig = SIGILL; 3309 n = TARGET_ILL_ILLOPC; 3310 goto do_signal_pc; 3311 case PGM_PROTECTION: 3312 case PGM_ADDRESSING: 3313 sig = SIGSEGV; 3314 /* XXX: check env->error_code */ 3315 n = TARGET_SEGV_MAPERR; 3316 addr = env->__excp_addr; 3317 goto do_signal; 3318 case PGM_EXECUTE: 3319 case PGM_SPECIFICATION: 3320 case PGM_SPECIAL_OP: 3321 case PGM_OPERAND: 3322 do_sigill_opn: 3323 sig = SIGILL; 3324 n = TARGET_ILL_ILLOPN; 3325 goto do_signal_pc; 3326 3327 case PGM_FIXPT_OVERFLOW: 3328 sig = SIGFPE; 3329 n = TARGET_FPE_INTOVF; 3330 goto do_signal_pc; 3331 case PGM_FIXPT_DIVIDE: 3332 sig = SIGFPE; 3333 n = TARGET_FPE_INTDIV; 3334 goto do_signal_pc; 3335 3336 case PGM_DATA: 3337 n = (env->fpc >> 8) & 0xff; 3338 if (n == 0xff) { 3339 /* compare-and-trap */ 3340 goto do_sigill_opn; 3341 } else { 3342 /* An IEEE exception, simulated or otherwise. */ 3343 if (n & 0x80) { 3344 n = TARGET_FPE_FLTINV; 3345 } else if (n & 0x40) { 3346 n = TARGET_FPE_FLTDIV; 3347 } else if (n & 0x20) { 3348 n = TARGET_FPE_FLTOVF; 3349 } else if (n & 0x10) { 3350 n = TARGET_FPE_FLTUND; 3351 } else if (n & 0x08) { 3352 n = TARGET_FPE_FLTRES; 3353 } else { 3354 /* ??? Quantum exception; BFP, DFP error. */ 3355 goto do_sigill_opn; 3356 } 3357 sig = SIGFPE; 3358 goto do_signal_pc; 3359 } 3360 3361 default: 3362 fprintf(stderr, "Unhandled program exception: %#x\n", n); 3363 cpu_dump_state(cs, stderr, fprintf, 0); 3364 exit(1); 3365 } 3366 break; 3367 3368 do_signal_pc: 3369 addr = env->psw.addr; 3370 do_signal: 3371 info.si_signo = sig; 3372 info.si_errno = 0; 3373 info.si_code = n; 3374 info._sifields._sigfault._addr = addr; 3375 queue_signal(env, info.si_signo, &info); 3376 break; 3377 3378 default: 3379 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); 3380 cpu_dump_state(cs, stderr, fprintf, 0); 3381 exit(1); 3382 } 3383 process_pending_signals (env); 3384 } 3385 } 3386 3387 #endif /* TARGET_S390X */ 3388 3389 THREAD CPUState *thread_cpu; 3390 3391 void task_settid(TaskState *ts) 3392 { 3393 if (ts->ts_tid == 0) { 3394 ts->ts_tid = (pid_t)syscall(SYS_gettid); 3395 } 3396 } 3397 3398 void stop_all_tasks(void) 3399 { 3400 /* 3401 * We trust that when using NPTL, start_exclusive() 3402 * handles thread stopping correctly. 3403 */ 3404 start_exclusive(); 3405 } 3406 3407 /* Assumes contents are already zeroed. */ 3408 void init_task_state(TaskState *ts) 3409 { 3410 int i; 3411 3412 ts->used = 1; 3413 ts->first_free = ts->sigqueue_table; 3414 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { 3415 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; 3416 } 3417 ts->sigqueue_table[i].next = NULL; 3418 } 3419 3420 CPUArchState *cpu_copy(CPUArchState *env) 3421 { 3422 CPUArchState *new_env = cpu_init(cpu_model); 3423 #if defined(TARGET_HAS_ICE) 3424 CPUBreakpoint *bp; 3425 CPUWatchpoint *wp; 3426 #endif 3427 3428 /* Reset non arch specific state */ 3429 cpu_reset(ENV_GET_CPU(new_env)); 3430 3431 memcpy(new_env, env, sizeof(CPUArchState)); 3432 3433 /* Clone all break/watchpoints. 3434 Note: Once we support ptrace with hw-debug register access, make sure 3435 BP_CPU break/watchpoints are handled correctly on clone. */ 3436 QTAILQ_INIT(&env->breakpoints); 3437 QTAILQ_INIT(&env->watchpoints); 3438 #if defined(TARGET_HAS_ICE) 3439 QTAILQ_FOREACH(bp, &env->breakpoints, entry) { 3440 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); 3441 } 3442 QTAILQ_FOREACH(wp, &env->watchpoints, entry) { 3443 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, 3444 wp->flags, NULL); 3445 } 3446 #endif 3447 3448 return new_env; 3449 } 3450 3451 static void handle_arg_help(const char *arg) 3452 { 3453 usage(); 3454 } 3455 3456 static void handle_arg_log(const char *arg) 3457 { 3458 int mask; 3459 3460 mask = qemu_str_to_log_mask(arg); 3461 if (!mask) { 3462 qemu_print_log_usage(stdout); 3463 exit(1); 3464 } 3465 qemu_set_log(mask); 3466 } 3467 3468 static void handle_arg_log_filename(const char *arg) 3469 { 3470 qemu_set_log_filename(arg); 3471 } 3472 3473 static void handle_arg_set_env(const char *arg) 3474 { 3475 char *r, *p, *token; 3476 r = p = strdup(arg); 3477 while ((token = strsep(&p, ",")) != NULL) { 3478 if (envlist_setenv(envlist, token) != 0) { 3479 usage(); 3480 } 3481 } 3482 free(r); 3483 } 3484 3485 static void handle_arg_unset_env(const char *arg) 3486 { 3487 char *r, *p, *token; 3488 r = p = strdup(arg); 3489 while ((token = strsep(&p, ",")) != NULL) { 3490 if (envlist_unsetenv(envlist, token) != 0) { 3491 usage(); 3492 } 3493 } 3494 free(r); 3495 } 3496 3497 static void handle_arg_argv0(const char *arg) 3498 { 3499 argv0 = strdup(arg); 3500 } 3501 3502 static void handle_arg_stack_size(const char *arg) 3503 { 3504 char *p; 3505 guest_stack_size = strtoul(arg, &p, 0); 3506 if (guest_stack_size == 0) { 3507 usage(); 3508 } 3509 3510 if (*p == 'M') { 3511 guest_stack_size *= 1024 * 1024; 3512 } else if (*p == 'k' || *p == 'K') { 3513 guest_stack_size *= 1024; 3514 } 3515 } 3516 3517 static void handle_arg_ld_prefix(const char *arg) 3518 { 3519 interp_prefix = strdup(arg); 3520 } 3521 3522 static void handle_arg_pagesize(const char *arg) 3523 { 3524 qemu_host_page_size = atoi(arg); 3525 if (qemu_host_page_size == 0 || 3526 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 3527 fprintf(stderr, "page size must be a power of two\n"); 3528 exit(1); 3529 } 3530 } 3531 3532 static void handle_arg_gdb(const char *arg) 3533 { 3534 gdbstub_port = atoi(arg); 3535 } 3536 3537 static void handle_arg_uname(const char *arg) 3538 { 3539 qemu_uname_release = strdup(arg); 3540 } 3541 3542 static void handle_arg_cpu(const char *arg) 3543 { 3544 cpu_model = strdup(arg); 3545 if (cpu_model == NULL || is_help_option(cpu_model)) { 3546 /* XXX: implement xxx_cpu_list for targets that still miss it */ 3547 #if defined(cpu_list) 3548 cpu_list(stdout, &fprintf); 3549 #endif 3550 exit(1); 3551 } 3552 } 3553 3554 #if defined(CONFIG_USE_GUEST_BASE) 3555 static void handle_arg_guest_base(const char *arg) 3556 { 3557 guest_base = strtol(arg, NULL, 0); 3558 have_guest_base = 1; 3559 } 3560 3561 static void handle_arg_reserved_va(const char *arg) 3562 { 3563 char *p; 3564 int shift = 0; 3565 reserved_va = strtoul(arg, &p, 0); 3566 switch (*p) { 3567 case 'k': 3568 case 'K': 3569 shift = 10; 3570 break; 3571 case 'M': 3572 shift = 20; 3573 break; 3574 case 'G': 3575 shift = 30; 3576 break; 3577 } 3578 if (shift) { 3579 unsigned long unshifted = reserved_va; 3580 p++; 3581 reserved_va <<= shift; 3582 if (((reserved_va >> shift) != unshifted) 3583 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS 3584 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) 3585 #endif 3586 ) { 3587 fprintf(stderr, "Reserved virtual address too big\n"); 3588 exit(1); 3589 } 3590 } 3591 if (*p) { 3592 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); 3593 exit(1); 3594 } 3595 } 3596 #endif 3597 3598 static void handle_arg_singlestep(const char *arg) 3599 { 3600 singlestep = 1; 3601 } 3602 3603 static void handle_arg_strace(const char *arg) 3604 { 3605 do_strace = 1; 3606 } 3607 3608 static void handle_arg_version(const char *arg) 3609 { 3610 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION 3611 ", Copyright (c) 2003-2008 Fabrice Bellard\n"); 3612 exit(0); 3613 } 3614 3615 struct qemu_argument { 3616 const char *argv; 3617 const char *env; 3618 bool has_arg; 3619 void (*handle_opt)(const char *arg); 3620 const char *example; 3621 const char *help; 3622 }; 3623 3624 static const struct qemu_argument arg_table[] = { 3625 {"h", "", false, handle_arg_help, 3626 "", "print this help"}, 3627 {"g", "QEMU_GDB", true, handle_arg_gdb, 3628 "port", "wait gdb connection to 'port'"}, 3629 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, 3630 "path", "set the elf interpreter prefix to 'path'"}, 3631 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, 3632 "size", "set the stack size to 'size' bytes"}, 3633 {"cpu", "QEMU_CPU", true, handle_arg_cpu, 3634 "model", "select CPU (-cpu help for list)"}, 3635 {"E", "QEMU_SET_ENV", true, handle_arg_set_env, 3636 "var=value", "sets targets environment variable (see below)"}, 3637 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, 3638 "var", "unsets targets environment variable (see below)"}, 3639 {"0", "QEMU_ARGV0", true, handle_arg_argv0, 3640 "argv0", "forces target process argv[0] to be 'argv0'"}, 3641 {"r", "QEMU_UNAME", true, handle_arg_uname, 3642 "uname", "set qemu uname release string to 'uname'"}, 3643 #if defined(CONFIG_USE_GUEST_BASE) 3644 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, 3645 "address", "set guest_base address to 'address'"}, 3646 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, 3647 "size", "reserve 'size' bytes for guest virtual address space"}, 3648 #endif 3649 {"d", "QEMU_LOG", true, handle_arg_log, 3650 "item[,...]", "enable logging of specified items " 3651 "(use '-d help' for a list of items)"}, 3652 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, 3653 "logfile", "write logs to 'logfile' (default stderr)"}, 3654 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, 3655 "pagesize", "set the host page size to 'pagesize'"}, 3656 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, 3657 "", "run in singlestep mode"}, 3658 {"strace", "QEMU_STRACE", false, handle_arg_strace, 3659 "", "log system calls"}, 3660 {"version", "QEMU_VERSION", false, handle_arg_version, 3661 "", "display version information and exit"}, 3662 {NULL, NULL, false, NULL, NULL, NULL} 3663 }; 3664 3665 static void usage(void) 3666 { 3667 const struct qemu_argument *arginfo; 3668 int maxarglen; 3669 int maxenvlen; 3670 3671 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" 3672 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" 3673 "\n" 3674 "Options and associated environment variables:\n" 3675 "\n"); 3676 3677 /* Calculate column widths. We must always have at least enough space 3678 * for the column header. 3679 */ 3680 maxarglen = strlen("Argument"); 3681 maxenvlen = strlen("Env-variable"); 3682 3683 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3684 int arglen = strlen(arginfo->argv); 3685 if (arginfo->has_arg) { 3686 arglen += strlen(arginfo->example) + 1; 3687 } 3688 if (strlen(arginfo->env) > maxenvlen) { 3689 maxenvlen = strlen(arginfo->env); 3690 } 3691 if (arglen > maxarglen) { 3692 maxarglen = arglen; 3693 } 3694 } 3695 3696 printf("%-*s %-*s Description\n", maxarglen+1, "Argument", 3697 maxenvlen, "Env-variable"); 3698 3699 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3700 if (arginfo->has_arg) { 3701 printf("-%s %-*s %-*s %s\n", arginfo->argv, 3702 (int)(maxarglen - strlen(arginfo->argv) - 1), 3703 arginfo->example, maxenvlen, arginfo->env, arginfo->help); 3704 } else { 3705 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, 3706 maxenvlen, arginfo->env, 3707 arginfo->help); 3708 } 3709 } 3710 3711 printf("\n" 3712 "Defaults:\n" 3713 "QEMU_LD_PREFIX = %s\n" 3714 "QEMU_STACK_SIZE = %ld byte\n", 3715 interp_prefix, 3716 guest_stack_size); 3717 3718 printf("\n" 3719 "You can use -E and -U options or the QEMU_SET_ENV and\n" 3720 "QEMU_UNSET_ENV environment variables to set and unset\n" 3721 "environment variables for the target process.\n" 3722 "It is possible to provide several variables by separating them\n" 3723 "by commas in getsubopt(3) style. Additionally it is possible to\n" 3724 "provide the -E and -U options multiple times.\n" 3725 "The following lines are equivalent:\n" 3726 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" 3727 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" 3728 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" 3729 "Note that if you provide several changes to a single variable\n" 3730 "the last change will stay in effect.\n"); 3731 3732 exit(1); 3733 } 3734 3735 static int parse_args(int argc, char **argv) 3736 { 3737 const char *r; 3738 int optind; 3739 const struct qemu_argument *arginfo; 3740 3741 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3742 if (arginfo->env == NULL) { 3743 continue; 3744 } 3745 3746 r = getenv(arginfo->env); 3747 if (r != NULL) { 3748 arginfo->handle_opt(r); 3749 } 3750 } 3751 3752 optind = 1; 3753 for (;;) { 3754 if (optind >= argc) { 3755 break; 3756 } 3757 r = argv[optind]; 3758 if (r[0] != '-') { 3759 break; 3760 } 3761 optind++; 3762 r++; 3763 if (!strcmp(r, "-")) { 3764 break; 3765 } 3766 3767 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3768 if (!strcmp(r, arginfo->argv)) { 3769 if (arginfo->has_arg) { 3770 if (optind >= argc) { 3771 usage(); 3772 } 3773 arginfo->handle_opt(argv[optind]); 3774 optind++; 3775 } else { 3776 arginfo->handle_opt(NULL); 3777 } 3778 break; 3779 } 3780 } 3781 3782 /* no option matched the current argv */ 3783 if (arginfo->handle_opt == NULL) { 3784 usage(); 3785 } 3786 } 3787 3788 if (optind >= argc) { 3789 usage(); 3790 } 3791 3792 filename = argv[optind]; 3793 exec_path = argv[optind]; 3794 3795 return optind; 3796 } 3797 3798 int main(int argc, char **argv, char **envp) 3799 { 3800 struct target_pt_regs regs1, *regs = ®s1; 3801 struct image_info info1, *info = &info1; 3802 struct linux_binprm bprm; 3803 TaskState *ts; 3804 CPUArchState *env; 3805 CPUState *cpu; 3806 int optind; 3807 char **target_environ, **wrk; 3808 char **target_argv; 3809 int target_argc; 3810 int i; 3811 int ret; 3812 int execfd; 3813 3814 module_call_init(MODULE_INIT_QOM); 3815 3816 qemu_init_auxval(envp); 3817 qemu_cache_utils_init(); 3818 3819 if ((envlist = envlist_create()) == NULL) { 3820 (void) fprintf(stderr, "Unable to allocate envlist\n"); 3821 exit(1); 3822 } 3823 3824 /* add current environment into the list */ 3825 for (wrk = environ; *wrk != NULL; wrk++) { 3826 (void) envlist_setenv(envlist, *wrk); 3827 } 3828 3829 /* Read the stack limit from the kernel. If it's "unlimited", 3830 then we can do little else besides use the default. */ 3831 { 3832 struct rlimit lim; 3833 if (getrlimit(RLIMIT_STACK, &lim) == 0 3834 && lim.rlim_cur != RLIM_INFINITY 3835 && lim.rlim_cur == (target_long)lim.rlim_cur) { 3836 guest_stack_size = lim.rlim_cur; 3837 } 3838 } 3839 3840 cpu_model = NULL; 3841 #if defined(cpudef_setup) 3842 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */ 3843 #endif 3844 3845 optind = parse_args(argc, argv); 3846 3847 /* Zero out regs */ 3848 memset(regs, 0, sizeof(struct target_pt_regs)); 3849 3850 /* Zero out image_info */ 3851 memset(info, 0, sizeof(struct image_info)); 3852 3853 memset(&bprm, 0, sizeof (bprm)); 3854 3855 /* Scan interp_prefix dir for replacement files. */ 3856 init_paths(interp_prefix); 3857 3858 init_qemu_uname_release(); 3859 3860 if (cpu_model == NULL) { 3861 #if defined(TARGET_I386) 3862 #ifdef TARGET_X86_64 3863 cpu_model = "qemu64"; 3864 #else 3865 cpu_model = "qemu32"; 3866 #endif 3867 #elif defined(TARGET_ARM) 3868 cpu_model = "any"; 3869 #elif defined(TARGET_UNICORE32) 3870 cpu_model = "any"; 3871 #elif defined(TARGET_M68K) 3872 cpu_model = "any"; 3873 #elif defined(TARGET_SPARC) 3874 #ifdef TARGET_SPARC64 3875 cpu_model = "TI UltraSparc II"; 3876 #else 3877 cpu_model = "Fujitsu MB86904"; 3878 #endif 3879 #elif defined(TARGET_MIPS) 3880 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 3881 cpu_model = "20Kc"; 3882 #else 3883 cpu_model = "24Kf"; 3884 #endif 3885 #elif defined TARGET_OPENRISC 3886 cpu_model = "or1200"; 3887 #elif defined(TARGET_PPC) 3888 #ifdef TARGET_PPC64 3889 cpu_model = "970fx"; 3890 #else 3891 cpu_model = "750"; 3892 #endif 3893 #else 3894 cpu_model = "any"; 3895 #endif 3896 } 3897 tcg_exec_init(0); 3898 cpu_exec_init_all(); 3899 /* NOTE: we need to init the CPU at this stage to get 3900 qemu_host_page_size */ 3901 env = cpu_init(cpu_model); 3902 if (!env) { 3903 fprintf(stderr, "Unable to find CPU definition\n"); 3904 exit(1); 3905 } 3906 cpu = ENV_GET_CPU(env); 3907 cpu_reset(cpu); 3908 3909 thread_cpu = cpu; 3910 3911 if (getenv("QEMU_STRACE")) { 3912 do_strace = 1; 3913 } 3914 3915 target_environ = envlist_to_environ(envlist, NULL); 3916 envlist_free(envlist); 3917 3918 #if defined(CONFIG_USE_GUEST_BASE) 3919 /* 3920 * Now that page sizes are configured in cpu_init() we can do 3921 * proper page alignment for guest_base. 3922 */ 3923 guest_base = HOST_PAGE_ALIGN(guest_base); 3924 3925 if (reserved_va || have_guest_base) { 3926 guest_base = init_guest_space(guest_base, reserved_va, 0, 3927 have_guest_base); 3928 if (guest_base == (unsigned long)-1) { 3929 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " 3930 "space for use as guest address space (check your virtual " 3931 "memory ulimit setting or reserve less using -R option)\n", 3932 reserved_va); 3933 exit(1); 3934 } 3935 3936 if (reserved_va) { 3937 mmap_next_start = reserved_va; 3938 } 3939 } 3940 #endif /* CONFIG_USE_GUEST_BASE */ 3941 3942 /* 3943 * Read in mmap_min_addr kernel parameter. This value is used 3944 * When loading the ELF image to determine whether guest_base 3945 * is needed. It is also used in mmap_find_vma. 3946 */ 3947 { 3948 FILE *fp; 3949 3950 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { 3951 unsigned long tmp; 3952 if (fscanf(fp, "%lu", &tmp) == 1) { 3953 mmap_min_addr = tmp; 3954 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr); 3955 } 3956 fclose(fp); 3957 } 3958 } 3959 3960 /* 3961 * Prepare copy of argv vector for target. 3962 */ 3963 target_argc = argc - optind; 3964 target_argv = calloc(target_argc + 1, sizeof (char *)); 3965 if (target_argv == NULL) { 3966 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); 3967 exit(1); 3968 } 3969 3970 /* 3971 * If argv0 is specified (using '-0' switch) we replace 3972 * argv[0] pointer with the given one. 3973 */ 3974 i = 0; 3975 if (argv0 != NULL) { 3976 target_argv[i++] = strdup(argv0); 3977 } 3978 for (; i < target_argc; i++) { 3979 target_argv[i] = strdup(argv[optind + i]); 3980 } 3981 target_argv[target_argc] = NULL; 3982 3983 ts = g_malloc0 (sizeof(TaskState)); 3984 init_task_state(ts); 3985 /* build Task State */ 3986 ts->info = info; 3987 ts->bprm = &bprm; 3988 env->opaque = ts; 3989 task_settid(ts); 3990 3991 execfd = qemu_getauxval(AT_EXECFD); 3992 if (execfd == 0) { 3993 execfd = open(filename, O_RDONLY); 3994 if (execfd < 0) { 3995 printf("Error while loading %s: %s\n", filename, strerror(errno)); 3996 _exit(1); 3997 } 3998 } 3999 4000 ret = loader_exec(execfd, filename, target_argv, target_environ, regs, 4001 info, &bprm); 4002 if (ret != 0) { 4003 printf("Error while loading %s: %s\n", filename, strerror(-ret)); 4004 _exit(1); 4005 } 4006 4007 for (wrk = target_environ; *wrk; wrk++) { 4008 free(*wrk); 4009 } 4010 4011 free(target_environ); 4012 4013 if (qemu_log_enabled()) { 4014 #if defined(CONFIG_USE_GUEST_BASE) 4015 qemu_log("guest_base 0x%lx\n", guest_base); 4016 #endif 4017 log_page_dump(); 4018 4019 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 4020 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 4021 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", 4022 info->start_code); 4023 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", 4024 info->start_data); 4025 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 4026 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", 4027 info->start_stack); 4028 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 4029 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 4030 } 4031 4032 target_set_brk(info->brk); 4033 syscall_init(); 4034 signal_init(); 4035 4036 #if defined(CONFIG_USE_GUEST_BASE) 4037 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay 4038 generating the prologue until now so that the prologue can take 4039 the real value of GUEST_BASE into account. */ 4040 tcg_prologue_init(&tcg_ctx); 4041 #endif 4042 4043 #if defined(TARGET_I386) 4044 cpu_x86_set_cpl(env, 3); 4045 4046 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 4047 env->hflags |= HF_PE_MASK; 4048 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 4049 env->cr[4] |= CR4_OSFXSR_MASK; 4050 env->hflags |= HF_OSFXSR_MASK; 4051 } 4052 #ifndef TARGET_ABI32 4053 /* enable 64 bit mode if possible */ 4054 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { 4055 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 4056 exit(1); 4057 } 4058 env->cr[4] |= CR4_PAE_MASK; 4059 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 4060 env->hflags |= HF_LMA_MASK; 4061 #endif 4062 4063 /* flags setup : we activate the IRQs by default as in user mode */ 4064 env->eflags |= IF_MASK; 4065 4066 /* linux register setup */ 4067 #ifndef TARGET_ABI32 4068 env->regs[R_EAX] = regs->rax; 4069 env->regs[R_EBX] = regs->rbx; 4070 env->regs[R_ECX] = regs->rcx; 4071 env->regs[R_EDX] = regs->rdx; 4072 env->regs[R_ESI] = regs->rsi; 4073 env->regs[R_EDI] = regs->rdi; 4074 env->regs[R_EBP] = regs->rbp; 4075 env->regs[R_ESP] = regs->rsp; 4076 env->eip = regs->rip; 4077 #else 4078 env->regs[R_EAX] = regs->eax; 4079 env->regs[R_EBX] = regs->ebx; 4080 env->regs[R_ECX] = regs->ecx; 4081 env->regs[R_EDX] = regs->edx; 4082 env->regs[R_ESI] = regs->esi; 4083 env->regs[R_EDI] = regs->edi; 4084 env->regs[R_EBP] = regs->ebp; 4085 env->regs[R_ESP] = regs->esp; 4086 env->eip = regs->eip; 4087 #endif 4088 4089 /* linux interrupt setup */ 4090 #ifndef TARGET_ABI32 4091 env->idt.limit = 511; 4092 #else 4093 env->idt.limit = 255; 4094 #endif 4095 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 4096 PROT_READ|PROT_WRITE, 4097 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4098 idt_table = g2h(env->idt.base); 4099 set_idt(0, 0); 4100 set_idt(1, 0); 4101 set_idt(2, 0); 4102 set_idt(3, 3); 4103 set_idt(4, 3); 4104 set_idt(5, 0); 4105 set_idt(6, 0); 4106 set_idt(7, 0); 4107 set_idt(8, 0); 4108 set_idt(9, 0); 4109 set_idt(10, 0); 4110 set_idt(11, 0); 4111 set_idt(12, 0); 4112 set_idt(13, 0); 4113 set_idt(14, 0); 4114 set_idt(15, 0); 4115 set_idt(16, 0); 4116 set_idt(17, 0); 4117 set_idt(18, 0); 4118 set_idt(19, 0); 4119 set_idt(0x80, 3); 4120 4121 /* linux segment setup */ 4122 { 4123 uint64_t *gdt_table; 4124 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 4125 PROT_READ|PROT_WRITE, 4126 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4127 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 4128 gdt_table = g2h(env->gdt.base); 4129 #ifdef TARGET_ABI32 4130 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4131 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4132 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4133 #else 4134 /* 64 bit code segment */ 4135 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4136 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4137 DESC_L_MASK | 4138 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4139 #endif 4140 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 4141 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4142 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 4143 } 4144 cpu_x86_load_seg(env, R_CS, __USER_CS); 4145 cpu_x86_load_seg(env, R_SS, __USER_DS); 4146 #ifdef TARGET_ABI32 4147 cpu_x86_load_seg(env, R_DS, __USER_DS); 4148 cpu_x86_load_seg(env, R_ES, __USER_DS); 4149 cpu_x86_load_seg(env, R_FS, __USER_DS); 4150 cpu_x86_load_seg(env, R_GS, __USER_DS); 4151 /* This hack makes Wine work... */ 4152 env->segs[R_FS].selector = 0; 4153 #else 4154 cpu_x86_load_seg(env, R_DS, 0); 4155 cpu_x86_load_seg(env, R_ES, 0); 4156 cpu_x86_load_seg(env, R_FS, 0); 4157 cpu_x86_load_seg(env, R_GS, 0); 4158 #endif 4159 #elif defined(TARGET_AARCH64) 4160 { 4161 int i; 4162 4163 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 4164 fprintf(stderr, 4165 "The selected ARM CPU does not support 64 bit mode\n"); 4166 exit(1); 4167 } 4168 4169 for (i = 0; i < 31; i++) { 4170 env->xregs[i] = regs->regs[i]; 4171 } 4172 env->pc = regs->pc; 4173 env->xregs[31] = regs->sp; 4174 } 4175 #elif defined(TARGET_ARM) 4176 { 4177 int i; 4178 cpsr_write(env, regs->uregs[16], 0xffffffff); 4179 for(i = 0; i < 16; i++) { 4180 env->regs[i] = regs->uregs[i]; 4181 } 4182 /* Enable BE8. */ 4183 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 4184 && (info->elf_flags & EF_ARM_BE8)) { 4185 env->bswap_code = 1; 4186 } 4187 } 4188 #elif defined(TARGET_UNICORE32) 4189 { 4190 int i; 4191 cpu_asr_write(env, regs->uregs[32], 0xffffffff); 4192 for (i = 0; i < 32; i++) { 4193 env->regs[i] = regs->uregs[i]; 4194 } 4195 } 4196 #elif defined(TARGET_SPARC) 4197 { 4198 int i; 4199 env->pc = regs->pc; 4200 env->npc = regs->npc; 4201 env->y = regs->y; 4202 for(i = 0; i < 8; i++) 4203 env->gregs[i] = regs->u_regs[i]; 4204 for(i = 0; i < 8; i++) 4205 env->regwptr[i] = regs->u_regs[i + 8]; 4206 } 4207 #elif defined(TARGET_PPC) 4208 { 4209 int i; 4210 4211 #if defined(TARGET_PPC64) 4212 #if defined(TARGET_ABI32) 4213 env->msr &= ~((target_ulong)1 << MSR_SF); 4214 #else 4215 env->msr |= (target_ulong)1 << MSR_SF; 4216 #endif 4217 #endif 4218 env->nip = regs->nip; 4219 for(i = 0; i < 32; i++) { 4220 env->gpr[i] = regs->gpr[i]; 4221 } 4222 } 4223 #elif defined(TARGET_M68K) 4224 { 4225 env->pc = regs->pc; 4226 env->dregs[0] = regs->d0; 4227 env->dregs[1] = regs->d1; 4228 env->dregs[2] = regs->d2; 4229 env->dregs[3] = regs->d3; 4230 env->dregs[4] = regs->d4; 4231 env->dregs[5] = regs->d5; 4232 env->dregs[6] = regs->d6; 4233 env->dregs[7] = regs->d7; 4234 env->aregs[0] = regs->a0; 4235 env->aregs[1] = regs->a1; 4236 env->aregs[2] = regs->a2; 4237 env->aregs[3] = regs->a3; 4238 env->aregs[4] = regs->a4; 4239 env->aregs[5] = regs->a5; 4240 env->aregs[6] = regs->a6; 4241 env->aregs[7] = regs->usp; 4242 env->sr = regs->sr; 4243 ts->sim_syscalls = 1; 4244 } 4245 #elif defined(TARGET_MICROBLAZE) 4246 { 4247 env->regs[0] = regs->r0; 4248 env->regs[1] = regs->r1; 4249 env->regs[2] = regs->r2; 4250 env->regs[3] = regs->r3; 4251 env->regs[4] = regs->r4; 4252 env->regs[5] = regs->r5; 4253 env->regs[6] = regs->r6; 4254 env->regs[7] = regs->r7; 4255 env->regs[8] = regs->r8; 4256 env->regs[9] = regs->r9; 4257 env->regs[10] = regs->r10; 4258 env->regs[11] = regs->r11; 4259 env->regs[12] = regs->r12; 4260 env->regs[13] = regs->r13; 4261 env->regs[14] = regs->r14; 4262 env->regs[15] = regs->r15; 4263 env->regs[16] = regs->r16; 4264 env->regs[17] = regs->r17; 4265 env->regs[18] = regs->r18; 4266 env->regs[19] = regs->r19; 4267 env->regs[20] = regs->r20; 4268 env->regs[21] = regs->r21; 4269 env->regs[22] = regs->r22; 4270 env->regs[23] = regs->r23; 4271 env->regs[24] = regs->r24; 4272 env->regs[25] = regs->r25; 4273 env->regs[26] = regs->r26; 4274 env->regs[27] = regs->r27; 4275 env->regs[28] = regs->r28; 4276 env->regs[29] = regs->r29; 4277 env->regs[30] = regs->r30; 4278 env->regs[31] = regs->r31; 4279 env->sregs[SR_PC] = regs->pc; 4280 } 4281 #elif defined(TARGET_MIPS) 4282 { 4283 int i; 4284 4285 for(i = 0; i < 32; i++) { 4286 env->active_tc.gpr[i] = regs->regs[i]; 4287 } 4288 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 4289 if (regs->cp0_epc & 1) { 4290 env->hflags |= MIPS_HFLAG_M16; 4291 } 4292 } 4293 #elif defined(TARGET_OPENRISC) 4294 { 4295 int i; 4296 4297 for (i = 0; i < 32; i++) { 4298 env->gpr[i] = regs->gpr[i]; 4299 } 4300 4301 env->sr = regs->sr; 4302 env->pc = regs->pc; 4303 } 4304 #elif defined(TARGET_SH4) 4305 { 4306 int i; 4307 4308 for(i = 0; i < 16; i++) { 4309 env->gregs[i] = regs->regs[i]; 4310 } 4311 env->pc = regs->pc; 4312 } 4313 #elif defined(TARGET_ALPHA) 4314 { 4315 int i; 4316 4317 for(i = 0; i < 28; i++) { 4318 env->ir[i] = ((abi_ulong *)regs)[i]; 4319 } 4320 env->ir[IR_SP] = regs->usp; 4321 env->pc = regs->pc; 4322 } 4323 #elif defined(TARGET_CRIS) 4324 { 4325 env->regs[0] = regs->r0; 4326 env->regs[1] = regs->r1; 4327 env->regs[2] = regs->r2; 4328 env->regs[3] = regs->r3; 4329 env->regs[4] = regs->r4; 4330 env->regs[5] = regs->r5; 4331 env->regs[6] = regs->r6; 4332 env->regs[7] = regs->r7; 4333 env->regs[8] = regs->r8; 4334 env->regs[9] = regs->r9; 4335 env->regs[10] = regs->r10; 4336 env->regs[11] = regs->r11; 4337 env->regs[12] = regs->r12; 4338 env->regs[13] = regs->r13; 4339 env->regs[14] = info->start_stack; 4340 env->regs[15] = regs->acr; 4341 env->pc = regs->erp; 4342 } 4343 #elif defined(TARGET_S390X) 4344 { 4345 int i; 4346 for (i = 0; i < 16; i++) { 4347 env->regs[i] = regs->gprs[i]; 4348 } 4349 env->psw.mask = regs->psw.mask; 4350 env->psw.addr = regs->psw.addr; 4351 } 4352 #else 4353 #error unsupported target CPU 4354 #endif 4355 4356 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) 4357 ts->stack_base = info->start_stack; 4358 ts->heap_base = info->brk; 4359 /* This will be filled in on the first SYS_HEAPINFO call. */ 4360 ts->heap_limit = 0; 4361 #endif 4362 4363 if (gdbstub_port) { 4364 if (gdbserver_start(gdbstub_port) < 0) { 4365 fprintf(stderr, "qemu: could not open gdbserver on port %d\n", 4366 gdbstub_port); 4367 exit(1); 4368 } 4369 gdb_handlesig(cpu, 0); 4370 } 4371 cpu_loop(env); 4372 /* never exits */ 4373 return 0; 4374 } 4375