1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include <stdlib.h> 20 #include <stdio.h> 21 #include <stdarg.h> 22 #include <string.h> 23 #include <errno.h> 24 #include <unistd.h> 25 #include <sys/mman.h> 26 #include <sys/syscall.h> 27 28 #include "qemu.h" 29 #include "qemu-common.h" 30 #include "cache-utils.h" 31 /* For tb_lock */ 32 #include "exec-all.h" 33 34 35 #include "envlist.h" 36 37 #define DEBUG_LOGFILE "/tmp/qemu.log" 38 39 char *exec_path; 40 41 int singlestep; 42 #if defined(CONFIG_USE_GUEST_BASE) 43 unsigned long mmap_min_addr; 44 unsigned long guest_base; 45 int have_guest_base; 46 #endif 47 48 static const char *interp_prefix = CONFIG_QEMU_PREFIX; 49 const char *qemu_uname_release = CONFIG_UNAME_RELEASE; 50 51 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 52 we allocate a bigger stack. Need a better solution, for example 53 by remapping the process stack directly at the right place */ 54 unsigned long x86_stack_size = 512 * 1024; 55 56 void gemu_log(const char *fmt, ...) 57 { 58 va_list ap; 59 60 va_start(ap, fmt); 61 vfprintf(stderr, fmt, ap); 62 va_end(ap); 63 } 64 65 #if defined(TARGET_I386) 66 int cpu_get_pic_interrupt(CPUState *env) 67 { 68 return -1; 69 } 70 #endif 71 72 /* timers for rdtsc */ 73 74 #if 0 75 76 static uint64_t emu_time; 77 78 int64_t cpu_get_real_ticks(void) 79 { 80 return emu_time++; 81 } 82 83 #endif 84 85 #if defined(CONFIG_USE_NPTL) 86 /***********************************************************/ 87 /* Helper routines for implementing atomic operations. */ 88 89 /* To implement exclusive operations we force all cpus to syncronise. 90 We don't require a full sync, only that no cpus are executing guest code. 91 The alternative is to map target atomic ops onto host equivalents, 92 which requires quite a lot of per host/target work. */ 93 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; 94 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; 95 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; 96 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; 97 static int pending_cpus; 98 99 /* Make sure everything is in a consistent state for calling fork(). */ 100 void fork_start(void) 101 { 102 mmap_fork_start(); 103 pthread_mutex_lock(&tb_lock); 104 pthread_mutex_lock(&exclusive_lock); 105 } 106 107 void fork_end(int child) 108 { 109 if (child) { 110 /* Child processes created by fork() only have a single thread. 111 Discard information about the parent threads. */ 112 first_cpu = thread_env; 113 thread_env->next_cpu = NULL; 114 pending_cpus = 0; 115 pthread_mutex_init(&exclusive_lock, NULL); 116 pthread_mutex_init(&cpu_list_mutex, NULL); 117 pthread_cond_init(&exclusive_cond, NULL); 118 pthread_cond_init(&exclusive_resume, NULL); 119 pthread_mutex_init(&tb_lock, NULL); 120 gdbserver_fork(thread_env); 121 } else { 122 pthread_mutex_unlock(&exclusive_lock); 123 pthread_mutex_unlock(&tb_lock); 124 } 125 mmap_fork_end(child); 126 } 127 128 /* Wait for pending exclusive operations to complete. The exclusive lock 129 must be held. */ 130 static inline void exclusive_idle(void) 131 { 132 while (pending_cpus) { 133 pthread_cond_wait(&exclusive_resume, &exclusive_lock); 134 } 135 } 136 137 /* Start an exclusive operation. 138 Must only be called from outside cpu_arm_exec. */ 139 static inline void start_exclusive(void) 140 { 141 CPUState *other; 142 pthread_mutex_lock(&exclusive_lock); 143 exclusive_idle(); 144 145 pending_cpus = 1; 146 /* Make all other cpus stop executing. */ 147 for (other = first_cpu; other; other = other->next_cpu) { 148 if (other->running) { 149 pending_cpus++; 150 cpu_exit(other); 151 } 152 } 153 if (pending_cpus > 1) { 154 pthread_cond_wait(&exclusive_cond, &exclusive_lock); 155 } 156 } 157 158 /* Finish an exclusive operation. */ 159 static inline void end_exclusive(void) 160 { 161 pending_cpus = 0; 162 pthread_cond_broadcast(&exclusive_resume); 163 pthread_mutex_unlock(&exclusive_lock); 164 } 165 166 /* Wait for exclusive ops to finish, and begin cpu execution. */ 167 static inline void cpu_exec_start(CPUState *env) 168 { 169 pthread_mutex_lock(&exclusive_lock); 170 exclusive_idle(); 171 env->running = 1; 172 pthread_mutex_unlock(&exclusive_lock); 173 } 174 175 /* Mark cpu as not executing, and release pending exclusive ops. */ 176 static inline void cpu_exec_end(CPUState *env) 177 { 178 pthread_mutex_lock(&exclusive_lock); 179 env->running = 0; 180 if (pending_cpus > 1) { 181 pending_cpus--; 182 if (pending_cpus == 1) { 183 pthread_cond_signal(&exclusive_cond); 184 } 185 } 186 exclusive_idle(); 187 pthread_mutex_unlock(&exclusive_lock); 188 } 189 190 void cpu_list_lock(void) 191 { 192 pthread_mutex_lock(&cpu_list_mutex); 193 } 194 195 void cpu_list_unlock(void) 196 { 197 pthread_mutex_unlock(&cpu_list_mutex); 198 } 199 #else /* if !CONFIG_USE_NPTL */ 200 /* These are no-ops because we are not threadsafe. */ 201 static inline void cpu_exec_start(CPUState *env) 202 { 203 } 204 205 static inline void cpu_exec_end(CPUState *env) 206 { 207 } 208 209 static inline void start_exclusive(void) 210 { 211 } 212 213 static inline void end_exclusive(void) 214 { 215 } 216 217 void fork_start(void) 218 { 219 } 220 221 void fork_end(int child) 222 { 223 if (child) { 224 gdbserver_fork(thread_env); 225 } 226 } 227 228 void cpu_list_lock(void) 229 { 230 } 231 232 void cpu_list_unlock(void) 233 { 234 } 235 #endif 236 237 238 #ifdef TARGET_I386 239 /***********************************************************/ 240 /* CPUX86 core interface */ 241 242 void cpu_smm_update(CPUState *env) 243 { 244 } 245 246 uint64_t cpu_get_tsc(CPUX86State *env) 247 { 248 return cpu_get_real_ticks(); 249 } 250 251 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 252 int flags) 253 { 254 unsigned int e1, e2; 255 uint32_t *p; 256 e1 = (addr << 16) | (limit & 0xffff); 257 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 258 e2 |= flags; 259 p = ptr; 260 p[0] = tswap32(e1); 261 p[1] = tswap32(e2); 262 } 263 264 static uint64_t *idt_table; 265 #ifdef TARGET_X86_64 266 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 267 uint64_t addr, unsigned int sel) 268 { 269 uint32_t *p, e1, e2; 270 e1 = (addr & 0xffff) | (sel << 16); 271 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 272 p = ptr; 273 p[0] = tswap32(e1); 274 p[1] = tswap32(e2); 275 p[2] = tswap32(addr >> 32); 276 p[3] = 0; 277 } 278 /* only dpl matters as we do only user space emulation */ 279 static void set_idt(int n, unsigned int dpl) 280 { 281 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 282 } 283 #else 284 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 285 uint32_t addr, unsigned int sel) 286 { 287 uint32_t *p, e1, e2; 288 e1 = (addr & 0xffff) | (sel << 16); 289 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 290 p = ptr; 291 p[0] = tswap32(e1); 292 p[1] = tswap32(e2); 293 } 294 295 /* only dpl matters as we do only user space emulation */ 296 static void set_idt(int n, unsigned int dpl) 297 { 298 set_gate(idt_table + n, 0, dpl, 0, 0); 299 } 300 #endif 301 302 void cpu_loop(CPUX86State *env) 303 { 304 int trapnr; 305 abi_ulong pc; 306 target_siginfo_t info; 307 308 for(;;) { 309 trapnr = cpu_x86_exec(env); 310 switch(trapnr) { 311 case 0x80: 312 /* linux syscall from int $0x80 */ 313 env->regs[R_EAX] = do_syscall(env, 314 env->regs[R_EAX], 315 env->regs[R_EBX], 316 env->regs[R_ECX], 317 env->regs[R_EDX], 318 env->regs[R_ESI], 319 env->regs[R_EDI], 320 env->regs[R_EBP]); 321 break; 322 #ifndef TARGET_ABI32 323 case EXCP_SYSCALL: 324 /* linux syscall from syscall intruction */ 325 env->regs[R_EAX] = do_syscall(env, 326 env->regs[R_EAX], 327 env->regs[R_EDI], 328 env->regs[R_ESI], 329 env->regs[R_EDX], 330 env->regs[10], 331 env->regs[8], 332 env->regs[9]); 333 env->eip = env->exception_next_eip; 334 break; 335 #endif 336 case EXCP0B_NOSEG: 337 case EXCP0C_STACK: 338 info.si_signo = SIGBUS; 339 info.si_errno = 0; 340 info.si_code = TARGET_SI_KERNEL; 341 info._sifields._sigfault._addr = 0; 342 queue_signal(env, info.si_signo, &info); 343 break; 344 case EXCP0D_GPF: 345 /* XXX: potential problem if ABI32 */ 346 #ifndef TARGET_X86_64 347 if (env->eflags & VM_MASK) { 348 handle_vm86_fault(env); 349 } else 350 #endif 351 { 352 info.si_signo = SIGSEGV; 353 info.si_errno = 0; 354 info.si_code = TARGET_SI_KERNEL; 355 info._sifields._sigfault._addr = 0; 356 queue_signal(env, info.si_signo, &info); 357 } 358 break; 359 case EXCP0E_PAGE: 360 info.si_signo = SIGSEGV; 361 info.si_errno = 0; 362 if (!(env->error_code & 1)) 363 info.si_code = TARGET_SEGV_MAPERR; 364 else 365 info.si_code = TARGET_SEGV_ACCERR; 366 info._sifields._sigfault._addr = env->cr[2]; 367 queue_signal(env, info.si_signo, &info); 368 break; 369 case EXCP00_DIVZ: 370 #ifndef TARGET_X86_64 371 if (env->eflags & VM_MASK) { 372 handle_vm86_trap(env, trapnr); 373 } else 374 #endif 375 { 376 /* division by zero */ 377 info.si_signo = SIGFPE; 378 info.si_errno = 0; 379 info.si_code = TARGET_FPE_INTDIV; 380 info._sifields._sigfault._addr = env->eip; 381 queue_signal(env, info.si_signo, &info); 382 } 383 break; 384 case EXCP01_DB: 385 case EXCP03_INT3: 386 #ifndef TARGET_X86_64 387 if (env->eflags & VM_MASK) { 388 handle_vm86_trap(env, trapnr); 389 } else 390 #endif 391 { 392 info.si_signo = SIGTRAP; 393 info.si_errno = 0; 394 if (trapnr == EXCP01_DB) { 395 info.si_code = TARGET_TRAP_BRKPT; 396 info._sifields._sigfault._addr = env->eip; 397 } else { 398 info.si_code = TARGET_SI_KERNEL; 399 info._sifields._sigfault._addr = 0; 400 } 401 queue_signal(env, info.si_signo, &info); 402 } 403 break; 404 case EXCP04_INTO: 405 case EXCP05_BOUND: 406 #ifndef TARGET_X86_64 407 if (env->eflags & VM_MASK) { 408 handle_vm86_trap(env, trapnr); 409 } else 410 #endif 411 { 412 info.si_signo = SIGSEGV; 413 info.si_errno = 0; 414 info.si_code = TARGET_SI_KERNEL; 415 info._sifields._sigfault._addr = 0; 416 queue_signal(env, info.si_signo, &info); 417 } 418 break; 419 case EXCP06_ILLOP: 420 info.si_signo = SIGILL; 421 info.si_errno = 0; 422 info.si_code = TARGET_ILL_ILLOPN; 423 info._sifields._sigfault._addr = env->eip; 424 queue_signal(env, info.si_signo, &info); 425 break; 426 case EXCP_INTERRUPT: 427 /* just indicate that signals should be handled asap */ 428 break; 429 case EXCP_DEBUG: 430 { 431 int sig; 432 433 sig = gdb_handlesig (env, TARGET_SIGTRAP); 434 if (sig) 435 { 436 info.si_signo = sig; 437 info.si_errno = 0; 438 info.si_code = TARGET_TRAP_BRKPT; 439 queue_signal(env, info.si_signo, &info); 440 } 441 } 442 break; 443 default: 444 pc = env->segs[R_CS].base + env->eip; 445 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 446 (long)pc, trapnr); 447 abort(); 448 } 449 process_pending_signals(env); 450 } 451 } 452 #endif 453 454 #ifdef TARGET_ARM 455 456 static void arm_cache_flush(abi_ulong start, abi_ulong last) 457 { 458 abi_ulong addr, last1; 459 460 if (last < start) 461 return; 462 addr = start; 463 for(;;) { 464 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1; 465 if (last1 > last) 466 last1 = last; 467 tb_invalidate_page_range(addr, last1 + 1); 468 if (last1 == last) 469 break; 470 addr = last1 + 1; 471 } 472 } 473 474 /* Handle a jump to the kernel code page. */ 475 static int 476 do_kernel_trap(CPUARMState *env) 477 { 478 uint32_t addr; 479 uint32_t cpsr; 480 uint32_t val; 481 482 switch (env->regs[15]) { 483 case 0xffff0fa0: /* __kernel_memory_barrier */ 484 /* ??? No-op. Will need to do better for SMP. */ 485 break; 486 case 0xffff0fc0: /* __kernel_cmpxchg */ 487 /* XXX: This only works between threads, not between processes. 488 It's probably possible to implement this with native host 489 operations. However things like ldrex/strex are much harder so 490 there's not much point trying. */ 491 start_exclusive(); 492 cpsr = cpsr_read(env); 493 addr = env->regs[2]; 494 /* FIXME: This should SEGV if the access fails. */ 495 if (get_user_u32(val, addr)) 496 val = ~env->regs[0]; 497 if (val == env->regs[0]) { 498 val = env->regs[1]; 499 /* FIXME: Check for segfaults. */ 500 put_user_u32(val, addr); 501 env->regs[0] = 0; 502 cpsr |= CPSR_C; 503 } else { 504 env->regs[0] = -1; 505 cpsr &= ~CPSR_C; 506 } 507 cpsr_write(env, cpsr, CPSR_C); 508 end_exclusive(); 509 break; 510 case 0xffff0fe0: /* __kernel_get_tls */ 511 env->regs[0] = env->cp15.c13_tls2; 512 break; 513 default: 514 return 1; 515 } 516 /* Jump back to the caller. */ 517 addr = env->regs[14]; 518 if (addr & 1) { 519 env->thumb = 1; 520 addr &= ~1; 521 } 522 env->regs[15] = addr; 523 524 return 0; 525 } 526 527 void cpu_loop(CPUARMState *env) 528 { 529 int trapnr; 530 unsigned int n, insn; 531 target_siginfo_t info; 532 uint32_t addr; 533 534 for(;;) { 535 cpu_exec_start(env); 536 trapnr = cpu_arm_exec(env); 537 cpu_exec_end(env); 538 switch(trapnr) { 539 case EXCP_UDEF: 540 { 541 TaskState *ts = env->opaque; 542 uint32_t opcode; 543 int rc; 544 545 /* we handle the FPU emulation here, as Linux */ 546 /* we get the opcode */ 547 /* FIXME - what to do if get_user() fails? */ 548 get_user_u32(opcode, env->regs[15]); 549 550 rc = EmulateAll(opcode, &ts->fpa, env); 551 if (rc == 0) { /* illegal instruction */ 552 info.si_signo = SIGILL; 553 info.si_errno = 0; 554 info.si_code = TARGET_ILL_ILLOPN; 555 info._sifields._sigfault._addr = env->regs[15]; 556 queue_signal(env, info.si_signo, &info); 557 } else if (rc < 0) { /* FP exception */ 558 int arm_fpe=0; 559 560 /* translate softfloat flags to FPSR flags */ 561 if (-rc & float_flag_invalid) 562 arm_fpe |= BIT_IOC; 563 if (-rc & float_flag_divbyzero) 564 arm_fpe |= BIT_DZC; 565 if (-rc & float_flag_overflow) 566 arm_fpe |= BIT_OFC; 567 if (-rc & float_flag_underflow) 568 arm_fpe |= BIT_UFC; 569 if (-rc & float_flag_inexact) 570 arm_fpe |= BIT_IXC; 571 572 FPSR fpsr = ts->fpa.fpsr; 573 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 574 575 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 576 info.si_signo = SIGFPE; 577 info.si_errno = 0; 578 579 /* ordered by priority, least first */ 580 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 581 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 582 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 583 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 584 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 585 586 info._sifields._sigfault._addr = env->regs[15]; 587 queue_signal(env, info.si_signo, &info); 588 } else { 589 env->regs[15] += 4; 590 } 591 592 /* accumulate unenabled exceptions */ 593 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 594 fpsr |= BIT_IXC; 595 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 596 fpsr |= BIT_UFC; 597 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 598 fpsr |= BIT_OFC; 599 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 600 fpsr |= BIT_DZC; 601 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 602 fpsr |= BIT_IOC; 603 ts->fpa.fpsr=fpsr; 604 } else { /* everything OK */ 605 /* increment PC */ 606 env->regs[15] += 4; 607 } 608 } 609 break; 610 case EXCP_SWI: 611 case EXCP_BKPT: 612 { 613 env->eabi = 1; 614 /* system call */ 615 if (trapnr == EXCP_BKPT) { 616 if (env->thumb) { 617 /* FIXME - what to do if get_user() fails? */ 618 get_user_u16(insn, env->regs[15]); 619 n = insn & 0xff; 620 env->regs[15] += 2; 621 } else { 622 /* FIXME - what to do if get_user() fails? */ 623 get_user_u32(insn, env->regs[15]); 624 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 625 env->regs[15] += 4; 626 } 627 } else { 628 if (env->thumb) { 629 /* FIXME - what to do if get_user() fails? */ 630 get_user_u16(insn, env->regs[15] - 2); 631 n = insn & 0xff; 632 } else { 633 /* FIXME - what to do if get_user() fails? */ 634 get_user_u32(insn, env->regs[15] - 4); 635 n = insn & 0xffffff; 636 } 637 } 638 639 if (n == ARM_NR_cacheflush) { 640 arm_cache_flush(env->regs[0], env->regs[1]); 641 } else if (n == ARM_NR_semihosting 642 || n == ARM_NR_thumb_semihosting) { 643 env->regs[0] = do_arm_semihosting (env); 644 } else if (n == 0 || n >= ARM_SYSCALL_BASE 645 || (env->thumb && n == ARM_THUMB_SYSCALL)) { 646 /* linux syscall */ 647 if (env->thumb || n == 0) { 648 n = env->regs[7]; 649 } else { 650 n -= ARM_SYSCALL_BASE; 651 env->eabi = 0; 652 } 653 if ( n > ARM_NR_BASE) { 654 switch (n) { 655 case ARM_NR_cacheflush: 656 arm_cache_flush(env->regs[0], env->regs[1]); 657 break; 658 case ARM_NR_set_tls: 659 cpu_set_tls(env, env->regs[0]); 660 env->regs[0] = 0; 661 break; 662 default: 663 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 664 n); 665 env->regs[0] = -TARGET_ENOSYS; 666 break; 667 } 668 } else { 669 env->regs[0] = do_syscall(env, 670 n, 671 env->regs[0], 672 env->regs[1], 673 env->regs[2], 674 env->regs[3], 675 env->regs[4], 676 env->regs[5]); 677 } 678 } else { 679 goto error; 680 } 681 } 682 break; 683 case EXCP_INTERRUPT: 684 /* just indicate that signals should be handled asap */ 685 break; 686 case EXCP_PREFETCH_ABORT: 687 addr = env->cp15.c6_insn; 688 goto do_segv; 689 case EXCP_DATA_ABORT: 690 addr = env->cp15.c6_data; 691 goto do_segv; 692 do_segv: 693 { 694 info.si_signo = SIGSEGV; 695 info.si_errno = 0; 696 /* XXX: check env->error_code */ 697 info.si_code = TARGET_SEGV_MAPERR; 698 info._sifields._sigfault._addr = addr; 699 queue_signal(env, info.si_signo, &info); 700 } 701 break; 702 case EXCP_DEBUG: 703 { 704 int sig; 705 706 sig = gdb_handlesig (env, TARGET_SIGTRAP); 707 if (sig) 708 { 709 info.si_signo = sig; 710 info.si_errno = 0; 711 info.si_code = TARGET_TRAP_BRKPT; 712 queue_signal(env, info.si_signo, &info); 713 } 714 } 715 break; 716 case EXCP_KERNEL_TRAP: 717 if (do_kernel_trap(env)) 718 goto error; 719 break; 720 default: 721 error: 722 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 723 trapnr); 724 cpu_dump_state(env, stderr, fprintf, 0); 725 abort(); 726 } 727 process_pending_signals(env); 728 } 729 } 730 731 #endif 732 733 #ifdef TARGET_SPARC 734 #define SPARC64_STACK_BIAS 2047 735 736 //#define DEBUG_WIN 737 738 /* WARNING: dealing with register windows _is_ complicated. More info 739 can be found at http://www.sics.se/~psm/sparcstack.html */ 740 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 741 { 742 index = (index + cwp * 16) % (16 * env->nwindows); 743 /* wrap handling : if cwp is on the last window, then we use the 744 registers 'after' the end */ 745 if (index < 8 && env->cwp == env->nwindows - 1) 746 index += 16 * env->nwindows; 747 return index; 748 } 749 750 /* save the register window 'cwp1' */ 751 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 752 { 753 unsigned int i; 754 abi_ulong sp_ptr; 755 756 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 757 #ifdef TARGET_SPARC64 758 if (sp_ptr & 3) 759 sp_ptr += SPARC64_STACK_BIAS; 760 #endif 761 #if defined(DEBUG_WIN) 762 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 763 sp_ptr, cwp1); 764 #endif 765 for(i = 0; i < 16; i++) { 766 /* FIXME - what to do if put_user() fails? */ 767 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 768 sp_ptr += sizeof(abi_ulong); 769 } 770 } 771 772 static void save_window(CPUSPARCState *env) 773 { 774 #ifndef TARGET_SPARC64 775 unsigned int new_wim; 776 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 777 ((1LL << env->nwindows) - 1); 778 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 779 env->wim = new_wim; 780 #else 781 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 782 env->cansave++; 783 env->canrestore--; 784 #endif 785 } 786 787 static void restore_window(CPUSPARCState *env) 788 { 789 #ifndef TARGET_SPARC64 790 unsigned int new_wim; 791 #endif 792 unsigned int i, cwp1; 793 abi_ulong sp_ptr; 794 795 #ifndef TARGET_SPARC64 796 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 797 ((1LL << env->nwindows) - 1); 798 #endif 799 800 /* restore the invalid window */ 801 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 802 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 803 #ifdef TARGET_SPARC64 804 if (sp_ptr & 3) 805 sp_ptr += SPARC64_STACK_BIAS; 806 #endif 807 #if defined(DEBUG_WIN) 808 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 809 sp_ptr, cwp1); 810 #endif 811 for(i = 0; i < 16; i++) { 812 /* FIXME - what to do if get_user() fails? */ 813 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 814 sp_ptr += sizeof(abi_ulong); 815 } 816 #ifdef TARGET_SPARC64 817 env->canrestore++; 818 if (env->cleanwin < env->nwindows - 1) 819 env->cleanwin++; 820 env->cansave--; 821 #else 822 env->wim = new_wim; 823 #endif 824 } 825 826 static void flush_windows(CPUSPARCState *env) 827 { 828 int offset, cwp1; 829 830 offset = 1; 831 for(;;) { 832 /* if restore would invoke restore_window(), then we can stop */ 833 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 834 #ifndef TARGET_SPARC64 835 if (env->wim & (1 << cwp1)) 836 break; 837 #else 838 if (env->canrestore == 0) 839 break; 840 env->cansave++; 841 env->canrestore--; 842 #endif 843 save_window_offset(env, cwp1); 844 offset++; 845 } 846 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 847 #ifndef TARGET_SPARC64 848 /* set wim so that restore will reload the registers */ 849 env->wim = 1 << cwp1; 850 #endif 851 #if defined(DEBUG_WIN) 852 printf("flush_windows: nb=%d\n", offset - 1); 853 #endif 854 } 855 856 void cpu_loop (CPUSPARCState *env) 857 { 858 int trapnr, ret; 859 target_siginfo_t info; 860 861 while (1) { 862 trapnr = cpu_sparc_exec (env); 863 864 switch (trapnr) { 865 #ifndef TARGET_SPARC64 866 case 0x88: 867 case 0x90: 868 #else 869 case 0x110: 870 case 0x16d: 871 #endif 872 ret = do_syscall (env, env->gregs[1], 873 env->regwptr[0], env->regwptr[1], 874 env->regwptr[2], env->regwptr[3], 875 env->regwptr[4], env->regwptr[5]); 876 if ((unsigned int)ret >= (unsigned int)(-515)) { 877 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 878 env->xcc |= PSR_CARRY; 879 #else 880 env->psr |= PSR_CARRY; 881 #endif 882 ret = -ret; 883 } else { 884 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 885 env->xcc &= ~PSR_CARRY; 886 #else 887 env->psr &= ~PSR_CARRY; 888 #endif 889 } 890 env->regwptr[0] = ret; 891 /* next instruction */ 892 env->pc = env->npc; 893 env->npc = env->npc + 4; 894 break; 895 case 0x83: /* flush windows */ 896 #ifdef TARGET_ABI32 897 case 0x103: 898 #endif 899 flush_windows(env); 900 /* next instruction */ 901 env->pc = env->npc; 902 env->npc = env->npc + 4; 903 break; 904 #ifndef TARGET_SPARC64 905 case TT_WIN_OVF: /* window overflow */ 906 save_window(env); 907 break; 908 case TT_WIN_UNF: /* window underflow */ 909 restore_window(env); 910 break; 911 case TT_TFAULT: 912 case TT_DFAULT: 913 { 914 info.si_signo = SIGSEGV; 915 info.si_errno = 0; 916 /* XXX: check env->error_code */ 917 info.si_code = TARGET_SEGV_MAPERR; 918 info._sifields._sigfault._addr = env->mmuregs[4]; 919 queue_signal(env, info.si_signo, &info); 920 } 921 break; 922 #else 923 case TT_SPILL: /* window overflow */ 924 save_window(env); 925 break; 926 case TT_FILL: /* window underflow */ 927 restore_window(env); 928 break; 929 case TT_TFAULT: 930 case TT_DFAULT: 931 { 932 info.si_signo = SIGSEGV; 933 info.si_errno = 0; 934 /* XXX: check env->error_code */ 935 info.si_code = TARGET_SEGV_MAPERR; 936 if (trapnr == TT_DFAULT) 937 info._sifields._sigfault._addr = env->dmmuregs[4]; 938 else 939 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; 940 queue_signal(env, info.si_signo, &info); 941 } 942 break; 943 #ifndef TARGET_ABI32 944 case 0x16e: 945 flush_windows(env); 946 sparc64_get_context(env); 947 break; 948 case 0x16f: 949 flush_windows(env); 950 sparc64_set_context(env); 951 break; 952 #endif 953 #endif 954 case EXCP_INTERRUPT: 955 /* just indicate that signals should be handled asap */ 956 break; 957 case EXCP_DEBUG: 958 { 959 int sig; 960 961 sig = gdb_handlesig (env, TARGET_SIGTRAP); 962 if (sig) 963 { 964 info.si_signo = sig; 965 info.si_errno = 0; 966 info.si_code = TARGET_TRAP_BRKPT; 967 queue_signal(env, info.si_signo, &info); 968 } 969 } 970 break; 971 default: 972 printf ("Unhandled trap: 0x%x\n", trapnr); 973 cpu_dump_state(env, stderr, fprintf, 0); 974 exit (1); 975 } 976 process_pending_signals (env); 977 } 978 } 979 980 #endif 981 982 #ifdef TARGET_PPC 983 static inline uint64_t cpu_ppc_get_tb (CPUState *env) 984 { 985 /* TO FIX */ 986 return 0; 987 } 988 989 uint32_t cpu_ppc_load_tbl (CPUState *env) 990 { 991 return cpu_ppc_get_tb(env) & 0xFFFFFFFF; 992 } 993 994 uint32_t cpu_ppc_load_tbu (CPUState *env) 995 { 996 return cpu_ppc_get_tb(env) >> 32; 997 } 998 999 uint32_t cpu_ppc_load_atbl (CPUState *env) 1000 { 1001 return cpu_ppc_get_tb(env) & 0xFFFFFFFF; 1002 } 1003 1004 uint32_t cpu_ppc_load_atbu (CPUState *env) 1005 { 1006 return cpu_ppc_get_tb(env) >> 32; 1007 } 1008 1009 uint32_t cpu_ppc601_load_rtcu (CPUState *env) 1010 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1011 1012 uint32_t cpu_ppc601_load_rtcl (CPUState *env) 1013 { 1014 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1015 } 1016 1017 /* XXX: to be fixed */ 1018 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) 1019 { 1020 return -1; 1021 } 1022 1023 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) 1024 { 1025 return -1; 1026 } 1027 1028 #define EXCP_DUMP(env, fmt, ...) \ 1029 do { \ 1030 fprintf(stderr, fmt , ## __VA_ARGS__); \ 1031 cpu_dump_state(env, stderr, fprintf, 0); \ 1032 qemu_log(fmt, ## __VA_ARGS__); \ 1033 if (logfile) \ 1034 log_cpu_state(env, 0); \ 1035 } while (0) 1036 1037 static int do_store_exclusive(CPUPPCState *env) 1038 { 1039 target_ulong addr; 1040 target_ulong page_addr; 1041 target_ulong val; 1042 int flags; 1043 int segv = 0; 1044 1045 addr = env->reserve_ea; 1046 page_addr = addr & TARGET_PAGE_MASK; 1047 start_exclusive(); 1048 mmap_lock(); 1049 flags = page_get_flags(page_addr); 1050 if ((flags & PAGE_READ) == 0) { 1051 segv = 1; 1052 } else { 1053 int reg = env->reserve_info & 0x1f; 1054 int size = (env->reserve_info >> 5) & 0xf; 1055 int stored = 0; 1056 1057 if (addr == env->reserve_addr) { 1058 switch (size) { 1059 case 1: segv = get_user_u8(val, addr); break; 1060 case 2: segv = get_user_u16(val, addr); break; 1061 case 4: segv = get_user_u32(val, addr); break; 1062 #if defined(TARGET_PPC64) 1063 case 8: segv = get_user_u64(val, addr); break; 1064 #endif 1065 default: abort(); 1066 } 1067 if (!segv && val == env->reserve_val) { 1068 val = env->gpr[reg]; 1069 switch (size) { 1070 case 1: segv = put_user_u8(val, addr); break; 1071 case 2: segv = put_user_u16(val, addr); break; 1072 case 4: segv = put_user_u32(val, addr); break; 1073 #if defined(TARGET_PPC64) 1074 case 8: segv = put_user_u64(val, addr); break; 1075 #endif 1076 default: abort(); 1077 } 1078 if (!segv) { 1079 stored = 1; 1080 } 1081 } 1082 } 1083 env->crf[0] = (stored << 1) | xer_so; 1084 env->reserve_addr = (target_ulong)-1; 1085 } 1086 if (!segv) { 1087 env->nip += 4; 1088 } 1089 mmap_unlock(); 1090 end_exclusive(); 1091 return segv; 1092 } 1093 1094 void cpu_loop(CPUPPCState *env) 1095 { 1096 target_siginfo_t info; 1097 int trapnr; 1098 uint32_t ret; 1099 1100 for(;;) { 1101 cpu_exec_start(env); 1102 trapnr = cpu_ppc_exec(env); 1103 cpu_exec_end(env); 1104 switch(trapnr) { 1105 case POWERPC_EXCP_NONE: 1106 /* Just go on */ 1107 break; 1108 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1109 cpu_abort(env, "Critical interrupt while in user mode. " 1110 "Aborting\n"); 1111 break; 1112 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1113 cpu_abort(env, "Machine check exception while in user mode. " 1114 "Aborting\n"); 1115 break; 1116 case POWERPC_EXCP_DSI: /* Data storage exception */ 1117 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n", 1118 env->spr[SPR_DAR]); 1119 /* XXX: check this. Seems bugged */ 1120 switch (env->error_code & 0xFF000000) { 1121 case 0x40000000: 1122 info.si_signo = TARGET_SIGSEGV; 1123 info.si_errno = 0; 1124 info.si_code = TARGET_SEGV_MAPERR; 1125 break; 1126 case 0x04000000: 1127 info.si_signo = TARGET_SIGILL; 1128 info.si_errno = 0; 1129 info.si_code = TARGET_ILL_ILLADR; 1130 break; 1131 case 0x08000000: 1132 info.si_signo = TARGET_SIGSEGV; 1133 info.si_errno = 0; 1134 info.si_code = TARGET_SEGV_ACCERR; 1135 break; 1136 default: 1137 /* Let's send a regular segfault... */ 1138 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1139 env->error_code); 1140 info.si_signo = TARGET_SIGSEGV; 1141 info.si_errno = 0; 1142 info.si_code = TARGET_SEGV_MAPERR; 1143 break; 1144 } 1145 info._sifields._sigfault._addr = env->nip; 1146 queue_signal(env, info.si_signo, &info); 1147 break; 1148 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1149 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx 1150 "\n", env->spr[SPR_SRR0]); 1151 /* XXX: check this */ 1152 switch (env->error_code & 0xFF000000) { 1153 case 0x40000000: 1154 info.si_signo = TARGET_SIGSEGV; 1155 info.si_errno = 0; 1156 info.si_code = TARGET_SEGV_MAPERR; 1157 break; 1158 case 0x10000000: 1159 case 0x08000000: 1160 info.si_signo = TARGET_SIGSEGV; 1161 info.si_errno = 0; 1162 info.si_code = TARGET_SEGV_ACCERR; 1163 break; 1164 default: 1165 /* Let's send a regular segfault... */ 1166 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1167 env->error_code); 1168 info.si_signo = TARGET_SIGSEGV; 1169 info.si_errno = 0; 1170 info.si_code = TARGET_SEGV_MAPERR; 1171 break; 1172 } 1173 info._sifields._sigfault._addr = env->nip - 4; 1174 queue_signal(env, info.si_signo, &info); 1175 break; 1176 case POWERPC_EXCP_EXTERNAL: /* External input */ 1177 cpu_abort(env, "External interrupt while in user mode. " 1178 "Aborting\n"); 1179 break; 1180 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1181 EXCP_DUMP(env, "Unaligned memory access\n"); 1182 /* XXX: check this */ 1183 info.si_signo = TARGET_SIGBUS; 1184 info.si_errno = 0; 1185 info.si_code = TARGET_BUS_ADRALN; 1186 info._sifields._sigfault._addr = env->nip - 4; 1187 queue_signal(env, info.si_signo, &info); 1188 break; 1189 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1190 /* XXX: check this */ 1191 switch (env->error_code & ~0xF) { 1192 case POWERPC_EXCP_FP: 1193 EXCP_DUMP(env, "Floating point program exception\n"); 1194 info.si_signo = TARGET_SIGFPE; 1195 info.si_errno = 0; 1196 switch (env->error_code & 0xF) { 1197 case POWERPC_EXCP_FP_OX: 1198 info.si_code = TARGET_FPE_FLTOVF; 1199 break; 1200 case POWERPC_EXCP_FP_UX: 1201 info.si_code = TARGET_FPE_FLTUND; 1202 break; 1203 case POWERPC_EXCP_FP_ZX: 1204 case POWERPC_EXCP_FP_VXZDZ: 1205 info.si_code = TARGET_FPE_FLTDIV; 1206 break; 1207 case POWERPC_EXCP_FP_XX: 1208 info.si_code = TARGET_FPE_FLTRES; 1209 break; 1210 case POWERPC_EXCP_FP_VXSOFT: 1211 info.si_code = TARGET_FPE_FLTINV; 1212 break; 1213 case POWERPC_EXCP_FP_VXSNAN: 1214 case POWERPC_EXCP_FP_VXISI: 1215 case POWERPC_EXCP_FP_VXIDI: 1216 case POWERPC_EXCP_FP_VXIMZ: 1217 case POWERPC_EXCP_FP_VXVC: 1218 case POWERPC_EXCP_FP_VXSQRT: 1219 case POWERPC_EXCP_FP_VXCVI: 1220 info.si_code = TARGET_FPE_FLTSUB; 1221 break; 1222 default: 1223 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1224 env->error_code); 1225 break; 1226 } 1227 break; 1228 case POWERPC_EXCP_INVAL: 1229 EXCP_DUMP(env, "Invalid instruction\n"); 1230 info.si_signo = TARGET_SIGILL; 1231 info.si_errno = 0; 1232 switch (env->error_code & 0xF) { 1233 case POWERPC_EXCP_INVAL_INVAL: 1234 info.si_code = TARGET_ILL_ILLOPC; 1235 break; 1236 case POWERPC_EXCP_INVAL_LSWX: 1237 info.si_code = TARGET_ILL_ILLOPN; 1238 break; 1239 case POWERPC_EXCP_INVAL_SPR: 1240 info.si_code = TARGET_ILL_PRVREG; 1241 break; 1242 case POWERPC_EXCP_INVAL_FP: 1243 info.si_code = TARGET_ILL_COPROC; 1244 break; 1245 default: 1246 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1247 env->error_code & 0xF); 1248 info.si_code = TARGET_ILL_ILLADR; 1249 break; 1250 } 1251 break; 1252 case POWERPC_EXCP_PRIV: 1253 EXCP_DUMP(env, "Privilege violation\n"); 1254 info.si_signo = TARGET_SIGILL; 1255 info.si_errno = 0; 1256 switch (env->error_code & 0xF) { 1257 case POWERPC_EXCP_PRIV_OPC: 1258 info.si_code = TARGET_ILL_PRVOPC; 1259 break; 1260 case POWERPC_EXCP_PRIV_REG: 1261 info.si_code = TARGET_ILL_PRVREG; 1262 break; 1263 default: 1264 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1265 env->error_code & 0xF); 1266 info.si_code = TARGET_ILL_PRVOPC; 1267 break; 1268 } 1269 break; 1270 case POWERPC_EXCP_TRAP: 1271 cpu_abort(env, "Tried to call a TRAP\n"); 1272 break; 1273 default: 1274 /* Should not happen ! */ 1275 cpu_abort(env, "Unknown program exception (%02x)\n", 1276 env->error_code); 1277 break; 1278 } 1279 info._sifields._sigfault._addr = env->nip - 4; 1280 queue_signal(env, info.si_signo, &info); 1281 break; 1282 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1283 EXCP_DUMP(env, "No floating point allowed\n"); 1284 info.si_signo = TARGET_SIGILL; 1285 info.si_errno = 0; 1286 info.si_code = TARGET_ILL_COPROC; 1287 info._sifields._sigfault._addr = env->nip - 4; 1288 queue_signal(env, info.si_signo, &info); 1289 break; 1290 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1291 cpu_abort(env, "Syscall exception while in user mode. " 1292 "Aborting\n"); 1293 break; 1294 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1295 EXCP_DUMP(env, "No APU instruction allowed\n"); 1296 info.si_signo = TARGET_SIGILL; 1297 info.si_errno = 0; 1298 info.si_code = TARGET_ILL_COPROC; 1299 info._sifields._sigfault._addr = env->nip - 4; 1300 queue_signal(env, info.si_signo, &info); 1301 break; 1302 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1303 cpu_abort(env, "Decrementer interrupt while in user mode. " 1304 "Aborting\n"); 1305 break; 1306 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1307 cpu_abort(env, "Fix interval timer interrupt while in user mode. " 1308 "Aborting\n"); 1309 break; 1310 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1311 cpu_abort(env, "Watchdog timer interrupt while in user mode. " 1312 "Aborting\n"); 1313 break; 1314 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1315 cpu_abort(env, "Data TLB exception while in user mode. " 1316 "Aborting\n"); 1317 break; 1318 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1319 cpu_abort(env, "Instruction TLB exception while in user mode. " 1320 "Aborting\n"); 1321 break; 1322 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1323 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); 1324 info.si_signo = TARGET_SIGILL; 1325 info.si_errno = 0; 1326 info.si_code = TARGET_ILL_COPROC; 1327 info._sifields._sigfault._addr = env->nip - 4; 1328 queue_signal(env, info.si_signo, &info); 1329 break; 1330 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1331 cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); 1332 break; 1333 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1334 cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); 1335 break; 1336 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1337 cpu_abort(env, "Performance monitor exception not handled\n"); 1338 break; 1339 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1340 cpu_abort(env, "Doorbell interrupt while in user mode. " 1341 "Aborting\n"); 1342 break; 1343 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1344 cpu_abort(env, "Doorbell critical interrupt while in user mode. " 1345 "Aborting\n"); 1346 break; 1347 case POWERPC_EXCP_RESET: /* System reset exception */ 1348 cpu_abort(env, "Reset interrupt while in user mode. " 1349 "Aborting\n"); 1350 break; 1351 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1352 cpu_abort(env, "Data segment exception while in user mode. " 1353 "Aborting\n"); 1354 break; 1355 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1356 cpu_abort(env, "Instruction segment exception " 1357 "while in user mode. Aborting\n"); 1358 break; 1359 /* PowerPC 64 with hypervisor mode support */ 1360 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1361 cpu_abort(env, "Hypervisor decrementer interrupt " 1362 "while in user mode. Aborting\n"); 1363 break; 1364 case POWERPC_EXCP_TRACE: /* Trace exception */ 1365 /* Nothing to do: 1366 * we use this exception to emulate step-by-step execution mode. 1367 */ 1368 break; 1369 /* PowerPC 64 with hypervisor mode support */ 1370 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1371 cpu_abort(env, "Hypervisor data storage exception " 1372 "while in user mode. Aborting\n"); 1373 break; 1374 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1375 cpu_abort(env, "Hypervisor instruction storage exception " 1376 "while in user mode. Aborting\n"); 1377 break; 1378 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1379 cpu_abort(env, "Hypervisor data segment exception " 1380 "while in user mode. Aborting\n"); 1381 break; 1382 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1383 cpu_abort(env, "Hypervisor instruction segment exception " 1384 "while in user mode. Aborting\n"); 1385 break; 1386 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1387 EXCP_DUMP(env, "No Altivec instructions allowed\n"); 1388 info.si_signo = TARGET_SIGILL; 1389 info.si_errno = 0; 1390 info.si_code = TARGET_ILL_COPROC; 1391 info._sifields._sigfault._addr = env->nip - 4; 1392 queue_signal(env, info.si_signo, &info); 1393 break; 1394 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1395 cpu_abort(env, "Programable interval timer interrupt " 1396 "while in user mode. Aborting\n"); 1397 break; 1398 case POWERPC_EXCP_IO: /* IO error exception */ 1399 cpu_abort(env, "IO error exception while in user mode. " 1400 "Aborting\n"); 1401 break; 1402 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1403 cpu_abort(env, "Run mode exception while in user mode. " 1404 "Aborting\n"); 1405 break; 1406 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1407 cpu_abort(env, "Emulation trap exception not handled\n"); 1408 break; 1409 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1410 cpu_abort(env, "Instruction fetch TLB exception " 1411 "while in user-mode. Aborting"); 1412 break; 1413 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1414 cpu_abort(env, "Data load TLB exception while in user-mode. " 1415 "Aborting"); 1416 break; 1417 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1418 cpu_abort(env, "Data store TLB exception while in user-mode. " 1419 "Aborting"); 1420 break; 1421 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1422 cpu_abort(env, "Floating-point assist exception not handled\n"); 1423 break; 1424 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1425 cpu_abort(env, "Instruction address breakpoint exception " 1426 "not handled\n"); 1427 break; 1428 case POWERPC_EXCP_SMI: /* System management interrupt */ 1429 cpu_abort(env, "System management interrupt while in user mode. " 1430 "Aborting\n"); 1431 break; 1432 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1433 cpu_abort(env, "Thermal interrupt interrupt while in user mode. " 1434 "Aborting\n"); 1435 break; 1436 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1437 cpu_abort(env, "Performance monitor exception not handled\n"); 1438 break; 1439 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1440 cpu_abort(env, "Vector assist exception not handled\n"); 1441 break; 1442 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1443 cpu_abort(env, "Soft patch exception not handled\n"); 1444 break; 1445 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1446 cpu_abort(env, "Maintenance exception while in user mode. " 1447 "Aborting\n"); 1448 break; 1449 case POWERPC_EXCP_STOP: /* stop translation */ 1450 /* We did invalidate the instruction cache. Go on */ 1451 break; 1452 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1453 /* We just stopped because of a branch. Go on */ 1454 break; 1455 case POWERPC_EXCP_SYSCALL_USER: 1456 /* system call in user-mode emulation */ 1457 /* WARNING: 1458 * PPC ABI uses overflow flag in cr0 to signal an error 1459 * in syscalls. 1460 */ 1461 #if 0 1462 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0], 1463 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]); 1464 #endif 1465 env->crf[0] &= ~0x1; 1466 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1467 env->gpr[5], env->gpr[6], env->gpr[7], 1468 env->gpr[8]); 1469 if (ret == (uint32_t)(-TARGET_QEMU_ESIGRETURN)) { 1470 /* Returning from a successful sigreturn syscall. 1471 Avoid corrupting register state. */ 1472 break; 1473 } 1474 if (ret > (uint32_t)(-515)) { 1475 env->crf[0] |= 0x1; 1476 ret = -ret; 1477 } 1478 env->gpr[3] = ret; 1479 #if 0 1480 printf("syscall returned 0x%08x (%d)\n", ret, ret); 1481 #endif 1482 break; 1483 case POWERPC_EXCP_STCX: 1484 if (do_store_exclusive(env)) { 1485 info.si_signo = TARGET_SIGSEGV; 1486 info.si_errno = 0; 1487 info.si_code = TARGET_SEGV_MAPERR; 1488 info._sifields._sigfault._addr = env->nip; 1489 queue_signal(env, info.si_signo, &info); 1490 } 1491 break; 1492 case EXCP_DEBUG: 1493 { 1494 int sig; 1495 1496 sig = gdb_handlesig(env, TARGET_SIGTRAP); 1497 if (sig) { 1498 info.si_signo = sig; 1499 info.si_errno = 0; 1500 info.si_code = TARGET_TRAP_BRKPT; 1501 queue_signal(env, info.si_signo, &info); 1502 } 1503 } 1504 break; 1505 case EXCP_INTERRUPT: 1506 /* just indicate that signals should be handled asap */ 1507 break; 1508 default: 1509 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); 1510 break; 1511 } 1512 process_pending_signals(env); 1513 } 1514 } 1515 #endif 1516 1517 #ifdef TARGET_MIPS 1518 1519 #define MIPS_SYS(name, args) args, 1520 1521 static const uint8_t mips_syscall_args[] = { 1522 MIPS_SYS(sys_syscall , 0) /* 4000 */ 1523 MIPS_SYS(sys_exit , 1) 1524 MIPS_SYS(sys_fork , 0) 1525 MIPS_SYS(sys_read , 3) 1526 MIPS_SYS(sys_write , 3) 1527 MIPS_SYS(sys_open , 3) /* 4005 */ 1528 MIPS_SYS(sys_close , 1) 1529 MIPS_SYS(sys_waitpid , 3) 1530 MIPS_SYS(sys_creat , 2) 1531 MIPS_SYS(sys_link , 2) 1532 MIPS_SYS(sys_unlink , 1) /* 4010 */ 1533 MIPS_SYS(sys_execve , 0) 1534 MIPS_SYS(sys_chdir , 1) 1535 MIPS_SYS(sys_time , 1) 1536 MIPS_SYS(sys_mknod , 3) 1537 MIPS_SYS(sys_chmod , 2) /* 4015 */ 1538 MIPS_SYS(sys_lchown , 3) 1539 MIPS_SYS(sys_ni_syscall , 0) 1540 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 1541 MIPS_SYS(sys_lseek , 3) 1542 MIPS_SYS(sys_getpid , 0) /* 4020 */ 1543 MIPS_SYS(sys_mount , 5) 1544 MIPS_SYS(sys_oldumount , 1) 1545 MIPS_SYS(sys_setuid , 1) 1546 MIPS_SYS(sys_getuid , 0) 1547 MIPS_SYS(sys_stime , 1) /* 4025 */ 1548 MIPS_SYS(sys_ptrace , 4) 1549 MIPS_SYS(sys_alarm , 1) 1550 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 1551 MIPS_SYS(sys_pause , 0) 1552 MIPS_SYS(sys_utime , 2) /* 4030 */ 1553 MIPS_SYS(sys_ni_syscall , 0) 1554 MIPS_SYS(sys_ni_syscall , 0) 1555 MIPS_SYS(sys_access , 2) 1556 MIPS_SYS(sys_nice , 1) 1557 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 1558 MIPS_SYS(sys_sync , 0) 1559 MIPS_SYS(sys_kill , 2) 1560 MIPS_SYS(sys_rename , 2) 1561 MIPS_SYS(sys_mkdir , 2) 1562 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 1563 MIPS_SYS(sys_dup , 1) 1564 MIPS_SYS(sys_pipe , 0) 1565 MIPS_SYS(sys_times , 1) 1566 MIPS_SYS(sys_ni_syscall , 0) 1567 MIPS_SYS(sys_brk , 1) /* 4045 */ 1568 MIPS_SYS(sys_setgid , 1) 1569 MIPS_SYS(sys_getgid , 0) 1570 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 1571 MIPS_SYS(sys_geteuid , 0) 1572 MIPS_SYS(sys_getegid , 0) /* 4050 */ 1573 MIPS_SYS(sys_acct , 0) 1574 MIPS_SYS(sys_umount , 2) 1575 MIPS_SYS(sys_ni_syscall , 0) 1576 MIPS_SYS(sys_ioctl , 3) 1577 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 1578 MIPS_SYS(sys_ni_syscall , 2) 1579 MIPS_SYS(sys_setpgid , 2) 1580 MIPS_SYS(sys_ni_syscall , 0) 1581 MIPS_SYS(sys_olduname , 1) 1582 MIPS_SYS(sys_umask , 1) /* 4060 */ 1583 MIPS_SYS(sys_chroot , 1) 1584 MIPS_SYS(sys_ustat , 2) 1585 MIPS_SYS(sys_dup2 , 2) 1586 MIPS_SYS(sys_getppid , 0) 1587 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 1588 MIPS_SYS(sys_setsid , 0) 1589 MIPS_SYS(sys_sigaction , 3) 1590 MIPS_SYS(sys_sgetmask , 0) 1591 MIPS_SYS(sys_ssetmask , 1) 1592 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 1593 MIPS_SYS(sys_setregid , 2) 1594 MIPS_SYS(sys_sigsuspend , 0) 1595 MIPS_SYS(sys_sigpending , 1) 1596 MIPS_SYS(sys_sethostname , 2) 1597 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 1598 MIPS_SYS(sys_getrlimit , 2) 1599 MIPS_SYS(sys_getrusage , 2) 1600 MIPS_SYS(sys_gettimeofday, 2) 1601 MIPS_SYS(sys_settimeofday, 2) 1602 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 1603 MIPS_SYS(sys_setgroups , 2) 1604 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 1605 MIPS_SYS(sys_symlink , 2) 1606 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 1607 MIPS_SYS(sys_readlink , 3) /* 4085 */ 1608 MIPS_SYS(sys_uselib , 1) 1609 MIPS_SYS(sys_swapon , 2) 1610 MIPS_SYS(sys_reboot , 3) 1611 MIPS_SYS(old_readdir , 3) 1612 MIPS_SYS(old_mmap , 6) /* 4090 */ 1613 MIPS_SYS(sys_munmap , 2) 1614 MIPS_SYS(sys_truncate , 2) 1615 MIPS_SYS(sys_ftruncate , 2) 1616 MIPS_SYS(sys_fchmod , 2) 1617 MIPS_SYS(sys_fchown , 3) /* 4095 */ 1618 MIPS_SYS(sys_getpriority , 2) 1619 MIPS_SYS(sys_setpriority , 3) 1620 MIPS_SYS(sys_ni_syscall , 0) 1621 MIPS_SYS(sys_statfs , 2) 1622 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 1623 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 1624 MIPS_SYS(sys_socketcall , 2) 1625 MIPS_SYS(sys_syslog , 3) 1626 MIPS_SYS(sys_setitimer , 3) 1627 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 1628 MIPS_SYS(sys_newstat , 2) 1629 MIPS_SYS(sys_newlstat , 2) 1630 MIPS_SYS(sys_newfstat , 2) 1631 MIPS_SYS(sys_uname , 1) 1632 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 1633 MIPS_SYS(sys_vhangup , 0) 1634 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 1635 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 1636 MIPS_SYS(sys_wait4 , 4) 1637 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 1638 MIPS_SYS(sys_sysinfo , 1) 1639 MIPS_SYS(sys_ipc , 6) 1640 MIPS_SYS(sys_fsync , 1) 1641 MIPS_SYS(sys_sigreturn , 0) 1642 MIPS_SYS(sys_clone , 6) /* 4120 */ 1643 MIPS_SYS(sys_setdomainname, 2) 1644 MIPS_SYS(sys_newuname , 1) 1645 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 1646 MIPS_SYS(sys_adjtimex , 1) 1647 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 1648 MIPS_SYS(sys_sigprocmask , 3) 1649 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 1650 MIPS_SYS(sys_init_module , 5) 1651 MIPS_SYS(sys_delete_module, 1) 1652 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 1653 MIPS_SYS(sys_quotactl , 0) 1654 MIPS_SYS(sys_getpgid , 1) 1655 MIPS_SYS(sys_fchdir , 1) 1656 MIPS_SYS(sys_bdflush , 2) 1657 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 1658 MIPS_SYS(sys_personality , 1) 1659 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 1660 MIPS_SYS(sys_setfsuid , 1) 1661 MIPS_SYS(sys_setfsgid , 1) 1662 MIPS_SYS(sys_llseek , 5) /* 4140 */ 1663 MIPS_SYS(sys_getdents , 3) 1664 MIPS_SYS(sys_select , 5) 1665 MIPS_SYS(sys_flock , 2) 1666 MIPS_SYS(sys_msync , 3) 1667 MIPS_SYS(sys_readv , 3) /* 4145 */ 1668 MIPS_SYS(sys_writev , 3) 1669 MIPS_SYS(sys_cacheflush , 3) 1670 MIPS_SYS(sys_cachectl , 3) 1671 MIPS_SYS(sys_sysmips , 4) 1672 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 1673 MIPS_SYS(sys_getsid , 1) 1674 MIPS_SYS(sys_fdatasync , 0) 1675 MIPS_SYS(sys_sysctl , 1) 1676 MIPS_SYS(sys_mlock , 2) 1677 MIPS_SYS(sys_munlock , 2) /* 4155 */ 1678 MIPS_SYS(sys_mlockall , 1) 1679 MIPS_SYS(sys_munlockall , 0) 1680 MIPS_SYS(sys_sched_setparam, 2) 1681 MIPS_SYS(sys_sched_getparam, 2) 1682 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 1683 MIPS_SYS(sys_sched_getscheduler, 1) 1684 MIPS_SYS(sys_sched_yield , 0) 1685 MIPS_SYS(sys_sched_get_priority_max, 1) 1686 MIPS_SYS(sys_sched_get_priority_min, 1) 1687 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 1688 MIPS_SYS(sys_nanosleep, 2) 1689 MIPS_SYS(sys_mremap , 4) 1690 MIPS_SYS(sys_accept , 3) 1691 MIPS_SYS(sys_bind , 3) 1692 MIPS_SYS(sys_connect , 3) /* 4170 */ 1693 MIPS_SYS(sys_getpeername , 3) 1694 MIPS_SYS(sys_getsockname , 3) 1695 MIPS_SYS(sys_getsockopt , 5) 1696 MIPS_SYS(sys_listen , 2) 1697 MIPS_SYS(sys_recv , 4) /* 4175 */ 1698 MIPS_SYS(sys_recvfrom , 6) 1699 MIPS_SYS(sys_recvmsg , 3) 1700 MIPS_SYS(sys_send , 4) 1701 MIPS_SYS(sys_sendmsg , 3) 1702 MIPS_SYS(sys_sendto , 6) /* 4180 */ 1703 MIPS_SYS(sys_setsockopt , 5) 1704 MIPS_SYS(sys_shutdown , 2) 1705 MIPS_SYS(sys_socket , 3) 1706 MIPS_SYS(sys_socketpair , 4) 1707 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 1708 MIPS_SYS(sys_getresuid , 3) 1709 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 1710 MIPS_SYS(sys_poll , 3) 1711 MIPS_SYS(sys_nfsservctl , 3) 1712 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 1713 MIPS_SYS(sys_getresgid , 3) 1714 MIPS_SYS(sys_prctl , 5) 1715 MIPS_SYS(sys_rt_sigreturn, 0) 1716 MIPS_SYS(sys_rt_sigaction, 4) 1717 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 1718 MIPS_SYS(sys_rt_sigpending, 2) 1719 MIPS_SYS(sys_rt_sigtimedwait, 4) 1720 MIPS_SYS(sys_rt_sigqueueinfo, 3) 1721 MIPS_SYS(sys_rt_sigsuspend, 0) 1722 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 1723 MIPS_SYS(sys_pwrite64 , 6) 1724 MIPS_SYS(sys_chown , 3) 1725 MIPS_SYS(sys_getcwd , 2) 1726 MIPS_SYS(sys_capget , 2) 1727 MIPS_SYS(sys_capset , 2) /* 4205 */ 1728 MIPS_SYS(sys_sigaltstack , 0) 1729 MIPS_SYS(sys_sendfile , 4) 1730 MIPS_SYS(sys_ni_syscall , 0) 1731 MIPS_SYS(sys_ni_syscall , 0) 1732 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 1733 MIPS_SYS(sys_truncate64 , 4) 1734 MIPS_SYS(sys_ftruncate64 , 4) 1735 MIPS_SYS(sys_stat64 , 2) 1736 MIPS_SYS(sys_lstat64 , 2) 1737 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 1738 MIPS_SYS(sys_pivot_root , 2) 1739 MIPS_SYS(sys_mincore , 3) 1740 MIPS_SYS(sys_madvise , 3) 1741 MIPS_SYS(sys_getdents64 , 3) 1742 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 1743 MIPS_SYS(sys_ni_syscall , 0) 1744 MIPS_SYS(sys_gettid , 0) 1745 MIPS_SYS(sys_readahead , 5) 1746 MIPS_SYS(sys_setxattr , 5) 1747 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 1748 MIPS_SYS(sys_fsetxattr , 5) 1749 MIPS_SYS(sys_getxattr , 4) 1750 MIPS_SYS(sys_lgetxattr , 4) 1751 MIPS_SYS(sys_fgetxattr , 4) 1752 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 1753 MIPS_SYS(sys_llistxattr , 3) 1754 MIPS_SYS(sys_flistxattr , 3) 1755 MIPS_SYS(sys_removexattr , 2) 1756 MIPS_SYS(sys_lremovexattr, 2) 1757 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 1758 MIPS_SYS(sys_tkill , 2) 1759 MIPS_SYS(sys_sendfile64 , 5) 1760 MIPS_SYS(sys_futex , 2) 1761 MIPS_SYS(sys_sched_setaffinity, 3) 1762 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 1763 MIPS_SYS(sys_io_setup , 2) 1764 MIPS_SYS(sys_io_destroy , 1) 1765 MIPS_SYS(sys_io_getevents, 5) 1766 MIPS_SYS(sys_io_submit , 3) 1767 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 1768 MIPS_SYS(sys_exit_group , 1) 1769 MIPS_SYS(sys_lookup_dcookie, 3) 1770 MIPS_SYS(sys_epoll_create, 1) 1771 MIPS_SYS(sys_epoll_ctl , 4) 1772 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 1773 MIPS_SYS(sys_remap_file_pages, 5) 1774 MIPS_SYS(sys_set_tid_address, 1) 1775 MIPS_SYS(sys_restart_syscall, 0) 1776 MIPS_SYS(sys_fadvise64_64, 7) 1777 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 1778 MIPS_SYS(sys_fstatfs64 , 2) 1779 MIPS_SYS(sys_timer_create, 3) 1780 MIPS_SYS(sys_timer_settime, 4) 1781 MIPS_SYS(sys_timer_gettime, 2) 1782 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 1783 MIPS_SYS(sys_timer_delete, 1) 1784 MIPS_SYS(sys_clock_settime, 2) 1785 MIPS_SYS(sys_clock_gettime, 2) 1786 MIPS_SYS(sys_clock_getres, 2) 1787 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 1788 MIPS_SYS(sys_tgkill , 3) 1789 MIPS_SYS(sys_utimes , 2) 1790 MIPS_SYS(sys_mbind , 4) 1791 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 1792 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 1793 MIPS_SYS(sys_mq_open , 4) 1794 MIPS_SYS(sys_mq_unlink , 1) 1795 MIPS_SYS(sys_mq_timedsend, 5) 1796 MIPS_SYS(sys_mq_timedreceive, 5) 1797 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 1798 MIPS_SYS(sys_mq_getsetattr, 3) 1799 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 1800 MIPS_SYS(sys_waitid , 4) 1801 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 1802 MIPS_SYS(sys_add_key , 5) 1803 MIPS_SYS(sys_request_key, 4) 1804 MIPS_SYS(sys_keyctl , 5) 1805 MIPS_SYS(sys_set_thread_area, 1) 1806 MIPS_SYS(sys_inotify_init, 0) 1807 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 1808 MIPS_SYS(sys_inotify_rm_watch, 2) 1809 MIPS_SYS(sys_migrate_pages, 4) 1810 MIPS_SYS(sys_openat, 4) 1811 MIPS_SYS(sys_mkdirat, 3) 1812 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 1813 MIPS_SYS(sys_fchownat, 5) 1814 MIPS_SYS(sys_futimesat, 3) 1815 MIPS_SYS(sys_fstatat64, 4) 1816 MIPS_SYS(sys_unlinkat, 3) 1817 MIPS_SYS(sys_renameat, 4) /* 4295 */ 1818 MIPS_SYS(sys_linkat, 5) 1819 MIPS_SYS(sys_symlinkat, 3) 1820 MIPS_SYS(sys_readlinkat, 4) 1821 MIPS_SYS(sys_fchmodat, 3) 1822 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 1823 MIPS_SYS(sys_pselect6, 6) 1824 MIPS_SYS(sys_ppoll, 5) 1825 MIPS_SYS(sys_unshare, 1) 1826 MIPS_SYS(sys_splice, 4) 1827 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 1828 MIPS_SYS(sys_tee, 4) 1829 MIPS_SYS(sys_vmsplice, 4) 1830 MIPS_SYS(sys_move_pages, 6) 1831 MIPS_SYS(sys_set_robust_list, 2) 1832 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 1833 MIPS_SYS(sys_kexec_load, 4) 1834 MIPS_SYS(sys_getcpu, 3) 1835 MIPS_SYS(sys_epoll_pwait, 6) 1836 MIPS_SYS(sys_ioprio_set, 3) 1837 MIPS_SYS(sys_ioprio_get, 2) 1838 }; 1839 1840 #undef MIPS_SYS 1841 1842 static int do_store_exclusive(CPUMIPSState *env) 1843 { 1844 target_ulong addr; 1845 target_ulong page_addr; 1846 target_ulong val; 1847 int flags; 1848 int segv = 0; 1849 int reg; 1850 int d; 1851 1852 addr = env->CP0_LLAddr; 1853 page_addr = addr & TARGET_PAGE_MASK; 1854 start_exclusive(); 1855 mmap_lock(); 1856 flags = page_get_flags(page_addr); 1857 if ((flags & PAGE_READ) == 0) { 1858 segv = 1; 1859 } else { 1860 reg = env->llreg & 0x1f; 1861 d = (env->llreg & 0x20) != 0; 1862 if (d) { 1863 segv = get_user_s64(val, addr); 1864 } else { 1865 segv = get_user_s32(val, addr); 1866 } 1867 if (!segv) { 1868 if (val != env->llval) { 1869 env->active_tc.gpr[reg] = 0; 1870 } else { 1871 if (d) { 1872 segv = put_user_u64(env->llnewval, addr); 1873 } else { 1874 segv = put_user_u32(env->llnewval, addr); 1875 } 1876 if (!segv) { 1877 env->active_tc.gpr[reg] = 1; 1878 } 1879 } 1880 } 1881 } 1882 env->CP0_LLAddr = -1; 1883 if (!segv) { 1884 env->active_tc.PC += 4; 1885 } 1886 mmap_unlock(); 1887 end_exclusive(); 1888 return segv; 1889 } 1890 1891 void cpu_loop(CPUMIPSState *env) 1892 { 1893 target_siginfo_t info; 1894 int trapnr, ret; 1895 unsigned int syscall_num; 1896 1897 for(;;) { 1898 cpu_exec_start(env); 1899 trapnr = cpu_mips_exec(env); 1900 cpu_exec_end(env); 1901 switch(trapnr) { 1902 case EXCP_SYSCALL: 1903 syscall_num = env->active_tc.gpr[2] - 4000; 1904 env->active_tc.PC += 4; 1905 if (syscall_num >= sizeof(mips_syscall_args)) { 1906 ret = -ENOSYS; 1907 } else { 1908 int nb_args; 1909 abi_ulong sp_reg; 1910 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 1911 1912 nb_args = mips_syscall_args[syscall_num]; 1913 sp_reg = env->active_tc.gpr[29]; 1914 switch (nb_args) { 1915 /* these arguments are taken from the stack */ 1916 /* FIXME - what to do if get_user() fails? */ 1917 case 8: get_user_ual(arg8, sp_reg + 28); 1918 case 7: get_user_ual(arg7, sp_reg + 24); 1919 case 6: get_user_ual(arg6, sp_reg + 20); 1920 case 5: get_user_ual(arg5, sp_reg + 16); 1921 default: 1922 break; 1923 } 1924 ret = do_syscall(env, env->active_tc.gpr[2], 1925 env->active_tc.gpr[4], 1926 env->active_tc.gpr[5], 1927 env->active_tc.gpr[6], 1928 env->active_tc.gpr[7], 1929 arg5, arg6/*, arg7, arg8*/); 1930 } 1931 if (ret == -TARGET_QEMU_ESIGRETURN) { 1932 /* Returning from a successful sigreturn syscall. 1933 Avoid clobbering register state. */ 1934 break; 1935 } 1936 if ((unsigned int)ret >= (unsigned int)(-1133)) { 1937 env->active_tc.gpr[7] = 1; /* error flag */ 1938 ret = -ret; 1939 } else { 1940 env->active_tc.gpr[7] = 0; /* error flag */ 1941 } 1942 env->active_tc.gpr[2] = ret; 1943 break; 1944 case EXCP_TLBL: 1945 case EXCP_TLBS: 1946 info.si_signo = TARGET_SIGSEGV; 1947 info.si_errno = 0; 1948 /* XXX: check env->error_code */ 1949 info.si_code = TARGET_SEGV_MAPERR; 1950 info._sifields._sigfault._addr = env->CP0_BadVAddr; 1951 queue_signal(env, info.si_signo, &info); 1952 break; 1953 case EXCP_CpU: 1954 case EXCP_RI: 1955 info.si_signo = TARGET_SIGILL; 1956 info.si_errno = 0; 1957 info.si_code = 0; 1958 queue_signal(env, info.si_signo, &info); 1959 break; 1960 case EXCP_INTERRUPT: 1961 /* just indicate that signals should be handled asap */ 1962 break; 1963 case EXCP_DEBUG: 1964 { 1965 int sig; 1966 1967 sig = gdb_handlesig (env, TARGET_SIGTRAP); 1968 if (sig) 1969 { 1970 info.si_signo = sig; 1971 info.si_errno = 0; 1972 info.si_code = TARGET_TRAP_BRKPT; 1973 queue_signal(env, info.si_signo, &info); 1974 } 1975 } 1976 break; 1977 case EXCP_SC: 1978 if (do_store_exclusive(env)) { 1979 info.si_signo = TARGET_SIGSEGV; 1980 info.si_errno = 0; 1981 info.si_code = TARGET_SEGV_MAPERR; 1982 info._sifields._sigfault._addr = env->active_tc.PC; 1983 queue_signal(env, info.si_signo, &info); 1984 } 1985 break; 1986 default: 1987 // error: 1988 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 1989 trapnr); 1990 cpu_dump_state(env, stderr, fprintf, 0); 1991 abort(); 1992 } 1993 process_pending_signals(env); 1994 } 1995 } 1996 #endif 1997 1998 #ifdef TARGET_SH4 1999 void cpu_loop (CPUState *env) 2000 { 2001 int trapnr, ret; 2002 target_siginfo_t info; 2003 2004 while (1) { 2005 trapnr = cpu_sh4_exec (env); 2006 2007 switch (trapnr) { 2008 case 0x160: 2009 env->pc += 2; 2010 ret = do_syscall(env, 2011 env->gregs[3], 2012 env->gregs[4], 2013 env->gregs[5], 2014 env->gregs[6], 2015 env->gregs[7], 2016 env->gregs[0], 2017 env->gregs[1]); 2018 env->gregs[0] = ret; 2019 break; 2020 case EXCP_INTERRUPT: 2021 /* just indicate that signals should be handled asap */ 2022 break; 2023 case EXCP_DEBUG: 2024 { 2025 int sig; 2026 2027 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2028 if (sig) 2029 { 2030 info.si_signo = sig; 2031 info.si_errno = 0; 2032 info.si_code = TARGET_TRAP_BRKPT; 2033 queue_signal(env, info.si_signo, &info); 2034 } 2035 } 2036 break; 2037 case 0xa0: 2038 case 0xc0: 2039 info.si_signo = SIGSEGV; 2040 info.si_errno = 0; 2041 info.si_code = TARGET_SEGV_MAPERR; 2042 info._sifields._sigfault._addr = env->tea; 2043 queue_signal(env, info.si_signo, &info); 2044 break; 2045 2046 default: 2047 printf ("Unhandled trap: 0x%x\n", trapnr); 2048 cpu_dump_state(env, stderr, fprintf, 0); 2049 exit (1); 2050 } 2051 process_pending_signals (env); 2052 } 2053 } 2054 #endif 2055 2056 #ifdef TARGET_CRIS 2057 void cpu_loop (CPUState *env) 2058 { 2059 int trapnr, ret; 2060 target_siginfo_t info; 2061 2062 while (1) { 2063 trapnr = cpu_cris_exec (env); 2064 switch (trapnr) { 2065 case 0xaa: 2066 { 2067 info.si_signo = SIGSEGV; 2068 info.si_errno = 0; 2069 /* XXX: check env->error_code */ 2070 info.si_code = TARGET_SEGV_MAPERR; 2071 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 2072 queue_signal(env, info.si_signo, &info); 2073 } 2074 break; 2075 case EXCP_INTERRUPT: 2076 /* just indicate that signals should be handled asap */ 2077 break; 2078 case EXCP_BREAK: 2079 ret = do_syscall(env, 2080 env->regs[9], 2081 env->regs[10], 2082 env->regs[11], 2083 env->regs[12], 2084 env->regs[13], 2085 env->pregs[7], 2086 env->pregs[11]); 2087 env->regs[10] = ret; 2088 break; 2089 case EXCP_DEBUG: 2090 { 2091 int sig; 2092 2093 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2094 if (sig) 2095 { 2096 info.si_signo = sig; 2097 info.si_errno = 0; 2098 info.si_code = TARGET_TRAP_BRKPT; 2099 queue_signal(env, info.si_signo, &info); 2100 } 2101 } 2102 break; 2103 default: 2104 printf ("Unhandled trap: 0x%x\n", trapnr); 2105 cpu_dump_state(env, stderr, fprintf, 0); 2106 exit (1); 2107 } 2108 process_pending_signals (env); 2109 } 2110 } 2111 #endif 2112 2113 #ifdef TARGET_MICROBLAZE 2114 void cpu_loop (CPUState *env) 2115 { 2116 int trapnr, ret; 2117 target_siginfo_t info; 2118 2119 while (1) { 2120 trapnr = cpu_mb_exec (env); 2121 switch (trapnr) { 2122 case 0xaa: 2123 { 2124 info.si_signo = SIGSEGV; 2125 info.si_errno = 0; 2126 /* XXX: check env->error_code */ 2127 info.si_code = TARGET_SEGV_MAPERR; 2128 info._sifields._sigfault._addr = 0; 2129 queue_signal(env, info.si_signo, &info); 2130 } 2131 break; 2132 case EXCP_INTERRUPT: 2133 /* just indicate that signals should be handled asap */ 2134 break; 2135 case EXCP_BREAK: 2136 /* Return address is 4 bytes after the call. */ 2137 env->regs[14] += 4; 2138 ret = do_syscall(env, 2139 env->regs[12], 2140 env->regs[5], 2141 env->regs[6], 2142 env->regs[7], 2143 env->regs[8], 2144 env->regs[9], 2145 env->regs[10]); 2146 env->regs[3] = ret; 2147 env->sregs[SR_PC] = env->regs[14]; 2148 break; 2149 case EXCP_DEBUG: 2150 { 2151 int sig; 2152 2153 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2154 if (sig) 2155 { 2156 info.si_signo = sig; 2157 info.si_errno = 0; 2158 info.si_code = TARGET_TRAP_BRKPT; 2159 queue_signal(env, info.si_signo, &info); 2160 } 2161 } 2162 break; 2163 default: 2164 printf ("Unhandled trap: 0x%x\n", trapnr); 2165 cpu_dump_state(env, stderr, fprintf, 0); 2166 exit (1); 2167 } 2168 process_pending_signals (env); 2169 } 2170 } 2171 #endif 2172 2173 #ifdef TARGET_M68K 2174 2175 void cpu_loop(CPUM68KState *env) 2176 { 2177 int trapnr; 2178 unsigned int n; 2179 target_siginfo_t info; 2180 TaskState *ts = env->opaque; 2181 2182 for(;;) { 2183 trapnr = cpu_m68k_exec(env); 2184 switch(trapnr) { 2185 case EXCP_ILLEGAL: 2186 { 2187 if (ts->sim_syscalls) { 2188 uint16_t nr; 2189 nr = lduw(env->pc + 2); 2190 env->pc += 4; 2191 do_m68k_simcall(env, nr); 2192 } else { 2193 goto do_sigill; 2194 } 2195 } 2196 break; 2197 case EXCP_HALT_INSN: 2198 /* Semihosing syscall. */ 2199 env->pc += 4; 2200 do_m68k_semihosting(env, env->dregs[0]); 2201 break; 2202 case EXCP_LINEA: 2203 case EXCP_LINEF: 2204 case EXCP_UNSUPPORTED: 2205 do_sigill: 2206 info.si_signo = SIGILL; 2207 info.si_errno = 0; 2208 info.si_code = TARGET_ILL_ILLOPN; 2209 info._sifields._sigfault._addr = env->pc; 2210 queue_signal(env, info.si_signo, &info); 2211 break; 2212 case EXCP_TRAP0: 2213 { 2214 ts->sim_syscalls = 0; 2215 n = env->dregs[0]; 2216 env->pc += 2; 2217 env->dregs[0] = do_syscall(env, 2218 n, 2219 env->dregs[1], 2220 env->dregs[2], 2221 env->dregs[3], 2222 env->dregs[4], 2223 env->dregs[5], 2224 env->aregs[0]); 2225 } 2226 break; 2227 case EXCP_INTERRUPT: 2228 /* just indicate that signals should be handled asap */ 2229 break; 2230 case EXCP_ACCESS: 2231 { 2232 info.si_signo = SIGSEGV; 2233 info.si_errno = 0; 2234 /* XXX: check env->error_code */ 2235 info.si_code = TARGET_SEGV_MAPERR; 2236 info._sifields._sigfault._addr = env->mmu.ar; 2237 queue_signal(env, info.si_signo, &info); 2238 } 2239 break; 2240 case EXCP_DEBUG: 2241 { 2242 int sig; 2243 2244 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2245 if (sig) 2246 { 2247 info.si_signo = sig; 2248 info.si_errno = 0; 2249 info.si_code = TARGET_TRAP_BRKPT; 2250 queue_signal(env, info.si_signo, &info); 2251 } 2252 } 2253 break; 2254 default: 2255 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 2256 trapnr); 2257 cpu_dump_state(env, stderr, fprintf, 0); 2258 abort(); 2259 } 2260 process_pending_signals(env); 2261 } 2262 } 2263 #endif /* TARGET_M68K */ 2264 2265 #ifdef TARGET_ALPHA 2266 void cpu_loop (CPUState *env) 2267 { 2268 int trapnr; 2269 target_siginfo_t info; 2270 2271 while (1) { 2272 trapnr = cpu_alpha_exec (env); 2273 2274 switch (trapnr) { 2275 case EXCP_RESET: 2276 fprintf(stderr, "Reset requested. Exit\n"); 2277 exit(1); 2278 break; 2279 case EXCP_MCHK: 2280 fprintf(stderr, "Machine check exception. Exit\n"); 2281 exit(1); 2282 break; 2283 case EXCP_ARITH: 2284 fprintf(stderr, "Arithmetic trap.\n"); 2285 exit(1); 2286 break; 2287 case EXCP_HW_INTERRUPT: 2288 fprintf(stderr, "External interrupt. Exit\n"); 2289 exit(1); 2290 break; 2291 case EXCP_DFAULT: 2292 fprintf(stderr, "MMU data fault\n"); 2293 exit(1); 2294 break; 2295 case EXCP_DTB_MISS_PAL: 2296 fprintf(stderr, "MMU data TLB miss in PALcode\n"); 2297 exit(1); 2298 break; 2299 case EXCP_ITB_MISS: 2300 fprintf(stderr, "MMU instruction TLB miss\n"); 2301 exit(1); 2302 break; 2303 case EXCP_ITB_ACV: 2304 fprintf(stderr, "MMU instruction access violation\n"); 2305 exit(1); 2306 break; 2307 case EXCP_DTB_MISS_NATIVE: 2308 fprintf(stderr, "MMU data TLB miss\n"); 2309 exit(1); 2310 break; 2311 case EXCP_UNALIGN: 2312 fprintf(stderr, "Unaligned access\n"); 2313 exit(1); 2314 break; 2315 case EXCP_OPCDEC: 2316 fprintf(stderr, "Invalid instruction\n"); 2317 exit(1); 2318 break; 2319 case EXCP_FEN: 2320 fprintf(stderr, "Floating-point not allowed\n"); 2321 exit(1); 2322 break; 2323 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1): 2324 call_pal(env, (trapnr >> 6) | 0x80); 2325 break; 2326 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1): 2327 fprintf(stderr, "Privileged call to PALcode\n"); 2328 exit(1); 2329 break; 2330 case EXCP_DEBUG: 2331 { 2332 int sig; 2333 2334 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2335 if (sig) 2336 { 2337 info.si_signo = sig; 2338 info.si_errno = 0; 2339 info.si_code = TARGET_TRAP_BRKPT; 2340 queue_signal(env, info.si_signo, &info); 2341 } 2342 } 2343 break; 2344 default: 2345 printf ("Unhandled trap: 0x%x\n", trapnr); 2346 cpu_dump_state(env, stderr, fprintf, 0); 2347 exit (1); 2348 } 2349 process_pending_signals (env); 2350 } 2351 } 2352 #endif /* TARGET_ALPHA */ 2353 2354 static void usage(void) 2355 { 2356 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n" 2357 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n" 2358 "Linux CPU emulator (compiled for %s emulation)\n" 2359 "\n" 2360 "Standard options:\n" 2361 "-h print this help\n" 2362 "-g port wait gdb connection to port\n" 2363 "-L path set the elf interpreter prefix (default=%s)\n" 2364 "-s size set the stack size in bytes (default=%ld)\n" 2365 "-cpu model select CPU (-cpu ? for list)\n" 2366 "-drop-ld-preload drop LD_PRELOAD for target process\n" 2367 "-E var=value sets/modifies targets environment variable(s)\n" 2368 "-U var unsets targets environment variable(s)\n" 2369 "-0 argv0 forces target process argv[0] to be argv0\n" 2370 #if defined(CONFIG_USE_GUEST_BASE) 2371 "-B address set guest_base address to address\n" 2372 #endif 2373 "\n" 2374 "Debug options:\n" 2375 "-d options activate log (logfile=%s)\n" 2376 "-p pagesize set the host page size to 'pagesize'\n" 2377 "-singlestep always run in singlestep mode\n" 2378 "-strace log system calls\n" 2379 "\n" 2380 "Environment variables:\n" 2381 "QEMU_STRACE Print system calls and arguments similar to the\n" 2382 " 'strace' program. Enable by setting to any value.\n" 2383 "You can use -E and -U options to set/unset environment variables\n" 2384 "for target process. It is possible to provide several variables\n" 2385 "by repeating the option. For example:\n" 2386 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" 2387 "Note that if you provide several changes to single variable\n" 2388 "last change will stay in effect.\n" 2389 , 2390 TARGET_ARCH, 2391 interp_prefix, 2392 x86_stack_size, 2393 DEBUG_LOGFILE); 2394 exit(1); 2395 } 2396 2397 THREAD CPUState *thread_env; 2398 2399 void task_settid(TaskState *ts) 2400 { 2401 if (ts->ts_tid == 0) { 2402 #ifdef CONFIG_USE_NPTL 2403 ts->ts_tid = (pid_t)syscall(SYS_gettid); 2404 #else 2405 /* when no threads are used, tid becomes pid */ 2406 ts->ts_tid = getpid(); 2407 #endif 2408 } 2409 } 2410 2411 void stop_all_tasks(void) 2412 { 2413 /* 2414 * We trust that when using NPTL, start_exclusive() 2415 * handles thread stopping correctly. 2416 */ 2417 start_exclusive(); 2418 } 2419 2420 /* Assumes contents are already zeroed. */ 2421 void init_task_state(TaskState *ts) 2422 { 2423 int i; 2424 2425 ts->used = 1; 2426 ts->first_free = ts->sigqueue_table; 2427 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { 2428 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; 2429 } 2430 ts->sigqueue_table[i].next = NULL; 2431 } 2432 2433 int main(int argc, char **argv, char **envp) 2434 { 2435 const char *filename; 2436 const char *cpu_model; 2437 struct target_pt_regs regs1, *regs = ®s1; 2438 struct image_info info1, *info = &info1; 2439 struct linux_binprm bprm; 2440 TaskState ts1, *ts = &ts1; 2441 CPUState *env; 2442 int optind; 2443 const char *r; 2444 int gdbstub_port = 0; 2445 char **target_environ, **wrk; 2446 char **target_argv; 2447 int target_argc; 2448 envlist_t *envlist = NULL; 2449 const char *argv0 = NULL; 2450 int i; 2451 int ret; 2452 2453 if (argc <= 1) 2454 usage(); 2455 2456 qemu_cache_utils_init(envp); 2457 2458 /* init debug */ 2459 cpu_set_log_filename(DEBUG_LOGFILE); 2460 2461 if ((envlist = envlist_create()) == NULL) { 2462 (void) fprintf(stderr, "Unable to allocate envlist\n"); 2463 exit(1); 2464 } 2465 2466 /* add current environment into the list */ 2467 for (wrk = environ; *wrk != NULL; wrk++) { 2468 (void) envlist_setenv(envlist, *wrk); 2469 } 2470 2471 cpu_model = NULL; 2472 optind = 1; 2473 for(;;) { 2474 if (optind >= argc) 2475 break; 2476 r = argv[optind]; 2477 if (r[0] != '-') 2478 break; 2479 optind++; 2480 r++; 2481 if (!strcmp(r, "-")) { 2482 break; 2483 } else if (!strcmp(r, "d")) { 2484 int mask; 2485 const CPULogItem *item; 2486 2487 if (optind >= argc) 2488 break; 2489 2490 r = argv[optind++]; 2491 mask = cpu_str_to_log_mask(r); 2492 if (!mask) { 2493 printf("Log items (comma separated):\n"); 2494 for(item = cpu_log_items; item->mask != 0; item++) { 2495 printf("%-10s %s\n", item->name, item->help); 2496 } 2497 exit(1); 2498 } 2499 cpu_set_log(mask); 2500 } else if (!strcmp(r, "E")) { 2501 r = argv[optind++]; 2502 if (envlist_setenv(envlist, r) != 0) 2503 usage(); 2504 } else if (!strcmp(r, "U")) { 2505 r = argv[optind++]; 2506 if (envlist_unsetenv(envlist, r) != 0) 2507 usage(); 2508 } else if (!strcmp(r, "0")) { 2509 r = argv[optind++]; 2510 argv0 = r; 2511 } else if (!strcmp(r, "s")) { 2512 if (optind >= argc) 2513 break; 2514 r = argv[optind++]; 2515 x86_stack_size = strtol(r, (char **)&r, 0); 2516 if (x86_stack_size <= 0) 2517 usage(); 2518 if (*r == 'M') 2519 x86_stack_size *= 1024 * 1024; 2520 else if (*r == 'k' || *r == 'K') 2521 x86_stack_size *= 1024; 2522 } else if (!strcmp(r, "L")) { 2523 interp_prefix = argv[optind++]; 2524 } else if (!strcmp(r, "p")) { 2525 if (optind >= argc) 2526 break; 2527 qemu_host_page_size = atoi(argv[optind++]); 2528 if (qemu_host_page_size == 0 || 2529 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 2530 fprintf(stderr, "page size must be a power of two\n"); 2531 exit(1); 2532 } 2533 } else if (!strcmp(r, "g")) { 2534 if (optind >= argc) 2535 break; 2536 gdbstub_port = atoi(argv[optind++]); 2537 } else if (!strcmp(r, "r")) { 2538 qemu_uname_release = argv[optind++]; 2539 } else if (!strcmp(r, "cpu")) { 2540 cpu_model = argv[optind++]; 2541 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) { 2542 /* XXX: implement xxx_cpu_list for targets that still miss it */ 2543 #if defined(cpu_list) 2544 cpu_list(stdout, &fprintf); 2545 #endif 2546 exit(1); 2547 } 2548 #if defined(CONFIG_USE_GUEST_BASE) 2549 } else if (!strcmp(r, "B")) { 2550 guest_base = strtol(argv[optind++], NULL, 0); 2551 have_guest_base = 1; 2552 #endif 2553 } else if (!strcmp(r, "drop-ld-preload")) { 2554 (void) envlist_unsetenv(envlist, "LD_PRELOAD"); 2555 } else if (!strcmp(r, "singlestep")) { 2556 singlestep = 1; 2557 } else if (!strcmp(r, "strace")) { 2558 do_strace = 1; 2559 } else 2560 { 2561 usage(); 2562 } 2563 } 2564 if (optind >= argc) 2565 usage(); 2566 filename = argv[optind]; 2567 exec_path = argv[optind]; 2568 2569 /* Zero out regs */ 2570 memset(regs, 0, sizeof(struct target_pt_regs)); 2571 2572 /* Zero out image_info */ 2573 memset(info, 0, sizeof(struct image_info)); 2574 2575 memset(&bprm, 0, sizeof (bprm)); 2576 2577 /* Scan interp_prefix dir for replacement files. */ 2578 init_paths(interp_prefix); 2579 2580 if (cpu_model == NULL) { 2581 #if defined(TARGET_I386) 2582 #ifdef TARGET_X86_64 2583 cpu_model = "qemu64"; 2584 #else 2585 cpu_model = "qemu32"; 2586 #endif 2587 #elif defined(TARGET_ARM) 2588 cpu_model = "any"; 2589 #elif defined(TARGET_M68K) 2590 cpu_model = "any"; 2591 #elif defined(TARGET_SPARC) 2592 #ifdef TARGET_SPARC64 2593 cpu_model = "TI UltraSparc II"; 2594 #else 2595 cpu_model = "Fujitsu MB86904"; 2596 #endif 2597 #elif defined(TARGET_MIPS) 2598 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 2599 cpu_model = "20Kc"; 2600 #else 2601 cpu_model = "24Kf"; 2602 #endif 2603 #elif defined(TARGET_PPC) 2604 #ifdef TARGET_PPC64 2605 cpu_model = "970"; 2606 #else 2607 cpu_model = "750"; 2608 #endif 2609 #else 2610 cpu_model = "any"; 2611 #endif 2612 } 2613 cpu_exec_init_all(0); 2614 /* NOTE: we need to init the CPU at this stage to get 2615 qemu_host_page_size */ 2616 env = cpu_init(cpu_model); 2617 if (!env) { 2618 fprintf(stderr, "Unable to find CPU definition\n"); 2619 exit(1); 2620 } 2621 thread_env = env; 2622 2623 if (getenv("QEMU_STRACE")) { 2624 do_strace = 1; 2625 } 2626 2627 target_environ = envlist_to_environ(envlist, NULL); 2628 envlist_free(envlist); 2629 2630 #if defined(CONFIG_USE_GUEST_BASE) 2631 /* 2632 * Now that page sizes are configured in cpu_init() we can do 2633 * proper page alignment for guest_base. 2634 */ 2635 guest_base = HOST_PAGE_ALIGN(guest_base); 2636 2637 /* 2638 * Read in mmap_min_addr kernel parameter. This value is used 2639 * When loading the ELF image to determine whether guest_base 2640 * is needed. 2641 * 2642 * When user has explicitly set the quest base, we skip this 2643 * test. 2644 */ 2645 if (!have_guest_base) { 2646 FILE *fp; 2647 2648 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { 2649 unsigned long tmp; 2650 if (fscanf(fp, "%lu", &tmp) == 1) { 2651 mmap_min_addr = tmp; 2652 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr); 2653 } 2654 fclose(fp); 2655 } 2656 } 2657 #endif /* CONFIG_USE_GUEST_BASE */ 2658 2659 /* 2660 * Prepare copy of argv vector for target. 2661 */ 2662 target_argc = argc - optind; 2663 target_argv = calloc(target_argc + 1, sizeof (char *)); 2664 if (target_argv == NULL) { 2665 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); 2666 exit(1); 2667 } 2668 2669 /* 2670 * If argv0 is specified (using '-0' switch) we replace 2671 * argv[0] pointer with the given one. 2672 */ 2673 i = 0; 2674 if (argv0 != NULL) { 2675 target_argv[i++] = strdup(argv0); 2676 } 2677 for (; i < target_argc; i++) { 2678 target_argv[i] = strdup(argv[optind + i]); 2679 } 2680 target_argv[target_argc] = NULL; 2681 2682 memset(ts, 0, sizeof(TaskState)); 2683 init_task_state(ts); 2684 /* build Task State */ 2685 ts->info = info; 2686 ts->bprm = &bprm; 2687 env->opaque = ts; 2688 task_settid(ts); 2689 2690 ret = loader_exec(filename, target_argv, target_environ, regs, 2691 info, &bprm); 2692 if (ret != 0) { 2693 printf("Error %d while loading %s\n", ret, filename); 2694 _exit(1); 2695 } 2696 2697 for (i = 0; i < target_argc; i++) { 2698 free(target_argv[i]); 2699 } 2700 free(target_argv); 2701 2702 for (wrk = target_environ; *wrk; wrk++) { 2703 free(*wrk); 2704 } 2705 2706 free(target_environ); 2707 2708 if (qemu_log_enabled()) { 2709 #if defined(CONFIG_USE_GUEST_BASE) 2710 qemu_log("guest_base 0x%lx\n", guest_base); 2711 #endif 2712 log_page_dump(); 2713 2714 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 2715 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 2716 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", 2717 info->start_code); 2718 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", 2719 info->start_data); 2720 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 2721 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", 2722 info->start_stack); 2723 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 2724 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 2725 } 2726 2727 target_set_brk(info->brk); 2728 syscall_init(); 2729 signal_init(); 2730 2731 #if defined(TARGET_I386) 2732 cpu_x86_set_cpl(env, 3); 2733 2734 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 2735 env->hflags |= HF_PE_MASK; 2736 if (env->cpuid_features & CPUID_SSE) { 2737 env->cr[4] |= CR4_OSFXSR_MASK; 2738 env->hflags |= HF_OSFXSR_MASK; 2739 } 2740 #ifndef TARGET_ABI32 2741 /* enable 64 bit mode if possible */ 2742 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) { 2743 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 2744 exit(1); 2745 } 2746 env->cr[4] |= CR4_PAE_MASK; 2747 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 2748 env->hflags |= HF_LMA_MASK; 2749 #endif 2750 2751 /* flags setup : we activate the IRQs by default as in user mode */ 2752 env->eflags |= IF_MASK; 2753 2754 /* linux register setup */ 2755 #ifndef TARGET_ABI32 2756 env->regs[R_EAX] = regs->rax; 2757 env->regs[R_EBX] = regs->rbx; 2758 env->regs[R_ECX] = regs->rcx; 2759 env->regs[R_EDX] = regs->rdx; 2760 env->regs[R_ESI] = regs->rsi; 2761 env->regs[R_EDI] = regs->rdi; 2762 env->regs[R_EBP] = regs->rbp; 2763 env->regs[R_ESP] = regs->rsp; 2764 env->eip = regs->rip; 2765 #else 2766 env->regs[R_EAX] = regs->eax; 2767 env->regs[R_EBX] = regs->ebx; 2768 env->regs[R_ECX] = regs->ecx; 2769 env->regs[R_EDX] = regs->edx; 2770 env->regs[R_ESI] = regs->esi; 2771 env->regs[R_EDI] = regs->edi; 2772 env->regs[R_EBP] = regs->ebp; 2773 env->regs[R_ESP] = regs->esp; 2774 env->eip = regs->eip; 2775 #endif 2776 2777 /* linux interrupt setup */ 2778 #ifndef TARGET_ABI32 2779 env->idt.limit = 511; 2780 #else 2781 env->idt.limit = 255; 2782 #endif 2783 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 2784 PROT_READ|PROT_WRITE, 2785 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 2786 idt_table = g2h(env->idt.base); 2787 set_idt(0, 0); 2788 set_idt(1, 0); 2789 set_idt(2, 0); 2790 set_idt(3, 3); 2791 set_idt(4, 3); 2792 set_idt(5, 0); 2793 set_idt(6, 0); 2794 set_idt(7, 0); 2795 set_idt(8, 0); 2796 set_idt(9, 0); 2797 set_idt(10, 0); 2798 set_idt(11, 0); 2799 set_idt(12, 0); 2800 set_idt(13, 0); 2801 set_idt(14, 0); 2802 set_idt(15, 0); 2803 set_idt(16, 0); 2804 set_idt(17, 0); 2805 set_idt(18, 0); 2806 set_idt(19, 0); 2807 set_idt(0x80, 3); 2808 2809 /* linux segment setup */ 2810 { 2811 uint64_t *gdt_table; 2812 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 2813 PROT_READ|PROT_WRITE, 2814 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 2815 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 2816 gdt_table = g2h(env->gdt.base); 2817 #ifdef TARGET_ABI32 2818 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 2819 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 2820 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 2821 #else 2822 /* 64 bit code segment */ 2823 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 2824 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 2825 DESC_L_MASK | 2826 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 2827 #endif 2828 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 2829 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 2830 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 2831 } 2832 cpu_x86_load_seg(env, R_CS, __USER_CS); 2833 cpu_x86_load_seg(env, R_SS, __USER_DS); 2834 #ifdef TARGET_ABI32 2835 cpu_x86_load_seg(env, R_DS, __USER_DS); 2836 cpu_x86_load_seg(env, R_ES, __USER_DS); 2837 cpu_x86_load_seg(env, R_FS, __USER_DS); 2838 cpu_x86_load_seg(env, R_GS, __USER_DS); 2839 /* This hack makes Wine work... */ 2840 env->segs[R_FS].selector = 0; 2841 #else 2842 cpu_x86_load_seg(env, R_DS, 0); 2843 cpu_x86_load_seg(env, R_ES, 0); 2844 cpu_x86_load_seg(env, R_FS, 0); 2845 cpu_x86_load_seg(env, R_GS, 0); 2846 #endif 2847 #elif defined(TARGET_ARM) 2848 { 2849 int i; 2850 cpsr_write(env, regs->uregs[16], 0xffffffff); 2851 for(i = 0; i < 16; i++) { 2852 env->regs[i] = regs->uregs[i]; 2853 } 2854 } 2855 #elif defined(TARGET_SPARC) 2856 { 2857 int i; 2858 env->pc = regs->pc; 2859 env->npc = regs->npc; 2860 env->y = regs->y; 2861 for(i = 0; i < 8; i++) 2862 env->gregs[i] = regs->u_regs[i]; 2863 for(i = 0; i < 8; i++) 2864 env->regwptr[i] = regs->u_regs[i + 8]; 2865 } 2866 #elif defined(TARGET_PPC) 2867 { 2868 int i; 2869 2870 #if defined(TARGET_PPC64) 2871 #if defined(TARGET_ABI32) 2872 env->msr &= ~((target_ulong)1 << MSR_SF); 2873 #else 2874 env->msr |= (target_ulong)1 << MSR_SF; 2875 #endif 2876 #endif 2877 env->nip = regs->nip; 2878 for(i = 0; i < 32; i++) { 2879 env->gpr[i] = regs->gpr[i]; 2880 } 2881 } 2882 #elif defined(TARGET_M68K) 2883 { 2884 env->pc = regs->pc; 2885 env->dregs[0] = regs->d0; 2886 env->dregs[1] = regs->d1; 2887 env->dregs[2] = regs->d2; 2888 env->dregs[3] = regs->d3; 2889 env->dregs[4] = regs->d4; 2890 env->dregs[5] = regs->d5; 2891 env->dregs[6] = regs->d6; 2892 env->dregs[7] = regs->d7; 2893 env->aregs[0] = regs->a0; 2894 env->aregs[1] = regs->a1; 2895 env->aregs[2] = regs->a2; 2896 env->aregs[3] = regs->a3; 2897 env->aregs[4] = regs->a4; 2898 env->aregs[5] = regs->a5; 2899 env->aregs[6] = regs->a6; 2900 env->aregs[7] = regs->usp; 2901 env->sr = regs->sr; 2902 ts->sim_syscalls = 1; 2903 } 2904 #elif defined(TARGET_MICROBLAZE) 2905 { 2906 env->regs[0] = regs->r0; 2907 env->regs[1] = regs->r1; 2908 env->regs[2] = regs->r2; 2909 env->regs[3] = regs->r3; 2910 env->regs[4] = regs->r4; 2911 env->regs[5] = regs->r5; 2912 env->regs[6] = regs->r6; 2913 env->regs[7] = regs->r7; 2914 env->regs[8] = regs->r8; 2915 env->regs[9] = regs->r9; 2916 env->regs[10] = regs->r10; 2917 env->regs[11] = regs->r11; 2918 env->regs[12] = regs->r12; 2919 env->regs[13] = regs->r13; 2920 env->regs[14] = regs->r14; 2921 env->regs[15] = regs->r15; 2922 env->regs[16] = regs->r16; 2923 env->regs[17] = regs->r17; 2924 env->regs[18] = regs->r18; 2925 env->regs[19] = regs->r19; 2926 env->regs[20] = regs->r20; 2927 env->regs[21] = regs->r21; 2928 env->regs[22] = regs->r22; 2929 env->regs[23] = regs->r23; 2930 env->regs[24] = regs->r24; 2931 env->regs[25] = regs->r25; 2932 env->regs[26] = regs->r26; 2933 env->regs[27] = regs->r27; 2934 env->regs[28] = regs->r28; 2935 env->regs[29] = regs->r29; 2936 env->regs[30] = regs->r30; 2937 env->regs[31] = regs->r31; 2938 env->sregs[SR_PC] = regs->pc; 2939 } 2940 #elif defined(TARGET_MIPS) 2941 { 2942 int i; 2943 2944 for(i = 0; i < 32; i++) { 2945 env->active_tc.gpr[i] = regs->regs[i]; 2946 } 2947 env->active_tc.PC = regs->cp0_epc; 2948 } 2949 #elif defined(TARGET_SH4) 2950 { 2951 int i; 2952 2953 for(i = 0; i < 16; i++) { 2954 env->gregs[i] = regs->regs[i]; 2955 } 2956 env->pc = regs->pc; 2957 } 2958 #elif defined(TARGET_ALPHA) 2959 { 2960 int i; 2961 2962 for(i = 0; i < 28; i++) { 2963 env->ir[i] = ((abi_ulong *)regs)[i]; 2964 } 2965 env->ipr[IPR_USP] = regs->usp; 2966 env->ir[30] = regs->usp; 2967 env->pc = regs->pc; 2968 env->unique = regs->unique; 2969 } 2970 #elif defined(TARGET_CRIS) 2971 { 2972 env->regs[0] = regs->r0; 2973 env->regs[1] = regs->r1; 2974 env->regs[2] = regs->r2; 2975 env->regs[3] = regs->r3; 2976 env->regs[4] = regs->r4; 2977 env->regs[5] = regs->r5; 2978 env->regs[6] = regs->r6; 2979 env->regs[7] = regs->r7; 2980 env->regs[8] = regs->r8; 2981 env->regs[9] = regs->r9; 2982 env->regs[10] = regs->r10; 2983 env->regs[11] = regs->r11; 2984 env->regs[12] = regs->r12; 2985 env->regs[13] = regs->r13; 2986 env->regs[14] = info->start_stack; 2987 env->regs[15] = regs->acr; 2988 env->pc = regs->erp; 2989 } 2990 #else 2991 #error unsupported target CPU 2992 #endif 2993 2994 #if defined(TARGET_ARM) || defined(TARGET_M68K) 2995 ts->stack_base = info->start_stack; 2996 ts->heap_base = info->brk; 2997 /* This will be filled in on the first SYS_HEAPINFO call. */ 2998 ts->heap_limit = 0; 2999 #endif 3000 3001 if (gdbstub_port) { 3002 gdbserver_start (gdbstub_port); 3003 gdb_handlesig(env, 0); 3004 } 3005 cpu_loop(env); 3006 /* never exits */ 3007 return 0; 3008 } 3009