1 /* 2 * host-signal.h: signal info dependent on the host architecture 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2021 Linaro Limited 6 * 7 * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. 8 * See the COPYING file in the top-level directory. 9 */ 10 11 #ifndef RISCV_HOST_SIGNAL_H 12 #define RISCV_HOST_SIGNAL_H 13 14 static inline uintptr_t host_signal_pc(ucontext_t *uc) 15 { 16 return uc->uc_mcontext.__gregs[REG_PC]; 17 } 18 19 static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) 20 { 21 uc->uc_mcontext.__gregs[REG_PC] = pc; 22 } 23 24 static inline void *host_signal_mask(ucontext_t *uc) 25 { 26 return &uc->uc_sigmask; 27 } 28 29 static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) 30 { 31 /* 32 * Detect store by reading the instruction at the program counter. 33 * Do not read more than 16 bits, because we have not yet determined 34 * the size of the instruction. 35 */ 36 const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc); 37 uint16_t insn = pinsn[0]; 38 39 /* 16-bit instructions */ 40 switch (insn & 0xe003) { 41 case 0xa000: /* c.fsd */ 42 case 0xc000: /* c.sw */ 43 case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */ 44 case 0xa002: /* c.fsdsp */ 45 case 0xc002: /* c.swsp */ 46 case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */ 47 return true; 48 } 49 50 /* 32-bit instructions, major opcodes */ 51 switch (insn & 0x7f) { 52 case 0x23: /* store */ 53 case 0x27: /* store-fp */ 54 return true; 55 case 0x2f: /* amo */ 56 /* 57 * The AMO function code is in bits 25-31, unread as yet. 58 * The AMO functions are LR (read), SC (write), and the 59 * rest are all read-modify-write. 60 */ 61 insn = pinsn[1]; 62 return (insn >> 11) != 2; /* LR */ 63 } 64 65 return false; 66 } 67 68 #endif 69