1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu.h" 22 #include "user-internals.h" 23 #include "elf.h" 24 #include "user/cpu_loop.h" 25 #include "signal-common.h" 26 #include "semihosting/common-semi.h" 27 #include "exec/page-protection.h" 28 #include "user/page-protection.h" 29 #include "target/arm/syndrome.h" 30 31 #define get_user_code_u32(x, gaddr, env) \ 32 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 33 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 34 (x) = bswap32(x); \ 35 } \ 36 __r; \ 37 }) 38 39 #define get_user_code_u16(x, gaddr, env) \ 40 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 41 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 42 (x) = bswap16(x); \ 43 } \ 44 __r; \ 45 }) 46 47 #define get_user_data_u32(x, gaddr, env) \ 48 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 49 if (!__r && arm_cpu_bswap_data(env)) { \ 50 (x) = bswap32(x); \ 51 } \ 52 __r; \ 53 }) 54 55 #define get_user_data_u16(x, gaddr, env) \ 56 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 57 if (!__r && arm_cpu_bswap_data(env)) { \ 58 (x) = bswap16(x); \ 59 } \ 60 __r; \ 61 }) 62 63 #define put_user_data_u32(x, gaddr, env) \ 64 ({ typeof(x) __x = (x); \ 65 if (arm_cpu_bswap_data(env)) { \ 66 __x = bswap32(__x); \ 67 } \ 68 put_user_u32(__x, (gaddr)); \ 69 }) 70 71 #define put_user_data_u16(x, gaddr, env) \ 72 ({ typeof(x) __x = (x); \ 73 if (arm_cpu_bswap_data(env)) { \ 74 __x = bswap16(__x); \ 75 } \ 76 put_user_u16(__x, (gaddr)); \ 77 }) 78 79 /* 80 * Similar to code in accel/tcg/user-exec.c, but outside the execution loop. 81 * Must be called with mmap_lock. 82 * We get the PC of the entry address - which is as good as anything, 83 * on a real kernel what you get depends on which mode it uses. 84 */ 85 static void *atomic_mmu_lookup(CPUArchState *env, uint32_t addr, int size) 86 { 87 int need_flags = PAGE_READ | PAGE_WRITE_ORG | PAGE_VALID; 88 int page_flags; 89 90 /* Enforce guest required alignment. */ 91 if (unlikely(addr & (size - 1))) { 92 force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr); 93 return NULL; 94 } 95 96 page_flags = page_get_flags(addr); 97 if (unlikely((page_flags & need_flags) != need_flags)) { 98 force_sig_fault(TARGET_SIGSEGV, 99 page_flags & PAGE_VALID ? 100 TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr); 101 return NULL; 102 } 103 104 return g2h(env_cpu(env), addr); 105 } 106 107 /* 108 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst 109 * Input: 110 * r0 = oldval 111 * r1 = newval 112 * r2 = pointer to target value 113 * 114 * Output: 115 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 116 * C set if *ptr was changed, clear if no exchange happened 117 */ 118 static void arm_kernel_cmpxchg32_helper(CPUARMState *env) 119 { 120 uint32_t oldval, newval, val, addr, cpsr, *host_addr; 121 122 /* Swap if host != guest endianness, for the host cmpxchg below */ 123 oldval = tswap32(env->regs[0]); 124 newval = tswap32(env->regs[1]); 125 addr = env->regs[2]; 126 127 mmap_lock(); 128 host_addr = atomic_mmu_lookup(env, addr, 4); 129 if (!host_addr) { 130 mmap_unlock(); 131 return; 132 } 133 134 val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval); 135 mmap_unlock(); 136 137 cpsr = (val == oldval) * CPSR_C; 138 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 139 env->regs[0] = cpsr ? 0 : -1; 140 } 141 142 /* 143 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst 144 * Input: 145 * r0 = pointer to oldval 146 * r1 = pointer to newval 147 * r2 = pointer to target value 148 * 149 * Output: 150 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 151 * C set if *ptr was changed, clear if no exchange happened 152 * 153 * Note segv's in kernel helpers are a bit tricky, we can set the 154 * data address sensibly but the PC address is just the entry point. 155 */ 156 static void arm_kernel_cmpxchg64_helper(CPUARMState *env) 157 { 158 uint64_t oldval, newval, val; 159 uint32_t addr, cpsr; 160 uint64_t *host_addr; 161 162 addr = env->regs[0]; 163 if (get_user_u64(oldval, addr)) { 164 goto segv; 165 } 166 167 addr = env->regs[1]; 168 if (get_user_u64(newval, addr)) { 169 goto segv; 170 } 171 172 mmap_lock(); 173 addr = env->regs[2]; 174 host_addr = atomic_mmu_lookup(env, addr, 8); 175 if (!host_addr) { 176 mmap_unlock(); 177 return; 178 } 179 180 /* Swap if host != guest endianness, for the host cmpxchg below */ 181 oldval = tswap64(oldval); 182 newval = tswap64(newval); 183 184 #ifdef CONFIG_ATOMIC64 185 val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval); 186 cpsr = (val == oldval) * CPSR_C; 187 #else 188 /* 189 * This only works between threads, not between processes, but since 190 * the host has no 64-bit cmpxchg, it is the best that we can do. 191 */ 192 start_exclusive(); 193 val = *host_addr; 194 if (val == oldval) { 195 *host_addr = newval; 196 cpsr = CPSR_C; 197 } else { 198 cpsr = 0; 199 } 200 end_exclusive(); 201 #endif 202 mmap_unlock(); 203 204 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 205 env->regs[0] = cpsr ? 0 : -1; 206 return; 207 208 segv: 209 force_sig_fault(TARGET_SIGSEGV, 210 page_get_flags(addr) & PAGE_VALID ? 211 TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr); 212 } 213 214 /* Handle a jump to the kernel code page. */ 215 static int 216 do_kernel_trap(CPUARMState *env) 217 { 218 uint32_t addr; 219 220 switch (env->regs[15]) { 221 case 0xffff0fa0: /* __kernel_memory_barrier */ 222 smp_mb(); 223 break; 224 case 0xffff0fc0: /* __kernel_cmpxchg */ 225 arm_kernel_cmpxchg32_helper(env); 226 break; 227 case 0xffff0fe0: /* __kernel_get_tls */ 228 env->regs[0] = cpu_get_tls(env); 229 break; 230 case 0xffff0f60: /* __kernel_cmpxchg64 */ 231 arm_kernel_cmpxchg64_helper(env); 232 break; 233 234 default: 235 return 1; 236 } 237 /* Jump back to the caller. */ 238 addr = env->regs[14]; 239 if (addr & 1) { 240 env->thumb = true; 241 addr &= ~1; 242 } 243 env->regs[15] = addr; 244 245 return 0; 246 } 247 248 static bool insn_is_linux_bkpt(uint32_t opcode, bool is_thumb) 249 { 250 /* 251 * Return true if this insn is one of the three magic UDF insns 252 * which the kernel treats as breakpoint insns. 253 */ 254 if (!is_thumb) { 255 return (opcode & 0x0fffffff) == 0x07f001f0; 256 } else { 257 /* 258 * Note that we get the two halves of the 32-bit T32 insn 259 * in the opposite order to the value the kernel uses in 260 * its undef_hook struct. 261 */ 262 return ((opcode & 0xffff) == 0xde01) || (opcode == 0xa000f7f0); 263 } 264 } 265 266 static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode) 267 { 268 TaskState *ts = get_task_state(env_cpu(env)); 269 int rc = EmulateAll(opcode, &ts->fpa, env); 270 int raise, enabled; 271 272 if (rc == 0) { 273 /* Illegal instruction */ 274 return false; 275 } 276 if (rc > 0) { 277 /* Everything ok. */ 278 env->regs[15] += 4; 279 return true; 280 } 281 282 /* FP exception */ 283 rc = -rc; 284 raise = 0; 285 286 /* Translate softfloat flags to FPSR flags */ 287 if (rc & float_flag_invalid) { 288 raise |= BIT_IOC; 289 } 290 if (rc & float_flag_divbyzero) { 291 raise |= BIT_DZC; 292 } 293 if (rc & float_flag_overflow) { 294 raise |= BIT_OFC; 295 } 296 if (rc & float_flag_underflow) { 297 raise |= BIT_UFC; 298 } 299 if (rc & float_flag_inexact) { 300 raise |= BIT_IXC; 301 } 302 303 /* Accumulate unenabled exceptions */ 304 enabled = ts->fpa.fpsr >> 16; 305 ts->fpa.fpsr |= raise & ~enabled; 306 307 if (raise & enabled) { 308 /* 309 * The kernel's nwfpe emulator does not pass a real si_code. 310 * It merely uses send_sig(SIGFPE, current, 1), which results in 311 * __send_signal() filling out SI_KERNEL with pid and uid 0 (under 312 * the "SEND_SIG_PRIV" case). That's what our force_sig() does. 313 */ 314 force_sig(TARGET_SIGFPE); 315 } else { 316 env->regs[15] += 4; 317 } 318 return true; 319 } 320 321 void cpu_loop(CPUARMState *env) 322 { 323 CPUState *cs = env_cpu(env); 324 int trapnr, si_signo, si_code; 325 unsigned int n, insn; 326 abi_ulong ret; 327 328 for(;;) { 329 cpu_exec_start(cs); 330 trapnr = cpu_exec(cs); 331 cpu_exec_end(cs); 332 process_queued_cpu_work(cs); 333 334 switch(trapnr) { 335 case EXCP_UDEF: 336 case EXCP_NOCP: 337 case EXCP_INVSTATE: 338 { 339 uint32_t opcode; 340 341 /* we handle the FPU emulation here, as Linux */ 342 /* we get the opcode */ 343 /* FIXME - what to do if get_user() fails? */ 344 get_user_code_u32(opcode, env->regs[15], env); 345 346 /* 347 * The Linux kernel treats some UDF patterns specially 348 * to use as breakpoints (instead of the architectural 349 * bkpt insn). These should trigger a SIGTRAP rather 350 * than SIGILL. 351 */ 352 if (insn_is_linux_bkpt(opcode, env->thumb)) { 353 goto excp_debug; 354 } 355 356 if (!env->thumb && emulate_arm_fpa11(env, opcode)) { 357 break; 358 } 359 360 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, 361 env->regs[15]); 362 } 363 break; 364 case EXCP_SWI: 365 { 366 env->eabi = true; 367 /* system call */ 368 if (env->thumb) { 369 /* Thumb is always EABI style with syscall number in r7 */ 370 n = env->regs[7]; 371 } else { 372 /* 373 * Equivalent of kernel CONFIG_OABI_COMPAT: read the 374 * Arm SVC insn to extract the immediate, which is the 375 * syscall number in OABI. 376 */ 377 /* FIXME - what to do if get_user() fails? */ 378 get_user_code_u32(insn, env->regs[15] - 4, env); 379 n = insn & 0xffffff; 380 if (n == 0) { 381 /* zero immediate: EABI, syscall number in r7 */ 382 n = env->regs[7]; 383 } else { 384 /* 385 * This XOR matches the kernel code: an immediate 386 * in the valid range (0x900000 .. 0x9fffff) is 387 * converted into the correct EABI-style syscall 388 * number; invalid immediates end up as values 389 * > 0xfffff and are handled below as out-of-range. 390 */ 391 n ^= ARM_SYSCALL_BASE; 392 env->eabi = false; 393 } 394 } 395 396 if (n > ARM_NR_BASE) { 397 switch (n) { 398 case ARM_NR_cacheflush: 399 /* nop */ 400 break; 401 case ARM_NR_set_tls: 402 cpu_set_tls(env, env->regs[0]); 403 env->regs[0] = 0; 404 break; 405 case ARM_NR_breakpoint: 406 env->regs[15] -= env->thumb ? 2 : 4; 407 goto excp_debug; 408 case ARM_NR_get_tls: 409 env->regs[0] = cpu_get_tls(env); 410 break; 411 default: 412 if (n < 0xf0800) { 413 /* 414 * Syscalls 0xf0000..0xf07ff (or 0x9f0000.. 415 * 0x9f07ff in OABI numbering) are defined 416 * to return -ENOSYS rather than raising 417 * SIGILL. Note that we have already 418 * removed the 0x900000 prefix. 419 */ 420 qemu_log_mask(LOG_UNIMP, 421 "qemu: Unsupported ARM syscall: 0x%x\n", 422 n); 423 env->regs[0] = -TARGET_ENOSYS; 424 } else { 425 /* 426 * Otherwise SIGILL. This includes any SWI with 427 * immediate not originally 0x9fxxxx, because 428 * of the earlier XOR. 429 * Like the real kernel, we report the addr of the 430 * SWI in the siginfo si_addr but leave the PC 431 * pointing at the insn after the SWI. 432 */ 433 abi_ulong faultaddr = env->regs[15]; 434 faultaddr -= env->thumb ? 2 : 4; 435 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, 436 faultaddr); 437 } 438 break; 439 } 440 } else { 441 ret = do_syscall(env, 442 n, 443 env->regs[0], 444 env->regs[1], 445 env->regs[2], 446 env->regs[3], 447 env->regs[4], 448 env->regs[5], 449 0, 0); 450 if (ret == -QEMU_ERESTARTSYS) { 451 env->regs[15] -= env->thumb ? 2 : 4; 452 } else if (ret != -QEMU_ESIGRETURN) { 453 env->regs[0] = ret; 454 } 455 } 456 } 457 break; 458 case EXCP_SEMIHOST: 459 do_common_semihosting(cs); 460 env->regs[15] += env->thumb ? 2 : 4; 461 break; 462 case EXCP_INTERRUPT: 463 /* just indicate that signals should be handled asap */ 464 break; 465 case EXCP_PREFETCH_ABORT: 466 case EXCP_DATA_ABORT: 467 /* For user-only we don't set TTBCR_EAE, so look at the FSR. */ 468 switch (env->exception.fsr & 0x1f) { 469 case 0x1: /* Alignment */ 470 si_signo = TARGET_SIGBUS; 471 si_code = TARGET_BUS_ADRALN; 472 break; 473 case 0x3: /* Access flag fault, level 1 */ 474 case 0x6: /* Access flag fault, level 2 */ 475 case 0x9: /* Domain fault, level 1 */ 476 case 0xb: /* Domain fault, level 2 */ 477 case 0xd: /* Permission fault, level 1 */ 478 case 0xf: /* Permission fault, level 2 */ 479 si_signo = TARGET_SIGSEGV; 480 si_code = TARGET_SEGV_ACCERR; 481 break; 482 case 0x5: /* Translation fault, level 1 */ 483 case 0x7: /* Translation fault, level 2 */ 484 si_signo = TARGET_SIGSEGV; 485 si_code = TARGET_SEGV_MAPERR; 486 break; 487 default: 488 g_assert_not_reached(); 489 } 490 force_sig_fault(si_signo, si_code, env->exception.vaddress); 491 break; 492 case EXCP_DEBUG: 493 case EXCP_BKPT: 494 excp_debug: 495 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[15]); 496 break; 497 case EXCP_KERNEL_TRAP: 498 if (do_kernel_trap(env)) 499 goto error; 500 break; 501 case EXCP_YIELD: 502 /* nothing to do here for user-mode, just resume guest code */ 503 break; 504 case EXCP_ATOMIC: 505 cpu_exec_step_atomic(cs); 506 break; 507 default: 508 error: 509 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 510 abort(); 511 } 512 process_pending_signals(env); 513 } 514 } 515 516 void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs) 517 { 518 CPUState *cpu = env_cpu(env); 519 TaskState *ts = get_task_state(cpu); 520 struct image_info *info = ts->info; 521 int i; 522 523 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, 524 CPSRWriteByInstr); 525 for(i = 0; i < 16; i++) { 526 env->regs[i] = regs->uregs[i]; 527 } 528 #if TARGET_BIG_ENDIAN 529 /* Enable BE8. */ 530 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 531 && (info->elf_flags & EF_ARM_BE8)) { 532 env->uncached_cpsr |= CPSR_E; 533 env->cp15.sctlr_el[1] |= SCTLR_E0E; 534 } else { 535 env->cp15.sctlr_el[1] |= SCTLR_B; 536 } 537 arm_rebuild_hflags(env); 538 #endif 539 540 ts->stack_base = info->start_stack; 541 ts->heap_base = info->brk; 542 /* This will be filled in on the first SYS_HEAPINFO call. */ 543 ts->heap_limit = 0; 544 } 545