1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu.h" 22 #include "user-internals.h" 23 #include "elf.h" 24 #include "user/cpu_loop.h" 25 #include "signal-common.h" 26 #include "semihosting/common-semi.h" 27 #include "exec/page-protection.h" 28 #include "user/page-protection.h" 29 #include "target/arm/syndrome.h" 30 31 #define get_user_code_u32(x, gaddr, env) \ 32 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 33 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 34 (x) = bswap32(x); \ 35 } \ 36 __r; \ 37 }) 38 39 /* 40 * Note that if we need to do data accesses here, they should do a 41 * bswap if arm_cpu_bswap_data() returns true. 42 */ 43 44 /* 45 * Similar to code in accel/tcg/user-exec.c, but outside the execution loop. 46 * Must be called with mmap_lock. 47 * We get the PC of the entry address - which is as good as anything, 48 * on a real kernel what you get depends on which mode it uses. 49 */ 50 static void *atomic_mmu_lookup(CPUArchState *env, uint32_t addr, int size) 51 { 52 int need_flags = PAGE_READ | PAGE_WRITE_ORG | PAGE_VALID; 53 int page_flags; 54 55 /* Enforce guest required alignment. */ 56 if (unlikely(addr & (size - 1))) { 57 force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr); 58 return NULL; 59 } 60 61 page_flags = page_get_flags(addr); 62 if (unlikely((page_flags & need_flags) != need_flags)) { 63 force_sig_fault(TARGET_SIGSEGV, 64 page_flags & PAGE_VALID ? 65 TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr); 66 return NULL; 67 } 68 69 return g2h(env_cpu(env), addr); 70 } 71 72 /* 73 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst 74 * Input: 75 * r0 = oldval 76 * r1 = newval 77 * r2 = pointer to target value 78 * 79 * Output: 80 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 81 * C set if *ptr was changed, clear if no exchange happened 82 */ 83 static void arm_kernel_cmpxchg32_helper(CPUARMState *env) 84 { 85 uint32_t oldval, newval, val, addr, cpsr, *host_addr; 86 87 /* Swap if host != guest endianness, for the host cmpxchg below */ 88 oldval = tswap32(env->regs[0]); 89 newval = tswap32(env->regs[1]); 90 addr = env->regs[2]; 91 92 mmap_lock(); 93 host_addr = atomic_mmu_lookup(env, addr, 4); 94 if (!host_addr) { 95 mmap_unlock(); 96 return; 97 } 98 99 val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval); 100 mmap_unlock(); 101 102 cpsr = (val == oldval) * CPSR_C; 103 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 104 env->regs[0] = cpsr ? 0 : -1; 105 } 106 107 /* 108 * See the Linux kernel's Documentation/arm/kernel_user_helpers.rst 109 * Input: 110 * r0 = pointer to oldval 111 * r1 = pointer to newval 112 * r2 = pointer to target value 113 * 114 * Output: 115 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 116 * C set if *ptr was changed, clear if no exchange happened 117 * 118 * Note segv's in kernel helpers are a bit tricky, we can set the 119 * data address sensibly but the PC address is just the entry point. 120 */ 121 static void arm_kernel_cmpxchg64_helper(CPUARMState *env) 122 { 123 uint64_t oldval, newval, val; 124 uint32_t addr, cpsr; 125 uint64_t *host_addr; 126 127 addr = env->regs[0]; 128 if (get_user_u64(oldval, addr)) { 129 goto segv; 130 } 131 132 addr = env->regs[1]; 133 if (get_user_u64(newval, addr)) { 134 goto segv; 135 } 136 137 mmap_lock(); 138 addr = env->regs[2]; 139 host_addr = atomic_mmu_lookup(env, addr, 8); 140 if (!host_addr) { 141 mmap_unlock(); 142 return; 143 } 144 145 /* Swap if host != guest endianness, for the host cmpxchg below */ 146 oldval = tswap64(oldval); 147 newval = tswap64(newval); 148 149 #ifdef CONFIG_ATOMIC64 150 val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval); 151 cpsr = (val == oldval) * CPSR_C; 152 #else 153 /* 154 * This only works between threads, not between processes, but since 155 * the host has no 64-bit cmpxchg, it is the best that we can do. 156 */ 157 start_exclusive(); 158 val = *host_addr; 159 if (val == oldval) { 160 *host_addr = newval; 161 cpsr = CPSR_C; 162 } else { 163 cpsr = 0; 164 } 165 end_exclusive(); 166 #endif 167 mmap_unlock(); 168 169 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 170 env->regs[0] = cpsr ? 0 : -1; 171 return; 172 173 segv: 174 force_sig_fault(TARGET_SIGSEGV, 175 page_get_flags(addr) & PAGE_VALID ? 176 TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr); 177 } 178 179 /* Handle a jump to the kernel code page. */ 180 static int 181 do_kernel_trap(CPUARMState *env) 182 { 183 uint32_t addr; 184 185 switch (env->regs[15]) { 186 case 0xffff0fa0: /* __kernel_memory_barrier */ 187 smp_mb(); 188 break; 189 case 0xffff0fc0: /* __kernel_cmpxchg */ 190 arm_kernel_cmpxchg32_helper(env); 191 break; 192 case 0xffff0fe0: /* __kernel_get_tls */ 193 env->regs[0] = cpu_get_tls(env); 194 break; 195 case 0xffff0f60: /* __kernel_cmpxchg64 */ 196 arm_kernel_cmpxchg64_helper(env); 197 break; 198 199 default: 200 return 1; 201 } 202 /* Jump back to the caller. */ 203 addr = env->regs[14]; 204 if (addr & 1) { 205 env->thumb = true; 206 addr &= ~1; 207 } 208 env->regs[15] = addr; 209 210 return 0; 211 } 212 213 static bool insn_is_linux_bkpt(uint32_t opcode, bool is_thumb) 214 { 215 /* 216 * Return true if this insn is one of the three magic UDF insns 217 * which the kernel treats as breakpoint insns. 218 */ 219 if (!is_thumb) { 220 return (opcode & 0x0fffffff) == 0x07f001f0; 221 } else { 222 /* 223 * Note that we get the two halves of the 32-bit T32 insn 224 * in the opposite order to the value the kernel uses in 225 * its undef_hook struct. 226 */ 227 return ((opcode & 0xffff) == 0xde01) || (opcode == 0xa000f7f0); 228 } 229 } 230 231 static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode) 232 { 233 TaskState *ts = get_task_state(env_cpu(env)); 234 int rc = EmulateAll(opcode, &ts->fpa, env); 235 int raise, enabled; 236 237 if (rc == 0) { 238 /* Illegal instruction */ 239 return false; 240 } 241 if (rc > 0) { 242 /* Everything ok. */ 243 env->regs[15] += 4; 244 return true; 245 } 246 247 /* FP exception */ 248 rc = -rc; 249 raise = 0; 250 251 /* Translate softfloat flags to FPSR flags */ 252 if (rc & float_flag_invalid) { 253 raise |= BIT_IOC; 254 } 255 if (rc & float_flag_divbyzero) { 256 raise |= BIT_DZC; 257 } 258 if (rc & float_flag_overflow) { 259 raise |= BIT_OFC; 260 } 261 if (rc & float_flag_underflow) { 262 raise |= BIT_UFC; 263 } 264 if (rc & float_flag_inexact) { 265 raise |= BIT_IXC; 266 } 267 268 /* Accumulate unenabled exceptions */ 269 enabled = ts->fpa.fpsr >> 16; 270 ts->fpa.fpsr |= raise & ~enabled; 271 272 if (raise & enabled) { 273 /* 274 * The kernel's nwfpe emulator does not pass a real si_code. 275 * It merely uses send_sig(SIGFPE, current, 1), which results in 276 * __send_signal() filling out SI_KERNEL with pid and uid 0 (under 277 * the "SEND_SIG_PRIV" case). That's what our force_sig() does. 278 */ 279 force_sig(TARGET_SIGFPE); 280 } else { 281 env->regs[15] += 4; 282 } 283 return true; 284 } 285 286 void cpu_loop(CPUARMState *env) 287 { 288 CPUState *cs = env_cpu(env); 289 int trapnr, si_signo, si_code; 290 unsigned int n, insn; 291 abi_ulong ret; 292 293 for(;;) { 294 cpu_exec_start(cs); 295 trapnr = cpu_exec(cs); 296 cpu_exec_end(cs); 297 process_queued_cpu_work(cs); 298 299 switch(trapnr) { 300 case EXCP_UDEF: 301 case EXCP_NOCP: 302 case EXCP_INVSTATE: 303 { 304 uint32_t opcode; 305 306 /* we handle the FPU emulation here, as Linux */ 307 /* we get the opcode */ 308 /* FIXME - what to do if get_user() fails? */ 309 get_user_code_u32(opcode, env->regs[15], env); 310 311 /* 312 * The Linux kernel treats some UDF patterns specially 313 * to use as breakpoints (instead of the architectural 314 * bkpt insn). These should trigger a SIGTRAP rather 315 * than SIGILL. 316 */ 317 if (insn_is_linux_bkpt(opcode, env->thumb)) { 318 goto excp_debug; 319 } 320 321 if (!env->thumb && emulate_arm_fpa11(env, opcode)) { 322 break; 323 } 324 325 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, 326 env->regs[15]); 327 } 328 break; 329 case EXCP_SWI: 330 { 331 env->eabi = true; 332 /* system call */ 333 if (env->thumb) { 334 /* Thumb is always EABI style with syscall number in r7 */ 335 n = env->regs[7]; 336 } else { 337 /* 338 * Equivalent of kernel CONFIG_OABI_COMPAT: read the 339 * Arm SVC insn to extract the immediate, which is the 340 * syscall number in OABI. 341 */ 342 /* FIXME - what to do if get_user() fails? */ 343 get_user_code_u32(insn, env->regs[15] - 4, env); 344 n = insn & 0xffffff; 345 if (n == 0) { 346 /* zero immediate: EABI, syscall number in r7 */ 347 n = env->regs[7]; 348 } else { 349 /* 350 * This XOR matches the kernel code: an immediate 351 * in the valid range (0x900000 .. 0x9fffff) is 352 * converted into the correct EABI-style syscall 353 * number; invalid immediates end up as values 354 * > 0xfffff and are handled below as out-of-range. 355 */ 356 n ^= ARM_SYSCALL_BASE; 357 env->eabi = false; 358 } 359 } 360 361 if (n > ARM_NR_BASE) { 362 switch (n) { 363 case ARM_NR_cacheflush: 364 /* nop */ 365 break; 366 case ARM_NR_set_tls: 367 cpu_set_tls(env, env->regs[0]); 368 env->regs[0] = 0; 369 break; 370 case ARM_NR_breakpoint: 371 env->regs[15] -= env->thumb ? 2 : 4; 372 goto excp_debug; 373 case ARM_NR_get_tls: 374 env->regs[0] = cpu_get_tls(env); 375 break; 376 default: 377 if (n < 0xf0800) { 378 /* 379 * Syscalls 0xf0000..0xf07ff (or 0x9f0000.. 380 * 0x9f07ff in OABI numbering) are defined 381 * to return -ENOSYS rather than raising 382 * SIGILL. Note that we have already 383 * removed the 0x900000 prefix. 384 */ 385 qemu_log_mask(LOG_UNIMP, 386 "qemu: Unsupported ARM syscall: 0x%x\n", 387 n); 388 env->regs[0] = -TARGET_ENOSYS; 389 } else { 390 /* 391 * Otherwise SIGILL. This includes any SWI with 392 * immediate not originally 0x9fxxxx, because 393 * of the earlier XOR. 394 * Like the real kernel, we report the addr of the 395 * SWI in the siginfo si_addr but leave the PC 396 * pointing at the insn after the SWI. 397 */ 398 abi_ulong faultaddr = env->regs[15]; 399 faultaddr -= env->thumb ? 2 : 4; 400 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, 401 faultaddr); 402 } 403 break; 404 } 405 } else { 406 ret = do_syscall(env, 407 n, 408 env->regs[0], 409 env->regs[1], 410 env->regs[2], 411 env->regs[3], 412 env->regs[4], 413 env->regs[5], 414 0, 0); 415 if (ret == -QEMU_ERESTARTSYS) { 416 env->regs[15] -= env->thumb ? 2 : 4; 417 } else if (ret != -QEMU_ESIGRETURN) { 418 env->regs[0] = ret; 419 } 420 } 421 } 422 break; 423 case EXCP_SEMIHOST: 424 do_common_semihosting(cs); 425 env->regs[15] += env->thumb ? 2 : 4; 426 break; 427 case EXCP_INTERRUPT: 428 /* just indicate that signals should be handled asap */ 429 break; 430 case EXCP_PREFETCH_ABORT: 431 case EXCP_DATA_ABORT: 432 /* For user-only we don't set TTBCR_EAE, so look at the FSR. */ 433 switch (env->exception.fsr & 0x1f) { 434 case 0x1: /* Alignment */ 435 si_signo = TARGET_SIGBUS; 436 si_code = TARGET_BUS_ADRALN; 437 break; 438 case 0x3: /* Access flag fault, level 1 */ 439 case 0x6: /* Access flag fault, level 2 */ 440 case 0x9: /* Domain fault, level 1 */ 441 case 0xb: /* Domain fault, level 2 */ 442 case 0xd: /* Permission fault, level 1 */ 443 case 0xf: /* Permission fault, level 2 */ 444 si_signo = TARGET_SIGSEGV; 445 si_code = TARGET_SEGV_ACCERR; 446 break; 447 case 0x5: /* Translation fault, level 1 */ 448 case 0x7: /* Translation fault, level 2 */ 449 si_signo = TARGET_SIGSEGV; 450 si_code = TARGET_SEGV_MAPERR; 451 break; 452 default: 453 g_assert_not_reached(); 454 } 455 force_sig_fault(si_signo, si_code, env->exception.vaddress); 456 break; 457 case EXCP_DEBUG: 458 case EXCP_BKPT: 459 excp_debug: 460 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[15]); 461 break; 462 case EXCP_KERNEL_TRAP: 463 if (do_kernel_trap(env)) 464 goto error; 465 break; 466 case EXCP_YIELD: 467 /* nothing to do here for user-mode, just resume guest code */ 468 break; 469 case EXCP_ATOMIC: 470 cpu_exec_step_atomic(cs); 471 break; 472 default: 473 error: 474 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 475 abort(); 476 } 477 process_pending_signals(env); 478 } 479 } 480 481 void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs) 482 { 483 CPUState *cpu = env_cpu(env); 484 TaskState *ts = get_task_state(cpu); 485 struct image_info *info = ts->info; 486 int i; 487 488 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, 489 CPSRWriteByInstr); 490 for(i = 0; i < 16; i++) { 491 env->regs[i] = regs->uregs[i]; 492 } 493 #if TARGET_BIG_ENDIAN 494 /* Enable BE8. */ 495 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 496 && (info->elf_flags & EF_ARM_BE8)) { 497 env->uncached_cpsr |= CPSR_E; 498 env->cp15.sctlr_el[1] |= SCTLR_E0E; 499 } else { 500 env->cp15.sctlr_el[1] |= SCTLR_B; 501 } 502 arm_rebuild_hflags(env); 503 #endif 504 505 ts->stack_base = info->start_stack; 506 ts->heap_base = info->brk; 507 /* This will be filled in on the first SYS_HEAPINFO call. */ 508 ts->heap_limit = 0; 509 } 510