1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu.h" 22 #include "user-internals.h" 23 #include "user/cpu_loop.h" 24 #include "signal-common.h" 25 #include "qemu/guest-random.h" 26 #include "semihosting/common-semi.h" 27 #include "target/arm/syndrome.h" 28 #include "target/arm/cpu-features.h" 29 30 /* AArch64 main loop */ 31 void cpu_loop(CPUARMState *env) 32 { 33 CPUState *cs = env_cpu(env); 34 int trapnr, ec, fsc, si_code, si_signo; 35 abi_long ret; 36 37 for (;;) { 38 cpu_exec_start(cs); 39 trapnr = cpu_exec(cs); 40 cpu_exec_end(cs); 41 process_queued_cpu_work(cs); 42 43 switch (trapnr) { 44 case EXCP_SWI: 45 /* On syscall, PSTATE.ZA is preserved, PSTATE.SM is cleared. */ 46 aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); 47 ret = do_syscall(env, 48 env->xregs[8], 49 env->xregs[0], 50 env->xregs[1], 51 env->xregs[2], 52 env->xregs[3], 53 env->xregs[4], 54 env->xregs[5], 55 0, 0); 56 if (ret == -QEMU_ERESTARTSYS) { 57 env->pc -= 4; 58 } else if (ret != -QEMU_ESIGRETURN) { 59 env->xregs[0] = ret; 60 } 61 break; 62 case EXCP_INTERRUPT: 63 /* just indicate that signals should be handled asap */ 64 break; 65 case EXCP_UDEF: 66 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); 67 break; 68 case EXCP_PREFETCH_ABORT: 69 case EXCP_DATA_ABORT: 70 ec = syn_get_ec(env->exception.syndrome); 71 switch (ec) { 72 case EC_DATAABORT: 73 case EC_INSNABORT: 74 /* Both EC have the same format for FSC, or close enough. */ 75 fsc = extract32(env->exception.syndrome, 0, 6); 76 switch (fsc) { 77 case 0x04 ... 0x07: /* Translation fault, level {0-3} */ 78 si_signo = TARGET_SIGSEGV; 79 si_code = TARGET_SEGV_MAPERR; 80 break; 81 case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ 82 case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ 83 si_signo = TARGET_SIGSEGV; 84 si_code = TARGET_SEGV_ACCERR; 85 break; 86 case 0x11: /* Synchronous Tag Check Fault */ 87 si_signo = TARGET_SIGSEGV; 88 si_code = TARGET_SEGV_MTESERR; 89 break; 90 case 0x21: /* Alignment fault */ 91 si_signo = TARGET_SIGBUS; 92 si_code = TARGET_BUS_ADRALN; 93 break; 94 default: 95 g_assert_not_reached(); 96 } 97 break; 98 case EC_PCALIGNMENT: 99 si_signo = TARGET_SIGBUS; 100 si_code = TARGET_BUS_ADRALN; 101 break; 102 default: 103 g_assert_not_reached(); 104 } 105 force_sig_fault(si_signo, si_code, env->exception.vaddress); 106 break; 107 case EXCP_DEBUG: 108 case EXCP_BKPT: 109 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); 110 break; 111 case EXCP_SEMIHOST: 112 do_common_semihosting(cs); 113 env->pc += 4; 114 break; 115 case EXCP_YIELD: 116 /* nothing to do here for user-mode, just resume guest code */ 117 break; 118 case EXCP_ATOMIC: 119 cpu_exec_step_atomic(cs); 120 break; 121 default: 122 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 123 abort(); 124 } 125 126 /* Check for MTE asynchronous faults */ 127 if (unlikely(env->cp15.tfsr_el[0])) { 128 env->cp15.tfsr_el[0] = 0; 129 force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0); 130 } 131 132 process_pending_signals(env); 133 /* Exception return on AArch64 always clears the exclusive monitor, 134 * so any return to running guest code implies this. 135 */ 136 env->exclusive_addr = -1; 137 } 138 } 139 140 void target_cpu_copy_regs(CPUArchState *env, target_pt_regs *regs) 141 { 142 ARMCPU *cpu = env_archcpu(env); 143 CPUState *cs = env_cpu(env); 144 TaskState *ts = get_task_state(cs); 145 struct image_info *info = ts->info; 146 int i; 147 148 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 149 fprintf(stderr, 150 "The selected ARM CPU does not support 64 bit mode\n"); 151 exit(EXIT_FAILURE); 152 } 153 154 for (i = 0; i < 31; i++) { 155 env->xregs[i] = regs->regs[i]; 156 } 157 env->pc = regs->pc; 158 env->xregs[31] = regs->sp; 159 #if TARGET_BIG_ENDIAN 160 env->cp15.sctlr_el[1] |= SCTLR_E0E; 161 for (i = 1; i < 4; ++i) { 162 env->cp15.sctlr_el[i] |= SCTLR_EE; 163 } 164 arm_rebuild_hflags(env); 165 #endif 166 167 if (cpu_isar_feature(aa64_pauth, cpu)) { 168 qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys)); 169 } 170 171 ts->stack_base = info->start_stack; 172 ts->heap_base = info->brk; 173 /* This will be filled in on the first SYS_HEAPINFO call. */ 174 ts->heap_limit = 0; 175 } 176