1*ef17dd6aSVivek Goyal /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*ef17dd6aSVivek Goyal /* 3*ef17dd6aSVivek Goyal * Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> 4*ef17dd6aSVivek Goyal * 5*ef17dd6aSVivek Goyal * This program is free software; you can redistribute it and/or modify 6*ef17dd6aSVivek Goyal * it under the terms of the GNU General Public License version 2 as 7*ef17dd6aSVivek Goyal * published by the Free Software Foundation. 8*ef17dd6aSVivek Goyal * 9*ef17dd6aSVivek Goyal * This program is distributed in the hope that it will be useful, 10*ef17dd6aSVivek Goyal * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*ef17dd6aSVivek Goyal * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*ef17dd6aSVivek Goyal * GNU General Public License for more details. 13*ef17dd6aSVivek Goyal * 14*ef17dd6aSVivek Goyal * You should have received a copy of the GNU General Public License 15*ef17dd6aSVivek Goyal * along with this program. If not, see <https://www.gnu.org/licenses/>. 16*ef17dd6aSVivek Goyal */ 17*ef17dd6aSVivek Goyal 18*ef17dd6aSVivek Goyal #ifdef __LP64__ 19*ef17dd6aSVivek Goyal #define __ARCH_WANT_NEW_STAT 20*ef17dd6aSVivek Goyal #define __ARCH_WANT_SET_GET_RLIMIT 21*ef17dd6aSVivek Goyal #endif /* __LP64__ */ 22*ef17dd6aSVivek Goyal 23*ef17dd6aSVivek Goyal #define __ARCH_WANT_SYS_CLONE3 24*ef17dd6aSVivek Goyal 25*ef17dd6aSVivek Goyal #include <asm-generic/unistd.h> 26*ef17dd6aSVivek Goyal 27*ef17dd6aSVivek Goyal /* 28*ef17dd6aSVivek Goyal * Allows the instruction cache to be flushed from userspace. Despite RISC-V 29*ef17dd6aSVivek Goyal * having a direct 'fence.i' instruction available to userspace (which we 30*ef17dd6aSVivek Goyal * can't trap!), that's not actually viable when running on Linux because the 31*ef17dd6aSVivek Goyal * kernel might schedule a process on another hart. There is no way for 32*ef17dd6aSVivek Goyal * userspace to handle this without invoking the kernel (as it doesn't know the 33*ef17dd6aSVivek Goyal * thread->hart mappings), so we've defined a RISC-V specific system call to 34*ef17dd6aSVivek Goyal * flush the instruction cache. 35*ef17dd6aSVivek Goyal * 36*ef17dd6aSVivek Goyal * __NR_riscv_flush_icache is defined to flush the instruction cache over an 37*ef17dd6aSVivek Goyal * address range, with the flush applying to either all threads or just the 38*ef17dd6aSVivek Goyal * caller. We don't currently do anything with the address range, that's just 39*ef17dd6aSVivek Goyal * in there for forwards compatibility. 40*ef17dd6aSVivek Goyal */ 41*ef17dd6aSVivek Goyal #ifndef __NR_riscv_flush_icache 42*ef17dd6aSVivek Goyal #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) 43*ef17dd6aSVivek Goyal #endif 44*ef17dd6aSVivek Goyal __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) 45