1*0694dabeSBin Meng /* 2*0694dabeSBin Meng * QEMU model of the SiFive SPI Controller 3*0694dabeSBin Meng * 4*0694dabeSBin Meng * Copyright (c) 2021 Wind River Systems, Inc. 5*0694dabeSBin Meng * 6*0694dabeSBin Meng * Author: 7*0694dabeSBin Meng * Bin Meng <bin.meng@windriver.com> 8*0694dabeSBin Meng * 9*0694dabeSBin Meng * This program is free software; you can redistribute it and/or modify it 10*0694dabeSBin Meng * under the terms and conditions of the GNU General Public License, 11*0694dabeSBin Meng * version 2 or later, as published by the Free Software Foundation. 12*0694dabeSBin Meng * 13*0694dabeSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 14*0694dabeSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15*0694dabeSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16*0694dabeSBin Meng * more details. 17*0694dabeSBin Meng * 18*0694dabeSBin Meng * You should have received a copy of the GNU General Public License along with 19*0694dabeSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 20*0694dabeSBin Meng */ 21*0694dabeSBin Meng 22*0694dabeSBin Meng #ifndef HW_SIFIVE_SPI_H 23*0694dabeSBin Meng #define HW_SIFIVE_SPI_H 24*0694dabeSBin Meng 25*0694dabeSBin Meng #define SIFIVE_SPI_REG_NUM (0x78 / 4) 26*0694dabeSBin Meng 27*0694dabeSBin Meng #define TYPE_SIFIVE_SPI "sifive.spi" 28*0694dabeSBin Meng #define SIFIVE_SPI(obj) OBJECT_CHECK(SiFiveSPIState, (obj), TYPE_SIFIVE_SPI) 29*0694dabeSBin Meng 30*0694dabeSBin Meng typedef struct SiFiveSPIState { 31*0694dabeSBin Meng SysBusDevice parent_obj; 32*0694dabeSBin Meng 33*0694dabeSBin Meng MemoryRegion mmio; 34*0694dabeSBin Meng qemu_irq irq; 35*0694dabeSBin Meng 36*0694dabeSBin Meng uint32_t num_cs; 37*0694dabeSBin Meng qemu_irq *cs_lines; 38*0694dabeSBin Meng 39*0694dabeSBin Meng SSIBus *spi; 40*0694dabeSBin Meng 41*0694dabeSBin Meng Fifo8 tx_fifo; 42*0694dabeSBin Meng Fifo8 rx_fifo; 43*0694dabeSBin Meng 44*0694dabeSBin Meng uint32_t regs[SIFIVE_SPI_REG_NUM]; 45*0694dabeSBin Meng } SiFiveSPIState; 46*0694dabeSBin Meng 47*0694dabeSBin Meng #endif /* HW_SIFIVE_SPI_H */ 48