1fff123b8SPhilippe Mathieu-Daudé /* 2fff123b8SPhilippe Mathieu-Daudé * QEMU PIIX South Bridge Emulation 3fff123b8SPhilippe Mathieu-Daudé * 4fff123b8SPhilippe Mathieu-Daudé * Copyright (c) 2006 Fabrice Bellard 5e29f2379SPhilippe Mathieu-Daudé * Copyright (c) 2018 Hervé Poussineau 6fff123b8SPhilippe Mathieu-Daudé * 7fff123b8SPhilippe Mathieu-Daudé * This work is licensed under the terms of the GNU GPL, version 2 or later. 8fff123b8SPhilippe Mathieu-Daudé * See the COPYING file in the top-level directory. 9fff123b8SPhilippe Mathieu-Daudé * 10fff123b8SPhilippe Mathieu-Daudé */ 11fff123b8SPhilippe Mathieu-Daudé 12fff123b8SPhilippe Mathieu-Daudé #ifndef HW_SOUTHBRIDGE_PIIX_H 13fff123b8SPhilippe Mathieu-Daudé #define HW_SOUTHBRIDGE_PIIX_H 14fff123b8SPhilippe Mathieu-Daudé 15edf5ca5dSMarkus Armbruster #include "hw/pci/pci_device.h" 16e47e5a5bSBernhard Beschow #include "hw/ide/pci.h" 17f0bc6bf7SBernhard Beschow #include "hw/rtc/mc146818rtc.h" 18*6fe4464cSBernhard Beschow #include "hw/usb/hcd-uhci.h" 19fff123b8SPhilippe Mathieu-Daudé 204b19de14SPhilippe Mathieu-Daudé /* PIRQRC[A:D]: PIRQx Route Control Registers */ 214b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCA 0x60 224b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCB 0x61 234b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCC 0x62 244b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCD 0x63 254b19de14SPhilippe Mathieu-Daudé 260063454aSPhilippe Mathieu-Daudé /* 270063454aSPhilippe Mathieu-Daudé * Reset Control Register: PCI-accessible ISA-Compatible Register at address 280063454aSPhilippe Mathieu-Daudé * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 290063454aSPhilippe Mathieu-Daudé */ 300063454aSPhilippe Mathieu-Daudé #define PIIX_RCR_IOPORT 0xcf9 310063454aSPhilippe Mathieu-Daudé 3214a026ddSPhilippe Mathieu-Daudé #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ 3314a026ddSPhilippe Mathieu-Daudé 34db1015e9SEduardo Habkost struct PIIXState { 3514a026ddSPhilippe Mathieu-Daudé PCIDevice dev; 3614a026ddSPhilippe Mathieu-Daudé 3714a026ddSPhilippe Mathieu-Daudé /* 3814a026ddSPhilippe Mathieu-Daudé * bitmap to track pic levels. 3914a026ddSPhilippe Mathieu-Daudé * The pic level is the logical OR of all the PCI irqs mapped to it 4014a026ddSPhilippe Mathieu-Daudé * So one PIC level is tracked by PIIX_NUM_PIRQS bits. 4114a026ddSPhilippe Mathieu-Daudé * 4214a026ddSPhilippe Mathieu-Daudé * PIRQ is mapped to PIC pins, we track it by 4332f29b26SBernhard Beschow * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with 4414a026ddSPhilippe Mathieu-Daudé * pic_irq * PIIX_NUM_PIRQS + pirq 4514a026ddSPhilippe Mathieu-Daudé */ 4632f29b26SBernhard Beschow #if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 4714a026ddSPhilippe Mathieu-Daudé #error "unable to encode pic state in 64bit in pic_levels." 4814a026ddSPhilippe Mathieu-Daudé #endif 4914a026ddSPhilippe Mathieu-Daudé uint64_t pic_levels; 5014a026ddSPhilippe Mathieu-Daudé 5140f70623SBernhard Beschow qemu_irq isa_irqs_in[ISA_NUM_IRQS]; 5214a026ddSPhilippe Mathieu-Daudé 5314a026ddSPhilippe Mathieu-Daudé /* This member isn't used. Just for save/load compatibility */ 5414a026ddSPhilippe Mathieu-Daudé int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; 5514a026ddSPhilippe Mathieu-Daudé 56f0bc6bf7SBernhard Beschow MC146818RtcState rtc; 57e47e5a5bSBernhard Beschow PCIIDEState ide; 58*6fe4464cSBernhard Beschow UHCIState uhci; 59f0bc6bf7SBernhard Beschow 6014a026ddSPhilippe Mathieu-Daudé /* Reset Control Register contents */ 6114a026ddSPhilippe Mathieu-Daudé uint8_t rcr; 6214a026ddSPhilippe Mathieu-Daudé 6314a026ddSPhilippe Mathieu-Daudé /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ 6414a026ddSPhilippe Mathieu-Daudé MemoryRegion rcr_mem; 65*6fe4464cSBernhard Beschow 66*6fe4464cSBernhard Beschow bool has_usb; 67db1015e9SEduardo Habkost }; 68db1015e9SEduardo Habkost typedef struct PIIXState PIIX3State; 6914a026ddSPhilippe Mathieu-Daudé 70fe47ad3aSEduardo Habkost #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" 718110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, 728110fa1dSEduardo Habkost TYPE_PIIX3_PCI_DEVICE) 73fe47ad3aSEduardo Habkost 743963e139SBernhard Beschow #define TYPE_PIIX3_DEVICE "PIIX3" 753963e139SBernhard Beschow #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" 763963e139SBernhard Beschow 77fff123b8SPhilippe Mathieu-Daudé #endif 78