1fff123b8SPhilippe Mathieu-Daudé /* 2fff123b8SPhilippe Mathieu-Daudé * QEMU PIIX South Bridge Emulation 3fff123b8SPhilippe Mathieu-Daudé * 4fff123b8SPhilippe Mathieu-Daudé * Copyright (c) 2006 Fabrice Bellard 5e29f2379SPhilippe Mathieu-Daudé * Copyright (c) 2018 Hervé Poussineau 6fff123b8SPhilippe Mathieu-Daudé * 7fff123b8SPhilippe Mathieu-Daudé * This work is licensed under the terms of the GNU GPL, version 2 or later. 8fff123b8SPhilippe Mathieu-Daudé * See the COPYING file in the top-level directory. 9fff123b8SPhilippe Mathieu-Daudé * 10fff123b8SPhilippe Mathieu-Daudé */ 11fff123b8SPhilippe Mathieu-Daudé 12fff123b8SPhilippe Mathieu-Daudé #ifndef HW_SOUTHBRIDGE_PIIX_H 13fff123b8SPhilippe Mathieu-Daudé #define HW_SOUTHBRIDGE_PIIX_H 14fff123b8SPhilippe Mathieu-Daudé 15fff123b8SPhilippe Mathieu-Daudé #define TYPE_PIIX4_PM "PIIX4_PM" 16fff123b8SPhilippe Mathieu-Daudé 17fff123b8SPhilippe Mathieu-Daudé I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 18fff123b8SPhilippe Mathieu-Daudé qemu_irq sci_irq, qemu_irq smi_irq, 19fff123b8SPhilippe Mathieu-Daudé int smm_enabled, DeviceState **piix4_pm); 20fff123b8SPhilippe Mathieu-Daudé 21*4b19de14SPhilippe Mathieu-Daudé /* PIRQRC[A:D]: PIRQx Route Control Registers */ 22*4b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCA 0x60 23*4b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCB 0x61 24*4b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCC 0x62 25*4b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCD 0x63 26*4b19de14SPhilippe Mathieu-Daudé 270063454aSPhilippe Mathieu-Daudé /* 280063454aSPhilippe Mathieu-Daudé * Reset Control Register: PCI-accessible ISA-Compatible Register at address 290063454aSPhilippe Mathieu-Daudé * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 300063454aSPhilippe Mathieu-Daudé */ 310063454aSPhilippe Mathieu-Daudé #define PIIX_RCR_IOPORT 0xcf9 320063454aSPhilippe Mathieu-Daudé 33e29f2379SPhilippe Mathieu-Daudé extern PCIDevice *piix4_dev; 34e29f2379SPhilippe Mathieu-Daudé 35e29f2379SPhilippe Mathieu-Daudé DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, 36e29f2379SPhilippe Mathieu-Daudé I2CBus **smbus, size_t ide_buses); 37e29f2379SPhilippe Mathieu-Daudé 38fff123b8SPhilippe Mathieu-Daudé #endif 39