1 #ifndef HW_ICH9_H 2 #define HW_ICH9_H 3 4 #include "hw/isa/isa.h" 5 #include "hw/sysbus.h" 6 #include "hw/i386/pc.h" 7 #include "hw/isa/apm.h" 8 #include "hw/acpi/acpi.h" 9 #include "hw/acpi/ich9.h" 10 #include "qom/object.h" 11 12 void ich9_lpc_set_irq(void *opaque, int irq_num, int level); 13 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx); 14 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin); 15 void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled); 16 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base); 17 18 void ich9_generate_smi(void); 19 20 #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ 21 22 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" 23 OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) 24 25 struct ICH9LPCState { 26 /* ICH9 LPC PCI to ISA bridge */ 27 PCIDevice d; 28 29 /* (pci device, intx) -> pirq 30 * In real chipset case, the unused slots are never used 31 * as ICH9 supports only D25-D31 irq routing. 32 * On the other hand in qemu case, any slot/function can be populated 33 * via command line option. 34 * So fallback interrupt routing for any devices in any slots is necessary. 35 */ 36 uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; 37 38 APMState apm; 39 ICH9LPCPMRegs pm; 40 uint32_t sci_level; /* track sci level */ 41 uint8_t sci_gsi; 42 43 /* 2.24 Pin Straps */ 44 struct { 45 bool spkr_hi; 46 } pin_strap; 47 48 /* 10.1 Chipset Configuration registers(Memory Space) 49 which is pointed by RCBA */ 50 uint8_t chip_config[ICH9_CC_SIZE]; 51 52 /* 53 * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0) 54 * 55 * register contents and IO memory region 56 */ 57 uint8_t rst_cnt; 58 MemoryRegion rst_cnt_mem; 59 60 /* SMI feature negotiation via fw_cfg */ 61 uint64_t smi_host_features; /* guest-invisible, host endian */ 62 uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little 63 * endian uint64_t */ 64 uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little 65 * endian uint64_t */ 66 uint8_t smi_features_ok; /* guest-visible, read-only; selecting it 67 * triggers feature lockdown */ 68 uint64_t smi_negotiated_features; /* guest-invisible, host endian */ 69 70 /* isa bus */ 71 ISABus *isa_bus; 72 MemoryRegion rcrb_mem; /* root complex register block */ 73 Notifier machine_ready; 74 75 qemu_irq gsi[GSI_NUM_PINS]; 76 }; 77 78 #define ICH9_MASK(bit, ms_bit, ls_bit) \ 79 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) 80 81 /* ICH9: Chipset Configuration Registers */ 82 #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) 83 84 #define ICH9_CC 85 #define ICH9_CC_D28IP 0x310C 86 #define ICH9_CC_D28IP_SHIFT 4 87 #define ICH9_CC_D28IP_MASK 0xf 88 #define ICH9_CC_D28IP_DEFAULT 0x00214321 89 #define ICH9_CC_D31IR 0x3140 90 #define ICH9_CC_D30IR 0x3142 91 #define ICH9_CC_D29IR 0x3144 92 #define ICH9_CC_D28IR 0x3146 93 #define ICH9_CC_D27IR 0x3148 94 #define ICH9_CC_D26IR 0x314C 95 #define ICH9_CC_D25IR 0x3150 96 #define ICH9_CC_DIR_DEFAULT 0x3210 97 #define ICH9_CC_D30IR_DEFAULT 0x0 98 #define ICH9_CC_DIR_SHIFT 4 99 #define ICH9_CC_DIR_MASK 0x7 100 #define ICH9_CC_OIC 0x31FF 101 #define ICH9_CC_OIC_AEN 0x1 102 #define ICH9_CC_GCS 0x3410 103 #define ICH9_CC_GCS_DEFAULT 0x00000020 104 #define ICH9_CC_GCS_NO_REBOOT (1 << 5) 105 106 /* D28:F[0-5] */ 107 #define ICH9_PCIE_DEV 28 108 #define ICH9_PCIE_FUNC_MAX 6 109 110 111 /* D29:F0 USB UHCI Controller #1 */ 112 #define ICH9_USB_UHCI1_DEV 29 113 #define ICH9_USB_UHCI1_FUNC 0 114 115 /* D30:F0 DMI-to-PCI bridge */ 116 #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" 117 #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 118 119 #define ICH9_D2P_BRIDGE_DEV 30 120 #define ICH9_D2P_BRIDGE_FUNC 0 121 122 #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) 123 124 #define ICH9_D2P_A2_REVISION 0x92 125 126 /* D31:F0 LPC Processor Interface */ 127 #define ICH9_RST_CNT_IOPORT 0xCF9 128 129 /* D31:F1 LPC controller */ 130 #define ICH9_A2_LPC "ICH9 A2 LPC" 131 #define ICH9_A2_LPC_SAVEVM_VERSION 0 132 133 #define ICH9_LPC_DEV 31 134 #define ICH9_LPC_FUNC 0 135 136 #define ICH9_A2_LPC_REVISION 0x2 137 #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ 138 139 #define ICH9_LPC_PMBASE 0x40 140 #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7) 141 #define ICH9_LPC_PMBASE_RTE 0x1 142 #define ICH9_LPC_PMBASE_DEFAULT 0x1 143 144 #define ICH9_LPC_ACPI_CTRL 0x44 145 #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 146 #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0) 147 #define ICH9_LPC_ACPI_CTRL_9 0x0 148 #define ICH9_LPC_ACPI_CTRL_10 0x1 149 #define ICH9_LPC_ACPI_CTRL_11 0x2 150 #define ICH9_LPC_ACPI_CTRL_20 0x4 151 #define ICH9_LPC_ACPI_CTRL_21 0x5 152 #define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 153 154 #define ICH9_LPC_PIRQA_ROUT 0x60 155 #define ICH9_LPC_PIRQB_ROUT 0x61 156 #define ICH9_LPC_PIRQC_ROUT 0x62 157 #define ICH9_LPC_PIRQD_ROUT 0x63 158 159 #define ICH9_LPC_PIRQE_ROUT 0x68 160 #define ICH9_LPC_PIRQF_ROUT 0x69 161 #define ICH9_LPC_PIRQG_ROUT 0x6a 162 #define ICH9_LPC_PIRQH_ROUT 0x6b 163 164 #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 165 #define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0) 166 #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 167 168 #define ICH9_LPC_GEN_PMCON_1 0xa0 169 #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) 170 #define ICH9_LPC_GEN_PMCON_2 0xa2 171 #define ICH9_LPC_GEN_PMCON_3 0xa4 172 #define ICH9_LPC_GEN_PMCON_LOCK 0xa6 173 174 #define ICH9_LPC_RCBA 0xf0 175 #define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14) 176 #define ICH9_LPC_RCBA_EN 0x1 177 #define ICH9_LPC_RCBA_DEFAULT 0x0 178 179 #define ICH9_LPC_PIC_NUM_PINS 16 180 #define ICH9_LPC_IOAPIC_NUM_PINS 24 181 182 #define ICH9_GPIO_GSI "gsi" 183 184 /* D31:F2 SATA Controller #1 */ 185 #define ICH9_SATA1_DEV 31 186 #define ICH9_SATA1_FUNC 2 187 188 /* D31:F0 power management I/O registers 189 offset from the address ICH9_LPC_PMBASE */ 190 191 /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ 192 #define ICH9_PMIO_SIZE 128 193 #define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) 194 195 #define ICH9_PMIO_PM1_STS 0x00 196 #define ICH9_PMIO_PM1_EN 0x02 197 #define ICH9_PMIO_PM1_CNT 0x04 198 #define ICH9_PMIO_PM1_TMR 0x08 199 #define ICH9_PMIO_GPE0_STS 0x20 200 #define ICH9_PMIO_GPE0_EN 0x28 201 #define ICH9_PMIO_GPE0_LEN 16 202 #define ICH9_PMIO_SMI_EN 0x30 203 #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) 204 #define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) 205 #define ICH9_PMIO_SMI_STS 0x34 206 #define ICH9_PMIO_TCO_RLD 0x60 207 #define ICH9_PMIO_TCO_LEN 32 208 209 /* FADT ACPI_ENABLE/ACPI_DISABLE */ 210 #define ICH9_APM_ACPI_ENABLE 0x2 211 #define ICH9_APM_ACPI_DISABLE 0x3 212 213 214 /* D31:F3 SMBus controller */ 215 #define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" 216 217 #define ICH9_A2_SMB_REVISION 0x02 218 #define ICH9_SMB_PI 0x00 219 220 #define ICH9_SMB_SMBMBAR0 0x10 221 #define ICH9_SMB_SMBMBAR1 0x14 222 #define ICH9_SMB_SMBM_BAR 0 223 #define ICH9_SMB_SMBM_SIZE (1 << 8) 224 #define ICH9_SMB_SMB_BASE 0x20 225 #define ICH9_SMB_SMB_BASE_BAR 4 226 #define ICH9_SMB_SMB_BASE_SIZE (1 << 5) 227 #define ICH9_SMB_HOSTC 0x40 228 #define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) 229 #define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) 230 #define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) 231 #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) 232 233 /* D31:F3 SMBus I/O and memory mapped I/O registers */ 234 #define ICH9_SMB_DEV 31 235 #define ICH9_SMB_FUNC 3 236 237 #define ICH9_SMB_HST_STS 0x00 238 #define ICH9_SMB_HST_CNT 0x02 239 #define ICH9_SMB_HST_CMD 0x03 240 #define ICH9_SMB_XMIT_SLVA 0x04 241 #define ICH9_SMB_HST_D0 0x05 242 #define ICH9_SMB_HST_D1 0x06 243 #define ICH9_SMB_HOST_BLOCK_DB 0x07 244 245 #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" 246 247 /* bit positions used in fw_cfg SMI feature negotiation */ 248 #define ICH9_LPC_SMI_F_BROADCAST_BIT 0 249 #define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1 250 #define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2 251 252 #endif /* HW_ICH9_H */ 253