1 #ifndef HW_ICH9_H 2 #define HW_ICH9_H 3 4 #include "hw/sysbus.h" 5 #include "hw/i386/pc.h" 6 #include "hw/isa/apm.h" 7 #include "hw/acpi/acpi.h" 8 #include "hw/acpi/ich9.h" 9 #include "qom/object.h" 10 11 void ich9_generate_smi(void); 12 13 #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ 14 15 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" 16 OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) 17 18 struct ICH9LPCState { 19 /* ICH9 LPC PCI to ISA bridge */ 20 PCIDevice d; 21 22 /* (pci device, intx) -> pirq 23 * In real chipset case, the unused slots are never used 24 * as ICH9 supports only D25-D31 irq routing. 25 * On the other hand in qemu case, any slot/function can be populated 26 * via command line option. 27 * So fallback interrupt routing for any devices in any slots is necessary. 28 */ 29 uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; 30 31 APMState apm; 32 ICH9LPCPMRegs pm; 33 uint32_t sci_level; /* track sci level */ 34 uint8_t sci_gsi; 35 36 /* 2.24 Pin Straps */ 37 struct { 38 bool spkr_hi; 39 } pin_strap; 40 41 /* 10.1 Chipset Configuration registers(Memory Space) 42 which is pointed by RCBA */ 43 uint8_t chip_config[ICH9_CC_SIZE]; 44 45 /* 46 * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0) 47 * 48 * register contents and IO memory region 49 */ 50 uint8_t rst_cnt; 51 MemoryRegion rst_cnt_mem; 52 53 /* SMI feature negotiation via fw_cfg */ 54 uint64_t smi_host_features; /* guest-invisible, host endian */ 55 uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little 56 * endian uint64_t */ 57 uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little 58 * endian uint64_t */ 59 uint8_t smi_features_ok; /* guest-visible, read-only; selecting it 60 * triggers feature lockdown */ 61 uint64_t smi_negotiated_features; /* guest-invisible, host endian */ 62 63 MemoryRegion rcrb_mem; /* root complex register block */ 64 Notifier machine_ready; 65 66 qemu_irq gsi[GSI_NUM_PINS]; 67 }; 68 69 #define ICH9_MASK(bit, ms_bit, ls_bit) \ 70 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) 71 72 /* ICH9: Chipset Configuration Registers */ 73 #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) 74 75 #define ICH9_CC 76 #define ICH9_CC_D28IP 0x310C 77 #define ICH9_CC_D28IP_SHIFT 4 78 #define ICH9_CC_D28IP_MASK 0xf 79 #define ICH9_CC_D28IP_DEFAULT 0x00214321 80 #define ICH9_CC_D31IR 0x3140 81 #define ICH9_CC_D30IR 0x3142 82 #define ICH9_CC_D29IR 0x3144 83 #define ICH9_CC_D28IR 0x3146 84 #define ICH9_CC_D27IR 0x3148 85 #define ICH9_CC_D26IR 0x314C 86 #define ICH9_CC_D25IR 0x3150 87 #define ICH9_CC_DIR_DEFAULT 0x3210 88 #define ICH9_CC_D30IR_DEFAULT 0x0 89 #define ICH9_CC_DIR_SHIFT 4 90 #define ICH9_CC_DIR_MASK 0x7 91 #define ICH9_CC_OIC 0x31FF 92 #define ICH9_CC_OIC_AEN 0x1 93 #define ICH9_CC_GCS 0x3410 94 #define ICH9_CC_GCS_DEFAULT 0x00000020 95 #define ICH9_CC_GCS_NO_REBOOT (1 << 5) 96 97 /* D28:F[0-5] */ 98 #define ICH9_PCIE_DEV 28 99 #define ICH9_PCIE_FUNC_MAX 6 100 101 102 /* D29:F0 USB UHCI Controller #1 */ 103 #define ICH9_USB_UHCI1_DEV 29 104 #define ICH9_USB_UHCI1_FUNC 0 105 106 /* D30:F0 DMI-to-PCI bridge */ 107 #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" 108 #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 109 110 #define ICH9_D2P_BRIDGE_DEV 30 111 #define ICH9_D2P_BRIDGE_FUNC 0 112 113 #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) 114 115 #define ICH9_D2P_A2_REVISION 0x92 116 117 /* D31:F0 LPC Processor Interface */ 118 #define ICH9_RST_CNT_IOPORT 0xCF9 119 120 /* D31:F1 LPC controller */ 121 #define ICH9_A2_LPC "ICH9 A2 LPC" 122 #define ICH9_A2_LPC_SAVEVM_VERSION 0 123 124 #define ICH9_LPC_DEV 31 125 #define ICH9_LPC_FUNC 0 126 127 #define ICH9_A2_LPC_REVISION 0x2 128 #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ 129 130 #define ICH9_LPC_PMBASE 0x40 131 #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7) 132 #define ICH9_LPC_PMBASE_RTE 0x1 133 #define ICH9_LPC_PMBASE_DEFAULT 0x1 134 135 #define ICH9_LPC_ACPI_CTRL 0x44 136 #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 137 #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0) 138 #define ICH9_LPC_ACPI_CTRL_9 0x0 139 #define ICH9_LPC_ACPI_CTRL_10 0x1 140 #define ICH9_LPC_ACPI_CTRL_11 0x2 141 #define ICH9_LPC_ACPI_CTRL_20 0x4 142 #define ICH9_LPC_ACPI_CTRL_21 0x5 143 #define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 144 145 #define ICH9_LPC_PIRQA_ROUT 0x60 146 #define ICH9_LPC_PIRQB_ROUT 0x61 147 #define ICH9_LPC_PIRQC_ROUT 0x62 148 #define ICH9_LPC_PIRQD_ROUT 0x63 149 150 #define ICH9_LPC_PIRQE_ROUT 0x68 151 #define ICH9_LPC_PIRQF_ROUT 0x69 152 #define ICH9_LPC_PIRQG_ROUT 0x6a 153 #define ICH9_LPC_PIRQH_ROUT 0x6b 154 155 #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 156 #define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0) 157 #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 158 159 #define ICH9_LPC_GEN_PMCON_1 0xa0 160 #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) 161 #define ICH9_LPC_GEN_PMCON_2 0xa2 162 #define ICH9_LPC_GEN_PMCON_3 0xa4 163 #define ICH9_LPC_GEN_PMCON_LOCK 0xa6 164 165 #define ICH9_LPC_RCBA 0xf0 166 #define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14) 167 #define ICH9_LPC_RCBA_EN 0x1 168 #define ICH9_LPC_RCBA_DEFAULT 0x0 169 170 #define ICH9_LPC_PIC_NUM_PINS 16 171 #define ICH9_LPC_IOAPIC_NUM_PINS 24 172 173 #define ICH9_GPIO_GSI "gsi" 174 175 /* D31:F2 SATA Controller #1 */ 176 #define ICH9_SATA1_DEV 31 177 #define ICH9_SATA1_FUNC 2 178 179 /* D31:F0 power management I/O registers 180 offset from the address ICH9_LPC_PMBASE */ 181 182 /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ 183 #define ICH9_PMIO_SIZE 128 184 #define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) 185 186 #define ICH9_PMIO_PM1_STS 0x00 187 #define ICH9_PMIO_PM1_EN 0x02 188 #define ICH9_PMIO_PM1_CNT 0x04 189 #define ICH9_PMIO_PM1_TMR 0x08 190 #define ICH9_PMIO_GPE0_STS 0x20 191 #define ICH9_PMIO_GPE0_EN 0x28 192 #define ICH9_PMIO_GPE0_LEN 16 193 #define ICH9_PMIO_SMI_EN 0x30 194 #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) 195 #define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) 196 #define ICH9_PMIO_SMI_STS 0x34 197 #define ICH9_PMIO_TCO_RLD 0x60 198 #define ICH9_PMIO_TCO_LEN 32 199 200 /* FADT ACPI_ENABLE/ACPI_DISABLE */ 201 #define ICH9_APM_ACPI_ENABLE 0x2 202 #define ICH9_APM_ACPI_DISABLE 0x3 203 204 205 /* D31:F3 SMBus controller */ 206 #define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" 207 208 #define ICH9_A2_SMB_REVISION 0x02 209 #define ICH9_SMB_PI 0x00 210 211 #define ICH9_SMB_SMBMBAR0 0x10 212 #define ICH9_SMB_SMBMBAR1 0x14 213 #define ICH9_SMB_SMBM_BAR 0 214 #define ICH9_SMB_SMBM_SIZE (1 << 8) 215 #define ICH9_SMB_SMB_BASE 0x20 216 #define ICH9_SMB_SMB_BASE_BAR 4 217 #define ICH9_SMB_SMB_BASE_SIZE (1 << 5) 218 #define ICH9_SMB_HOSTC 0x40 219 #define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) 220 #define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) 221 #define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) 222 #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) 223 224 /* D31:F3 SMBus I/O and memory mapped I/O registers */ 225 #define ICH9_SMB_DEV 31 226 #define ICH9_SMB_FUNC 3 227 228 #define ICH9_SMB_HST_STS 0x00 229 #define ICH9_SMB_HST_CNT 0x02 230 #define ICH9_SMB_HST_CMD 0x03 231 #define ICH9_SMB_XMIT_SLVA 0x04 232 #define ICH9_SMB_HST_D0 0x05 233 #define ICH9_SMB_HST_D1 0x06 234 #define ICH9_SMB_HOST_BLOCK_DB 0x07 235 236 #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" 237 238 /* bit positions used in fw_cfg SMI feature negotiation */ 239 #define ICH9_LPC_SMI_F_BROADCAST_BIT 0 240 #define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1 241 #define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2 242 243 #endif /* HW_ICH9_H */ 244