12a6a4076SMarkus Armbruster #ifndef SH_INTC_H 22a6a4076SMarkus Armbruster #define SH_INTC_H 380f515e6Sbalrog 4*ec150c7eSMarkus Armbruster #include "exec/memory.h" 583c9f4caSPaolo Bonzini #include "hw/irq.h" 696e2fc41Saurel32 780f515e6Sbalrog typedef unsigned char intc_enum; 880f515e6Sbalrog 980f515e6Sbalrog struct intc_vect { 1080f515e6Sbalrog intc_enum enum_id; 1180f515e6Sbalrog unsigned short vect; 1280f515e6Sbalrog }; 1380f515e6Sbalrog 1480f515e6Sbalrog #define INTC_VECT(enum_id, vect) { enum_id, vect } 1580f515e6Sbalrog 1680f515e6Sbalrog struct intc_group { 1780f515e6Sbalrog intc_enum enum_id; 1880f515e6Sbalrog intc_enum enum_ids[32]; 1980f515e6Sbalrog }; 2080f515e6Sbalrog 21001faf32SBlue Swirl #define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } } 2280f515e6Sbalrog 2380f515e6Sbalrog struct intc_mask_reg { 2480f515e6Sbalrog unsigned long set_reg, clr_reg, reg_width; 2580f515e6Sbalrog intc_enum enum_ids[32]; 2680f515e6Sbalrog unsigned long value; 2780f515e6Sbalrog }; 2880f515e6Sbalrog 2980f515e6Sbalrog struct intc_prio_reg { 3080f515e6Sbalrog unsigned long set_reg, clr_reg, reg_width, field_width; 3180f515e6Sbalrog intc_enum enum_ids[16]; 3280f515e6Sbalrog unsigned long value; 3380f515e6Sbalrog }; 3480f515e6Sbalrog 35b1503cdaSmalc #define _INTC_ARRAY(a) a, ARRAY_SIZE(a) 3680f515e6Sbalrog 3780f515e6Sbalrog struct intc_source { 3880f515e6Sbalrog unsigned short vect; 3980f515e6Sbalrog intc_enum next_enum_id; 4080f515e6Sbalrog 41e96e2044Sths int asserted; /* emulates the interrupt signal line from device to intc */ 4280f515e6Sbalrog int enable_count; 4380f515e6Sbalrog int enable_max; 44e96e2044Sths int pending; /* emulates the result of signal and masking */ 45e96e2044Sths struct intc_desc *parent; 4680f515e6Sbalrog }; 4780f515e6Sbalrog 4880f515e6Sbalrog struct intc_desc { 49b279e5efSBenoît Canet MemoryRegion iomem; 50b279e5efSBenoît Canet MemoryRegion *iomem_aliases; 5196e2fc41Saurel32 qemu_irq *irqs; 5280f515e6Sbalrog struct intc_source *sources; 5380f515e6Sbalrog int nr_sources; 5480f515e6Sbalrog struct intc_mask_reg *mask_regs; 5580f515e6Sbalrog int nr_mask_regs; 5680f515e6Sbalrog struct intc_prio_reg *prio_regs; 5780f515e6Sbalrog int nr_prio_regs; 58e96e2044Sths int pending; /* number of interrupt sources that has pending set */ 5980f515e6Sbalrog }; 6080f515e6Sbalrog 61e96e2044Sths int sh_intc_get_pending_vector(struct intc_desc *desc, int imask); 6280f515e6Sbalrog struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id); 63e96e2044Sths void sh_intc_toggle_source(struct intc_source *source, 64e96e2044Sths int enable_adj, int assert_adj); 6580f515e6Sbalrog 6680f515e6Sbalrog void sh_intc_register_sources(struct intc_desc *desc, 6780f515e6Sbalrog struct intc_vect *vectors, 6880f515e6Sbalrog int nr_vectors, 6980f515e6Sbalrog struct intc_group *groups, 7080f515e6Sbalrog int nr_groups); 7180f515e6Sbalrog 72b279e5efSBenoît Canet int sh_intc_init(MemoryRegion *sysmem, 73b279e5efSBenoît Canet struct intc_desc *desc, 7480f515e6Sbalrog int nr_sources, 7580f515e6Sbalrog struct intc_mask_reg *mask_regs, 7680f515e6Sbalrog int nr_mask_regs, 7780f515e6Sbalrog struct intc_prio_reg *prio_regs, 7880f515e6Sbalrog int nr_prio_regs); 7980f515e6Sbalrog 80c6d86a33Sbalrog void sh_intc_set_irl(void *opaque, int n, int level); 81c6d86a33Sbalrog 822a6a4076SMarkus Armbruster #endif /* SH_INTC_H */ 83