12a6a4076SMarkus Armbruster #ifndef SH_INTC_H 22a6a4076SMarkus Armbruster #define SH_INTC_H 380f515e6Sbalrog 4*8be545baSRichard Henderson #include "system/memory.h" 596e2fc41Saurel32 680f515e6Sbalrog typedef unsigned char intc_enum; 780f515e6Sbalrog 880f515e6Sbalrog struct intc_vect { 980f515e6Sbalrog intc_enum enum_id; 1080f515e6Sbalrog unsigned short vect; 1180f515e6Sbalrog }; 1280f515e6Sbalrog 1380f515e6Sbalrog #define INTC_VECT(enum_id, vect) { enum_id, vect } 1480f515e6Sbalrog 1580f515e6Sbalrog struct intc_group { 1680f515e6Sbalrog intc_enum enum_id; 1780f515e6Sbalrog intc_enum enum_ids[32]; 1880f515e6Sbalrog }; 1980f515e6Sbalrog 20001faf32SBlue Swirl #define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } } 2180f515e6Sbalrog 2280f515e6Sbalrog struct intc_mask_reg { 2380f515e6Sbalrog unsigned long set_reg, clr_reg, reg_width; 2480f515e6Sbalrog intc_enum enum_ids[32]; 2580f515e6Sbalrog unsigned long value; 2680f515e6Sbalrog }; 2780f515e6Sbalrog 2880f515e6Sbalrog struct intc_prio_reg { 2980f515e6Sbalrog unsigned long set_reg, clr_reg, reg_width, field_width; 3080f515e6Sbalrog intc_enum enum_ids[16]; 3180f515e6Sbalrog unsigned long value; 3280f515e6Sbalrog }; 3380f515e6Sbalrog 34b1503cdaSmalc #define _INTC_ARRAY(a) a, ARRAY_SIZE(a) 3580f515e6Sbalrog 3680f515e6Sbalrog struct intc_source { 3780f515e6Sbalrog unsigned short vect; 3880f515e6Sbalrog intc_enum next_enum_id; 3980f515e6Sbalrog 40e96e2044Sths int asserted; /* emulates the interrupt signal line from device to intc */ 4180f515e6Sbalrog int enable_count; 4280f515e6Sbalrog int enable_max; 43e96e2044Sths int pending; /* emulates the result of signal and masking */ 44e96e2044Sths struct intc_desc *parent; 4580f515e6Sbalrog }; 4680f515e6Sbalrog 4780f515e6Sbalrog struct intc_desc { 48b279e5efSBenoît Canet MemoryRegion iomem; 49b279e5efSBenoît Canet MemoryRegion *iomem_aliases; 5096e2fc41Saurel32 qemu_irq *irqs; 5180f515e6Sbalrog struct intc_source *sources; 5280f515e6Sbalrog int nr_sources; 5380f515e6Sbalrog struct intc_mask_reg *mask_regs; 5480f515e6Sbalrog int nr_mask_regs; 5580f515e6Sbalrog struct intc_prio_reg *prio_regs; 5680f515e6Sbalrog int nr_prio_regs; 57e96e2044Sths int pending; /* number of interrupt sources that has pending set */ 5880f515e6Sbalrog }; 5980f515e6Sbalrog 60e96e2044Sths int sh_intc_get_pending_vector(struct intc_desc *desc, int imask); 619b12fb10SBALATON Zoltan 62e96e2044Sths void sh_intc_toggle_source(struct intc_source *source, 63e96e2044Sths int enable_adj, int assert_adj); 6480f515e6Sbalrog 6580f515e6Sbalrog void sh_intc_register_sources(struct intc_desc *desc, 6680f515e6Sbalrog struct intc_vect *vectors, 6780f515e6Sbalrog int nr_vectors, 6880f515e6Sbalrog struct intc_group *groups, 6980f515e6Sbalrog int nr_groups); 7080f515e6Sbalrog 71b279e5efSBenoît Canet int sh_intc_init(MemoryRegion *sysmem, 72b279e5efSBenoît Canet struct intc_desc *desc, 7380f515e6Sbalrog int nr_sources, 7480f515e6Sbalrog struct intc_mask_reg *mask_regs, 7580f515e6Sbalrog int nr_mask_regs, 7680f515e6Sbalrog struct intc_prio_reg *prio_regs, 7780f515e6Sbalrog int nr_prio_regs); 7880f515e6Sbalrog 79c6d86a33Sbalrog void sh_intc_set_irl(void *opaque, int n, int level); 80c6d86a33Sbalrog 812a6a4076SMarkus Armbruster #endif /* SH_INTC_H */ 82