xref: /qemu/include/hw/s390x/css.h (revision 57065a70d00c36f5d20d430eb64d16db8e761c31)
1df1fe5bbSCornelia Huck /*
2df1fe5bbSCornelia Huck  * Channel subsystem structures and definitions.
3df1fe5bbSCornelia Huck  *
4df1fe5bbSCornelia Huck  * Copyright 2012 IBM Corp.
5df1fe5bbSCornelia Huck  * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
6df1fe5bbSCornelia Huck  *
7df1fe5bbSCornelia Huck  * This work is licensed under the terms of the GNU GPL, version 2 or (at
8df1fe5bbSCornelia Huck  * your option) any later version. See the COPYING file in the top-level
9df1fe5bbSCornelia Huck  * directory.
10df1fe5bbSCornelia Huck  */
11df1fe5bbSCornelia Huck 
12df1fe5bbSCornelia Huck #ifndef CSS_H
13df1fe5bbSCornelia Huck #define CSS_H
14df1fe5bbSCornelia Huck 
152283f4d6SFei Li #include "cpu.h"
16a28d8391SYi Min Zhao #include "hw/s390x/adapter.h"
17a28d8391SYi Min Zhao #include "hw/s390x/s390_flic.h"
18bd3f16acSPaolo Bonzini #include "hw/s390x/ioinst.h"
19f16bbb9bSDavid Hildenbrand #include "sysemu/kvm.h"
20df1fe5bbSCornelia Huck 
21df1fe5bbSCornelia Huck /* Channel subsystem constants. */
22cf249935SSascha Silbe #define MAX_DEVNO 65535
23df1fe5bbSCornelia Huck #define MAX_SCHID 65535
24df1fe5bbSCornelia Huck #define MAX_SSID 3
25882b3b97SCornelia Huck #define MAX_CSSID 255
26df1fe5bbSCornelia Huck #define MAX_CHPID 255
27df1fe5bbSCornelia Huck 
28dde522bbSFei Li #define MAX_ISC 7
29dde522bbSFei Li 
30df1fe5bbSCornelia Huck #define MAX_CIWS 62
31df1fe5bbSCornelia Huck 
32cf249935SSascha Silbe #define VIRTUAL_CSSID 0xfe
336c15e9bfSJing Liu #define VIRTIO_CCW_CHPID 0   /* used by convention */
34cf249935SSascha Silbe 
35df1fe5bbSCornelia Huck typedef struct CIW {
36df1fe5bbSCornelia Huck     uint8_t type;
37df1fe5bbSCornelia Huck     uint8_t command;
38df1fe5bbSCornelia Huck     uint16_t count;
39df1fe5bbSCornelia Huck } QEMU_PACKED CIW;
40df1fe5bbSCornelia Huck 
41df1fe5bbSCornelia Huck typedef struct SenseId {
42df1fe5bbSCornelia Huck     /* common part */
43df1fe5bbSCornelia Huck     uint8_t reserved;        /* always 0x'FF' */
44df1fe5bbSCornelia Huck     uint16_t cu_type;        /* control unit type */
45df1fe5bbSCornelia Huck     uint8_t cu_model;        /* control unit model */
46df1fe5bbSCornelia Huck     uint16_t dev_type;       /* device type */
47df1fe5bbSCornelia Huck     uint8_t dev_model;       /* device model */
48df1fe5bbSCornelia Huck     uint8_t unused;          /* padding byte */
49df1fe5bbSCornelia Huck     /* extended part */
50df1fe5bbSCornelia Huck     CIW ciw[MAX_CIWS];       /* variable # of CIWs */
51df1fe5bbSCornelia Huck } QEMU_PACKED SenseId;
52df1fe5bbSCornelia Huck 
53df1fe5bbSCornelia Huck /* Channel measurements, from linux/drivers/s390/cio/cmf.c. */
54df1fe5bbSCornelia Huck typedef struct CMB {
55df1fe5bbSCornelia Huck     uint16_t ssch_rsch_count;
56df1fe5bbSCornelia Huck     uint16_t sample_count;
57df1fe5bbSCornelia Huck     uint32_t device_connect_time;
58df1fe5bbSCornelia Huck     uint32_t function_pending_time;
59df1fe5bbSCornelia Huck     uint32_t device_disconnect_time;
60df1fe5bbSCornelia Huck     uint32_t control_unit_queuing_time;
61df1fe5bbSCornelia Huck     uint32_t device_active_only_time;
62df1fe5bbSCornelia Huck     uint32_t reserved[2];
63df1fe5bbSCornelia Huck } QEMU_PACKED CMB;
64df1fe5bbSCornelia Huck 
65df1fe5bbSCornelia Huck typedef struct CMBE {
66df1fe5bbSCornelia Huck     uint32_t ssch_rsch_count;
67df1fe5bbSCornelia Huck     uint32_t sample_count;
68df1fe5bbSCornelia Huck     uint32_t device_connect_time;
69df1fe5bbSCornelia Huck     uint32_t function_pending_time;
70df1fe5bbSCornelia Huck     uint32_t device_disconnect_time;
71df1fe5bbSCornelia Huck     uint32_t control_unit_queuing_time;
72df1fe5bbSCornelia Huck     uint32_t device_active_only_time;
73df1fe5bbSCornelia Huck     uint32_t device_busy_time;
74df1fe5bbSCornelia Huck     uint32_t initial_command_response_time;
75df1fe5bbSCornelia Huck     uint32_t reserved[7];
76df1fe5bbSCornelia Huck } QEMU_PACKED CMBE;
77df1fe5bbSCornelia Huck 
78*57065a70SHalil Pasic typedef enum CcwDataStreamOp {
79*57065a70SHalil Pasic     CDS_OP_R = 0, /* read, false when used as is_write */
80*57065a70SHalil Pasic     CDS_OP_W = 1, /* write, true when used as is_write */
81*57065a70SHalil Pasic     CDS_OP_A = 2  /* advance, should not be used as is_write */
82*57065a70SHalil Pasic } CcwDataStreamOp;
83*57065a70SHalil Pasic 
84*57065a70SHalil Pasic /* normal usage is via SuchchDev.cds instead of instantiating */
85*57065a70SHalil Pasic typedef struct CcwDataStream {
86*57065a70SHalil Pasic #define CDS_F_IDA   0x01
87*57065a70SHalil Pasic #define CDS_F_MIDA  0x02
88*57065a70SHalil Pasic #define CDS_F_I2K   0x04
89*57065a70SHalil Pasic #define CDS_F_C64   0x08
90*57065a70SHalil Pasic #define CDS_F_STREAM_BROKEN  0x80
91*57065a70SHalil Pasic     uint8_t flags;
92*57065a70SHalil Pasic     uint8_t at_idaw;
93*57065a70SHalil Pasic     uint16_t at_byte;
94*57065a70SHalil Pasic     uint16_t count;
95*57065a70SHalil Pasic     uint32_t cda_orig;
96*57065a70SHalil Pasic     int (*op_handler)(struct CcwDataStream *cds, void *buff, int len,
97*57065a70SHalil Pasic                       CcwDataStreamOp op);
98*57065a70SHalil Pasic     hwaddr cda;
99*57065a70SHalil Pasic } CcwDataStream;
100*57065a70SHalil Pasic 
101bd3f16acSPaolo Bonzini typedef struct SubchDev SubchDev;
102df1fe5bbSCornelia Huck struct SubchDev {
103df1fe5bbSCornelia Huck     /* channel-subsystem related things: */
104df1fe5bbSCornelia Huck     uint8_t cssid;
105df1fe5bbSCornelia Huck     uint8_t ssid;
106df1fe5bbSCornelia Huck     uint16_t schid;
107df1fe5bbSCornelia Huck     uint16_t devno;
108df1fe5bbSCornelia Huck     SCHIB curr_status;
109df1fe5bbSCornelia Huck     uint8_t sense_data[32];
110df1fe5bbSCornelia Huck     hwaddr channel_prog;
111df1fe5bbSCornelia Huck     CCW1 last_cmd;
112df1fe5bbSCornelia Huck     bool last_cmd_valid;
113a327c921SCornelia Huck     bool ccw_fmt_1;
1147e749462SCornelia Huck     bool thinint_active;
115e8601dd5SCornelia Huck     uint8_t ccw_no_data_cnt;
116517ff12cSHalil Pasic     uint16_t migrated_schid; /* used for missmatch detection */
117ff443fe6SHalil Pasic     ORB orb;
118*57065a70SHalil Pasic     CcwDataStream cds;
119df1fe5bbSCornelia Huck     /* transport-provided data: */
120df1fe5bbSCornelia Huck     int (*ccw_cb) (SubchDev *, CCW1);
12162ac4a52SThomas Huth     void (*disable_cb)(SubchDev *);
122b5f5a3afSHalil Pasic     int (*do_subchannel_work) (SubchDev *);
123df1fe5bbSCornelia Huck     SenseId id;
124df1fe5bbSCornelia Huck     void *driver_data;
125df1fe5bbSCornelia Huck };
126df1fe5bbSCornelia Huck 
127517ff12cSHalil Pasic extern const VMStateDescription vmstate_subch_dev;
128517ff12cSHalil Pasic 
1298f3cf012SXiao Feng Ren /*
1308f3cf012SXiao Feng Ren  * Identify a device within the channel subsystem.
1318f3cf012SXiao Feng Ren  * Note that this can be used to identify either the subchannel or
1328f3cf012SXiao Feng Ren  * the attached I/O device, as there's always one I/O device per
1338f3cf012SXiao Feng Ren  * subchannel.
1348f3cf012SXiao Feng Ren  */
1358f3cf012SXiao Feng Ren typedef struct CssDevId {
1368f3cf012SXiao Feng Ren     uint8_t cssid;
1378f3cf012SXiao Feng Ren     uint8_t ssid;
1388f3cf012SXiao Feng Ren     uint16_t devid;
1398f3cf012SXiao Feng Ren     bool valid;
1408f3cf012SXiao Feng Ren } CssDevId;
1418f3cf012SXiao Feng Ren 
1421b6b7d10SFam Zheng extern const PropertyInfo css_devid_propinfo;
1438f3cf012SXiao Feng Ren 
1448f3cf012SXiao Feng Ren #define DEFINE_PROP_CSS_DEV_ID(_n, _s, _f) \
1458f3cf012SXiao Feng Ren     DEFINE_PROP(_n, _s, _f, css_devid_propinfo, CssDevId)
1468f3cf012SXiao Feng Ren 
147a28d8391SYi Min Zhao typedef struct IndAddr {
148a28d8391SYi Min Zhao     hwaddr addr;
149a28d8391SYi Min Zhao     uint64_t map;
150a28d8391SYi Min Zhao     unsigned long refcnt;
151517ff12cSHalil Pasic     int32_t len;
152a28d8391SYi Min Zhao     QTAILQ_ENTRY(IndAddr) sibling;
153a28d8391SYi Min Zhao } IndAddr;
154a28d8391SYi Min Zhao 
155517ff12cSHalil Pasic extern const VMStateDescription vmstate_ind_addr;
156517ff12cSHalil Pasic 
157517ff12cSHalil Pasic #define VMSTATE_PTR_TO_IND_ADDR(_f, _s)                                   \
158517ff12cSHalil Pasic     VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*)
159517ff12cSHalil Pasic 
160a28d8391SYi Min Zhao IndAddr *get_indicator(hwaddr ind_addr, int len);
161a28d8391SYi Min Zhao void release_indicator(AdapterInfo *adapter, IndAddr *indicator);
162a28d8391SYi Min Zhao int map_indicator(AdapterInfo *adapter, IndAddr *indicator);
163a28d8391SYi Min Zhao 
164df1fe5bbSCornelia Huck typedef SubchDev *(*css_subch_cb_func)(uint8_t m, uint8_t cssid, uint8_t ssid,
165df1fe5bbSCornelia Huck                                        uint16_t schid);
166df1fe5bbSCornelia Huck int css_create_css_image(uint8_t cssid, bool default_image);
167df1fe5bbSCornelia Huck bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno);
168df1fe5bbSCornelia Huck void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
169df1fe5bbSCornelia Huck                       uint16_t devno, SubchDev *sch);
170df1fe5bbSCornelia Huck void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type);
1718f3cf012SXiao Feng Ren int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id);
1726c15e9bfSJing Liu unsigned int css_find_free_chpid(uint8_t cssid);
173b4436a0bSCornelia Huck uint16_t css_build_subchannel_id(SubchDev *sch);
1748ca2b376SXiao Feng Ren void copy_scsw_to_guest(SCSW *dest, const SCSW *src);
1758ca2b376SXiao Feng Ren void css_inject_io_interrupt(SubchDev *sch);
176df1fe5bbSCornelia Huck void css_reset(void);
177df1fe5bbSCornelia Huck void css_reset_sch(SubchDev *sch);
1785c8d6f00SDong Jia Shi void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
1795c8d6f00SDong Jia Shi                    int chain, uint16_t rsid);
180df1fe5bbSCornelia Huck void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
181df1fe5bbSCornelia Huck                            int hotplugged, int add);
182df1fe5bbSCornelia Huck void css_generate_chp_crws(uint8_t cssid, uint8_t chpid);
1838cba80c3SFrank Blaschka void css_generate_css_crws(uint8_t cssid);
184c81b4f89SSong Shan Gong void css_clear_sei_pending(void);
185bab482d7SXiao Feng Ren int s390_ccw_cmd_request(ORB *orb, SCSW *scsw, void *data);
186b5f5a3afSHalil Pasic int do_subchannel_work_virtual(SubchDev *sub);
187b5f5a3afSHalil Pasic int do_subchannel_work_passthrough(SubchDev *sub);
18803cf077aSCornelia Huck 
1895b00bef2SFei Li typedef enum {
1905b00bef2SFei Li     CSS_IO_ADAPTER_VIRTIO = 0,
1915b00bef2SFei Li     CSS_IO_ADAPTER_PCI = 1,
1925b00bef2SFei Li     CSS_IO_ADAPTER_TYPE_NUMS,
1935b00bef2SFei Li } CssIoAdapterType;
1945b00bef2SFei Li 
19525a08b8dSYi Min Zhao void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
1962283f4d6SFei Li int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
197dde522bbSFei Li uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
198dde522bbSFei Li void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
1991497c160SFei Li                               uint8_t flags, Error **errp);
2001497c160SFei Li 
2011497c160SFei Li #ifndef CONFIG_KVM
2021497c160SFei Li #define S390_ADAPTER_SUPPRESSIBLE 0x01
2031497c160SFei Li #else
2041497c160SFei Li #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
2051497c160SFei Li #endif
206bd3f16acSPaolo Bonzini 
207bd3f16acSPaolo Bonzini #ifndef CONFIG_USER_ONLY
208bd3f16acSPaolo Bonzini SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
209bd3f16acSPaolo Bonzini                          uint16_t schid);
210bd3f16acSPaolo Bonzini bool css_subch_visible(SubchDev *sch);
211bd3f16acSPaolo Bonzini void css_conditional_io_interrupt(SubchDev *sch);
212bd3f16acSPaolo Bonzini int css_do_stsch(SubchDev *sch, SCHIB *schib);
213bd3f16acSPaolo Bonzini bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
214bd3f16acSPaolo Bonzini int css_do_msch(SubchDev *sch, const SCHIB *schib);
215bd3f16acSPaolo Bonzini int css_do_xsch(SubchDev *sch);
216bd3f16acSPaolo Bonzini int css_do_csch(SubchDev *sch);
217bd3f16acSPaolo Bonzini int css_do_hsch(SubchDev *sch);
218bd3f16acSPaolo Bonzini int css_do_ssch(SubchDev *sch, ORB *orb);
219bd3f16acSPaolo Bonzini int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
220bd3f16acSPaolo Bonzini void css_do_tsch_update_subch(SubchDev *sch);
221bd3f16acSPaolo Bonzini int css_do_stcrw(CRW *crw);
222bd3f16acSPaolo Bonzini void css_undo_stcrw(CRW *crw);
223bd3f16acSPaolo Bonzini int css_do_tpi(IOIntCode *int_code, int lowcore);
224bd3f16acSPaolo Bonzini int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
225bd3f16acSPaolo Bonzini                          int rfmt, void *buf);
226bd3f16acSPaolo Bonzini void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
227bd3f16acSPaolo Bonzini int css_enable_mcsse(void);
228bd3f16acSPaolo Bonzini int css_enable_mss(void);
229bd3f16acSPaolo Bonzini int css_do_rsch(SubchDev *sch);
230bd3f16acSPaolo Bonzini int css_do_rchp(uint8_t cssid, uint8_t chpid);
231bd3f16acSPaolo Bonzini bool css_present(uint8_t cssid);
232bd3f16acSPaolo Bonzini #endif
233bd3f16acSPaolo Bonzini 
2341b6b7d10SFam Zheng extern const PropertyInfo css_devid_ro_propinfo;
235c35fc6aaSDong Jia Shi 
236c35fc6aaSDong Jia Shi #define DEFINE_PROP_CSS_DEV_ID_RO(_n, _s, _f) \
237c35fc6aaSDong Jia Shi     DEFINE_PROP(_n, _s, _f, css_devid_ro_propinfo, CssDevId)
238c35fc6aaSDong Jia Shi 
239cf249935SSascha Silbe /**
240cf249935SSascha Silbe  * Create a subchannel for the given bus id.
241cf249935SSascha Silbe  *
242817d4a6bSDong Jia Shi  * If @p bus_id is valid, and @p squash_mcss is true, verify that it is
243817d4a6bSDong Jia Shi  * not already in use in the default css, and find a free devno from the
244817d4a6bSDong Jia Shi  * default css image for it.
245817d4a6bSDong Jia Shi  * If @p bus_id is valid, and @p squash_mcss is false, verify that it is
246817d4a6bSDong Jia Shi  * not already in use, and find a free devno for it.
247817d4a6bSDong Jia Shi  * If @p bus_id is not valid, and if either @p squash_mcss or @p is_virtual
248817d4a6bSDong Jia Shi  * is true, find a free subchannel id and device number across all
249817d4a6bSDong Jia Shi  * subchannel sets from the default css image.
250817d4a6bSDong Jia Shi  * If @p bus_id is not valid, and if both @p squash_mcss and @p is_virtual
251817d4a6bSDong Jia Shi  * are false, find a non-full css image and find a free subchannel id and
252817d4a6bSDong Jia Shi  * device number across all subchannel sets from it.
253817d4a6bSDong Jia Shi  *
254817d4a6bSDong Jia Shi  * If either of the former actions succeed, allocate a subchannel structure,
255817d4a6bSDong Jia Shi  * initialise it with the bus id, subchannel id and device number, register
256817d4a6bSDong Jia Shi  * it with the CSS and return it. Otherwise return NULL.
257cf249935SSascha Silbe  *
258cf249935SSascha Silbe  * The caller becomes owner of the returned subchannel structure and
259cf249935SSascha Silbe  * is responsible for unregistering and freeing it.
260cf249935SSascha Silbe  */
261817d4a6bSDong Jia Shi SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss,
262817d4a6bSDong Jia Shi                          Error **errp);
263e996583eSHalil Pasic 
264e996583eSHalil Pasic /** Turn on css migration */
265e996583eSHalil Pasic void css_register_vmstate(void);
266e996583eSHalil Pasic 
267*57065a70SHalil Pasic 
268*57065a70SHalil Pasic void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb);
269*57065a70SHalil Pasic 
270*57065a70SHalil Pasic static inline void ccw_dstream_rewind(CcwDataStream *cds)
271*57065a70SHalil Pasic {
272*57065a70SHalil Pasic     cds->at_byte = 0;
273*57065a70SHalil Pasic     cds->at_idaw = 0;
274*57065a70SHalil Pasic     cds->cda = cds->cda_orig;
275*57065a70SHalil Pasic }
276*57065a70SHalil Pasic 
277*57065a70SHalil Pasic static inline bool ccw_dstream_good(CcwDataStream *cds)
278*57065a70SHalil Pasic {
279*57065a70SHalil Pasic     return !(cds->flags & CDS_F_STREAM_BROKEN);
280*57065a70SHalil Pasic }
281*57065a70SHalil Pasic 
282*57065a70SHalil Pasic static inline uint16_t ccw_dstream_residual_count(CcwDataStream *cds)
283*57065a70SHalil Pasic {
284*57065a70SHalil Pasic     return cds->count - cds->at_byte;
285*57065a70SHalil Pasic }
286*57065a70SHalil Pasic 
287*57065a70SHalil Pasic static inline uint16_t ccw_dstream_avail(CcwDataStream *cds)
288*57065a70SHalil Pasic {
289*57065a70SHalil Pasic     return ccw_dstream_good(cds) ? ccw_dstream_residual_count(cds) : 0;
290*57065a70SHalil Pasic }
291*57065a70SHalil Pasic 
292*57065a70SHalil Pasic static inline int ccw_dstream_advance(CcwDataStream *cds, int len)
293*57065a70SHalil Pasic {
294*57065a70SHalil Pasic     return cds->op_handler(cds, NULL, len, CDS_OP_A);
295*57065a70SHalil Pasic }
296*57065a70SHalil Pasic 
297*57065a70SHalil Pasic static inline int ccw_dstream_write_buf(CcwDataStream *cds, void *buff, int len)
298*57065a70SHalil Pasic {
299*57065a70SHalil Pasic     return cds->op_handler(cds, buff, len, CDS_OP_W);
300*57065a70SHalil Pasic }
301*57065a70SHalil Pasic 
302*57065a70SHalil Pasic static inline int ccw_dstream_read_buf(CcwDataStream *cds, void *buff, int len)
303*57065a70SHalil Pasic {
304*57065a70SHalil Pasic     return cds->op_handler(cds, buff, len, CDS_OP_R);
305*57065a70SHalil Pasic }
306*57065a70SHalil Pasic 
307*57065a70SHalil Pasic #define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v))
308*57065a70SHalil Pasic #define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v))
309*57065a70SHalil Pasic 
310df1fe5bbSCornelia Huck #endif
311