1a7240d1eSMichael Clark /* 2a7240d1eSMichael Clark * SiFive U series machine interface 3a7240d1eSMichael Clark * 4a7240d1eSMichael Clark * Copyright (c) 2017 SiFive, Inc. 5a7240d1eSMichael Clark * 6a7240d1eSMichael Clark * This program is free software; you can redistribute it and/or modify it 7a7240d1eSMichael Clark * under the terms and conditions of the GNU General Public License, 8a7240d1eSMichael Clark * version 2 or later, as published by the Free Software Foundation. 9a7240d1eSMichael Clark * 10a7240d1eSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 11a7240d1eSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12a7240d1eSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13a7240d1eSMichael Clark * more details. 14a7240d1eSMichael Clark * 15a7240d1eSMichael Clark * You should have received a copy of the GNU General Public License along with 16a7240d1eSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 17a7240d1eSMichael Clark */ 18a7240d1eSMichael Clark 19a7240d1eSMichael Clark #ifndef HW_SIFIVE_U_H 20a7240d1eSMichael Clark #define HW_SIFIVE_U_H 21a7240d1eSMichael Clark 225a7f76a3SAlistair Francis #include "hw/net/cadence_gem.h" 23ec150c7eSMarkus Armbruster #include "hw/riscv/riscv_hart.h" 2420f41c86SBin Meng #include "hw/riscv/sifive_cpu.h" 255a7f76a3SAlistair Francis 262308092bSAlistair Francis #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" 272308092bSAlistair Francis #define RISCV_U_SOC(obj) \ 282308092bSAlistair Francis OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) 292308092bSAlistair Francis 302308092bSAlistair Francis typedef struct SiFiveUSoCState { 312308092bSAlistair Francis /*< private >*/ 322308092bSAlistair Francis SysBusDevice parent_obj; 332308092bSAlistair Francis 342308092bSAlistair Francis /*< public >*/ 35ecdfe393SBin Meng CPUClusterState e_cluster; 36ecdfe393SBin Meng CPUClusterState u_cluster; 37ecdfe393SBin Meng RISCVHartArrayState e_cpus; 38ecdfe393SBin Meng RISCVHartArrayState u_cpus; 392308092bSAlistair Francis DeviceState *plic; 405a7f76a3SAlistair Francis CadenceGEMState gem; 412308092bSAlistair Francis } SiFiveUSoCState; 422308092bSAlistair Francis 43a7240d1eSMichael Clark typedef struct SiFiveUState { 44a7240d1eSMichael Clark /*< private >*/ 45a7240d1eSMichael Clark SysBusDevice parent_obj; 46a7240d1eSMichael Clark 47a7240d1eSMichael Clark /*< public >*/ 482308092bSAlistair Francis SiFiveUSoCState soc; 49a7240d1eSMichael Clark void *fdt; 50a7240d1eSMichael Clark int fdt_size; 51a7240d1eSMichael Clark } SiFiveUState; 52a7240d1eSMichael Clark 53a7240d1eSMichael Clark enum { 54a7240d1eSMichael Clark SIFIVE_U_DEBUG, 55a7240d1eSMichael Clark SIFIVE_U_MROM, 56a7240d1eSMichael Clark SIFIVE_U_CLINT, 57a7240d1eSMichael Clark SIFIVE_U_PLIC, 58a7240d1eSMichael Clark SIFIVE_U_UART0, 59a7240d1eSMichael Clark SIFIVE_U_UART1, 605a7f76a3SAlistair Francis SIFIVE_U_DRAM, 615a7f76a3SAlistair Francis SIFIVE_U_GEM 62a7240d1eSMichael Clark }; 63a7240d1eSMichael Clark 64a7240d1eSMichael Clark enum { 65a7240d1eSMichael Clark SIFIVE_U_UART0_IRQ = 3, 665a7f76a3SAlistair Francis SIFIVE_U_UART1_IRQ = 4, 675a7f76a3SAlistair Francis SIFIVE_U_GEM_IRQ = 0x35 68a7240d1eSMichael Clark }; 69a7240d1eSMichael Clark 702a8756edSMichael Clark enum { 71fe93582cSAnup Patel SIFIVE_U_CLOCK_FREQ = 1000000000, 72*e1724d09SBin Meng SIFIVE_U_HFCLK_FREQ = 33333333, 73*e1724d09SBin Meng SIFIVE_U_RTCCLK_FREQ = 1000000, 74fe93582cSAnup Patel SIFIVE_U_GEM_CLOCK_FREQ = 125000000 752a8756edSMichael Clark }; 762a8756edSMichael Clark 77f3d47d58SBin Meng #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 78ecdfe393SBin Meng #define SIFIVE_U_COMPUTE_CPU_COUNT 4 79f3d47d58SBin Meng 80a7240d1eSMichael Clark #define SIFIVE_U_PLIC_HART_CONFIG "MS" 810feb4a71SAlistair Francis #define SIFIVE_U_PLIC_NUM_SOURCES 54 82a7240d1eSMichael Clark #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 830feb4a71SAlistair Francis #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04 84a7240d1eSMichael Clark #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 85a7240d1eSMichael Clark #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 86a7240d1eSMichael Clark #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 87a7240d1eSMichael Clark #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 88a7240d1eSMichael Clark #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 89a7240d1eSMichael Clark 90a7240d1eSMichael Clark #endif 91